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IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O
FEATURES:
- - - - - - - - - Typical tSK(0) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP and 0.40mm pitch TVSOP packages Extended commercial range of -40C to +85C VCC = 3.3V 0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range CMOS power levels (0.4 W typ. static) All inputs, outputs and I/O are 5 Volt tolerant Supports hot insertion
IDT74LVC16373A
DESCRIPTION:
The LVC16373A 16-bit transparent D-type latch is built using advanced dual metal CMOS technology. This high-speed, low-power latch is ideal for temporary storage of data. The LVC16373A can be used for implementing memory address latches, I/O ports, and bus drivers. The Output Enable and Latch Enable controls are organized to operate each device as two 8bit latches or one 16-bit latch. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. All pins of the LVC16373A can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/ 5V supply system. The LVC16373A has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
Drive Features for LVC16373A: - High Output Drivers: 24mA - Reduced system switching noise
APPLICATIONS:
* 5V and 3.3V mixed voltage systems * Data communication and telecommunication systems
Functional Block Diagram
1O E
1
2O E
24
1LE
48
2LE
25
1D 1
47
D
2
2D 1
36
D
13
CQ
1Q 1
CQ
2Q 1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
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c 1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4624/1
IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM(2) Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND
(1)
Unit V V C mA mA mA
LVC Link
Max. - 0.5 to +6.5 - 0.5 to +6.5 - 65 to +150 - 50 to +50 - 50 100
1O E 1Q 1 1Q 2
1 2 3 4 5 6 7 8 9 10 11 SO48-1 12 SO48-2 13 SO48-3 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1LE 1D 1 1D 2
VTERM(3) TSTG IOUT IIK IOK ICC ISS
GND
1Q 3 1Q 4
GND
1D 3 1D 4
VCC
1Q 5 1Q 6
VCC
1D 5 1D 6
GND
1Q 7 1Q 8 2Q 1 2Q 2
GND
1D 7 1D 8 2D 1 2D 2
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
CAPACITANCE (TA = +25OC, f = 1.0MHz)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 6.5 6.5 Max. 6 8 8 Unit pF pF pF
LVC Link
GND
2Q 3 2Q 4
GND
2D 3 2D 4
NOTE: 1. As applicable to the device type.
VCC
2Q 5 2Q 6
VCC
2D 5 2D 6
PIN DESCRIPTION
Pin Names xDx xLE xOE xQx Description Data Inputs Latch Enable Input (Active HIGH) Output Enable Inputs (Active LOW) 3-State Outputs
GND
2Q 7 2Q 8 2O E
GND
2D 7 2D 8 2LE
FUNCTION TABLE(1)
xDx Inputs xLE H H L X xOE L L L H Outputs xQx H L Q0 Z
SSOP/ TSSOP/ TVSOP TOP VIEW
H L X X
NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance Q0 = Output level of Q before the indicated steady-state input conditions were established.
c 1998 Integrated Device Technology, Inc.
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DSC-123456
IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40OC to +85OC
Symbol VIH VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN or VO 5.5V VCC = 2.3V, IIN = - 18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC 3.6 VIN 5.5V(2) Quiescent Power Supply Current Variation One input at VCC - 0.6V other inputs at VCC or GND -- -- -- -- -- -- -- - 0.7 100 -- -- -- 50 - 1.2 -- 10 10 500 A
LVC Link
Test Conditions VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VI = 0 to 5.5V VO = 0 to 5.5V
Min. 1.7 2 -- -- -- --
Typ.(1) -- -- -- -- -- --
Max. -- -- 0.7 0.8 5 10
Unit V V A A A V mV A
NOTES: 1. Typical values are at VCC = 3.3V, +25C ambient. 2. This applies in the disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3.0V VCC = 3.0V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3.0V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2.2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55
LVC Link
Unit V
V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to +85C.
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IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 25C
Symbol CPD CPD Parameter Power Dissipation Capacitance per latch Outputs enabled Power Dissipation Capacitance per latch Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 39 6 Unit pF pF
SWITCHING CHARACTERISTICS
Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW tSK(o) Parameter Propagation Delay xDx to xQx Propagation Delay xLE to xQx Output Enable Time xOE to xQx Output Disable Time xOE to xQx Set-up Time Data before LE HIGH or LOW Hold Time Data after LE HIGH or LOW Pulse Width LE HIGH Output Skew (2)
(1) VCC = 2.7V Min. -- -- -- -- 1.7 1.2 3.3 -- Max. 4.9 5.3 5.7 6.3 -- -- -- -- VCC = 3.3V0.3V Min. 1.6 2.1 1.3 2.5 1.7 1.2 3.3 -- Max. 4.2 4.6 4.7 5.9 -- -- -- 500 Unit ns ns ns ns ns ns ns ps
NOTES: 1. See test circuits and waveforms. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction.
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IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V 0.3V 6 2.7 1.5 300 300 50 VCC(1) = 2.7V 6 2.7 1.5 300 300 50 VCC(2)= 2.5V 0.2V Unit 2 x Vcc V Vcc VCC / 2 150 150 30 V V mV mV pF
LVC Link
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
LVC Link
TEST CIRCUITS FOR ALL OUTPUTS
VCC 500 Pulse Generator
(1, 2)
VLOAD Open GND
ENABLE AND DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT SW ITCH NORMALLY CLOSED LOW tPZH OUTPUT SW ITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VOL+VLZ VOL VOH VOH-VHZ 0V
LVC Link
VIN D.U.T.
VOUT
RT
500 CL
LVC Link
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTE: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
SET-UP, HOLD, AND RELEASE TIMES
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL tREM tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
LVC Link
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other tests Switch VLOAD
tH
GND Open
LVC Link
OUTPUT SKEW - tsk (x)
INPUT tPLH1 tPHL1
tSU
tH
VIH VT 0V VOH
PULSE WIDTH
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
OUTPUT 1
tSK (x)
tSK (x)
VT VOL VOH
VT
OUTPUT 2 tPLH2 tPHL2
VT VOL
VT
LVC Link
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
LVC Link
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IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
EXTENDED COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX LVC X Bus-Hold XX Family XXXX Device Type XX Package Temp. Range
PV PA PF 373A 16 Blank 74
Shrink Sm all Outline Package (SO48-1) Thin Shrink Small Outline Package (SO48-2) Thin Very Sm all Outline Package (SO48-3) 16-Bit Transparent D-Type Latch with 3-State Outputs Double-Density with Resistors, 24mA No Bus-hold -40C to +85C
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