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MC74VHC1G66, NLVHC1G66 SPST (NO) Normally Open Analog Switch
The MC74VHC1G66, NLVHC1G66 is a single pole single throw (SPST) analog switch. It achieves high speed propagation delays and low ON resistances while maintaining low power dissipation. This bilateral switch controls analog and digital voltages that may vary across the full power-supply range (from VCC to GND). The MC74VHC1G66, NLVHC1G66 is compatible in function to a single gate of the High Speed CMOS MC74VHC4066 and the metal-gate CMOS MC14066. The device has been designed so that the ON resistances (RON) are much lower and more linear over input voltage than RON of the metal-gate CMOS or High Speed CMOS analog switches. The newer NLVHC offers the same functionality in a 1.2x1.0x0.55mm UDFN6 package. The ON/OFF control inputs are compatible with standard CMOS outputs. The ON/OFF control input structure provides protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. This input structure helps prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc.
Features http://onsemi.com MARKING DIAGRAMS
5 SC-88A DF SUFFIX CASE 419A 5 1 TSOP-5 DT SUFFIX CASE 483 V9 M G G M 1 5 V9 M G G 1
1 UDFN6 MU SUFFIX CASE 517AA
VW M G
* * * * * * * *
High Speed: tPD = 20 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 1.0 mA (Max) at TA = 25C Diode Protection Provided on Inputs and Outputs Improved Linearity and Lower ON Resistance over Input Voltage Chip Complexity: 11 FETs or 3 Equivalent Gates ON/OFF Control Input has OVT Chip Complexity: FETs = 11 Pb-Free Packages are Available
V9, V = Device Code M = Date Code* W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location.
PIN ASSIGNMENT
1 2 3 4 5 IN/OUT XA OUT/IN YA GND ON/OFF CONTROL VCC
FUNCTION TABLE
On/Off Control Input L H State of Analog Switch Off On
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2007
1
February, 2007 - Rev. 13
Publication Order Number: MC74VHC1G66/D
MC74VHC1G66, NLVHC1G66
IN/OUT XA
1
5
VCC
IN/OUT XA
1
6
VCC
OUT/IN YA
2
OUT/IN YA
2
5
NC
GND
3
4
ON/OFF CONTROL
GND
3
4
ON/OFF CONTROL
(SC-88A, TSOP-5)
(UDFN6)
Figure 1. Pinout Diagrams
ON/OFF CONTROL IN/OUT XA U
X1 1 1 U OUT/IN YA
Figure 2. Logic Symbol
MAXIMUM RATINGS
Symbol VCC VIN VIS IIK ICC TSTG TL TJ qJA PD MSL FR VESD DC Supply Voltage Digital Input Voltage Analog Output Voltage Digital Input Diode Current DC Supply Current, VCC and GND Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature Under Bias Thermal Resistance Power Dissipation in Still Air at 85C Moisture Sensitivity Flammability Rating ESD Withstand Voltage Oxygen Index: 28 to 34 Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Above VCC and Below GND at 125C (Note 5) SC70-5 (Note 1) SOT23-5 SC70-5 SOT23-5 Characteristics Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC +0.5 -20 +25 *65 to )150 260 )150 350 230 150 200 Level 1 UL 94 V-0 @ 0.125 in u2000 u200 N/A $500 V Unit V V V mA mA C C C C/W mW
ILATCHUP
Latchup Performance
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Measured with minimum pad spacing on an FR4 board, using 10 mm-by-1 inch, 2-ounce copper trace with no air flow. 2. Tested to EIA/JESD22-A114-A. 3. Tested to EIA/JESD22-A115-A. 4. Tested to JESD22-C101-A. 5. Tested to EIA/JESD78.
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MC74VHC1G66, NLVHC1G66
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN VIS TA tr, tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature Range Input Rise and Fall Time ON/OFF Control Input VCC = 3.3 V 0.3 V VCC = 5.0 V 0.5 V Characteristics Min 2.0 GND GND -55 0 0 Max 5.5 5.5 VCC +125 100 20 Unit V V V C ns/V
NORMALIZED FAILURE RATE
Device Junction Temperature versus Time to 0.1% Bond Failures
Junction Temperature C 80 90 100 110 120 130 140 Time, Hours 1,032,200 419,300 178,700 79,600 37,000 17,800 8,900 Time, Years 117.8 47.9 20.4 9.4 4.2 2.0 1.0
FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 130 C TJ =120 C TJ =110 C TJ =100 C TJ = 90 C TJ = 80 C 100
1 1 10 TIME, YEARS 1000
Figure 3. Failure Rate vs. Time Junction Temperature
DC ELECTRICAL CHARACTERISTICS
VCC (V) 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5 0 to 5.5 5.5 3.0 4.5 5.5 5.5 TA = 25C Min 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 0.1 Max TA 85C Min 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 1.0 Max -55 TA 125C Min 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 1.0 Max Unit V
Symbol VIH
Parameter Minimum High-Level Input Voltage ON/OFF Control Input Maximum Low-Level Input Voltage ON/OFF Control Input Maximum Input Leakage Current ON/OFF Control Input Maximum Quiescent Supply Current Maximum "ON" Resistance Maximum Off-Channel Leakage Current
Test Conditions RON = Per Spec
VIL
RON = Per Spec
V
IIN
VIN = VCC or GND
mA
ICC RON
VIN = VCC or GND VIO = 0 V VIN = VIH VIS = VCC or GND |IIS| 5 mA (Figure 4) VIN = VIL VIS = VCC or GND Switch Off (Figure 5)
1.0 60 45 40 0.1
20 70 50 45 0.5
40 100 60 55 1.0
mA W
IOFF
mA
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MC74VHC1G66, NLVHC1G66
I I II I I I IIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIII I I II I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II I I I II I I I I II I I I I I II II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I II IIIIIIIIIIIIIIII II I I II I I IIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II I I II IIIIIIIIIII I II I I II I I II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I II I I II I I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II I I I I IIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIII II I I II I I II I I II I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II I I II I IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIIIIIIII I I I II I I I I I I II I I II II III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS Cload = 50 pF, Input tr/tf = 3.0 ns
VCC (V) 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5 0.0 5.0 TA = 25C Typ 1 0.6 0.6 0.6 32 28 24 20 32 28 24 20 3 4 4 TA 85CIIIIII -55 TA 125CII Max 6 3 1 1 Min Max 7 4 2 1 Unit ns Symbol tPLH, tPHL Parameter Test Conditions Min Max 5 2 1 1 Min Maximum Propagation Delay, Input X to Y YA = Open (Figure 14) tPLZ, tPHZ Maximum Propagation Delay, ON/OFF Control to Analog Output Maximum Propagation Delay, ON/OFF Control to Analog Output Maximum Input Capacitance RL = 1000 W (Figure 15) 40 35 30 25 40 35 30 25 10 10 10 45 40 35 30 45 40 35 30 10 10 10 50 45 40 35 50 45 40 35 10 10 10 ns tPZL, tPZH RL = 1000 W (Figure 15) ns CIN ON/OFF Control Input Control Input = GND Analog I/O Feedthrough pF Typical @ 25C, VCC = 5.0 V 18 CPD Power Dissipation Capacitance (Note 6) pF 6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I IIII I I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I III III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I III III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Symbol BW Parameter Test Conditions VCC 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 Limit 25C 150 175 180 Unit Maximum On-Channel Bandwidth or Minimum Frequency Response (Figure 10) Off-Channel Feedthrough Isolation (Figure 11) fin = 1 MHz Sine Wave Adjust fin voltage to obtain 0 dBm at VOS Increase fin = frequency until dB meter reads -3 dB RL = 50 W fin = Sine Wave Adjust fin voltage to obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W MHz ISOoff -80 -80 -80 45 60 130 dB NOISEfeed Feedthrough Noise Control to Switch (Figure 12) Total Harmonic Distortion (Figure 13) Vin 1 MHz Square Wave (tr = tf = 2 ns) RL = 600 W mVPP THD fin = 1 kHz, RL = 10 kW THD = THDMeasured - THDSource VIS = 3.0 VPP sine wave VIS = 5.0 VPP sine wave % 3.3 5.5 0.30 0.15
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MC74VHC1G66, NLVHC1G66
PLOTTER POWER SUPPLY - + VCC 1 2 VCC 3 4 A 3 4 5 VCC 1 2 5 VIL VCC DC PARAMETER ANALYZER
COMPUTER
Figure 4. On Resistance Test Set-Up
Figure 5. Maximum Off-Channel Leakage Current Test Set-Up
VCC A N/C 1 2 3 4 5
VCC 1 VIH TEST POINT 2 3 4 5
VCC
VCC
Figure 6. Maximum On-Channel Leakage Current Test Set-Up
Figure 7. Propagation Delay Test Set-Up
Switch to Position 2 when testing tPLZ and tPZL Switch to Position 1 when testing tPHZ and tPZH TEST POINT VCC 1 1 2 VCC 1 2 *Includes all probe and jig capacitance. RL 2 C L* 3 4 N/C 2 3 4 5 VCC N/C 1 5 VCC A
Figure 8. Propagation Delay Output Enable/Disable Test Set-Up
Figure 9. Power Dissipation Capacitance Test Set-Up
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MC74VHC1G66, NLVHC1G66
VOS 0.1 mF fin 1 2 dB Meter 3 4 dB Meter RL 5 VCC fin 0.1 mF 1 2 3 4 5 VIS VOS VCC
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 10. Maximum On-Channel Bandwidth Test Set-Up
Figure 11. Off-Channel Feedthrough Isolation Test Set-Up
(VCC)/2
RL RL VOS IS 1 2 3 4 5
VCC v 1 MHz
V
t r + t + 2 ns
IN
f
VCC GND
*Includes all probe and jig capacitance.
Figure 12. Feedthrough Noise, ON/OFF Control to Analog Out, Test Set-Up
To Distortion Meter (VCC)/2 0.1 mF RL VOS fin 1 2 3 4 5 VIS VCC
*Includes all probe and jig capacitance.
Figure 13. Total Harmonic Distortion Test Set-Up
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MC74VHC1G66, NLVHC1G66
XA
VCC 50% tPLH 50% VCC tPHL VOH
YA
50% VCC
VOL
Figure 14. Propagation Delay, Analog In to Analog Out Waveforms
tr Control 90% 10% tPZL 50% VCC Analog Out 50% VCC tPZH
tf VCC
50% VCC tPLZ
High Impedance 10% 90% tPHZ VOL VOH High Impedance
Figure 15. Propagation Delay, ON/OFF Control
ORDERING INFORMATION
Device MC74VHC1G66DFT1 MC74VHC1G66DFT1G MC74VHC1G66DFT2 MC74VHC1G66DFT2G MC74VHC1G66DTT1 MC74VHC1G66DTT1G NLVHC1G66MUR2G Package SC-88A SC-88A (Pb-Free) SC-88A SC-88A (Pb-Free) TSOP-5 TSOP-5 (Pb-Free) UDFN6 (Pb-Free) 3000 / Tape & Reel Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
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MC74VHC1G66, NLVHC1G66
PACKAGE DIMENSIONS
SC-88A, SOT-353, SC-70 CASE 419A-02 ISSUE J
A G
5
4
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419A-01 OBSOLETE. NEW STANDARD 419A-02. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS.
S
1 2 3
-B-
DIM A B C D G H J K N S
D 5 PL
0.2 (0.008)
M
B
M
N J C
INCHES MIN MAX 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 BSC --- 0.004 0.004 0.010 0.004 0.012 0.008 REF 0.079 0.087
MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC --- 0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20
H
K
SOLDERING FOOTPRINT*
0.50 0.0197
0.65 0.025 0.65 0.025 0.40 0.0157
1.9 0.0748
SCALE 20:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74VHC1G66, NLVHC1G66
PACKAGE DIMENSIONS
TSOP-5, SOT23-5 CASE 483-02 ISSUE F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY. DIM A B C D G H J K L M S MILLIMETERS MIN MAX 3.00 BSC 1.50 BSC 0.90 1.10 0.25 0.50 0.95 BSC 0.01 0.10 0.10 0.26 0.20 0.60 1.25 1.55 0_ 10 _ 2.50 3.00
NOTE 5 2X
D 5X 0.20 C A B
5 1 2 4 3
0.10 T 0.20 T L G A
M B S K
DETAIL Z
2X
DETAIL Z
J C 0.05 H T
SEATING PLANE
SOLDERING FOOTPRINT*
1.9 0.074
0.95 0.037
2.4 0.094 1.0 0.039 0.7 0.028
SCALE 10:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74VHC1G66, NLVHC1G66
PACKAGE DIMENSIONS
UDFN6, 1.2x1.0, 0.4P CASE 517AA-01 ISSUE A
D A B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.127 REF 0.15 0.25 1.00 BSC 1.20 BSC 0.40 BSC 0.30 0.40 0.40 0.50
PIN ONE REFERENCE 2X
0.10 C
2X
0.10 C 0.10 C
10X
0.08 C
L2
6X
b 0.10 C A B 0.05 C
NOTE 3 6 4
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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EE EE EE
1
E
TOP VIEW
(A3) A SIDE VIEW A1
5X 3 SEATING PLANE
DIM A A1 A3 b D E e L L2
C L
MOUNTING FOOTPRINT*
6X
0.42
6X
0.22
e BOTTOM VIEW 0.40 PITCH 1.07
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74VHC1G66/D

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