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| User's Manual V850E/IA1 32-Bit Single-Chip Microcontrollers Hardware PD703116 PD703116(A) PD703116(A1) PD70F3116 PD70F3116(A) PD70F3116(A1) Document No. U14492EJ5V0UD00 (5th edition) Date Published August 2005 N CP(K) 1999, 2002 Printed in Japan [MEMO] 2 User's Manual U14492EJ5V0UD NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. User's Manual U14492EJ5V0UD 3 These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. * The information in this document is current as of March, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 4 User's Manual U14492EJ5V0UD Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 NEC Electronics (Europe) GmbH Duesseldorf, Germany Tel: 0211-65030 * Sucursal en Espana NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 Madrid, Spain Tel: 091-504 27 87 * Succursale Francaise Velizy-Villacoublay, France Tel: 01-30-67 58 00 * Filiale Italiana NEC Electronics Shanghai Ltd. Shanghai, P.R. China Tel: 021-5888-5400 Milano, Italy Tel: 02-66 75 41 * Branch The Netherlands NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Eindhoven, The Netherlands Tel: 040-265 40 10 * Tyskland Filial NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 Taeby, Sweden Tel: 08-63 87 200 * United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 J05.6 User's Manual U14492EJ5V0UD 5 INTRODUCTION Readers This manual is intended for users who wish to understand the functions of the V850E/IA1 and design application systems using it. The target products are as follows. * Standard products: PD703116, 70F3116 * Special products: PD703116(A), 703116(A1), 70F3116(A), 70F3116(A1) Purpose This manual introduces the hardware functions of the V850E/IA1 shown below for user's understanding. Organization This manual is divided into two parts: (V850E1 Architecture User's Manual). Hardware (this manual) and Architecture Hardware * Pin functions * CPU function * Internal peripheral functions * Flash memory programming * Electrical specifications How to Read This Manual Architecture * Data type * Register set * Instruction format and instruction set * Interrupt and exception * Pipeline operation It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. Cautions 1. The application examples in this manual apply to "standard" quality grade products for general electronic systems. "special" quality grade product, thoroughly When the using an example in this manual for an application that requires a evaluate component and circuit to be actually used to see if they satisfy the special quality grade. 2. When using this manual as a manual for a special grade product, read the part numbers as follows. PD703116 703116(A), 703116(A1) PD70F3116 70F3116(A), 70F3116(A1) * To find the details of a register where the name is known Refer to APPENDIX B REGISTER INDEX. * To understand the details of an instruction function Refer to the V850E1 Architecture User's Manual. * To know details of the electrical specifications of the V850E/IA1 Refer to CHAPTER 18 ELECTRICAL SPECIFICATIONS. 6 User's Manual U14492EJ5V0UD * To understand the overall functions of the V850E/IA1 Read this manual according to the CONTENTS. * How to read register formats The name of a bit whose number is in angle brackets (<>) is defined as a reserved word in the device file. When the register format of each register describes 0 or 1, other values are prohibited to be specified. The mark Conventions shows major revised points. Higher digits on the left and lower digits on the right xxx (overscore over pin or signal name) Higher address on the top and lower address on the bottom Note: Caution: Remark: Numeric representation: Footnote for item marked with Note in the text Information requiring particular attention Supplementary information Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Prefix indicating power of 2 (address space, memory capacity): K (kilo): 210 = 1,024 M (mega): 220 = 1,0242 G (giga): 230 = 1,0243 Data type: Word ... 32 bits Halfword ... 16 bits Byte ... 8 bits Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850E/IA1 Document Name V850E1 Architecture User's Manual V850E/IA1 Hardware User's Manual V850E/IA1, V850E/IA2 AC Motor Inverter Control Using Vector Operation Application Note Inverter Control by V850 Series 120 Excitation Method Control by ZeroCross Detection Application Note Inverter Control by V850 Series Vector Control by Encoder Application Note Inverter Control by V850 Series Vector Control by Hole Sensor Application Note V850 Series Flash Memory Self-Programming User's Manual U15673E U17338E U17324E U17209E Document No. U14559E This manual U14868E Data significance: Active low representation: Memory map address: User's Manual U14492EJ5V0UD 7 Documents related to development tools (User's Manuals) Document Name IE-V850E-MC, IE-V850E-MC-A (In-circuit emulator) IE-703116-MC-EM1 (In-circuit emulator option board) CA850 (Ver. 3.00) (C compiler package) Operation C Language Assembly Language Link Directives PM+ (Ver. 6.00) (Project manager) ID850 (Ver. 3.00) (Integrated debugger) Operation Document No. U14487E U14700E U17293E U17291E U17292E U17294E U17178E U17358E U17241E U16218E U14873E TW850 (Ver. 2.00) (Performance analysis tuning tool) SM850 (Ver. 2.50) (System simulator) SM850 (Ver. 2.00 or later) (System simulator) SM+ (System simulator) Operation External Part User Open Interface Specification Operation User Open Interface RX850 (Ver. 3.13 or later) (Real-time OS) Basics Installation Technical RX850 Pro (Ver. 3.15) (Real-time OS) Basics Installation Technical RD850 (Ver. 3.01) (Task debugger) RD850 Pro (Ver. 3.01) (Task debugger) AZ850 (Ver. 3.10) (System performance analyzer) PG-FP4 Flash memory programmer U17246E U17247E U13430E U13410E U13431E U13773E U13774E U13772E U13737E U13916E U14410E U15260E 8 User's Manual U14492EJ5V0UD CONTENTS CHAPTER 1 INTRODUCTION .................................................................................................................18 1.1 Outline........................................................................................................................................ 18 1.2 Features ..................................................................................................................................... 21 1.3 Applications............................................................................................................................... 23 1.4 Ordering Information ................................................................................................................ 23 1.5 Pin Configuration (Top View)................................................................................................... 24 1.6 Configuration of Function Block............................................................................................. 26 1.6.1 1.6.2 Internal block diagram ..................................................................................................................26 Internal units.................................................................................................................................27 1.7 Differences Between Products ................................................................................................ 29 CHAPTER 2 PIN FUNCTIONS ................................................................................................................30 2.1 List of Pin Functions ................................................................................................................ 30 2.2 Pin Status................................................................................................................................... 36 2.3 Description of Pin Functions ................................................................................................... 37 2.4 Types of Pin I/O Circuit and Connection of Unused Pins..................................................... 45 2.5 Pin I/O Circuits .......................................................................................................................... 47 CHAPTER 3 CPU FUNCTION.................................................................................................................48 3.1 Features ..................................................................................................................................... 48 3.2 CPU Register Set ...................................................................................................................... 49 3.2.1 3.2.2 Program register set.....................................................................................................................50 System register set.......................................................................................................................51 Operation modes..........................................................................................................................57 Operation mode specification .......................................................................................................58 CPU address space .....................................................................................................................59 Image ...........................................................................................................................................60 Wrap-around of CPU address space............................................................................................61 Memory map ................................................................................................................................62 Area..............................................................................................................................................63 External memory expansion .........................................................................................................67 Recommended use of address space ..........................................................................................68 On-chip peripheral I/O registers ...................................................................................................70 Programmable peripheral I/O registers ........................................................................................81 Specific registers ..........................................................................................................................98 System wait control register (VSWC) ...........................................................................................98 Cautions .......................................................................................................................................98 3.3 Operation Modes....................................................................................................................... 57 3.3.1 3.3.2 3.4 Address Space .......................................................................................................................... 59 3.4.1 3.4.2 3.4.3 3.4.4 3.4.5 3.4.6 3.4.7 3.4.8 3.4.9 3.4.10 3.4.11 3.4.12 CHAPTER 4 BUS CONTROL FUNCTION...........................................................................................100 4.1 Features ................................................................................................................................... 100 4.2 Bus Control Pins..................................................................................................................... 100 4.2.1 Pin status during internal ROM, internal RAM, and on-chip peripheral I/O access.....................100 4.3 Memory Block Function ......................................................................................................... 101 User's Manual U14492EJ5V0UD 9 4.3.1 Chip select control function ....................................................................................................... 102 4.4 4.5 Bus Cycle Type Control Function ......................................................................................... 105 Bus Access .............................................................................................................................. 106 4.5.1 4.5.2 4.5.3 4.5.4 Number of access clocks........................................................................................................... 106 Bus sizing function..................................................................................................................... 107 Word data processing format..................................................................................................... 107 Bus width ................................................................................................................................... 108 Programmable wait function ...................................................................................................... 114 External wait function ................................................................................................................ 116 Relationship between programmable wait and external wait ..................................................... 116 4.6 Wait Function........................................................................................................................... 114 4.6.1 4.6.2 4.6.3 4.7 4.8 Idle State Insertion Function.................................................................................................. 117 Bus Hold Function .................................................................................................................. 118 4.8.1 4.8.2 4.8.3 4.8.4 Function outline ......................................................................................................................... 118 Bus hold procedure ................................................................................................................... 118 Operation in power save mode.................................................................................................. 119 Bus hold timing .......................................................................................................................... 119 4.9 Bus Priority Order ................................................................................................................... 120 4.10 Boundary Operation Conditions............................................................................................ 120 4.10.1 4.10.2 Program space .......................................................................................................................... 120 Data space ................................................................................................................................ 120 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION .................................................................121 5.1 SRAM, External ROM, External I/O Interface........................................................................ 121 5.1.1 5.1.2 Features .................................................................................................................................... 121 SRAM, external ROM, external I/O access ............................................................................... 122 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) ....................................................................127 6.1 Features ................................................................................................................................... 127 6.2 Configuration........................................................................................................................... 128 6.3 Control Registers .................................................................................................................... 129 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 DMA source address registers 0 to 3 (DSA0 to DSA3) ............................................................. 129 DMA destination address registers 0 to 3 (DDA0 to DDA3) ...................................................... 131 DMA transfer count registers 0 to 3 (DBC0 to DBC3)................................................................ 133 DMA addressing control registers 0 to 3 (DADC0 to DADC3) ................................................... 134 DMA channel control registers 0 to 3 (DCHC0 to DCHC3)........................................................ 136 DMA disable status register (DDIS)........................................................................................... 138 DMA restart register (DRST) ..................................................................................................... 138 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) ............................................................. 139 Single transfer mode ................................................................................................................. 142 Single-step transfer mode ......................................................................................................... 144 Block transfer mode................................................................................................................... 145 Two-cycle transfer ..................................................................................................................... 145 Transfer type and transfer target ............................................................................................... 146 External bus cycles during DMA transfer (two-cycle transfer) ................................................... 147 User's Manual U14492EJ5V0UD 6.4 Transfer Mode.......................................................................................................................... 142 6.4.1 6.4.2 6.4.3 6.5 6.6 Transfer Types......................................................................................................................... 145 6.5.1 6.6.1 6.6.2 Transfer Target ........................................................................................................................ 146 10 6.7 6.8 6.9 6.10 6.11 6.12 DMA Channel Priorities .......................................................................................................... 147 Next Address Setting Function ............................................................................................. 147 DMA Transfer Start Factors ................................................................................................... 149 Forcible Interruption............................................................................................................... 150 DMA Transfer End................................................................................................................... 150 Forcible Termination .............................................................................................................. 151 6.12.1 Restriction related to DMA transfer forcible termination .............................................................152 6.13 Times Related to DMA Transfer............................................................................................. 153 6.14 Precautions.............................................................................................................................. 154 6.14.1 Interrupt factors .........................................................................................................................155 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION..................................................156 7.1 Features ................................................................................................................................... 156 7.2 Non-Maskable Interrupt.......................................................................................................... 160 7.2.1 7.2.2 7.2.3 7.2.4 Operation ...................................................................................................................................161 Restore.......................................................................................................................................163 Non-maskable interrupt status flag (NP) ....................................................................................164 Edge detection function..............................................................................................................164 Operation ...................................................................................................................................165 Restore.......................................................................................................................................167 Priorities of maskable interrupts .................................................................................................168 Interrupt control register (xxICn).................................................................................................172 Interrupt mask registers 0 to 3 (IMR0 to IMR3) ..........................................................................175 In-service priority register (ISPR) ...............................................................................................176 Maskable interrupt status flag (ID)..............................................................................................177 Interrupt trigger mode selection..................................................................................................177 Operation ...................................................................................................................................186 Restore.......................................................................................................................................187 Exception status flag (EP) ..........................................................................................................188 Illegal opcode definition..............................................................................................................189 Debug trap .................................................................................................................................191 7.3 Maskable Interrupts ................................................................................................................ 165 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.4 Software Exception................................................................................................................. 186 7.4.1 7.4.2 7.4.3 7.5 Exception Trap ........................................................................................................................ 189 7.5.1 7.5.2 7.6 7.7 7.8 Multiple Interrupt Servicing Control ..................................................................................... 193 Interrupt Response Time........................................................................................................ 194 Periods in Which CPU Does Not Acknowledge Interrupts ................................................. 196 CHAPTER 8 CLOCK GENERATION FUNCTION ...............................................................................197 8.1 Features ................................................................................................................................... 197 8.2 Configuration .......................................................................................................................... 197 8.3 Input Clock Selection ............................................................................................................. 198 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 Direct mode ................................................................................................................................198 PLL mode...................................................................................................................................198 Peripheral command register (PHCMD).....................................................................................199 Clock control register (CKC).......................................................................................................200 Peripheral status register (PHS).................................................................................................202 8.4 PLL Lockup.............................................................................................................................. 203 User's Manual U14492EJ5V0UD 11 8.5 Power Save Control ................................................................................................................ 204 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 Overview ................................................................................................................................... 204 Control registers ........................................................................................................................ 207 HALT mode ............................................................................................................................... 210 IDLE mode................................................................................................................................. 212 Software STOP mode................................................................................................................ 214 Oscillation stabilization time security specification..................................................................... 216 Time base counter (TBC) .......................................................................................................... 217 8.6 Securing Oscillation Stabilization Time................................................................................ 216 8.6.1 8.6.2 CHAPTER 9 TIMER/COUNTER FUNCTION ........................................................................................218 9.1 Timer 0...................................................................................................................................... 218 9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 Features (timer 0) ...................................................................................................................... 218 Function overview (timer 0) ....................................................................................................... 219 Basic configuration .................................................................................................................... 220 Control registers ........................................................................................................................ 226 Operation................................................................................................................................... 250 Operation timing ........................................................................................................................ 284 Features (timer 1) ...................................................................................................................... 293 Function overview (timer 1) ....................................................................................................... 293 Basic configuration .................................................................................................................... 295 Control registers ........................................................................................................................ 299 Operation................................................................................................................................... 313 Supplementary description of internal operation........................................................................ 323 Features (timer 2) ...................................................................................................................... 326 Function overview (timer 2) ....................................................................................................... 326 Basic configuration .................................................................................................................... 328 Control registers ........................................................................................................................ 335 Operation................................................................................................................................... 352 PWM output operation when timer 2 operates in compare mode .............................................. 370 Features (timer 3) ...................................................................................................................... 373 Function overview (timer 3) ....................................................................................................... 373 Basic configuration .................................................................................................................... 374 Control registers ........................................................................................................................ 379 Operation................................................................................................................................... 385 Application examples................................................................................................................. 392 Precautions................................................................................................................................ 398 Features (timer 4) ...................................................................................................................... 399 Function overview (timer 4) ....................................................................................................... 399 Basic configuration .................................................................................................................... 400 Control register .......................................................................................................................... 404 Operation................................................................................................................................... 405 Application example .................................................................................................................. 407 Precautions................................................................................................................................ 407 User's Manual U14492EJ5V0UD 9.2 Timer 1...................................................................................................................................... 293 9.2.1 9.2.2 9.2.3 9.2.4 9.2.5 9.2.6 9.3 Timer 2...................................................................................................................................... 326 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.4 Timer 3...................................................................................................................................... 373 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.4.7 9.5 Timer 4...................................................................................................................................... 399 9.5.1 9.5.2 9.5.3 9.5.4 9.5.5 9.5.6 9.5.7 12 9.6 Timer Connection Function ................................................................................................... 408 9.6.1 9.6.2 Overview ....................................................................................................................................408 Control register...........................................................................................................................409 CHAPTER 10 SERIAL INTERFACE FUNCTION ................................................................................410 10.1 Features ................................................................................................................................... 410 10.2 Asynchronous Serial Interface 0 (UART0) ........................................................................... 411 10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.2.6 10.2.7 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 10.3.7 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.4.6 Features .....................................................................................................................................411 Configuration ..............................................................................................................................412 Control registers .........................................................................................................................414 Interrupt requests .......................................................................................................................421 Operation ...................................................................................................................................422 Dedicated baud rate generator 0 (BRG0)...................................................................................434 Precautions ................................................................................................................................441 Features .....................................................................................................................................442 Configuration ..............................................................................................................................443 Control registers .........................................................................................................................445 Interrupt requests .......................................................................................................................454 Operation ...................................................................................................................................455 Synchronous mode ....................................................................................................................464 Dedicated baud rate generators 1, 2 (BRG1, BRG2) .................................................................469 Features .....................................................................................................................................477 Configuration ..............................................................................................................................477 Control registers .........................................................................................................................479 Operation ...................................................................................................................................493 Output pins .................................................................................................................................508 Dedicated baud rate generator 3 (BRG3)...................................................................................509 10.3 Asynchronous Serial Interfaces 1, 2 (UART1, UART2) ....................................................... 442 10.4 Clocked Serial Interfaces 0, 1 (CSI0, CSI1)........................................................................... 477 CHAPTER 11 FCAN CONTROLLER....................................................................................................513 11.1 Function Overview.................................................................................................................. 513 11.2 Configuration .......................................................................................................................... 514 11.3 Configuration of Messages and Buffers............................................................................... 516 11.4 Time Stamp Function ............................................................................................................. 517 11.5 Message Processing .............................................................................................................. 520 11.5.1 11.5.2 Message transmission................................................................................................................520 Message reception .....................................................................................................................522 11.6 Mask Function ......................................................................................................................... 523 11.7 Protocol.................................................................................................................................... 525 11.7.1 11.7.2 11.8.1 11.8.2 11.8.3 11.8.4 11.8.5 Protocol mode function...............................................................................................................525 Message formats........................................................................................................................526 Determination of bus priority ......................................................................................................535 Bit stuffing ..................................................................................................................................535 Multi-master ...............................................................................................................................535 Multi-cast ....................................................................................................................................535 CAN sleep mode/CAN stop mode function ................................................................................536 User's Manual U14492EJ5V0UD 11.8 Functions ................................................................................................................................. 535 13 11.8.6 11.8.7 Error control function ................................................................................................................. 536 Baud rate control function.......................................................................................................... 539 11.9 Cautions on Bit Set/Clear Function....................................................................................... 542 11.10 Control Registers .................................................................................................................... 544 11.11 Operations ............................................................................................................................... 596 11.11.1 Initialization processing ............................................................................................................. 596 11.11.2 Transmit setting ......................................................................................................................... 609 11.11.3 Receive setting .......................................................................................................................... 610 11.11.4 CAN sleep mode ....................................................................................................................... 612 11.11.5 CAN stop mode ......................................................................................................................... 613 11.12 Rules for Correct Setting of Baud Rate ................................................................................ 615 11.13 Ensuring Data Consistency ................................................................................................... 619 11.13.1 Sequential data read ................................................................................................................. 619 11.13.2 Burst read mode ........................................................................................................................ 620 11.14 Interrupt Conditions................................................................................................................ 621 11.14.1 Interrupts that are generated for FCAN controller...................................................................... 621 11.14.2 Interrupts that are generated for global CAN interface .............................................................. 621 11.15 How to Shut Down FCAN Controller ..................................................................................... 622 11.16 Cautions on Use ...................................................................................................................... 623 CHAPTER 12 NBD FUNCTION (PD70F3116) ...................................................................................625 12.1 Overview .................................................................................................................................. 625 12.2 NBD Function Register Map................................................................................................... 626 12.3 NBD Function Protocol........................................................................................................... 627 12.4 NBD Function .......................................................................................................................... 630 12.4.1 12.4.2 12.4.3 RAM monitoring, accessing NBD space.................................................................................... 630 Event detection function ............................................................................................................ 632 Chip ID registers (TID0 to TID2) ................................................................................................ 633 12.5 Control Registers .................................................................................................................... 634 12.6 Restrictions on NBD ............................................................................................................... 637 12.6.1 12.6.2 12.6.3 12.6.4 General restrictions ................................................................................................................... 637 Restrictions related to read or write of RAM by NBD................................................................. 637 Restrictions related to NBD event trigger function ..................................................................... 637 How to detect termination of DMA initialization via NBD tool..................................................... 637 12.7 Initialization Required for DMA (2 Channels) ....................................................................... 638 CHAPTER 13 A/D CONVERTER ..........................................................................................................642 13.1 Features ................................................................................................................................... 642 13.2 Configuration........................................................................................................................... 642 13.3 Control Registers .................................................................................................................... 646 13.4 Interrupt Requests .................................................................................................................. 655 13.5 A/D Converter Operation ........................................................................................................ 656 13.5.1 13.5.2 13.6.1 13.6.2 A/D converter basic operation ................................................................................................... 656 Operation modes and trigger modes ......................................................................................... 657 Operation in select mode........................................................................................................... 660 Operation in scan mode ............................................................................................................ 661 13.6 Operation in A/D Trigger Mode .............................................................................................. 660 13.7 Operation in A/D Trigger Polling Mode ................................................................................. 662 14 User's Manual U14492EJ5V0UD 13.7.1 13.7.2 13.8.1 13.8.2 13.9.1 13.9.2 Operation in select mode ...........................................................................................................662 Operation in scan mode .............................................................................................................663 Operation in select mode ...........................................................................................................664 Operation in scan mode .............................................................................................................665 Operation in select mode ...........................................................................................................666 Operation in scan mode .............................................................................................................667 13.8 Operation in Timer Trigger Mode .......................................................................................... 664 13.9 Operation in External Trigger Mode...................................................................................... 666 13.10 Precautions on Operation ...................................................................................................... 668 13.10.1 Stopping A/D conversion operation ............................................................................................668 13.10.2 Trigger input during A/D conversion operation ...........................................................................668 13.10.3 External or timer trigger interval .................................................................................................668 13.10.4 Operation in standby modes ......................................................................................................668 13.10.5 Compare match interrupt in timer trigger mode ..........................................................................669 13.10.6 Timing that makes the A/D conversion result undefined ............................................................669 13.11 How to Read A/D Converter Characteristics Table ............................................................. 670 CHAPTER 14 PORT FUNCTIONS........................................................................................................674 14.1 Features ................................................................................................................................... 674 14.2 Basic Configuration of Ports ................................................................................................. 674 14.3 Pin Functions of Each Port .................................................................................................... 689 14.3.1 14.3.2 14.3.3 14.3.4 14.3.5 14.3.6 14.3.7 14.3.8 14.3.9 Port 0..........................................................................................................................................689 Port 1..........................................................................................................................................690 Port 2..........................................................................................................................................693 Port 3..........................................................................................................................................696 Port 4..........................................................................................................................................698 Port DH ......................................................................................................................................700 Port DL .......................................................................................................................................702 Port CS.......................................................................................................................................704 Port CT.......................................................................................................................................706 14.3.10 Port CM ......................................................................................................................................708 14.4 Operation of Port Function .................................................................................................... 710 14.4.1 14.4.2 14.4.3 14.5.1 14.5.2 14.5.3 Writing to I/O port .......................................................................................................................710 Reading from I/O port.................................................................................................................710 Output status of alternate function in control mode ....................................................................710 Interrupt pins ..............................................................................................................................711 Timer 10, timer 11, timer 3 input pins .........................................................................................712 Timer 2 input pins.......................................................................................................................716 14.5 Noise Eliminator...................................................................................................................... 711 CHAPTER 15 RESET FUNCTION ........................................................................................................719 15.1 Features ................................................................................................................................... 719 15.2 Pin Functions .......................................................................................................................... 719 15.3 Initialization ............................................................................................................................. 721 CHAPTER 16 FLASH MEMORY (PD70F3116).................................................................................727 16.1 Features ................................................................................................................................... 727 16.2 Writing by Flash Programmer................................................................................................ 727 User's Manual U14492EJ5V0UD 15 16.3 Programming Environment.................................................................................................... 729 16.4 Communication Mode............................................................................................................. 729 16.5 Pin Connection ........................................................................................................................ 731 16.5.1 16.5.2 16.5.3 16.5.4 16.5.5 16.5.6 16.5.7 16.5.8 16.6.1 16.6.2 16.6.3 16.6.4 16.7.1 16.7.2 16.7.3 16.7.4 16.7.5 16.7.6 16.7.7 16.7.8 16.7.9 VPP pin ....................................................................................................................................... 731 Serial interface pin..................................................................................................................... 731 RESET pin................................................................................................................................. 733 NMI pin ...................................................................................................................................... 733 MODE0 to MODE2 pins ............................................................................................................ 733 Port pins .................................................................................................................................... 733 Other signal pins........................................................................................................................ 733 Power supply ............................................................................................................................. 734 Flash memory control ................................................................................................................ 734 Flash memory programming mode............................................................................................ 735 Selection of communication mode............................................................................................. 735 Communication commands ....................................................................................................... 736 Outline of self-programming ...................................................................................................... 737 Self-programming function ........................................................................................................ 738 Outline of self-programming interface........................................................................................ 738 Hardware environment .............................................................................................................. 739 Software environment................................................................................................................ 741 Self-programming function number ........................................................................................... 742 Calling parameters .................................................................................................................... 743 Contents of RAM parameters .................................................................................................... 744 Errors during self-programming ................................................................................................. 745 16.6 Programming Method ............................................................................................................. 734 16.7 Flash Memory Programming by Self-Programming ............................................................ 737 16.7.10 Flash information ....................................................................................................................... 745 16.7.11 Area number.............................................................................................................................. 746 16.7.12 Flash programming mode control register (FLPMC).................................................................. 747 16.7.13 Calling device internal processing ............................................................................................. 749 16.7.14 Erasing flash memory flow ........................................................................................................ 752 16.7.15 Continuous writing flow.............................................................................................................. 753 16.7.16 Internal verify flow...................................................................................................................... 754 16.7.17 Acquiring flash information flow ................................................................................................. 755 16.7.18 Self-programming library ........................................................................................................... 756 16.8 How to Distinguish Flash Memory and Mask ROM Versions ............................................. 758 CHAPTER 17 TURNING ON/OFF POWER .........................................................................................759 CHAPTER 18 ELECTRICAL SPECIFICATIONS ..................................................................................761 18.1 Normal Operation Mode ......................................................................................................... 761 18.2 Flash Memory Programming Mode (PD70F3116 only)...................................................... 787 CHAPTER 19 PACKAGE DRAWING....................................................................................................789 CHAPTER 20 RECOMMENDED SOLDERING CONDITIONS............................................................790 APPENDIX A NOTES ON TARGET SYSTEM DESIGN ....................................................................791 16 User's Manual U14492EJ5V0UD APPENDIX B REGISTER INDEX..........................................................................................................792 APPENDIX C INSTRUCTION SET LIST..............................................................................................803 C.1 Functions ................................................................................................................................. 803 C.2 Instruction Set (Alphabetical Order) ..................................................................................... 806 APPENDIX D REVISION HISTORY ......................................................................................................812 D.1 Major Revisions in This Edition ............................................................................................ 812 D.2 Revision History up to Previous Edition .............................................................................. 814 User's Manual U14492EJ5V0UD 17 CHAPTER 1 INTRODUCTION The V850E/IA1 is a product in the V850 Series of NEC Electronics Corporation single-chip microcontrollers. This chapter provides an overview of the V850E/IA1. 1.1 Outline The V850E/IA1 is a 32-bit single-chip microcontroller that realizes high-precision inverter control of a motor due to high-speed operation. It uses the V850E1 CPU of the V850 Series and has on-chip ROM, RAM, bus interface, DMA controller, a variety of timers including a 3-phase sine wave PWM timer for a motor, various serial interfaces including FCAN, and peripheral facilities such as A/D converters. (1) Implementation of V850E1 CPU The V850E1 CPU supports a RISC instruction set in which instruction execution speeds are increased greatly through the use of basic instructions that execute one instruction per clock and optimized pipelines. Moreover, it supports multiply instructions using a 32-bit hardware multiplier, saturated product-sum operation instructions, and bit manipulation instructions as optimum instructions for digital servo control applications. Object code efficiency is increased in the C compiler by using 2-byte length basic instructions and instructions corresponding to high-level languages, which makes a program compact. Furthermore, since interrupt response time including processing by the on-chip interrupt controller also is fast, this CPU is suited to the realm of advanced real-time control. (2) External bus interface function As the external bus interface, there is a multiplex bus configuration that is an address bus (24 bits) and data bus (select 8 bits or 16 bits) suitable for compact system design. connected. In the DMA controller, a transfer is started using software and transfers between external memories can be made concurrent with internal CPU operations or data transfers. Real-time control such as motor control or communication control also can be realized simultaneously due to high speed, high-performance CPU instruction execution. (3) On-chip flash memory (PD70F3116) The on-chip flash memory version (PD70F3116), which has a quickly accessible flash memory on-chip, can shorten system development time since it is possible to rewrite a program with the V850E/IA1 mounted in an application system. Moreover, it can greatly improve maintainability after a system ships. (4) Complete middleware, development environment products The V850E/IA1 can execute JPEG, JBIG, MH/MR/MMR and other middleware fast. multimedia systems can be realized easily by combining with this middleware. A development environment that integrates an optimizing C compiler, debugger, in-circuit emulator, simulator, and system performance analyzer also is provided. Moreover, since middleware for realizing speech recognition, speech synthesis, and other processing also is provided, SRAM and ROM memories can be 18 User's Manual U14492EJ5V0UD CHAPTER 1 INTRODUCTION Table 1-1 lists the differences between the V850E/IA1 and V850E/IA2. between the V850E/IA1 and V850E/IA2 register setting values. Table 1-2 lists the differences Table 1-1. Differences Between V850E/IA1 and V850E/IA2 Item Maximum operating frequency Internal ROM Mask ROM Flash memory Internal RAM Timer Timer 00, 01 50 MHz Note V850E/IA1 40 MHz V850E/IA2 PD703116: 256 KB PD70F3116: 256 KB 10 KB Provided PD703114: 128 KB PD70F3114: 128 KB 6 KB Buffer register, compare register, and compare match interrupt added Timer 10, 11 Provided Timer 10: Provided, Timer 11: Not provided Timer 20, 21 Timer 3 Provided Provided Provided TO3 output buffer off function added by INTP4 input Timer 4 Serial interface UART0 UART1 UART2 CSI0 CSI1 FCAN Debug support function A/D converter Analog input NBD Provided Provided Provided Provided Provided Provided Provided Provided Provided Provided Provided (pins also used with CSI1) Not provided Provided Provided (pins also used with UART1) Not provided Not provided Total of two circuits: 16 ch A/D converter 0: 8 ch A/D converter 1: 8 ch Total of two circuits: 14 ch A/D converter 0: 6 ch A/D converter 1: 8 ch Alternate-function pins VDD = RVDD = 5.0 V 0.5 V Internal regulator 100-pin plastic LQFP 100-pin plastic QFP AVDD, AVREF pins Supply voltage Independent pins VDD3 = 3.3 V 0.3 V VDD5 = 5.0 V 0.5 V Package 144-pin plastic LQFP Note The maximum operating frequency of the in-circuit emulator is 40 MHz. A frequency of 50 MHz can be supported by upgrading the in-circuit emulator, so contact an NEC Electronics sales representative or distributor. Remark For details, refer to the user's manual of each product. User's Manual U14492EJ5V0UD 19 CHAPTER 1 INTRODUCTION Table 1-2. Differences Between V850E/IA1 and V850E/IA2 Register Setting Values Register Name System wait control register (VSWC) Timer 1/timer 2 clock selection register (PRM02) 12H 00H or 01H V850E/IA1 Note V850E/IA2 02H 01H (initial value 00H) Notes 1. Setting the TESnE1 and TESnE0 bits of timer 2 count clock/control edge select register 0 (CSE0) to 11B (both rising/falling edges) is prohibited when the PRM2 bit of the timer 1/timer 2 clock selection register (PRM02) is 1B (fCLK = fXX/2) 2. Set the VSWC register to 15H when the PRM2 bit of the timer 1/timer 2 clock selection register (PRM02) = 0B (fCLK = fXX/4). Remark For details, refer to the user's manual of each product. 20 User's Manual U14492EJ5V0UD CHAPTER 1 INTRODUCTION 1.2 Features 80 Number of instructions Minimum instruction execution time 20 ns (@ internal 50 MHz operation) General-purpose registers Instruction set 32 bits x 32 registers V850E1 CPU Signed multiplication (32 bits x 32 bits 64 bits): 1 or 2 clocks Saturated operation instructions (with overflow/underflow detection function) 32-bit shift instruction: 1 clock Bit manipulation instructions Long/short format load/store instructions Signed load instructions Memory space 256 MB linear address space (shared by program and data) Chip select output function: 8 spaces Memory block division function: 2, 4, or 8 MB/block Programmable wait function Idle state insertion function External bus interface 16-bit data bus (address/data multiplex) 16-/8-bit bus sizing function Bus hold function External wait function On-chip memory Product Name Internal ROM 256 KB (mask ROM) 256 KB (flash memory) Internal RAM 10 KB 10 KB PD703116 PD70F3116 Interrupts/exceptions External interrupts: 20 (including NMI) Internal interrupts: 45 sources Exceptions: 1 cause 8 levels of priority definable Memory access control SRAM controller User's Manual U14492EJ5V0UD 21 CHAPTER 1 INTRODUCTION DMA controller 4-channel configuration Transfer unit: Transfer type: Transfer modes: Transfer subjects: Transfer requests: 8 bits/16 bits 2-cycle transfer Single transfer, single-step transfer, block transfer Memory Memory, Memory I/O, I/O I/O On-chip peripheral I/O, software Maximum transfer count: 65,536 (216) Next address setting function I/O lines Input ports: 8 I/O ports: Timer/counter function 75 16-bit timer for 3-phase sine wave PWM inverter control: 2 channels 16-bit up/down counter/timer for 2-phase encoder input: 2 channels General-purpose 16-bit timer/counter: 2 channels General-purpose 16-bit timer/event counter: 1 channel 16-bit interval timer: 1 channel Serial interface Asynchronous serial interface (UART): 3 channels Clocked serial interface (CSI): 2 channels FCAN (Full Controller Area Network): 1 channel NBD (Non Break Debug) function: 1 channel (PD70F3116 only) RAM monitoring Event detection A/D converter Clock generator 10-bit resolution A/D converter: 8 channels x 2 units Multiplication function (x1, x2.5, x5, x10) using PLL clock synthesizer Divide-by-2 function using external clock input Power-saving function Power supply voltage Package CMOS technology HALT, IDLE, and software STOP modes Internal unit: 3.3 V, A/D converter: 5 V, external pin: 5 V 144-pin plastic LQFP (fine pitch) (20 x 20) Full static circuits 22 User's Manual U14492EJ5V0UD CHAPTER 1 INTRODUCTION 1.3 Applications * PD703116, 70F3116: Consumer equipment (inverter air conditioner) Industrial equipment (motor control, general-purpose inverter) * PD703116(A), 703116(A1), 70F3116(A), 70F3116(A1): Automobile applications (electrical power steering, electric car control) 1.4 Ordering Information Part No. Package 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) Quality Grade Standard Standard Standard Standard Special Special Special Special Special Special Special Special PD703116GJ-xxx-UEN PD703116GJ-xxx-UEN-A PD70F3116GJ-UEN PD70F3116GJ-UEN-A PD703116GJ(A)-xxx-UEN PD703116GJ(A)-xxx-UEN-A PD703116GJ(A1)-xxx-UEN PD703116GJ(A1)-xxx-UEN-A PD70F3116GJ(A)-UEN PD70F3116GJ(A)-UEN-A PD70F3116GJ(A1)-UEN PD70F3116GJ(A1)-UEN-A Remarks 1. xxx indicates the ROM code suffix. 2. Products with -A at the end of the part number are lead-free products. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Electronics Corporation to know the specification of the quality grade on the device and its recommended applications. Differences between PD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), and 70F3116(A1) Part No. Item Quality grade Maximum operating frequency (MHz) Operating ambient temperature (TA) -40 to +85C -40 to +110C -40 to +85C -40 to +110C Standard grade 50 Note PD703116 PD703116(A) PD703116(A1) PD70F3116 PD70F3116(A) PD70F3116(A1) Special grade 32 Standard grade 50 Note Special grade 32 Note The maximum operating frequency of the in-circuit emulator is 40 MHz. A frequency of 50 MHz can be supported by upgrading the in-circuit emulator, so contact an NEC Electronics sales representative or distributor. User's Manual U14492EJ5V0UD 23 CHAPTER 1 INTRODUCTION 1.5 Pin Configuration (Top View) * 144-pin plastic LQFP (fine pitch) (20 x 20) PD703116GJ-xxx-UEN, 703116GJ-xxx-UEN-A, 703116GJ(A)-xxx-UEN, 703116GJ(A)-xxx-UEN-A, PD703116GJ(A1)-xxx-UEN, 703116GJ(A1)-xxx-UEN-A, 70F3116GJ-UEN, 70F3116GJ-UEN-A, PD70F3116GJ(A)-UEN, 70F3116GJ(A)-UEN-A, 70F3116GJ(A1)-UEN, 70F3116GJ(A1)-UEN-A ANI06 ANI05 ANI04 ANI03 ANI02 ANI01 ANI00 AVREF0 AVSS AVDD TO015 TO014 TO013 TO012 TO011 TO010 VDD3 VSS3 VSS5 VDD5 TO005 TO004 TO003 TO002 TO001 TO000 INTP6/P07 INTP5/P06 INTP4/P05 ADTRG1/INTP3/P04 ADTRG0/INTP2/P03 ESO1/INTP1/P02 ESO0/INTP0/P01 NMI/P00Note 3 TCLR11/INTP111/P15 TCUD11/INTP110/P14 ANI07 AVDD AVSS AVREF1 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 ANI16 ANI17 TRIG_DBG AD3_DBG AD2_DBG AD1_DBG AD0_DBG SYNC CLK_DBG RESET CVDD CVSS X1 X2 CKSEL MODE0 MODE1 MODE2 SI0/P40 SO0/P41 SCK0/P42 SI1/P43 SO1/P44 SCK1/P45 CRXD/P46 CTXD/P47 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 Note 1 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 TIUD11/TO11/P13 TCLR10/INTP101/P12 TCUD10/INTP100/P11 TIUD10/TO10/P10 PCM4 HLDRQ/PCM3 HLDAK/PCM2 CLKOUT/PCM1 WAIT/PCM0 PCT7 ASTB/PCT6 PCT5 RD/PCT4 PCT3 PCT2 UWR/PCT1 LWR/PCT0 VDD5 VSS5 Note 2 CS7/PCS7 CS6/PCS6 CS5/PCS5 CS4/PCS4 CS3/PCS3 CS2/PCS2 CS1/PCS1 CS0/PCS0 A23/PDH7 A22/PDH6 A21/PDH5 A20/PDH4 A19/PDH3 A18/PDH2 A17/PDH1 A16/PDH0 Notes 1. PD70F3116 only As follows in PD703116. TRIG_DBG: IC1, AD0_DBG to AD3_DBG: IC2, SYNC: IC3, CLK_DBG: IC4 2. 3. PD703116: IC5 PD70F3116: VPP The NMI/P00 pin always functions as the NMI pin. The NMI pin level can be read by reading the P0.P00 bit. Cautions 1. When using the PD70F3116 in normal mode, connect the VPP pin to VSS5. 2. When using the PD703116, the processing when the IC1 to IC5 pins are unused is as follows. IC1 to IC4 pins: Leave open. IC5 pin: Independently connect to VSS5 via a resistor. 24 RXD0/P30 TXD0/P31 RXD1/P32 TXD1/P33 ASCK1/P34 RXD2/P35 TXD2/P36 ASCK2/P37 TI2/INTP20/P20 TO21/INTP21/P21 TO22/INTP22/P22 TO23/INTP23/P23 TO24/INTP24/P24 TCLR2/INTP25/P25 TI3/INTP30/TCLR3/P26 TO3/INTP31/P27 VDD3 VSS3 VSS5 VDD5 AD0/PDL0 AD1/PDL1 AD2/PDL2 AD3/PDL3 AD4/PDL4 AD5/PDL5 AD6/PDL6 AD7/PDL7 AD8/PDL8 AD9/PDL9 AD10/PDL10 AD11/PDL11 AD12/PDL12 AD13/PDL13 AD14/PDL14 AD15/PDL15 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 User's Manual U14492EJ5V0UD CHAPTER 1 INTRODUCTION Pin Identification A16 to A23: AD0 to AD15: ADTRG0, ADTRG1: ANI00 to ANI07, ANI10 to ANI17: ASCK1, ASCK2: ASTB: AVDD: AVREF0, AVREF1: AVSS: CKSEL: CLK_DBG: CLKOUT: CRXD: CS0 to CS7: CTXD: CVDD: CVSS: ESO0, ESO1: HLDAK: HLDRQ: IC1 to IC5: INTP0 to INTP6, INTP100, INTP101, INTP110, INTP111, INTP20 to INTP25, INTP30, INTP31: LWR: MODE0 to MODE2: NMI: P00 to P07: P10 to P15: Lower write strobe Mode Non-maskable interrupt request Port 0 Port 1 Asynchronous serial clock Address strobe Analog power supply Analog reference voltage Analog ground Clock generator operating mode select Debug clock Clock output Receive data for controller area network Chip select Transmit data for controller area network Clock generator power supply Clock generator ground Emergency shut off Hold acknowledge Hold request Internally connected External interrupt input Address bus Address/data bus A/D trigger input Analog input P20 to P27: P30 to P37: P40 to P47: PCM0 to PCM4: PCS0 to PCS7: PCT0 to PCT7: PDH0 to PDH7: PDL0 to PDL15: RD: RESET: RXD0 to RXD2: SCK0, SCK1: SI0, SI1: SO0, SO1: SYNC: TCLR10, TCLR11, TCLR2, TCLR3: TCUD10, TCUD11: TI2, TI3: TIUD10, TIUD11: TO000 to TO005, TO010 to TO015, TO10, TO11, TO21 to TO24, TO3: TRIG_DBG: TXD0 to TXD2: UWR: VDD3, VDD5: VPP: VSS3, VSS5: WAIT: X1, X2: Debug trigger Transmit data Upper write strobe Power supply Programming power supply Ground Wait Crystal Timer control pulse input Timer input Timer count pulse input Timer output Port 2 Port 3 Port 4 Port CM Port CS Port CT Port DH Port DL Read strobe Reset Receive data Serial clock Serial input Serial output Debug synchronization Timer clear AD0_DBG to AD3_DBG: Debug address/data bus User's Manual U14492EJ5V0UD 25 CHAPTER 1 INTRODUCTION 1.6 Configuration of Function Block 1.6.1 Internal block diagram NMI INTP0 to INTP6 INTP20 to INTP25 INTP30, INTP31 INTP100, INTP101 INTP110, INTP111 ESO0, ESO1 TO000 to TO005, TO010 to TO015 TIUD10/TO10, TCUD10, TCLR10 TIUD11/TO11, TCUD11, TCLR11 TI2, TCLR2, TO21 to TO24 TI3/TCLR3, TO3 TXD0 RXD0 TXD1 RXD1 ASCK1 TXD2 RXD2 ASCK2 SO0 SI0 SCK0 SO1 SI1 SCK1 CTXD CRXD CLK_DBG SYNC AD0_DBG to AD3_DBG TRIG_DBG INTC ROM PC Note 1 32-bit barrel shifter TM0: 2 ch TM1: 2 ch TM2: 2 ch TM3: 1 ch TM4: 1 ch System register RAM 10 KB UART0 BRG0 UART1 BRG1 UART2 BRG2 CSI0 BRG3 CSI1 FCAN Ports Generalpurpose registers 32bitsx32 CPU BCU Instruction queue MEMC SRAMC HLDRQ HLDAK CS0 to CS7 RD ASTB UWR LWR WAIT A16 to A23 Multiplier 32x32 64 ROMC ALU AD0 to AD15 DMAC ADC0 ADC1 CG CKSEL CLKOUT X1 X2 CVDD CVSS MODE0 to MODE2 RESET VDD5 VSS5 VDD3 VSS3 VPPNote 4 ADTRG0 ANI00 to ANI07 AVSS AVREF0 AVDD PDL0 to PDL15 PDH0 to PDH7 PCS0 to PCS7 PCT0 to PCT7 PCM0 to PCM4 P40 to P47 P30 to P37 P20 to P27 P10 to P15 P00 to P07 ADTRG1 ANI10 to ANI17 AVSS AVREF1 AVDD Note 2 NBDNote 3 System controller Notes 1. PD703116: 256 KB (mask ROM) PD70F3116: 256 KB (flash memory) 2. PD70F3116 only As follows in PD703116. TRIG_DBG: IC1, AD0_DBG to AD3_DBG: IC2, SYNC: IC3, CLK_DBG: IC4 PD70F3116 only 4. PD70F3116 only In the PD703116, the VPP pin is assigned as the IC5 pin. 3. 26 User's Manual U14492EJ5V0UD CHAPTER 1 INTRODUCTION 1.6.2 Internal units (1) CPU The CPU uses 5-stage pipeline control to execute address calculation, arithmetic and logical operation, data transfer, and most other instruction processing in one clock. A multiplier (16 bits x 16 bits 32 bits or 32 bits x 32 bits 64 bits), barrel shifter (32-bit), and other dedicated hardware are on-chip to accelerate complex instruction processing. (2) Bus control unit (BCU) The BCU starts a required external bus cycle based on a physical address obtained from the CPU. If there is no bus cycle start request from the CPU when fetching an instruction from an external memory area, the BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is fetched into the internal instruction queue of the CPU. (3) Memory controller (MEMC) The MEMC controls SRAM, ROM, and various I/O for external memory expansion. (4) DMA controller (DMAC) The DMA transfers data between memory and I/O in place of the CPU. The address mode is two-cycle transfer. The three bus modes are single transfer, single-step transfer, and block transfer. (5) ROM There is on-chip flash memory (256 KB) in the PD70F3116, and mask ROM (256 KB) in the PD703116. On an instruction fetch, the ROM can be accessed by the CPU in one clock. When single-chip mode 0 or flash memory programming mode is set, ROM is mapped starting from address 00000000H. When single-chip mode 1 is set, it is mapped starting from address 00100000H. ROM cannot be accessed if ROMless mode 0 or 1 is set. (6) RAM RAM is mapped starting from address FFFFC000H. It can be accessed by the CPU in one clock on an instruction fetch or data access. (7) Interrupt controller (INTC) The INTC services hardware interrupt requests from on-chip peripheral I/O and external sources (NMI, INTP0 to INTP6, INTP20 to INTP25, INTP30, INTP31, INTP100, INTP101, INTP110, INTP111). For these interrupt requests, eight levels of interrupt priority can be defined and multiprocessing controls against the interrupt sources can be performed. (8) Clock generator (CG) The CG provides a frequency that is 1, 2.5, 5, or 10 times (using the on-chip PLL) or 1/2 times (not using the on-chip PLL) the input clock (fX) as the internal system clock (fXX). As the input clock, connect an external resonator to pins X1 and X2 (only when using the on-chip PLL synthesizer) or input an external clock from the X1 pin. User's Manual U14492EJ5V0UD 27 CHAPTER 1 INTRODUCTION (9) Timer/counter function This unit incorporates a 2-channel 16-bit timer (TM0) for 3-phase sine wave PWM inverter control, a 2channel 16-bit up/down counter (TM1) that can be used for 2-phase encoder input or as a general-purpose timer, a 2-channel 16-bit general-purpose timer unit (TM2), a 1-channel 16-bit timer/event counter (TM3), and a 1-channel 16-bit interval timer (TM4) on-chip, and can measure the pulse interval or frequency and can output a programmable pulse. (10) Serial interface A 3-channel asynchronous serial interface (UART), 2-channel clocked serial interface (CSI), and 1-channel FCAN are provided as serial interfaces. The UART performs data transfer using pins TXDn and RXDn (n = 0 to 2). The CSI performs data transfer using pins SOm, SIm, and SCKm (m = 0, 1). FCAN performs data transfer using pins CTXD and CRXD. (11) NBD function There is a 1-channel NBD on-chip as a debugging interface (PD70F3116 only). (12) A/D converter (ADC) Two units of a high-speed, high-resolution 10-bit A/D converter having eight analog input pins are implemented. The ADC converts using a successive approximation method. (13) Ports As shown in the table below, ports function as general-purpose ports and as control pins. Port Port 0 I/O 8-bit input NMI input Timer/counter output stop signal input External interrupt input A/D converter external trigger input Port 1 6-bit I/O Timer/counter I/O External interrupt input Port 2 8-bit I/O Timer/counter I/O External interrupt input Port 3 Port 4 Port DH Port DL Port CS Port CT Port CM 8-bit I/O 8-bit I/O 8-bit I/O 16-bit I/O 8-bit I/O 8-bit I/O 5-bit I/O Serial interface I/O (UART0 to UART2) Serial interface I/O (CSI0, CSI1, FCAN) External address bus (A16 to A23) External address/data bus (AD0 to AD15) External bus interface control signal output External bus interface control signal output Wait insertion signal input Internal system clock output External bus interface control signal I/O Control Functions 28 User's Manual U14492EJ5V0UD CHAPTER 1 INTRODUCTION 1.7 Differences Between Products Item PD703116 Mask ROM 256 KB PD703116(A) PD703116(A1) PD70F3116 Flash memory PD70F3116(A) PD70F3116(A1) Internal ROM Internal RAM NBD (Non Break Debug) function 10 KB Not provided (IC1 to IC4) Provided (TRIG_DBG, AD0_DBG to AD3_DBG, SYNC, CLK_DBG) Flash memory programming pin Flash memory programming mode Quality grade Electrical specifications Other Not provided (IC5) Provided (VPP) Not provided Provided (MODE0 = H/L, MODE1 = H, MODE2 = L, VPP = 7.8 V) Standard grade Special grade Standard grade Special grade The maximum operating frequency, operating ambient temperature, and power supply current differ (refer to CHAPTER 18 ELECTRICAL SPECIFICATIONS). The noise immunity and noise radiation differ because the circuit scale and mask layout are different. User's Manual U14492EJ5V0UD 29 CHAPTER 2 PIN FUNCTIONS The names and functions of the V850E/IA1 pins are shown below. These pins can be divided by function into port pins and non-port pins. 2.1 List of Pin Functions (1) Port pins (1/3) Pin Name I/O I Port 0 8-bit input-only port P00 is also used for indicating the NMI pin status. The NMI pin level can be read by reading the P0.P00 bit. P00 functions as an NMI input when a valid edge is input. Function Alternate Function NMI ESO0/INTP0 ESO1/INTP1 ADTRG0/INTP2 ADTRG1/INTP3 INTP4 INTP5 INTP6 I/O Port 1 6-bit I/O port Input/output can be specified in 1-bit units. TIUD10/TO10 TCUD10/INTP100 TCLR10/INTP101 TIUD11/TO11 TCUD11/INTP110 TCLR11/INTP111 I/O Port 2 8-bit I/O port Input/output can be specified in 1-bit units. TI2/INTP20 TO21/INTP21 TO22/INTP22 TO23/INTP23 TO24/INTP24 TCLR2/INTP25 TI3/TCLR3/INTP30 TO3/INTP31 I/O Port 3 8-bit I/O port Input/output can be specified in 1-bit units. RXD0 TXD0 RXD1 TXD1 ASCK1 RXD2 TXD2 ASCK2 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 30 User's Manual U14492EJ5V0UD CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name P40 P41 P42 P43 P44 P45 P46 P47 PCM0 PCM1 PCM2 PCM3 PCM4 PCT0 PCT1 PCT2 PCT3 PCT4 PCT5 PCT6 PCT7 PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 PCS6 PCS7 PDH0 PDH1 PDH2 PDH3 PDH4 PDH5 PDH6 PDH7 I/O Port DH 8-bit I/O port Input/output can be specified in 1-bit units. I/O Port CS 8-bit I/O port Input/output can be specified in 1-bit units. CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 A16 A17 A18 A19 A20 A21 A22 A23 ASTB - RD - I/O Port CT 8-bit I/O port Input/output can be specified in 1-bit units. LWR UWR - - I/O Port CM 5-bit I/O port Input/output can be specified in 1-bit units. I/O I/O Port 4 8-bit I/O port Input/output can be specified in 1-bit units. Function Alternate Function SI0 SO0 SCK0 SI1 SO1 SCK1 CRXD CTXD WAIT CLKOUT HLDAK HLDRQ - User's Manual U14492EJ5V0UD 31 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name PDL0 PDL1 PDL2 PDL3 PDL4 PDL5 PDL6 PDL7 PDL8 PDL9 PDL10 PDL11 PDL12 PDL13 PDL14 PDL15 I/O I/O Port DL 16-bit I/O port Input/output can be specified in 1-bit units. Function Alternate Function AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 32 User's Manual U14492EJ5V0UD CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/3) Pin Name TO000 TO001 TO002 TO003 TO004 TO005 TO010 TO011 TO012 TO013 TO014 TO015 TO10 TO11 TO21 TO22 TO23 TO24 TO3 ESO0 ESO1 TIUD10 TIUD11 TCUD10 TCUD11 TCLR10 TCLR11 TI2 TI3 TCLR2 TCLR3 INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 I External maskable interrupt request input I Timer 2 or 3 clear signal input I Timer 2 or 3 external count clock input I Clear signal input to up/down counter (timer 10 or 11) I Count operation switching signal to up/down counter (timer 10 or 11) I External count clock input to up/down counter (timer 10 or 11) O I Timer 3 pulse signal output Timer 00 or 01 output stop signal input O Timer 2 pulse signal output O Timer 10 or 11 pulse signal output O Timer 01 pulse signal output I/O O Timer 00 pulse signal output Function Alternate Function - - - - - - - - - - - - P10/TIUD10 P13/TIUD11 P21/INTP21 P22/INTP22 P23/INTP23 P24/INTP24 P27/INTP31 P01/INTP0 P02/INTP1 P10/TO10 P13/TO11 P11/INTP100 P14/INTP110 P12/INTP101 P15/INTP111 P20/INTP20 P26/INTP30/TCLR3 P25/INTP25 P26/INTP31/TI3 P01/ESO0 P02/ESO1 P03/ADTRG0 P04/ADTRG1 P05 P06 P07 User's Manual U14492EJ5V0UD 33 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name INTP100 INTP101 INTP110 INTP111 INTP20 INTP21 INTP22 INTP23 INTP24 INTP25 INTP30 INTP31 SO0 SO1 SI0 SI1 SCK0 SCK1 TXD0 TXD1 TXD2 RXD0 RXD1 RXD2 ASCK1 ASCK2 CTXD CRXD ANI00 to ANI07 ANI10 to ANI17 ADTRG0 ADTRG1 NMI MODE0 MODE1 MODE2 VPP Note 1 I/O I Function External maskable interrupt request input and timer 10 external capture trigger input External maskable interrupt request input and timer 11 external capture trigger input External maskable interrupt request input and timer 2 external capture trigger input Alternate Function P11/TCUD10 P12/TCLR10 P14/TCUD11 P15/TCLR11 P20/TI2 P21/TO21 P22/TO22 P23/TO23 P24/TO24 P25/TCLR2 I I I External maskable interrupt request input and timer 3 external capture trigger input Serial transmit data output (3-wire) of CSI0 and CSI1 P26/TI3/TCLR3 P27/TO3 P41 P44 O I Serial receive data input (3-wire) of CSI0 and CSI1 P40 P43 I/O Serial clock I/O (3-wire) of CSI0 and CSI1 P42 P45 O Serial transmit data output of UART0 to UART2 P31 P33 P36 I Serial receive data input of UART0 to UART2 P30 P32 P35 I/O Serial clock I/O of UART1 and UART2 P34 P37 O I I FCAN serial transmit data output FCAN serial receive data input Analog input to A/D converter P47 P46 - - I External trigger input to A/D converter P03/INTP2 P04/INTP3 I I Non-maskable interrupt request input Specifies V850E/IA1 operation mode P00 - - - - Note 2 Power application for flash memory write Internal connection pins - - IC1 to IC5 - Notes 1. PD70F3116 only 2. PD703116 only 34 User's Manual U14492EJ5V0UD CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name WAIT HLDAK HLDRQ LWR UWR RD ASTB CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 AD0 to AD15 A16 to A23 RESET X1 X2 CLKOUT CKSEL AVREF0 AVREF1 AVDD AVSS CVDD CVSS VDD5 VSS5 VDD3 VSS3 CLK_DBG SYNC Note Note I/O I O I O O O O O Function Control signal input to insert wait in bus cycle Bus hold acknowledge output Bus hold request input External data lower byte write strobe signal output External data upper byte write strobe signal output External data bus read strobe signal output External data bus address strobe signal output Chip select signal output Alternate Function PCM0 PCM2 PCM3 PCT0 PCT1 PCT4 PCT6 PCS0 PCS1 PCS2 PCS3 PCS4 PCS5 PCS6 PCS7 I/O O I I - O I I I - - - - - - - - I I 16-bit address/data bus for external memory Upper 8-bit address bus for external memory System reset input Crystal resonator connection pin for system clock generation Input to X1 pin when providing clocks from outside. System clock output Input specifying clock generator operation mode Reference voltage input for A/D converter 0 Reference voltage input for A/D converter 1 Positive power supply for A/D converter Ground potential for A/D converter Positive power supply for dedicated clock generator Ground potential for dedicated clock generator Positive power supply for peripheral interface Ground potential for peripheral interface 3.3 V positive power supply pin for internal CPU Ground potential for internal CPU Debugging interface clock input (3.3 V interface) Debugging interface command synchronization input (3.3 V interface) Command interface input for debugging (3.3 V interface) PDL0 to PDL15 PDH0 to PDH7 - - - PCM1 - - - - - - - - - - - - - - - - - AD0_DBG AD1_DBG AD2_DBG AD3_DBG Note I/O Note Note Note TRIG_DBG Note O Address match trigger signal output for debugging (3.3 V interface) - Note PD70F3116 only User's Manual U14492EJ5V0UD 35 CHAPTER 2 PIN FUNCTIONS 2.2 Pin Status The following table shows the status of each pin after a reset, in power-saving mode (software STOP mode, IDLE, HALT), on a DMA transfer, and on a bus hold. Operating Status Reset (Single-Chip Mode 0) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Reset (Single-Chip IDLE Mode/ HALT Mode/ During DMA Transfer Operating Operating Operating Operating Operating Operating Operating Operating Operating Operating Bus Hold Pin A16 to A23 (PDH0 to PDH7) AD0 to AD15 (PDL0 to PDL15) CS0 to CS7 (PCS0 to PCS7) LWR, UWR (PCT0, PCT1) RD (PCT4) ASTB (PCT6) WAIT (PCM0) CLKOUT (PCM1) HLDAK (PCM2) HLDRQ (PCM3) Software STOP Mode 1, ROMless Mode Mode 0 or 1) Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Operating Hi-Z Hi-Z Hi-Z Hi-Z H H H H - L H - Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z - Operating L Operating Caution When controlling the external bus using an ASIC or the like in standby mode, provide a separate controller. Remark Hi-Z: High impedance H: L: -: High-level output Low-level output No input sampling 36 User's Manual U14492EJ5V0UD CHAPTER 2 PIN FUNCTIONS 2.3 Description of Pin Functions (1) P00 to P07 (Port 0) ... Input Port 0 is an 8-bit input-only port in which all pins are fixed for input. Besides functioning as an input port, in control mode, P00 to P07 operate as NMI input, timer/counter output stop signal input, external interrupt request input, and A/D converter (ADC) external trigger input. Normally, if function pins also serve as ports, one mode or the other is selected using a port mode control register. However, there is no such register for P00 to P07. Therefore, the input port cannot be switched with the NMI input pin, timer/counter output stop signal input pin, external interrupt request input pin, and A/D converter (ADC) external trigger input pin. Read the status of each pin by reading the port. (a) Port mode P00 to P07 are input-only. (b) Control mode P00 to P07 also serve as NMI, ESO0, ESO1, ADTRG0, ADTRG1, and INTP0 to INTP6 pins, but they cannot be switched. (i) NMI (Non-maskable interrupt request) ... Input This is non-maskable interrupt request input. (ii) ESO0, ESO1 (Emergency shut off) ... Input These pins input timer 00 and timer 01 output stop signals. (iii) INTP0 to INTP6 (External interrupt input) ... Input These are external interrupt request input pins. (iv) ADTRG0, ADTRG1 (A/D trigger input) ... Input These are A/D converter external trigger input pins. (2) P10 to P15 (Port 1) ... I/O Port 1 is a 6-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as an I/O port, in control mode, P10 to P15 operate as timer/counter I/O and external interrupt request input. An operation mode of port or control mode can be selected for each bit and specified by the port 1 mode control register (PMC1). (a) Port mode P10 to P15 can be set to input or output in 1-bit units using the port 1 mode register (PM1). (b) Control mode P10 to P15 can be set to port or control mode in 1-bit units using PMC1. (i) TO10, TO11 (Timer output) ... Output These pins output timer 10 and timer 11 pulse signals. (ii) TIUD10, TIUD11 (Timer count pulse input) ... Input These are external count clock input pins to the up/down counter (timer 10, timer 11). User's Manual U14492EJ5V0UD 37 CHAPTER 2 PIN FUNCTIONS (iii) TCUD10, TCUD11 (Timer control pulse input) ... Input These pins input count operation switching signals to the up/down counter (timer 10, timer 11). (iv) TCLR10, TCLR11 (Timer clear) ... Input These are clear signal input pins to the up/down counter (timer 10, timer 11). (v) INTP100, INTP101 (External interrupt input) ... Input These are external interrupt request input pins and timer 10 external capture trigger input pins. (vi) INTP110, INTP111 (External interrupt input) ... Input These are external interrupt request input pins and timer 11 external capture trigger input pins. (3) P20 to P27 (Port 2) ... I/O Port 2 is an 8-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as an I/O port, in control mode, P20 to P27 operate as timer/counter I/O and external interrupt request input. An operation mode of port or control mode can be selected for each bit and specified by the port 2 mode control register (PMC2). (a) Port mode P20 to P27 can be set to input or output in 1-bit units using the port 2 mode register (PM2). (b) Control mode P20 to P27 can be set to port or control mode in 1-bit units using PMC2. (i) TO21 to TO24 (Timer output) ... Output These pins output a timer 2 pulse signal. (ii) TO3 (Timer output) ... Output This pin outputs a timer 3 pulse signal. (iii) TI2, TI3 (Timer input) ... Input These are timer 2 and timer 3 external count clock input pins. (iv) TCLR2, TCLR3 (Timer clear) ... Input These are timer 2 and timer 3 clear signal input pins. (v) INTP20 to INTP25 (External interrupt input) ... Input These are external interrupt request input pins and timer 2 external capture trigger input pins. (vi) INTP30, INTP31 (External interrupt input) ... Input These are external interrupt request input pins and timer 3 external capture trigger input pins. 38 User's Manual U14492EJ5V0UD CHAPTER 2 PIN FUNCTIONS (4) P30 to P37 (Port 3) ... I/O Port 3 is an 8-bit I/O that can be set to input or output in 1-bit units. Besides functioning as an I/O port, in control mode, P30 to P37 operate as serial interface (UART0 to UART2) I/O. An operation mode of port or control mode can be selected for each bit and specified by the port 3 mode control register (PMC3). (a) Port mode P30 to P37 can be set to input or output in 1-bit units using the port 3 mode register (PM3). (b) Control mode P30 to P37 can be set to port or control mode in 1-bit units using PMC3. (i) TXD0 to TXD2 (Transmit data) ... Output These pins output serial transmit data of UART0 to UART2. (ii) RXD0 to RXD2 (Receive data) ... Input These pins input serial receive data of UART0 to UART2. (iii) ASCK1, ASCK2 (Asynchronous serial clock) ... I/O These are UART1 and UART2 serial clock I/O pins. (5) P40 to P47 (Port 4) ... I/O Port 4 is an 8-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as an I/O port, in control mode, P40 to P47 operate as serial interface (CSI0, CSI1, FCAN) I/O. An operation mode of port or control mode can be selected for each bit and specified by the port 4 mode control register (PMC4). (a) Port mode P40 to P47 can be set to input or output in 1-bit units using the port 4 mode register (PM4). (b) Control mode P40 to P47 can be set to port or control mode in 1-bit units using PMC4. (i) SO0, SO1 (Serial output) ... Output These pins output CSI0 and CSI1 serial transmit data. (ii) SI0, SI1 (Serial input) ... Input These pins input CSI0 and CSI1 serial receive data. (iii) SCK0, SCK1 (Serial clock) ... I/O These are CSI0 and CSI1 serial clock I/O pins. (iv) CTXD (Transmit data for controller area network) ... Output This pin outputs FCAN serial transmit data. User's Manual U14492EJ5V0UD 39 CHAPTER 2 PIN FUNCTIONS (v) CRXD (Receive data for controller area network) ... Input This pin inputs FCAN serial receive data. (6) PCM0 to PCM4 (Port CM) ... I/O Port CM is a 5-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode, PCM0 to PCM4 operate as wait insertion signal input, internal system clock output, and bus hold control signal output. An operation mode of port or control mode can be selected for each bit and specified by the port CM mode control register (PMCCM). (a) Port mode PCM0 to PCM4 can be set to input or output in 1-bit units using the port CM mode register (PMCM). (b) Control mode PCM0 to PCM4 can be set to port or control mode in 1-bit units using PMCCM. (i) WAIT (Wait) ... Input This control signal input pin, which inserts a data wait in a bus cycle, can input asynchronously with respect to a CLKOUT signal. Sampling is done at the falling edge of a CLKOUT signal in a bus cycle in a T2 or TW state. If the setup or hold time is not secured in the sampling timing, wait insertion may not be performed. (ii) CLKOUT (Clock output) ... Output This is an internal system clock output pin. In single-chip mode 1 and ROMless mode 0 or 1, output is not performed by the CLKOUT pin because it is in port mode during the reset period. To perform CLKOUT output, set this pin to control mode using the port CM mode control register (PMCCM). (iii) HLDAK (Hold acknowledge) ... Output This is an acknowledge signal output pin that shows that the V850E/IA1 received a bus hold request and that the external address/data bus and various strobe pins entered in a high-impedance state. While this signal is active, the external address/data bus and various strobe pins become highimpedance and transfer the bus mastership to the external bus master. (iv) HLDRQ (Hold request) ... Input This is the input pin by which an external device requests that the V850E/IA1 release the external address/data bus and various strobe pins. The signal via this pin can be input asynchronously with respect to the CLKOUT signal. When this pin becomes active, the V850E/IA1 makes the external address/data bus and various strobe pins high-impedance after the executing bus cycle terminates (or immediately if there is none) and releases the bus by making the HLDAK signal active. To reliably set bus hold status, keep the HLDRQ signal active until a HLDAK signal is output. 40 User's Manual U14492EJ5V0UD CHAPTER 2 PIN FUNCTIONS (7) PCT0 to PCT7 (Port CT) ... I/O Port CT is an 8-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode, it operates as control signal output for when memory is expanded externally. An operation mode of port or control mode can be selected for each bit and specified by the port CT mode control register (PMCCT). (a) Port mode PCT0 to PCT7 can be set to input or output in 1-bit units using the port CT mode register (PMCT). (b) Control mode PCT0 to PCT7 can be set to port or control mode in 1-bit units using PMCCT. (i) LWR (Lower byte write strobe) ... Output This is a strobe signal that shows that the executing bus cycle is a write cycle for SRAM, external ROM, or an external peripheral I/O area. In the data bus, the lower byte is in effect. If the bus cycle is a lower memory write, it becomes active at the falling edge of a T1 state CLKOUT signal and becomes inactive at the falling edge of a T2 state CLKOUT signal. (ii) UWR (Upper byte write strobe) ... Output This is a strobe signal that shows that the executing bus cycle is a write cycle for SRAM, external ROM, or an external peripheral I/O area. In the data bus, the upper byte is in effect. If the bus cycle is an upper memory write, it becomes active at the falling edge of a T1 state CLKOUT signal and becomes inactive at the falling edge of a T2 state CLKOUT signal. (iii) RD (Read strobe) ... Output This is a strobe signal that shows that the executing bus cycle is a read cycle for SRAM, external ROM, or external peripheral I/O. It is inactive in an idle state (TI). (iv) ASTB (Address strobe) ... Output This is the external address bus latch strobe signal output pin. Output becomes low level in synchronous with the falling edge of the clock in a T1 state bus cycle, and high level in synchronous with the falling edge of the clock in a T3 state. (8) PCS0 to PCS7 (Port CS) ... I/O Port CS is an 8-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode, these operate as chip select signal output for when memory is expanded externally. An operation mode of port or control can be selected for each bit and specified by the port CS mode control register (PMCCS). (a) Port mode PCS0 to PCS7 can be set to input or output in 1-bit units using the port CS mode register (PMCS). User's Manual U14492EJ5V0UD 41 CHAPTER 2 PIN FUNCTIONS (b) Control mode PCS0 to PCS7 can be set to port or control mode in 1-bit units using PMCCS. (i) CS0 to CS7 (Chip select) ... Output This is the chip select signal for external SRAM, external ROM, or external peripheral I/O. The signal CSn is assigned to memory block n (n = 0 to 7). This is active for the period during which a bus cycle that accesses the corresponding memory block is activated. It is inactive in an idle state (TI). (9) PDH0 to PDH7 (Port DH) ... I/O Port DH is an 8-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode (external expansion mode), these operate as the address bus (A16 to A23) for when memory is expanded externally. An operation mode of port or control mode can be selected for each bit and specified by the port DH mode control register (PMCDH). (a) Port mode PDH0 to PDH7 can be set to input or output in 1-bit units using the port DH mode register (PMDH). (b) Control mode PDH0 to PDH7 can be used as A16 to A23 by using PMCDH. (i) A16 to A23 (Address) ... Output This pin outputs the upper 8-bit address of the 24-bit address in the address bus on an external access. (10) PDL0 to PDL7 (Port DL) ... I/O Port DL is a 16-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode (external expansion mode), these operate as the address/data bus (AD0 to AD15) for when memory is expanded externally. An operation mode of port or control mode can be selected for each bit and specified by the port DL mode control register (PMCDL). (a) Port mode PDL0 to PDL15 can be set to input or output in 1-bit units using the port DL mode register (PMDL). (b) Control mode PDL0 to PDL15 can be used as AD0 to AD15 by using PMCDL. (i) AD0 to AD15 (Address/data bus) ... I/O This is a multiplexed bus for an address or data on an external access. When used for an address (T1 state) they are 24-bit address output pins A0 to A15, and when used for data (T2, TW, T3) they are 16-bit data I/O bus pins. (11) TO000 to TO005 (Timer output) ... Output These pins output the pulse signal of timer 00. 42 User's Manual U14492EJ5V0UD CHAPTER 2 PIN FUNCTIONS (12) TO010 to TO015 (Timer output) ... Output These pins output the pulse signal of timer 01. (13) ANI00 to ANI07, ANI10 to ANI17 (Analog input) ... Input These are analog input pins to the A/D converter. (14) CKSEL (Clock generator operating mode select) ... Input This is the input pin that specifies the operation mode of the clock generator. Fix it so that the input level does not change during operation. (15) MODE0 to MODE2 (Mode) ... Input These are the input pins that specify the operation mode. Operation modes are broadly divided into normal operation modes and flash memory programming mode. The normal operation modes are single-chip modes 0 and 1 and ROMless modes 0 and 1 (see 3.3 Operation Modes for details). The operation mode is determined by sampling the status of each of pins MODE0 to MODE2 on a reset. Fix these so that the input level does not change during operation. (a) PD703116 MODE2 L L L L MODE1 L L H H MODE0 L H L H Setting prohibited Normal operation mode Operation Mode ROMless mode 0 ROMless mode 1 Single-chip mode 0 Single-chip mode 1 Other than above (b) PD70F3116 VPP 0V 0V 0V 0V 7.8 V MODE2 MODE1 MODE0 L L L L L L L H H H L H L H x Flash memory programming mode Setting prohibited Normal operation mode Operation Mode ROMless mode 0 ROMless mode 1 Single-chip mode 0 Single-chip mode 1 Other than above Remark L: Low-level input H: High-level input x: don't care (16) RESET (Reset) ... Input RESET input is asynchronous input. When a signal having a certain low level width is input in asynchronous with the operation clock, a system reset that takes precedence over all operations occurs. Besides a normal initialize or start, this signal is also used to release a standby mode (HALT, IDLE, software STOP). User's Manual U14492EJ5V0UD 43 CHAPTER 2 PIN FUNCTIONS (17) X1, X2 (Crystal) These pins connect a resonator for system clock generation. They also can input external clocks. For external clock input, connect to the X1 pin and leave the X2 pin open. (18) CVDD (Power supply for clock generator) This is the positive power supply pin for the clock generator. (19) CVSS (Ground for clock generator) This is the ground pin for the clock generator. (20) VDD5 (Power supply) This is the positive power supply pin for the peripheral interface. (21) VSS5 (Ground) This is the ground pin for the peripheral interface. (22) VDD3 (Power supply) This is the positive power supply pin for the internal CPU. (23) VSS3 (Ground) This is the ground pin for the internal CPU. (24) CLK_DBG (Debug clock) ... Input This is the clock input pin for the debug interface (3.3 V interface). (25) SYNC (Debug synchronization) ... Input This is the command synchronization input pin for debugging (3.3 V interface). (26) AD0_DBG to AD3_DBG (Debug address/data bus) ... I/O These are command interface pins for debugging (3.3 V interface). (27) TRIG_DBG (Debug trigger) ... Output This is the address match trigger signal output pin for debugging (3.3 V interface). (28) AVDD (Analog power supply) This is the analog positive power supply pin for the A/D converter. (29) AVSS (Analog ground) This is the ground pin for the A/D converter. (30) AVREF0, AVREF1 (Analog reference voltage) ... Input These are the reference voltage supply pins for the A/D converter. 44 User's Manual U14492EJ5V0UD CHAPTER 2 PIN FUNCTIONS 2.4 Types of Pin I/O Circuit and Connection of Unused Pins Connection of a 1 to 10 k resistor is recommended when connecting to VDD5, VSS5, CVDD, CVSS, or AVSS via a resistor. (1/2) Pin P00/NMI P01/ESO0/INTP0 P02/ESO1/INTP1 P03/ADTRG0/INTP2 P04/ADTRG1/INTP3 P05/INTP4 to P07/INTP6 P10/TIUD10/TO10 P11/TCUD10/INTP100 P12/TCLR10/INTP101 P13/TIUD11/TO11 P14/TCUD11/INTP110 P15/TCLR11/INTP111 P20/TI2/INTP20 P21/TO21/INTP21 to P24/TO24/INTP24 P25/TCLR2/INTP25 P26/TI3/TCLR3/INTP30 P27/TO3/INTP31 P30/RXD0 P31/TXD0 P32/RXD1 P33/TXD1 P34/ASCK1 P35/RXD2 P36/TXD2 P37/ASCK2 P40/SI0 P41/SO0 P42/SCK0 P43/SI1 P44/SO1 P45/SCK1 P46/CRXD P47/CTXD PCM0/WAIT PCM1/CLKOUT PCM2/HLDAK 5 5 5-AC 5 5-AC 5 5-AC 5 5-AC 5 5-AC 5-AC Input status: Independently connect to VDD5 or VSS5 via a resistor. Output status: Leave open. I/O Circuit Type 2 Recommended Connection Connect directly to VSS5. User's Manual U14492EJ5V0UD 45 CHAPTER 2 PIN FUNCTIONS (2/2) Pin PCM3/HLDRQ PCM4 PCT0/LWR PCT1/UWR PCT2 PCT3 PCT4/RD PCT5 PCT6/ASTB PCT7 PCS0/CS0 PCS1/CS1 PCS2/CS2 PCS3/CS3 PCS4/CS4 PCS5/CS5 PCS6/CS6 PCS7/CS7 PDH0/A16 to PDH7/A23 PDL0/AD0 to PDL15/AD15 AD0_DBG to AD3_DBG TRIG_DBG CLK_DBG SYNC Note 1 Note 1 Note 1 I/O Circuit Type 5 Recommended Connection Input status: Independently connect to VDD5 or VSS5 via a resistor. Output status: Leave open. 5-AC 3 2 Independently connect to CVDD or CVSS via a resistor. Leave open (low-level output). Independently connect to CVSS via a resistor. Independently connect to CVDD via a resistor. Note 1 IC1 to IC4 Note 2 - 7 4 2 Leave open. Connect to AVSS. Leave open. - Connect to VSS5. Independently connect to VSS5 via a resistor. - - ANI00 to ANI07, ANI10 to ANI17 TO000 to TO005, TO010 to TO015 MODE0 to MODE2 VPP Note 1 IC5 Note 2 RESET CKSEL X2 AVSS AVREF0, AVREF1 AVDD - - - - Leave open. Connect to VSS5. Connect to VSS5. Connect to VDD5. Notes 1. PD70F3116 only 2. PD703116 only 46 User's Manual U14492EJ5V0UD CHAPTER 2 PIN FUNCTIONS 2.5 Pin I/O Circuits Type 2 Type 5 VDD Data IN Output disable N-ch P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Input enable Type 3 Type 5-AC VDD VDD P-ch OUT N-ch Input enable Output disable N-ch Data P-ch IN/OUT Type 4 VDD Data P-ch Type 7 P-ch OUT Output disable N-ch IN N-ch + _ Comparator VREF (threshold voltage) Push-pull output with possible high-impedance output (P-ch, N-ch both off) User's Manual U14492EJ5V0UD 47 CHAPTER 3 CPU FUNCTION The CPU of the V850E/IA1 is based on RISC architecture and executes almost all instructions in one clock cycle, using 5-stage pipeline control. 3.1 Features * Minimum instruction execution time: 20 ns (@ internal 50 MHz operation) * Memory space Program space: 64 MB linear Data space: * Internal 32-bit architecture * Five-stage pipeline control * Multiplication/division instructions * Saturated operation instructions * One-clock 32-bit shift instruction * Long/short format load/store instructions * Four types of bit manipulation instructions * SET1 * CLR1 * NOT1 * TST1 4 GB linear * Thirty-two 32-bit general-purpose registers 48 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION 3.2 CPU Register Set The registers of the V850E/IA1 can be classified into two categories: a general-purpose program register set and a dedicated system register set. All the registers are 32-bit width. For details, refer to V850E1 Architecture User's Manual. (1) Program register set 31 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (Element pointer (EP)) (Link pointer (LP)) (Stack pointer (SP)) (Global pointer (GP)) (Text pointer (TP)) 0 (Zero register) (Assembler-reserved register) (2) System register set 31 EIPC EIPSW (Status saving register during interrupt) (Status saving register during interrupt) 0 FEPC (Status saving register during NMI) FEPSW (Status saving register during NMI) ECR (Interrupt source register) PSW (Program status word) CTPC (Status saving register during CALLT execution) CTPSW (Status saving register during CALLT execution) DBPC (Status saving register during exception/debug trap) DBPSW (Status saving register during exception/debug trap) CTBP (CALLT base pointer) 31 PC (Program counter) 0 User's Manual U14492EJ5V0UD 49 CHAPTER 3 CPU FUNCTION 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used as a data variable or address variable. However, r0 and r30 are implicitly used by instructions, and care must be exercised when using these registers. r0 is a register that always holds 0, and is used for operations using 0 and offset 0 addressing. r30 is used, by means of the SLD and SST instructions, as a base pointer for when memory is accessed. Also, r1, r3 to r5, and r31 are implicitly used by the assembler and C compiler. Therefore, before using these registers, their contents must be saved so that they are not lost. The contents must be restored to these registers after they have been used. r2 is sometimes used by a real-time OS. r2 can be used as a register for variables when it is not being used by the real-time OS. Table 3-1. Program Registers Name r0 r1 r2 r3 r4 r5 Usage Zero register Assembler-reserved register Always holds 0 Working register for generating address Operation Address/data variable register (when not being used by the real-time OS) Stack pointer Global pointer Text pointer Used to generate stack frame when function is called Used to access global variable in data area Register to indicate the start of the text area (where program code is located) r6 to r29 r30 Address/data variable registers Element pointer Base pointer for generating address when memory is accessed Used by compiler when calling function Holds instruction address during program execution r31 PC Link pointer Program counter Remark For detailed descriptions about r1, r3 to r5, and r31, which are used by the assembler and C compiler, refer to CA850 (C Compiler Package) Assembly Language User's Manual. (2) Program counter (PC) This register holds the instruction address during program execution. The lower 26 bits of this register are valid, and bits 31 to 26 are fixed to 0. If a carry occurs from bit 25 to 26, it is ignored. Bit 0 is fixed to 0, and branching to an odd address cannot be performed. 31 PC Fixed to 0 26 25 Instruction address during execution 10 0 Initial value 00000000H 50 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. To read/write these system registers, specify a system register number indicated below using the system register load/store instruction (LDSR or STSR instruction). Table 3-2. System Register Numbers No. System Register Name Operand Specification LDSR Instruction 0 1 2 3 4 5 6 to 15 16 17 18 19 20 21 to 31 Status saving register during interrupt (EIPC) Note 1 STSR Instruction Status saving register during interrupt (EIPSW) Status saving register during NMI (FEPC) Status saving register during NMI (FEPSW) Interrupt source register (ECR) Program status word (PSW) Note 1 x x x Reserved number for future function expansion (operations that access these register numbers cannot be guaranteed). Status saving register during CALLT execution (CTPC) Status saving register during CALLT execution (CTPSW) Status saving register during exception/debug trap (DBPC) Status saving register during exception/debug trap (DBPSW) CALLT base pointer (CTBP) Reserved number for future function expansion (operations that access these register numbers cannot be guaranteed). Note 2 Note 2 Note 2 Note 2 x x Notes 1. 2. Because this register has only one set, to allow multiple interrupts, it is necessary to save this register by program. These registers can be accessed only after DBTRAP instruction execution and before DBRETI instruction execution. Caution Even if bit 0 of EIPC, FEPC, or CTPC is set to 1 with the LDSR instruction, bit 0 will be ignored when the program is returned by the RETI instruction after interrupt servicing (because bit 0 of the PC is fixed to 0). When setting the value of EIPC, FEPC, or CTPC, use an even value (bit 0 = 0). Remark : Access allowed x: Access prohibited User's Manual U14492EJ5V0UD 51 CHAPTER 3 CPU FUNCTION (1) Interrupt status saving registers (EIPC, EIPSW) There are two interrupt status saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (PC) are saved to EIPC and the contents of the program status word (PSW) are saved to EIPSW (upon occurrence of a non-maskable interrupt (NMI), the contents are saved to the NMI status saving registers (FEPC, FEPSW)). The address of the next instruction following the instruction executed when a software exception or maskable interrupt occurs is saved to EIPC, except for some instructions (refer to 7.8 Periods in Which CPU Does Not Acknowledge Interrupts). The current PSW contents are saved to EIPSW. Since there is only one set of interrupt status saving registers, the contents of these registers must be saved by the program when multiple interrupt servicing is enabled. Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved (fixed to 0) for future function expansion. When the RETI instruction is executed, the values in EIPC and EIPSW are restored to the PC and PSW, respectively. 31 EIPC 26 25 (PC contents saved) 0 After reset 0xxxxxxxH (x: Undefined) 87 0 After reset 000000xxH (x: Undefined) 000000 31 EIPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents saved) 52 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION (2) NMI status saving registers (FEPC, FEPSW) There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to FEPC and the contents of the program status word (PSW) are saved to FEPSW. The address of the next instruction following the instruction executed when a non-maskable interrupt occurs is saved to FEPC, except for some instructions. The current PSW contents are saved to FEPSW. Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved (fixed to 0) for future function expansion. When the RETI instruction has been executed, the values of FEPC and FEPSW are restored to the PC and PSW, respectively. 31 FEPC 26 25 (PC contents saved) 0 After reset 0xxxxxxxH (x: Undefined) 87 0 After reset 000000xxH (x: Undefined) 000000 31 FEPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents saved) (3) Interrupt source register (ECR) Upon occurrence of an interrupt or an exception, the interrupt source register (ECR) holds the source of an interrupt or an exception. The value held by ECR is the exception code coded for each interrupt source. This register is a read-only register, and thus data cannot be written to it using the LDSR instruction. 31 ECR FECC 16 15 EICC 0 After reset 00000000H Bit position 31 to 16 15 to 0 Bit name FECC EICC Description Non-maskable interrupt (NMI) exception code Exception, maskable interrupt exception code User's Manual U14492EJ5V0UD 53 CHAPTER 3 CPU FUNCTION (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the new contents become valid immediately following completion of LDSR instruction execution. Interrupt request acknowledgment is held pending while a write to the PSW is being executed by the LDSR instruction. Bits 31 to 8 are reserved (fixed to 0) for future function expansion. (1/2) 31 PSW RFU 876543210 NP EP ID SAT CY OV S Z After reset 00000020H Bit position 31 to 8 7 Flag name RFU NP Reserved field. Fixed to 0. Description Indicates that non-maskable interrupt (NMI) servicing is in progress. This flag is set to 1 when an NMI request is acknowledged, and disables multiple interrupts. 0: NMI servicing not in progress 1: NMI servicing in progress 6 EP Indicates that exception processing is in progress. This flag is set to 1 when an exception occurs. Moreover, interrupt requests can be acknowledged even when this bit is set. 0: Exception processing not in progress 1: Exception processing in progress 5 ID Indicates whether maskable interrupt request acknowledgment is enabled. 0: Interrupt enabled (EI) 1: Interrupt disabled (DI) Note 4 SAT Indicates that the result of executing a saturated operation instruction has overflowed and that the calculation result is saturated. Since this is a cumulative flag, it is set to 1 when the result of a saturated operation instruction becomes saturated, and it is not cleared to 0 even if the operation results of successive instructions do not become saturated. This flag is neither set nor cleared when arithmetic operation instructions are executed. 0: Not saturated 1: Saturated 3 CY Indicates whether carry or borrow occurred as the result of an operation. 0: No carry or borrow occurred 1: Carry or borrow occurred Note 2 OV Indicates whether overflow occurred during an operation. 0: No overflow occurred 1: Overflow occurred. 1 S Note Indicates whether the result of an operation is negative. 0: Operation result is positive or 0. 1: Operation result is negative. 0 Z Indicates whether operation result is 0. 0: Operation result is not 0. 1: Operation result is 0. Remark Note is explained on the following page. 54 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION (2/2) Note During saturated operation, the saturated operation results are determined by the contents of the OV flag and S flag. The SAT flag is set (to 1) only when the OV flag is set (to 1) during saturated operation. Operation result status SAT Maximum positive value exceeded Maximum negative value exceeded Positive (maximum value not exceeded) Negative (maximum value not exceeded) 1 1 Holds value before operation 1 1 0 Flag status OV 0 1 0 1 S Saturated operation result 7FFFFFFFH 80000000H Actual operation result (5) CALLT execution status saving registers (CTPC, CTPSW) There are two CALLT execution status saving registers, CTPC and CTPSW. When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and the program status word (PSW) contents are saved to CTPSW. The contents saved to CTPC consist of the address of the next instruction after the CALLT instruction. The current PSW contents are saved to CTPSW. Bits 31 to 26 of CTPC and bits 31 to 8 of CTPSW are reserved (fixed to 0) for future function expansion. 31 CTPC 26 25 (PC contents saved) 0 After reset 0xxxxxxxH (x: Undefined) 87 0 After reset 000000xxH (x: Undefined) 000000 31 CTPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents saved) User's Manual U14492EJ5V0UD 55 CHAPTER 3 CPU FUNCTION (6) Exception/debug trap status saving registers (DBPC, DBPSW) There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and the program status word (PSW) contents are saved to DBPSW. The contents saved to DBPC consist of the address of the next instruction after the instruction executed when an exception trap or debug trap occurs. The current PSW contents are saved to DBPSW. These registers can be read or written only in the period between DBTRAP instruction execution and DBRET instruction execution. Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved (fixed to 0) for future function expansion. When the DBRET instruction has been executed, the values of DBPC and DBPSW are restored to the PC and PSW, respectively. 31 DBPC 26 25 (PC contents saved) 0 After reset 0xxxxxxxH (x: Undefined) 87 0 After reset 000000xxH (x: Undefined) 000000 31 DBPSW 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (PSW contents saved) (7) CALLT base pointer (CTBP) The CALLT base pointer (CTBP) is used to specify table addresses and generate target addresses (bit 0 is fixed to 0). Bits 31 to 26 are reserved (fixed to 0) for future function expansion. 31 CTBP 26 25 (Base address) 0 0 000000 After reset 0xxxxxxxH (x: Undefined) 56 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION 3.3 3.3.1 pins. Operation Modes Operation modes The V850E/IA1 has the following operation modes. Mode specification is carried out by the MODE0 to MODE2 (1) Normal operation mode (a) Single-chip modes 0, 1 Access to the internal ROM is enabled. In single-chip mode 0, after the system reset is cleared, each pin related to the bus interface enters the port mode, program execution branches to the reset entry address of the internal ROM, and instruction processing starts. By setting the PMCDH, PMCDL, PMCCS, PMCCT, and PMCCM registers to control mode by instruction, an external device can be connected to the external memory area. In single-chip mode 1, after the system reset is cleared, each pin related to the bus interface enters the control mode, program execution branches to the external device's (memory) reset entry address, and instruction processing starts. The internal ROM area is mapped from address 100000H. (b) ROMless modes 0, 1 After the system reset is cleared, each pin related to the bus interface enters the control mode, program execution branches to the external device's (memory) reset entry address, and instruction processing starts. Fetching of instructions and data access for internal ROM becomes impossible. In ROMless mode 0, the data bus is a 16-bit data bus and in ROMless mode 1, the data bus is an 8-bit data bus. (2) Flash memory programming mode (PD70F3116 only) If this mode is specified, it becomes possible for the flash programmer to run a program to the internal flash memory. The initial values of the registers differ depending on the mode. Operation Mode Normal operation mode ROMless mode 0 ROMless mode 1 Single-chip mode 0 Single-chip mode 1 PMCDH FFH FFH 00H FFH PMCDL FFFFH FFFFH 0000H FFFFH PMCCS FFH FFH 00H FFH PMCCT PMCCM 53H 53H 00H 53H 0FH 0FH 00H 0FH BSC 5555H 0000H 5555H 5555H User's Manual U14492EJ5V0UD 57 CHAPTER 3 CPU FUNCTION 3.3.2 Operation mode specification The operation mode is specified according to the status of pins MODE0 to MODE2. In an application system fix the specification of these pins and do not change them during operation. Operation is not guaranteed if these pins are changed during operation. (a) PD703116 MODE2 L L L MODE1 L L H MODE0 L H L Operation Mode Normal operation mode ROMless mode 0 ROMless mode 1 Single-chip mode 0 Remark 16-bit data bus 8-bit data bus Internal ROM area is allocated from address 000000H. L H H Single-chip mode 1 Internal ROM area is allocated from address 100000H. Other than above Setting prohibited (b) PD70F3116 VPP 0V 0V 0V MODE2 MODE1 MODE0 L L L L L H L H L Operation Mode Normal operation mode ROMless mode 0 ROMless mode 1 Single-chip mode 0 Remark 16-bit data bus 8-bit data bus Internal ROM area is allocated from address 000000H. 0V L H H Single-chip mode 1 Internal ROM area is allocated from address 100000H. 7.8 V L H H/L Flash memory programming mode Setting prohibited -- Other than above Remark L: Low-level input H: High-level input 58 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION 3.4 3.4.1 Address Space CPU address space The CPU of the V850E/IA1 is of 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). Also, in instruction address addressing, a maximum of 64 MB of linear address space (program space) is supported. Figure 3-1 shows the CPU address space. Figure 3-1. CPU Address Space CPU address space FFFFFFFFH Data area (4 GB linear) 04000000H 03FFFFFFH Program area (64 MB linear) 00000000H User's Manual U14492EJ5V0UD 59 CHAPTER 3 CPU FUNCTION 3.4.2 Image 16 images, each containing a 256 MB physical address space, are seen in the 4 GB CPU address space. In actuality, the same 256 MB physical address space is accessed regardless of the values of bits 31 to 28 of the CPU address. Figure 3-2 shows the image of the virtual addressing space. Physical address x0000000H can be seen as CPU address 00000000H, and in addition, can be seen as address 10000000H, address 20000000H, ... , address E0000000H, or address F0000000H. Figure 3-2. Image on Address Space CPU address space FFFFFFFFH Image F0000000H EFFFFFFFH Image Physical address space E0000000H DFFFFFFFH Image External memory 20000000H 1FFFFFFFH Internal ROM On-chip peripheral I/O Internal RAM FFFFFFFH 0000000H Image 10000000H 0FFFFFFFH Image 00000000H 60 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION 3.4.3 Wrap-around of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to 26 as a result of branch address calculation, the higher 6 bits ignore the carry or borrow. Therefore, the upper-limit address of the program space, address 03FFFFFFH, and the lower-limit address 00000000H become contiguous addresses. Wrap-around refers to a situation like this whereby the lowerlimit address and upper-limit address become contiguous. Caution The 4 KB area of 03FFF000H to 03FFFFFFH can be seen as an image of 0FFFF000H to 0FFFFFFFH. No instruction can be fetched from this area because this area is defined as on-chip peripheral I/O area. Therefore, do not execute any branch address calculation in which the result will reside in any part of this area. 00000001H 00000000H Program space (+) direction 03FFFFFFH 03FFFFFEH Program space ( ) direction (2) Data space The result of an operand address calculation that exceeds 32 bits is ignored. Therefore, the upper-limit address of the program space, address FFFFFFFFH, and the lower-limit address 00000000H are contiguous addresses, and the data space is wrapped around at the boundary of these addresses. 00000001H 00000000H Data space (+) direction FFFFFFFFH FFFFFFFEH Data space ( ) direction User's Manual U14492EJ5V0UD 61 CHAPTER 3 CPU FUNCTION 3.4.4 Memory map The V850E/IA1 reserves areas as shown below. Each mode is specified by the MODE0 to MODE2 pins. Figure 3-3. Memory Map Single-chip mode 0 Single-chip mode 1 ROMless mode 0, 1 xFFFFFFFH On-chip peripheral I/O area xFFFF000H xFFFEFFFH xFFFE800H xFFFE7FFH On-chip peripheral I/O area On-chip peripheral I/O area 4 KB Internal RAM area Internal RAM area Internal RAM area 10 KB xFFFC000H xFFFBFFFH 256 MB Access prohibitedNote External memory area External memory area x0200000H x01FFFFFH Internal ROM area x0100000H x00FFFFFH 1 MB Internal ROM area x0000000H External memory area 1 MB Note By setting the PMCDH, PMCDL, PMCCS, PMCCT, and PMCCM registers to control mode, this area can be used as external memory area. 62 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION 3.4.5 Area (1) Internal ROM/internal flash memory area (a) Memory map Up to 1 MB of internal ROM/internal flash memory area is reserved. 256 KB are provided in the following addresses as physical internal ROM (mask ROM/flash memory). * In single-chip mode 0: Addresses 000000H to 03FFFFH (addresses 040000H to 0FFFFFH are undefined) * In single-chip mode 1: Addresses 0100000H to 013FFFFH (addresses 0140000H to 01FFFFFH are undefined) Figure 3-4. Internal ROM/Internal Flash Memory Area Single-chip mode 0 0FFFFFH 1FFFFFH Single-chip mode 1 Undefined Undefined 040000H 03FFFFH 000000H Internal ROM/ internal flash memory area 140000H 13FFFFH 100000H Internal ROM/ internal flash memory area (b) Interrupt/exception table The V850E/IA1 increases the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. The collection of these handler addresses is called an interrupt/exception table, which is located in the internal ROM area. When an interrupt/exception request is acknowledged, execution jumps to the handler address, and the program written at that memory is executed. Table 3-3 shows the sources of interrupts/exceptions, and the corresponding addresses. Remark When in ROMless modes 0, 1, or in single-chip mode 1, in order to resume correct operation after reset, provide a handler address to the reset routine in address 0 of the external memory. User's Manual U14492EJ5V0UD 63 CHAPTER 3 CPU FUNCTION Table 3-3. Interrupt/Exception Table Start Address of Interrupt/Exception Table 00000000H 00000010H 00000040H 00000050H 00000060H 00000080H 00000090H 000000A0H 000000B0H 000000C0H 000000D0H 000000E0H 000000F0H 00000100H 00000110H 00000120H 00000130H 00000140H 00000150H 00000160H 00000170H 00000180H 00000190H 000001A0H 000001B0H 000001C0H 000001D0H 000001E0H 000001F0H Interrupt/Exception Source RESET NMI0 TRAP0n (n = 0 to F) TRAP1n (n = 0 to F) ILGOP/DBG0 INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTDET0 INTDET1 INTTM00 INTCM003 INTTM01 INTCM013 INTP100/INTCC100 INTP101/INTCC101 INTCM100 INTCM101 INTP110/INTCC110 INTP111/INTCC111 INTCM110 INTCM111 INTTM20 INTTM21 INTP20/INTCC20 Start Address of Interrupt/Exception Table 00000200H 00000210H 00000220H 00000230H 00000240H 00000250H 00000260H 00000270H 00000280H 00000290H 000002A0H 000002B0H 000002C0H 000002D0H 000002E0H 000002F0H 00000300H 00000310H 00000320H 00000330H 00000340H 00000350H 00000360H 00000370H 00000380H 00000390H 000003A0H 000003B0H Interrupt/Exception Source INTP21/INTCC21 INTP22/INTCC22 INTP23/INTCC23 INTP24/INTCC24 INTP25/INTCC25 INTTM3 INTP30/INTCC30 INTP31/INTCC31 INTCM4 INTDMA0 INTDMA1 INTDMA2 INTDMA3 INTCREC INTCTRX INTCERR INTCMAC INTCSI0 INTCSI1 INTSR0 INTST0 INTSER0 INTSR1 INTST1 INTSR2 INTST2 INTAD0 INTAD1 64 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION (c) Internal ROM area relocation function If set in single-chip mode 1, the internal ROM area is located beginning from address 100000H, so booting from external memory becomes possible. Therefore, in order to resume correct operation after reset, provide a handler address to the reset routine in address 0 of the external memory. Figure 3-5. Internal ROM Area in Single-Chip Mode 1 200000H 1FFFFFH Internal ROM area 100000H 0FFFFFH External memory area 000000H Block 0 Note Note See 4.3 Memory Block Function. (2) Internal RAM area 12 KB of memory, addresses FFFC000H to FFFEFFFH, is reserved for the internal RAM area. The 12 KB area of 3FFC000H to 3FFEFFFH can be seen as an image of FFFC000H to FFFEFFFH. In the V850E/IA1, 10 KB of memory, addresses FFFC000H to FFFE7FFH, is provided as physical internal RAM. Access to the area of addresses FFFE800H to FFFEFFFH is prohibited. FFFEFFFH Access prohibited FFFE800H FFFE7FFH Internal RAM area (10 KB) FFFC000H User's Manual U14492EJ5V0UD 65 CHAPTER 3 CPU FUNCTION (3) On-chip peripheral I/O area 4 KB of memory, addresses FFFF000H to FFFFFFFH, is provided as an on-chip peripheral I/O area. An image of addresses FFFF000H to FFFFFFFH can be seen in the area between addresses 3FFF000H and 3FFFFFFHNote. Note Access to the area of addresses 3FFF000H to 3FFFFFFH is prohibited. To access the on-chip peripheral I/O, specify addresses FFFF000H to FFFFFFFH. FFFFFFFH On-chip peripheral I/O area (4 KB) FFFF000H On-chip peripheral I/O registers associated with the operation mode specification and the state monitoring for the on-chip peripherals I/O are all memory-mapped to the on-chip peripheral I/O area. Program fetches cannot be executed from this area. Cautions 1. The least significant bit of an address is not decoded. Therefore, if byte access is executed in the register at an odd address (2n + 1), the register at the even address (2n) will be accessed because of the hardware specification. 2. In the V850E/IA1, no registers exist that are capable of word access, but if a register is word accessed, halfword access is performed twice in the order of lower address, then higher address of the word area, ignoring the lower 2 bits of the address. 3. For registers in which byte access is possible, if halfword access is executed, the higher 8 bits become undefined during the read operation, and the lower 8 bits of data are written to the register during the write operation. 4. Addresses that are not defined as registers are reserved for future expansion. If these addresses are accessed, the operation is undefined and not guaranteed. 5. Addresses 3FFF000H to 3FFFFFFH cannot be specified as the source/destination address of DMA transfer. Be sure to use addresses FFFF000H to FFFFFFFH for the source/destination address of DMA transfer. In the on-chip peripheral I/O area, a 16 KB area of addresses from x0000H to x3FFFH is provided as a programmable peripheral I/O area. Within this area, the area between x2000H and x2FFFH is used exclusively for the FCAN controller (see 3.4.9 Programmable peripheral I/O registers). Caution When emulating the FCAN controller using the in-circuit emulator (IE-V850E-MC or IE703116-MC-EM1), perform the following settings in the Configuration screen that appears when the debugger is started. * Set the start address of the programmable peripheral I/O area that is set using the BPC register to the Programmable I/O Area field. * Map the programmable peripheral I/O area as "Target" or "Emulation RAM" in the Memory Mapping field. 66 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION (4) External memory area 256 MB are available for external memory area. The lower 64 MB can be used as program/data area and the higher 192 MB as data area. * When in single-chip mode 0: * When in single-chip mode 1: x0100000H to xFFFBFFFH x0000000H to x00FFFFFH, x0200000H to xFFFBFFFH * When in ROMless modes 0 and 1: x0000000H to xFFFBFFFH Access to the external memory area uses the chip-select signal assigned to each memory block (which is carried out in the CS unit set by chip area selection control registers 0 and 1 (CSC0, CSC1)). Note that, the internal ROM, internal RAM, on-chip peripheral I/O, and programmable peripheral I/O areas cannot be accessed as external memory areas. 3.4.6 External memory expansion By setting the port n mode control register (PMCn) to control mode, an external device can be connected to the external memory space using each pin of ports DH, DL, CS, CT, and CM. Each register is set by selecting control mode for each pin of these ports using PMCn (n = DH, DL, CS, CT, CM). Note that the status after reset differs as shown below in accordance with the operating mode specification set by pins MODE0 to MODE2 (refer to 3.3 Operation Modes for details of the operation modes). (a) In the case of ROMless mode 0 Because each pin of ports DH, DL, CS, CT, and CM enters control mode following a reset, external memory can be used without making changes to the port n mode control register (PMCn) (the external data bus width is 16 bits). (b) In the case of ROMless mode 1 Because each pin of ports DH, DL, CS, CT, and CM enters control mode following a reset, external memory can be used without making changes to the port n mode control register (PMCn) (the external data bus width is 8 bits). (c) In the case of single-chip mode 0 Since the internal ROM area is accessed after a reset, each pin of ports DH, DL, CS, CT, and CM enters the port mode, and external devices cannot be used. To use external memory, set the port n mode control register (PMCn). (d) In the case of single-chip mode 1 The internal ROM area is allocated from address 100000H. As a result, because each pin of ports DH, DL, CS, CT, and CM enters control mode following a reset, external memory can be used without making changes to the port n mode control register (PMCn) (the external data bus width is 16 bits). Remark n = DH, DL, CS, CT, CM User's Manual U14492EJ5V0UD 67 CHAPTER 3 CPU FUNCTION 3.4.7 Recommended use of address space The architecture of the V850E/IA1 requires that a register that serves as a pointer be secured for address generation when accessing operand data in the data space. Operand data access from instruction can be directly executed at the address in this pointer register 32 KB. However, because there is a limit to which general-purpose registers are used as a pointer register, by minimizing the deterioration of address calculation performance when changing the pointer value, the number of usable general-purpose registers for handling variables is maximized, and the program size can be saved. To enhance the efficiency of using the pointer in connection with the memory map of the V850E/IA1, the following points are recommended: (1) Program space Of the 32 bits of the program counter (PC), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. Therefore, a contiguous 64 MB space starting from address 00000000H corresponds to the memory map of the program space. (2) Data space For the efficient use of resources that make use of the wrap-around feature of the data space, the continuous 16 MB address spaces 00000000H to 00FFFFFFH and FF000000H to FFFFFFFFH of the 4 GB CPU are used as the data space. With the V850E/IA1, a 256 MB physical address space is seen as 16 images in the 4 GB CPU address space. The highest bit (bit 25) of this 26-bit address is assigned as address signextended to 32 bits. Example Application of wrap-around 0003FFFFH 00007FFFH Internal ROM area (R =) 00000000H FFFFF000H FFFFEFFFH FFFFE800H FFFFE7FFH Internal RAM area FFFFC000H FFFFBFFFH 32 KB On-chip peripheral I/O area 4 KB 10 KB FFFF8000H External memory area 16 KB When R = r0 (zero register) is specified with the LD/ST disp16 [R] instruction, an addressing range of 00000000H 32 KB can be referenced with the sign-extended disp16. By mapping the external memory in the 16 KB area in the figure, all resources including internal hardware can be accessed with one pointer. The zero register (r0) is a register set to 0 by the hardware, and eliminates the need for additional registers for the pointer. 68 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION Figure 3-6. Recommended Memory Map Program space FFFFFFFFH FFFFFA78H FFFFFA77H FFFFF000H FFFFEFFFH FFFFE800H FFFFE7FFH FFFFC000H FFFFBFFFH Data space On-chip peripheral I/O Internal RAM On-chip peripheral I/O xFFFFFFFH xFFFFA78H xFFFFA77H xFFFF000H xFFFEFFFH Internal RAM xFFFE800H xFFFE7FFH xFFFC000H xFFFBFFFH On-chip peripheral I/ONote Internal RAM External memory 04000000H 03FFFFFFH 03FFF000H 03FFEFFFH 03FFE800H 03FFE7FFH 03FFC000H 03FFBFFFH External memory Program space 64 MB External memory Internal ROM x0100000H x00FFFFFH x0040000H x003FFFFH 00100000H 000FFFFFH Internal ROM 00040000H 0003FFFFH 00000000H Internal ROM x0000000H Note Access to this area is prohibited. To access the on-chip peripheral I/O, specify addresses FFFF000H to FFFFFFFH. Remarks 1. The arrows indicate the recommended area. 2. This is a recommended memory map when the V850E/IA1 is set to single-chip mode 0, and used in external expansion mode. User's Manual U14492EJ5V0UD 69 CHAPTER 3 CPU FUNCTION 3.4.8 On-chip peripheral I/O registers (1/11) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit 8 Bits 16 Bits Undefined Undefined Undefined Undefined Undefined Undefined Undefined FFFFH FFH FFH FFH FFH FFH FFH 0000H/FFFFH 00H/FFH 00H/FFH 00H/FFH 00H/FFH 00H/53H 00H/0FH 2C11H 2C11H 0000H 0000H/5555H 77H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Initial Value FFFFF004H Port DL PDL PDLL PDLH PDH PCS PCT PCM PMDL PMDLL PMDLH PMDH PMCS PMCT PMCM PMCDL PMCDLL PMCDLH PMCDH PMCCS PMCCT PMCCM CSC0 CSC1 BPC BSC VSWC DSA0L DSA0H DDA0L DDA0H DSA1L DSA1H DDA1L DDA1H DSA2L DSA2H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FFFFF004H Port DLL FFFFF005H Port DLH FFFFF006H FFFFF008H FFFFF00AH FFFFF00CH FFFFF024H Port DH Port CS Port CT Port CM Port DL mode register FFFFF024H Port DL mode register L FFFFF025H Port DL mode register H FFFFF026H FFFFF028H FFFFF02AH FFFFF02CH FFFFF044H Port DH mode register Port CS mode register Port CT mode register Port CM mode register Port DL mode control register FFFFF044H Port DL mode control register L FFFFF045H Port DL mode control register H FFFFF046H FFFFF048H FFFFF04AH FFFFF04CH FFFFF060H FFFFF062H FFFFF064H FFFFF066H FFFFF06EH FFFFF080H FFFFF082H FFFFF084H FFFFF086H FFFFF088H FFFFF08AH FFFFF08CH FFFFF08EH FFFFF090H FFFFF092H Port DH mode control register Port CS mode control register Port CT mode control register Port CM mode control register Chip area selection control register 0 Chip area selection control register 1 Peripheral area selection control register Bus size configuration register System wait control register DMA source address register 0L DMA source address register 0H DMA destination address register 0L DMA destination address register 0H DMA source address register 1L DMA source address register 1H DMA destination address register 1L DMA destination address register 1H DMA source address register 2L DMA source address register 2H 70 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION (2/11) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF094H FFFFF096H FFFFF098H FFFFF09AH FFFFF09CH FFFFF09EH FFFFF0C0H FFFFF0C2H FFFFF0C4H FFFFF0C6H FFFFF0D0H FFFFF0D2H FFFFF0D4H FFFFF0D6H FFFFF0E0H FFFFF0E2H FFFFF0E4H FFFFF0E6H FFFFF0F0H FFFFF0F2H FFFFF100H FFFFF100H FFFFF101H FFFFF102H FFFFF102H FFFFF103H FFFFF104H DMA destination address register 2L DMA destination address register 2H DMA source address register 3L DMA source address register 3H DMA destination address register 3L DMA destination address register 3H DMA transfer count register 0 DMA transfer count register 1 DMA transfer count register 2 DMA transfer count register 3 DMA addressing control register 0 DMA addressing control register 1 DMA addressing control register 2 DMA addressing control register 3 DMA channel control register 0 DMA channel control register 1 DMA channel control register 2 DMA channel control register 3 DMA disable status register DMA restart register Interrupt mask register 0 Interrupt mask register 0L Interrupt mask register 0H Interrupt mask register 1 Interrupt mask register 1L Interrupt mask register 1H Interrupt mask register 2 DDA2L DDA2H DSA3L DSA3H DDA3L DDA3H DBC0 DBC1 DBC2 DBC3 DADC0 DADC1 DADC2 DADC3 DCHC0 DCHC1 DCHC2 DCHC3 DDIS DRST IMR0 IMR0L IMR0H IMR1 IMR1L IMR1H IMR2 IMR2L IMR2H IMR3 IMR3L IMR3H P0IC0 P0IC1 P0IC2 P0IC3 P0IC4 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 Bits 16 Bits Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H 0000H 0000H 0000H 00H 00H 00H 00H 00H 00H FFFFH FFH FFH FFFFH FFH FFH FFFFH FFH FFH FFFFH FFH FFH 47H 47H 47H 47H 47H Initial Value FFFFF104H Interrupt mask register 2L FFFFF105H Interrupt mask register 2H FFFFF106H FFFFF106H FFFFF107H FFFFF110H FFFFF112H FFFFF114H FFFFF116H FFFFF118H Interrupt mask register 3 Interrupt mask register 3L Interrupt mask register 3H Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register User's Manual U14492EJ5V0UD 71 CHAPTER 3 CPU FUNCTION (3/11) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF11AH FFFFF11CH FFFFF11EH FFFFF120H FFFFF122H FFFFF124H FFFFF126H FFFFF128H FFFFF12AH FFFFF12CH FFFFF12EH FFFFF130H FFFFF132H FFFFF134H FFFFF136H FFFFF138H FFFFF13AH FFFFF13CH FFFFF13EH FFFFF140H FFFFF142H FFFFF144H FFFFF146H FFFFF148H FFFFF14AH FFFFF14CH FFFFF14EH FFFFF150H FFFFF152H FFFFF154H FFFFF156H FFFFF158H FFFFF15AH FFFFF15CH FFFFF15EH FFFFF160H FFFFF162H Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register P0IC5 P0IC6 DETIC0 DETIC1 TM0IC0 CM03IC0 TM0IC1 CM03IC1 CC10IC0 CC10IC1 CM10IC0 CM10IC1 CC11IC0 CC11IC1 CM11IC0 CM11IC1 TM2IC0 TM2IC1 CC2IC0 CC2IC1 CC2IC2 CC2IC3 CC2IC4 CC2IC5 TM3IC0 CC3IC0 CC3IC1 CM4IC0 DMAIC0 DMAIC1 DMAIC2 DMAIC3 CANIC0 CANIC1 CANIC2 CANIC3 CSIIC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 Bits 16 Bits 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H Initial Value 72 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION (4/11) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF164H FFFFF166H FFFFF168H FFFFF16AH FFFFF16CH FFFFF16EH FFFFF170H FFFFF172H FFFFF174H FFFFF176H FFFFF1FAH FFFFF1FCH FFFFF1FEH FFFFF200H Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register In-service priority register Command register Power save control register A/D scan mode register 00 CSIIC1 SRIC0 STIC0 SEIC0 SRIC1 STIC1 SRIC2 STIC2 ADIC0 ADIC1 ISPR PRCMD PSC ADSCM00 ADSCM00L ADSCM00H Initial Value 8 Bits 16 Bits 47H 47H 47H 47H 47H 47H 47H 47H 47H 47H 00H Undefined 00H 0000H 00H 00H 0000H 00H 00H 0000H 00H 00H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 00H 00H 0000H 00H 00H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R R R R R R R R/W R/W R/W R/W R R/W FFFFF200H A/D scan mode register 00L FFFFF201H A/D scan mode register 00H FFFFF202H A/D scan mode register 01 ADSCM01 ADSCM01L ADSCM01H FFFFF202H A/D scan mode register 01L FFFFF203H A/D scan mode register 01H FFFFF204H A/D voltage detection mode register 0 ADETM0 ADETM0L ADETM0H FFFFF204H A/D voltage detection mode register 0L FFFFF205H A/D voltage detection mode register 0H FFFFF210H FFFFF212H FFFFF214H FFFFF216H FFFFF218H FFFFF21AH FFFFF21CH FFFFF21EH FFFFF240H A/D conversion result register 00 A/D conversion result register 01 A/D conversion result register 02 A/D conversion result register 03 A/D conversion result register 04 A/D conversion result register 05 A/D conversion result register 06 A/D conversion result register 07 A/D scan mode register 10 ADCR00 ADCR01 ADCR02 ADCR03 ADCR04 ADCR05 ADCR06 ADCR07 ADSCM10 ADSCM10L ADSCM10H FFFFF240H A/D scan mode register 10L FFFFF241H A/D scan mode register 10H FFFFF242H A/D scan mode register 11 ADSCM11 ADSCM11L ADSCM11H FFFFF242H A/D scan mode register 11L FFFFF243H A/D scan mode register 11H User's Manual U14492EJ5V0UD 73 CHAPTER 3 CPU FUNCTION (5/11) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF244H A/D voltage detection mode register 1 ADETM1 ADETM1L ADETM1H Initial Value 8 Bits 16 Bits 0000H 00H 00H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 00H Undefined Undefined Undefined Undefined Undefined FFH FFH FFH FFH 00H 00H 00H 00H 00H 00H CCCCH CCCCH 3333H 3333H 0000H AAAAH 0000H 0000H 00H 0FFFH R/W R/W R/W R R R R R R R R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W FFFFF244H A/D voltage detection mode register 1L FFFFF245H A/D voltage detection mode register 1H FFFFF250H FFFFF252H FFFFF254H FFFFF256H FFFFF258H FFFFF25AH FFFFF25CH FFFFF25EH FFFFF280H FFFFF400H FFFFF402H FFFFF404H FFFFF406H FFFFF408H FFFFF422H FFFFF424H FFFFF426H FFFFF428H FFFFF442H FFFFF444H FFFFF446H FFFFF448H FFFFF462H FFFFF464H FFFFF480H FFFFF482H FFFFF484H FFFFF486H FFFFF488H FFFFF48AH FFFFF540H FFFFF542H FFFFF544H FFFFF570H A/D conversion result register 10 A/D conversion result register 11 A/D conversion result register 12 A/D conversion result register 13 A/D conversion result register 14 A/D conversion result register 15 A/D conversion result register 16 A/D conversion result register 17 A/D internal trigger selection register Port 0 Port 1 Port 2 Port 3 Port 4 Port 1 mode register Port 2 mode register Port 3 mode register Port 4 mode register Port 1 mode control register Port 2 mode control register Port 3 mode control register Port 4 mode control register Port 1 function control register Port 2 function control register Bus cycle type configuration register 0 Bus cycle type configuration register 1 Data wait control register 0 Data wait control register 1 Address wait control register Bus cycle control register Timer 4 Compare register 4 Timer control register 4 Dead-time timer reload register 0 ADCR10 ADCR11 ADCR12 ADCR13 ADCR14 ADCR15 ADCR16 ADCR17 ITRG0 P0 P1 P2 P3 P4 PM1 PM2 PM3 PM4 PMC1 PMC2 PMC3 PMC4 PFC1 PFC2 BCT0 BCT1 DWC0 DWC1 AWC BCC TM4 CM4 TMC4 DTRR0 74 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION (6/11) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF572H FFFFF574H FFFFF576H FFFFF578H FFFFF57AH Buffer register CM00 Buffer register CM01 Buffer register CM02 Buffer register CM03 Timer control register 00 BFCM00 BFCM01 BFCM02 BFCM03 TMC00 TMC00L TMC00H TUC00 TOMR0 PSTO0 POER0 SPEC0 DTRR1 BFCM10 BFCM11 BFCM12 BFCM13 TMC01 TMC01L TMC01H TUC01 TOMR1 PSTO1 POER1 SPEC1 PRM01 PRM02 TM10 CM100 CM101 CC100 CC101 CCR0 TUM0 TMC10 SESA10 PRM10 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 Bits 16 Bits FFFFH FFFFH FFFFH FFFFH 0508H 08H 05H 01H 00H 00H 00H 0000H 0FFFH FFFFH FFFFH FFFFH FFFFH 0508H 08H 05H 01H 00H 00H 00H 0000H 00H 00H 0000H 0000H 0000H 0000H 0000H 00H 00H 00H 00H 07H Initial Value FFFFF57AH Timer control register 00L FFFFF57BH Timer control register 00H FFFFF57CH FFFFF57DH FFFFF57EH FFFFF57FH FFFFF580H FFFFF5B0H FFFFF5B2H FFFFF5B4H FFFFF5B6H FFFFF5B8H FFFFF5BAH Timer unit control register 00 Timer output mode register 0 PWM software timing output register 0 PWM output enable register 0 TOMR write enable register 0 Dead-time timer reload register 1 Buffer register CM10 Buffer register CM11 Buffer register CM12 Buffer register CM13 Timer control register 01 FFFFF5BAH Timer control register 01L FFFFF5BBH Timer control register 01H FFFFF5BCH FFFFF5BDH FFFFF5BEH FFFFF5BFH FFFFF5C0H FFFFF5D0H FFFFF5D8H FFFFF5E0H FFFFF5E2H FFFFF5E4H FFFFF5E6H FFFFF5E8H FFFFF5EAH FFFFF5EBH FFFFF5ECH FFFFF5EDH FFFFF5EEH Timer unit control register 01 Timer output mode register 1 PWM software timing output register 1 PWM output enable register 1 TOMR write enable register 1 Timer 0 clock selection register Timer 1/timer 2 clock selection register Timer 10 Compare register 100 Compare register 101 Capture/compare register 100 Capture/compare register 101 Capture/compare control register 0 Timer unit mode register 0 Timer control register 10 Signal edge selection register 10 Prescaler mode register 10 User's Manual U14492EJ5V0UD 75 CHAPTER 3 CPU FUNCTION (7/11) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF5EFH FFFFF5F6H FFFFF5F8H FFFFF600H FFFFF602H FFFFF604H FFFFF606H FFFFF608H FFFFF60AH FFFFF60BH FFFFF60CH FFFFF60DH FFFFF60EH FFFFF60FH FFFFF616H FFFFF618H FFFFF620H FFFFF630H FFFFF631H FFFFF632H FFFFF633H FFFFF634H FFFFF635H FFFFF640H Status register 0 CC101 capture input selection register STATUS0 CSL10 R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W 8 Bits 16 Bits 00H 00H 00H 0000H 0000H 0000H 0000H 0000H 00H 00H 00H 00H 07H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0000H 00H 00H 0000H Initial Value Timer 10 noise elimination time selection register NRC10 Timer 11 Compare register 110 Compare register 111 Capture/compare register 110 Capture/compare register 111 Capture/compare control register 1 Timer unit mode register 1 Timer control register 11 Signal edge selection register 11 Prescaler mode register 11 Status register 1 CC111 capture input selection register TM11 CM110 CM111 CC110 CC111 CCR1 TUM1 TMC11 SESA11 PRM11 STATUS1 CSL11 Timer 11 noise elimination time selection register NRC11 Timer connection selection register 0 Timer 2 input filter mode register 0 Timer 2 input filter mode register 1 Timer 2 input filter mode register 2 Timer 2 input filter mode register 3 Timer 2 input filter mode register 4 Timer 2 input filter mode register 5 Timer 2 clock stop register 0 TMIC0 FEM0 FEM1 FEM2 FEM3 FEM4 FEM5 STOPTE0 STOPTE0L STOPTE0H FFFFF640H Timer 2 clock stop register 0L FFFFF641H Timer 2 clock stop register 0H FFFFF642H Timer 2 count clock/control edge selection register 0 FFFFF642H Timer 2 count clock/control edge selection register 0L FFFFF643H Timer 2 count clock/control edge selection register 0H FFFFF644H Timer 2 sub-channel input event edge selection register 0 FFFFF644H Timer 2 sub-channel input event edge selection register 0L FFFFF645H Timer 2 sub-channel input event edge selection register 0H CSE0 CSE0L R/W 00H CSE0H R/W 00H SESE0 R/W 0000H SESE0L R/W 00H SESE0H R/W 00H 76 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION (8/11) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF646H Timer 2 time base control register 0 TCRE0 TCRE0L TCRE0H OCTLE0 OCTLE0L OCTLE0H CMSE050 R/W R/W R/W R/W R/W R/W R/W 8 Bits 16 Bits 0000H 00H 00H 0000H 00H 00H 0000H Initial Value FFFFF646H Timer 2 time base control register 0L FFFFF647H Timer 2 time base control register 0H FFFFF648H Timer 2 output control register 0 FFFFF648H Timer 2 output control register 0L FFFFF649H Timer 2 output control register 0H FFFFF64AH Timer 2 sub-channel 0, 5 capture/compare control register Timer 2 sub-channel 1, 2 capture/compare control register FFFFF64EH Timer 2 sub-channel 3, 4 capture/compare control register FFFFF650H Timer 2 sub-channel 1 sub capture/compare register FFFFF652H Timer 2 sub-channel 1 main capture/compare register FFFFF654H Timer 2 sub-channel 2 sub capture/compare register FFFFF656H Timer 2 sub-channel 2 main capture/compare register Timer 2 sub-channel 3 sub capture/compare register FFFFF65AH Timer 2 sub-channel 3 main capture/compare register FFFFF65CH Timer 2 sub-channel 4 sub capture/compare register FFFFF65EH Timer 2 sub-channel 4 main capture/compare register FFFFF660H Timer 2 sub-channel 0 capture/compare register FFFFF662H Timer 2 sub-channel 5 capture/compare register Timer 2 time base status register 0 FFFFF64CH CMSE120 R/W 0000H CMSE340 R/W 0000H CVSE10 R/W 0000H CVPE10 R 0000H CVSE20 R/W 0000H CVPE20 R 0000H FFFFF658H CVSE30 R/W 0000H CVPE30 R 0000H CVSE40 R/W 0000H CVPE40 R 0000H CVSE00 R/W 0000H CVSE50 R/W 0000H FFFFF664H TBSTATE0 TBSTATE0L TBSTATE0H CCSTATE0 R/W R/W R/W R/W 0101H 01H 01H 0000H FFFFF664H Timer 2 time base status register 0L FFFFF665H Timer 2 time base status register 0H FFFFF666H Timer 2 capture/compare 1 to 4 status register 0 FFFFF666H Timer 2 capture/compare 1 to 4 status register 0L FFFFF667H Timer 2 capture/compare 1 to 4 status register 0H CCSTATE0L R/W 00H CCSTATE0H R/W 00H User's Manual U14492EJ5V0UD 77 CHAPTER 3 CPU FUNCTION (9/11) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF668H Timer 2 output delay register 0 ODELE0 ODELE0L ODELE0H CSCE0 TM3 CC30 CC31 TMC30 TMC31 SESC PRM03 NRC3 PHCMD PHS DTFR0 DTFR1 DTFR2 DTFR3 PSMR CKC LOCKR INTM0 INTM1 INTM2 FLPMC CSIM0 R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R R 8 Bits 16 Bits 0000H 00H 00H 0000H 0000H 0000H 0000H 00H 20H 00H 00H 00H Undefined 00H 00H 00H 00H 00H 00H 00H 0000000xB 00H 00H 00H 08H/0CH/00H 00H 00H 0000H 00H Note Initial Value FFFFF668H Timer 2 output delay register 0L FFFFF669H Timer 2 output delay register 0H FFFFF66AH FFFFF680H FFFFF682H FFFFF684H FFFFF686H FFFFF688H FFFFF689H FFFFF690H FFFFF698H FFFFF800H FFFFF802H FFFFF810H FFFFF812H FFFFF814H FFFFF816H FFFFF820H FFFFF822H FFFFF824H FFFFF880H FFFFF882H FFFFF884H FFFFF8D4H FFFFF900H FFFFF901H FFFFF902H Timer 2 software event capture register Timer 3 Capture/compare register 30 Capture/compare register 31 Timer control register 30 Timer control register 31 Valid edge selection register Timer 3 clock selection register Timer 3 noise elimination time selection register Peripheral command register Peripheral status register DMA trigger factor register 0 DMA trigger factor register 1 DMA trigger factor register 2 DMA trigger factor register 3 Power save mode register Clock control register Lock register External interrupt mode register 0 External interrupt mode register 1 External interrupt mode register 2 Flash programming mode control register Clocked serial interface mode register 0 Clocked serial interface clock selection register 0 CSIC0 Clocked serial interface receive buffer register 0 SIRB0 SIRBL0 FFFFF902H Clocked serial interface receive buffer register L0 FFFFF904H Clocked serial interface transmit buffer register 0 FFFFF904H Clocked serial interface transmit buffer register L0 SOTB0 R/W 0000H SOTBL0 R/W 00H Note PD703116: 00H PD70F3116: 08H or 0CH (For details, refer to 16.7.12 Flash programming mode control register (FLPMC).) 78 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION (10/11) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFF906H Clocked serial interface read-only receive buffer register 0 FFFFF906H Clocked serial interface read-only receive buffer register L0 FFFFF908H Clocked serial interface initial transmit buffer register 0 FFFFF908H Clocked serial interface initial transmit buffer register L0 FFFFF90AH Serial I/O shift register 0 SIO0 SIOL0 CSIM1 CSIC1 R R R/W R/W 0000H 00H 00H 00H SOTBFL0 R/W 00H SOTBF0 R/W 0000H SIRBEL0 R 00H SIRBE0 R 8 Bits 16 Bits 0000H Initial Value FFFFF90AH Serial I/O shift register L0 FFFFF910H FFFFF911H Clocked serial interface mode register 1 Clocked serial interface clock selection register 1 FFFFF912H Clocked serial interface receive buffer register 1 SIRB1 SIRBL1 R R 0000H 00H FFFFF912H Clocked serial interface receive buffer register L1 FFFFF914H Clocked serial interface transmit buffer register 1 SOTB1 R/W R/W 0000H 00H FFFFF914H Clocked serial interface transmit buffer register SOTBL1 L1 FFFFF916H Clocked serial interface read-only receive buffer register 1 SIRBE1 R 0000H FFFFF916H Clocked serial interface read-only receive buffer register L1 FFFFF918H Clocked serial interface initial transmit buffer register 1 FFFFF918H Clocked serial interface initial transmit buffer register L1 FFFFF91AH Serial I/O shift register 1 SIRBEL1 R 00H SOTBF1 R/W 0000H SOTBFL1 R/W 00H SIO1 SIOL1 PRSM3 PRSCM3 PRM04 R R R/W R/W R/W R/W R R R/W R 0000H 00H 00H 00H 00H 01H FFH 00H FFH 00H FFFFF91AH Serial I/O shift register L1 FFFFF920H FFFFF922H FFFFF930H FFFFFA00H FFFFFA02H FFFFFA03H FFFFFA04H FFFFFA05H Prescaler mode register 3 Prescaler compare register 3 FCAN clock selection register Asynchronous serial interface mode register 0 ASIM0 Receive buffer register 0 Asynchronous serial interface status register 0 Transmit buffer register 0 Asynchronous serial interface transmit status register 0 RXB0 ASIS0 TXB0 ASIF0 FFFFFA06H Clock selection register 0 CKSR0 R/W 00H User's Manual U14492EJ5V0UD 79 CHAPTER 3 CPU FUNCTION (11/11) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit FFFFFA07H FFFFFA20H FFFFFA22H FFFFFA24H FFFFFA26H FFFFFA28H FFFFFA2AH FFFFFA2CH FFFFFA2EH FFFFFA30H FFFFFA40H FFFFFA42H FFFFFA44H FFFFFA46H FFFFFA48H FFFFFA4AH FFFFFA4CH FFFFFA4EH FFFFFA50H FFFFFA60H Baud rate generator control register 0 2-frame continuous reception buffer register 1 Receive buffer register L1 BRGC0 RXB1 RXBL1 R/W R R W W R/W R/W R R/W R/W R R W W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R R R R 8 Bits 16 Bits FFH Undefined Undefined Undefined Undefined 81H 00H 00H 00H 00H Undefined Undefined Undefined Undefined 81H 00H 00H 00H 00H 0000H 00H 00H 0000H 00H 00H Undefined Undefined Undefined Undefined Initial Value 2-frame continuous transmission shift register 1 TXS1 Transmit shift register L1 TXSL1 Asynchronous serial interface mode register 10 ASIM10 Asynchronous serial interface mode register 11 ASIM11 Asynchronous serial interface status register 1 Prescaler mode register 1 Prescaler compare register 1 2-frame continuous reception buffer register 2 Receive buffer register L2 ASIS1 PRSM1 PRSCM1 RXB2 RXBL2 2-frame continuous transmission shift register 2 TXS2 Transmit shift register L2 TXSL2 Asynchronous serial interface mode register 20 ASIM20 Asynchronous serial interface mode register 21 ASIM21 Asynchronous serial interface status register 2 Prescaler mode register 2 Prescaler compare register 2 RAM access data buffer register L ASIS2 PRSM2 PRSCM2 NBDL NBDLL NBDLU NBDH NBDHL NBDHU NBDMSL NBDMSH NBDMDL NBDMDH FFFFFA60H RAM access data buffer register LL FFFFFA61H RAM access data buffer register LU FFFFFA62H RAM access data buffer register H FFFFFA62H RAM access data buffer register HL FFFFFA63H RAM access data buffer register HU FFFFFA64H FFFFFA66H FFFFFA68H FFFFFA6AH DMA source address setting register SL DMA source address setting register SH DMA destination address setting register DL DMA destination address setting register DH 80 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION 3.4.9 Programmable peripheral I/O registers In the V850E/IA1, the 16 KB area of x0000H to x3FFFH is provided as a programmable peripheral I/O area. In this area, the area between x2000H and x2FFFH is used exclusively for the FCAN controller. The internal bus of the V850E/IA1 becomes active when the on-chip peripheral I/O register area (FFFF000H to FFFFFFFH) or the programmable peripheral I/O register area (xxxxm000H to xxxxnFFFH) is accessed (m = xx00B, n = xx11B). However, the on-chip peripheral I/O area is allocated to the last 4 KB of the programmable peripheral I/O register area. Note that when data is written to this area, the written contents are reflected on the on-chip peripheral I/O area. Therefore, access to this area is prohibited. To access the on-chip peripheral I/O area, be sure to specify addresses FFFF000H to FFFFFFFH. Figure 3-7. Programmable Peripheral I/O Register (Outline) 3FFFFFFH 3FFF000H 3FFEFFFH On-chip peripheral I/O register Internal local bus xxxxNFFFH xxxxM000H Programmable peripheral I/O register On-chip peripheral x3FFFH x3000H I/O area x2FFFH Programmable x2000H peripheral x1FFFH I/O area x0000H Dedicated area for FCAN controller 0000000H Caution The CAN message buffer register can allocate address xxxx freely as a programmable peripheral I/O register. But once the address xxxx is set, it cannot be changed. Remark M = xx00B N = xx11B The peripheral area selection control register (BPC) is used for programmable peripheral I/O register area selection. Caution When emulating the FCAN controller using the in-circuit emulator (IE-V850E-MC or IE-703116MC-EM1), perform the following settings in the Configuration screen that appears when the debugger is started. * Set the start address of the programmable peripheral I/O area that is set using the BPC register to the Programmable I/O Area field. * Map the programmable peripheral I/O area as "Target" or "Emulation RAM" in the Memory Mapping field. User's Manual U14492EJ5V0UD 81 CHAPTER 3 CPU FUNCTION (1) Peripheral area selection control register (BPC) This register can be read/written in 16-bit units. 15 BPC PA15 14 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value 0000H PA13 PA12 PA11 PA10 PA09 PA08 PA07 PA06 PA05 PA04 PA03 PA02 PA01 PA00 FFFFF064H Bit position 15 Bit name PA15 Function Enables/disables usage of programmable peripheral I/O area PA15 0 1 Usage of programmable peripheral I/O area Disables usage of programmable peripheral I/O area Enables usage of programmable peripheral I/O area 13 to 0 PA13 to PA00 Specifies an address in programmable peripheral I/O area (corresponds to A27 to A14, respectively). An example of setting for the programmable peripheral I/O register allocation address is shown below. Figure 3-8. Example of Programmable Peripheral I/O Register Allocation Address Setting 24 M_DLC00 address 20 16 12 8 4 0 xxxx xxxxxxxxxx10100000000100 BPC register = x200H x000001000000000 24 Allocation address 20 16 12 8 4 0 0000100000000010100000000100 0 8 0 2 8 0 4 H When BPC register = x200H, the M_DLC00 register is allocated at address 0802804H. A list of the programmable peripheral I/O registers is shown below. 82 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION (1/15) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit xxxxn804H xxxxn805H xxxxn806H xxxxn808H xxxxn809H xxxxn80AH xxxxn80BH xxxxn80CH xxxxn80DH xxxxn80EH xxxxn80FH xxxxn810H xxxxn812H xxxxn814H xxxxn815H xxxxn816H xxxxn824H xxxxn825H xxxxn826H xxxxn828H xxxxn829H xxxxn82AH xxxxn82BH xxxxn82CH xxxxn82DH xxxxn82EH xxxxn82FH xxxxn830H xxxxn832H xxxxn834H xxxxn835H xxxxn836H xxxxn844H xxxxn845H xxxxn846H xxxxn848H CAN message data length register 00 CAN message control register 00 CAN message time stamp register 00 CAN message data register 000 CAN message data register 001 CAN message data register 002 CAN message data register 003 CAN message data register 004 CAN message data register 005 CAN message data register 006 CAN message data register 007 CAN message ID register L00 CAN message ID register H00 CAN message configuration register 00 CAN message status register 00 CAN status set/clear register 00 CAN message data length register 01 CAN message control register 01 CAN message time stamp register 01 CAN message data register 010 CAN message data register 011 CAN message data register 012 CAN message data register 013 CAN message data register 014 CAN message data register 015 CAN message data register 016 CAN message data register 017 CAN message ID register L01 CAN message ID register H01 CAN message configuration register 01 CAN message status register 01 CAN status set/clear register 01 CAN message data length register 02 CAN message control register 02 CAN message time stamp register 02 CAN message data register 020 M_DLC00 M_CTRL00 M_TIME00 M_DATA000 M_DATA001 M_DATA002 M_DATA003 M_DATA004 M_DATA005 M_DATA006 M_DATA007 M_IDL00 M_IDH00 M_CONF00 M_STAT00 SC_STAT00 M_DLC01 M_CTRL01 M_TIME01 M_DATA010 M_DATA011 M_DATA012 M_DATA013 M_DATA014 M_DATA015 M_DATA016 M_DATA017 M_IDL01 M_IDH01 M_CONF01 M_STAT01 SC_STAT01 M_DLC02 M_CTRL02 M_TIME02 M_DATA020 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W 8 Bits 16 Bits Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Initial Value Remark n = 2, 6, A, or E User's Manual U14492EJ5V0UD 83 CHAPTER 3 CPU FUNCTION (2/15) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit xxxxn849H xxxxn84AH xxxxn84BH xxxxn84CH xxxxn84DH xxxxn84EH xxxxn84FH xxxxn850H xxxxn852H xxxxn854H xxxxn855H xxxxn856H xxxxn864H xxxxn865H xxxxn866H xxxxn868H xxxxn869H xxxxn86AH xxxxn86BH xxxxn86CH xxxxn86DH xxxxn86EH xxxxn86FH xxxxn870H xxxxn872H xxxxn874H xxxxn875H xxxxn876H xxxxn884H xxxxn885H xxxxn886H xxxxn888H xxxxn889H xxxxn88AH xxxxn88BH xxxxn88CH CAN message data register 021 CAN message data register 022 CAN message data register 023 CAN message data register 024 CAN message data register 025 CAN message data register 026 CAN message data register 027 CAN message ID register L02 CAN message ID register H02 CAN message configuration register 02 CAN message status register 02 CAN status set/clear register 02 CAN message data length register 03 CAN message control register 03 CAN message time stamp register 03 CAN message data register 030 CAN message data register 031 CAN message data register 032 CAN message data register 033 CAN message data register 034 CAN message data register 035 CAN message data register 036 CAN message data register 037 CAN message ID register L03 CAN message ID register H03 CAN message configuration register 03 CAN message status register 03 CAN status set/clear register 03 CAN message data length register 04 CAN message control register 04 CAN message time stamp register 04 CAN message data register 040 CAN message data register 041 CAN message data register 042 CAN message data register 043 CAN message data register 044 M_DATA021 M_DATA022 M_DATA023 M_DATA024 M_DATA025 M_DATA026 M_DATA027 M_IDL02 M_IDH02 M_CONF02 M_STAT02 SC_STAT02 M_DLC03 M_CTRL03 M_TIME03 M_DATA030 M_DATA031 M_DATA032 M_DATA033 M_DATA034 M_DATA035 M_DATA036 M_DATA037 M_IDL03 M_IDH03 M_CONF03 M_STAT03 SC_STAT03 M_DLC04 M_CTRL04 M_TIME04 M_DATA040 M_DATA041 M_DATA042 M_DATA043 M_DATA044 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W 8 Bits 16 Bits Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Initial Value Remark n = 2, 6, A, or E 84 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION (3/15) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit xxxxn88DH xxxxn88EH xxxxn88FH xxxxn890H xxxxn882H xxxxn894H xxxxn895H xxxxn896H xxxxn8A4H xxxxn8A5H xxxxn8A6H xxxxn8A8H xxxxn8A9H xxxxn8AAH xxxxn8ABH xxxxn8ACH xxxxn8ADH xxxxn8AEH xxxxn8AFH xxxxn8B0H xxxxn8B2H xxxxn8B4H xxxxn8B5H xxxxn8B6H xxxxn8C4H xxxxn8C5H xxxxn8C6H xxxxn8C8H xxxxn8C9H xxxxn8CAH xxxxn8CBH xxxxn8CCH xxxxn8CDH xxxxn8CEH xxxxn8CFH xxxxn8D0H CAN message data register 045 CAN message data register 046 CAN message data register 047 CAN message ID register L04 CAN message ID register H04 CAN message configuration register 04 CAN message status register 04 CAN status set/clear register 04 CAN message data length register 05 CAN message control register 05 CAN message time stamp register 05 CAN message data register 050 CAN message data register 051 CAN message data register 052 CAN message data register 053 CAN message data register 054 CAN message data register 055 CAN message data register 056 CAN message data register 057 CAN message ID register L05 CAN message ID register H05 CAN message configuration register 05 CAN message status register 05 CAN status set/clear register 05 CAN message data length register 06 CAN message control register 06 CAN message time stamp register 06 CAN message data register 060 CAN message data register 061 CAN message data register 062 CAN message data register 063 CAN message data register 064 CAN message data register 065 CAN message data register 066 CAN message data register 067 CAN message ID register L06 M_DATA045 M_DATA046 M_DATA047 M_IDL04 M_IDH04 M_CONF04 M_STAT04 SC_STAT04 M_DLC05 M_CTRL05 M_TIME05 M_DATA050 M_DATA051 M_DATA052 M_DATA053 M_DATA054 M_DATA055 M_DATA056 M_DATA057 M_IDL05 M_IDH05 M_CONF05 M_STAT05 SC_STAT05 M_DLC06 M_CTRL06 M_TIME06 M_DATA060 M_DATA061 M_DATA062 M_DATA063 M_DATA064 M_DATA065 M_DATA066 M_DATA067 M_IDL06 R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 Bits 16 Bits Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Initial Value Remark n = 2, 6, A, or E User's Manual U14492EJ5V0UD 85 CHAPTER 3 CPU FUNCTION (4/15) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit xxxxn8D2H xxxxn8D4H xxxxn8D5H xxxxn8D6H xxxxn8E4H xxxxn8E5H xxxxn8E6H xxxxn8E8H xxxxn8E9H xxxxn8EAH xxxxn8EBH xxxxn8ECH xxxxn8EDH xxxxn8EEH xxxxn8EFH xxxxn8F0H xxxxn8F2H xxxxn8F4H xxxxn8F5H xxxxn8F6H xxxxn904H xxxxn905H xxxxn906H xxxxn908H xxxxn909H xxxxn90AH xxxxn90BH xxxxn90CH xxxxn90DH xxxxn90EH xxxxn90FH xxxxn910H xxxxn912H xxxxn914H xxxxn915H xxxxn916H CAN message ID register H06 CAN message configuration register 06 CAN message status register 06 CAN status set/clear register 06 CAN message data length register 07 CAN message control register 07 CAN message time stamp register 07 CAN message data register 070 CAN message data register 071 CAN message data register 072 CAN message data register 073 CAN message data register 074 CAN message data register 075 CAN message data register 076 CAN message data register 077 CAN message ID register L07 CAN message ID register H07 CAN message configuration register 07 CAN message status register 07 CAN status set/clear register 07 CAN message data length register 08 CAN message control register 08 CAN message time stamp register 08 CAN message data register 080 CAN message data register 081 CAN message data register 082 CAN message data register 083 CAN message data register 084 CAN message data register 085 CAN message data register 086 CAN message data register 087 CAN message ID register L08 CAN message ID register H08 CAN message configuration register 08 CAN message status register 08 CAN status set/clear register 08 M_IDH06 M_CONF06 M_STAT06 SC_STAT06 M_DLC07 M_CTRL07 M_TIME07 M_DATA070 M_DATA071 M_DATA072 M_DATA073 M_DATA074 M_DATA075 M_DATA076 M_DATA077 M_IDL07 M_IDH07 M_CONF07 M_STAT07 SC_STAT07 M_DLC08 M_CTRL08 M_TIME08 M_DATA080 M_DATA081 M_DATA082 M_DATA083 M_DATA084 M_DATA085 M_DATA086 M_DATA087 M_IDL08 M_IDH08 M_CONF08 M_STAT08 SC_STAT08 R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W 8 Bits 16 Bits Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Initial Value Remark n = 2, 6, A, or E 86 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION (5/15) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit xxxxn924H xxxxn925H xxxxn926H xxxxn928H xxxxn929H xxxxn92AH xxxxn92BH xxxxn92CH xxxxn92DH xxxxn92EH xxxxn92FH xxxxn930H xxxxn932H xxxxn934H xxxxn935H xxxxn936H xxxxn944H xxxxn945H xxxxn946H xxxxn948H xxxxn949H xxxxn94AH xxxxn94BH xxxxn94CH xxxxn94DH xxxxn94EH xxxxn94FH xxxxn950H xxxxn952H xxxxn954H xxxxn955H xxxxn956H xxxxn964H xxxxn965H xxxxn966H xxxxn968H CAN message data length register 09 CAN message control register 09 CAN message time stamp register 09 CAN message data register 090 CAN message data register 091 CAN message data register 092 CAN message data register 093 CAN message data register 094 CAN message data register 095 CAN message data register 096 CAN message data register 097 CAN message ID register L09 CAN message ID register H09 CAN message configuration register 09 CAN message status register 09 CAN status set/clear register 09 CAN message data length register 10 CAN message control register 10 CAN message time stamp register 10 CAN message data register 100 CAN message data register 101 CAN message data register 102 CAN message data register 103 CAN message data register 104 CAN message data register 105 CAN message data register 106 CAN message data register 107 CAN message ID register L10 CAN message ID register H10 CAN message configuration register 10 CAN message status register 10 CAN status set/clear register 10 CAN message data length register 11 CAN message control register 11 CAN message time stamp register 11 CAN message data register 110 M_DLC09 M_CTRL09 M_TIME09 M_DATA090 M_DATA091 M_DATA092 M_DATA093 M_DATA094 M_DATA095 M_DATA096 M_DATA097 M_IDL09 M_IDH09 M_CONF09 M_STAT09 SC_STAT09 M_DLC10 M_CTRL10 M_TIME10 M_DATA100 M_DATA101 M_DATA102 M_DATA103 M_DATA104 M_DATA105 M_DATA106 M_DATA107 M_IDL10 M_IDH10 M_CONF10 M_STAT10 SC_STAT10 M_DLC11 M_CTRL11 M_TIME11 M_DATA110 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W 8 Bits 16 Bits Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Initial Value Remark n = 2, 6, A, or E User's Manual U14492EJ5V0UD 87 CHAPTER 3 CPU FUNCTION (6/15) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit xxxxn969H xxxxn96AH xxxxn96BH xxxxn96CH xxxxn96DH xxxxn96EH xxxxn96FH xxxxn970H xxxxn972H xxxxn974H xxxxn975H xxxxn976H xxxxn984H xxxxn985H xxxxn986H xxxxn988H xxxxn989H xxxxn98AH xxxxn98BH xxxxn98CH xxxxn98DH xxxxn98EH xxxxn98FH xxxxn990H xxxxn992H xxxxn994H xxxxn995H xxxxn996H xxxxn9A4H xxxxn9A5H xxxxn9A6H xxxxn9A8H xxxxn9A9H xxxxn9AAH xxxxn9ABH xxxxn9ACH CAN message data register 111 CAN message data register 112 CAN message data register 113 CAN message data register 114 CAN message data register 115 CAN message data register 116 CAN message data register 117 CAN message ID register L11 CAN message ID register H11 CAN message configuration register 11 CAN message status register 11 CAN status set/clear register 11 CAN message data length register 12 CAN message control register 12 CAN message time stamp register 12 CAN message data register 120 CAN message data register 121 CAN message data register 122 CAN message data register 123 CAN message data register 124 CAN message data register 125 CAN message data register 126 CAN message data register 127 CAN message ID register L12 CAN message ID register H12 CAN message configuration register 12 CAN message status register 12 CAN status set/clear register 12 CAN message data length register 13 CAN message control register 13 CAN message time stamp register 13 CAN message data register 130 CAN message data register 131 CAN message data register 132 CAN message data register 133 CAN message data register 134 M_DATA111 M_DATA112 M_DATA113 M_DATA114 M_DATA115 M_DATA116 M_DATA117 M_IDL11 M_IDH11 M_CONF11 M_STAT11 SC_STAT11 M_DLC12 M_CTRL12 M_TIME12 M_DATA120 M_DATA121 M_DATA122 M_DATA123 M_DATA124 M_DATA125 M_DATA126 M_DATA127 M_IDL12 M_IDH12 M_CONF12 M_STAT12 SC_STAT12 M_DLC13 M_CTRL13 M_TIME13 M_DATA130 M_DATA131 M_DATA132 M_DATA133 M_DATA134 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W 8 Bits 16 Bits Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Initial Value Remark n = 2, 6, A, or E 88 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION (7/15) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit xxxxn9ADH xxxxn9AEH xxxxn9AFH xxxxn9B0H xxxxn9B2H xxxxn9B4H xxxxn9B5H xxxxn9B6H xxxxn9C4H xxxxn9C5H xxxxn9C6H xxxxn9C8H xxxxn9C9H xxxxn9CAH xxxxn9CBH xxxxn9CCH xxxxn9CDH xxxxn9CEH xxxxn9CFH xxxxn9D0H xxxxn9D2H xxxxn9D4H xxxxn9D5H xxxxn9D6H xxxxn9E4H xxxxn9E5H xxxxn9E6H xxxxn9E8H xxxxn9E9H xxxxn9EAH xxxxn9EBH xxxxn9ECH xxxxn9EDH xxxxn9EEH xxxxn9EFH xxxxn9F0H CAN message data register 135 CAN message data register 136 CAN message data register 137 CAN message ID register L13 CAN message ID register H13 CAN message configuration register 13 CAN message status register 13 CAN status set/clear register 13 CAN message data length register 14 CAN message control register 14 CAN message time stamp register 14 CAN message data register 140 CAN message data register 141 CAN message data register 142 CAN message data register 143 CAN message data register 144 CAN message data register 145 CAN message data register 146 CAN message data register 147 CAN message ID register L14 CAN message ID register H14 CAN message configuration register 14 CAN message status register 14 CAN status set/clear register 14 CAN message data length register 15 CAN message control register 15 CAN message time stamp register 15 CAN message data register 150 CAN message data register 151 CAN message data register 152 CAN message data register 153 CAN message data register 154 CAN message data register 155 CAN message data register 156 CAN message data register 157 CAN message ID register L15 M_DATA135 M_DATA136 M_DATA137 M_IDL13 M_IDH13 M_CONF13 M_STAT13 SC_STAT13 M_DLC14 M_CTRL14 M_TIME14 M_DATA140 M_DATA141 M_DATA142 M_DATA143 M_DATA144 M_DATA145 M_DATA146 M_DATA147 M_IDL14 M_IDH14 M_CONF14 M_STAT14 SC_STAT14 M_DLC15 M_CTRL15 M_TIME15 M_DATA150 M_DATA151 M_DATA152 M_DATA153 M_DATA154 M_DATA155 M_DATA156 M_DATA157 M_IDL15 R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 Bits 16 Bits Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Initial Value Remark n = 2, 6, A, or E User's Manual U14492EJ5V0UD 89 CHAPTER 3 CPU FUNCTION (8/15) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit xxxxn9F2H xxxxn9F4H xxxxn9F5H xxxxn9F6H xxxxnA04H xxxxnA05H xxxxnA06H xxxxnA08H xxxxnA09H xxxxnA0AH xxxxnA0BH xxxxnA0CH xxxxnA0DH xxxxnA0EH xxxxnA0FH xxxxnA10H xxxxnA12H xxxxnA14H xxxxnA15H xxxxnA16H xxxxnA24H xxxxnA25H xxxxnA26H xxxxnA28H xxxxnA29H xxxxnA2AH xxxxnA2BH xxxxnA2CH xxxxnA2DH xxxxnA2EH xxxxnA2FH xxxxnA30H xxxxnA32H xxxxnA34H xxxxnA35H xxxxnA36H CAN message ID register H15 CAN message configuration register 15 CAN message status register 15 CAN status set/clear register 15 CAN message data length register 16 CAN message control register 16 CAN message time stamp register 16 CAN message data register 160 CAN message data register 161 CAN message data register 162 CAN message data register 163 CAN message data register 164 CAN message data register 165 CAN message data register 166 CAN message data register 167 CAN message ID register L16 CAN message ID register H16 CAN message configuration register 16 CAN message status register 16 CAN status set/clear register 16 CAN message data length register 17 CAN message control register 17 CAN message time stamp register 17 CAN message data register 170 CAN message data register 171 CAN message data register 172 CAN message data register 173 CAN message data register 174 CAN message data register 175 CAN message data register 176 CAN message data register 177 CAN message ID register L17 CAN message ID register H17 CAN message configuration register 17 CAN message status register 17 CAN status set/clear register 17 M_IDH15 M_CONF15 M_STAT15 SC_STAT15 M_DLC16 M_CTRL16 M_TIME16 M_DATA160 M_DATA161 M_DATA162 M_DATA163 M_DATA164 M_DATA165 M_DATA166 M_DATA167 M_IDL16 M_IDH16 M_CONF16 M_STAT16 SC_STAT16 M_DLC17 M_CTRL17 M_TIME17 M_DATA170 M_DATA171 M_DATA172 M_DATA173 M_DATA174 M_DATA175 M_DATA176 M_DATA177 M_IDL17 M_IDH17 M_CONF17 M_STAT17 SC_STAT17 R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W 8 Bits 16 Bits Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Initial Value Remark n = 2, 6, A, or E 90 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION (9/15) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit xxxxnA44H xxxxnA45H xxxxnA46H xxxxnA48H xxxxnA49H xxxxnA4AH xxxxnA4BH xxxxnA4CH xxxxnA4DH xxxxnA4EH xxxxnA4FH xxxxnA50H xxxxnA52H xxxxnA54H xxxxnA55H xxxxnA56H xxxxnA64H xxxxnA65H xxxxnA66H xxxxnA68H xxxxnA69H xxxxnA6AH xxxxnA6BH xxxxnA6CH xxxxnA6DH xxxxnA6EH xxxxnA6FH xxxxnA70H xxxxnA72H xxxxnA74H xxxxnA75H xxxxnA76H xxxxnA84H xxxxnA85H xxxxnA86H xxxxnA88H CAN message data length register 18 CAN message control register 18 CAN message time stamp register 18 CAN message data register 180 CAN message data register 181 CAN message data register 182 CAN message data register 183 CAN message data register 184 CAN message data register 185 CAN message data register 186 CAN message data register 187 CAN message ID register L18 CAN message ID register H18 CAN message configuration register 18 CAN message status register 18 CAN status set/clear register 18 CAN message data length register 19 CAN message control register 19 CAN message time stamp register 19 CAN message data register 190 CAN message data register 191 CAN message data register 192 CAN message data register 193 CAN message data register 194 CAN message data register 195 CAN message data register 196 CAN message data register 197 CAN message ID register L19 CAN message ID register H19 CAN message configuration register 19 CAN message status register 19 CAN status set/clear register 19 CAN message data length register 20 CAN message control register 20 CAN message time stamp register 20 CAN message data register 200 M_DLC18 M_CTRL18 M_TIME18 M_DATA180 M_DATA181 M_DATA182 M_DATA183 M_DATA184 M_DATA185 M_DATA186 M_DATA187 M_IDL18 M_IDH18 M_CONF18 M_STAT18 SC_STAT18 M_DLC19 M_CTRL19 M_TIME19 M_DATA190 M_DATA191 M_DATA192 M_DATA193 M_DATA194 M_DATA195 M_DATA196 M_DATA197 M_IDL19 M_IDH19 M_CONF19 M_STAT19 SC_STAT19 M_DLC20 M_CTRL20 M_TIME20 M_DATA200 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W 8 Bits 16 Bits Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Initial Value Remark n = 2, 6, A, or E User's Manual U14492EJ5V0UD 91 CHAPTER 3 CPU FUNCTION (10/15) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit xxxxnA89H xxxxnA8AH xxxxnA8BH xxxxnA8CH xxxxnA8DH xxxxnA8EH xxxxnA8FH xxxxnA90H xxxxnA92H xxxxnA94H xxxxnA95H xxxxnA96H xxxxnAA4H xxxxnAA5H xxxxnAA6H xxxxnAA8H xxxxnAA9H xxxxnAAAH xxxxnAABH xxxxnAACH xxxxnAADH xxxxnAAEH xxxxnAAFH xxxxnAB0H xxxxnAB2H xxxxnAB4H xxxxnAB5H xxxxnAB6H xxxxnAC4H xxxxnAC5H xxxxnAC6H xxxxnAC8H xxxxnAC9H xxxxnACAH xxxxnACBH xxxxnACCH CAN message data register 201 CAN message data register 202 CAN message data register 203 CAN message data register 204 CAN message data register 205 CAN message data register 206 CAN message data register 207 CAN message ID register L20 CAN message ID register H20 CAN message configuration register 20 CAN message status register 20 CAN status set/clear register 20 CAN message data length register 21 CAN message control register 21 CAN message time stamp register 21 CAN message data register 210 CAN message data register 211 CAN message data register 212 CAN message data register 213 CAN message data register 214 CAN message data register 215 CAN message data register 216 CAN message data register 217 CAN message ID register L21 CAN message ID register H21 CAN message configuration register 21 CAN message status register 21 CAN status set/clear register 21 CAN message data length register 22 CAN message control register 22 CAN message time stamp register 22 CAN message data register 220 CAN message data register 221 CAN message data register 222 CAN message data register 223 CAN message data register 224 M_DATA201 M_DATA202 M_DATA203 M_DATA204 M_DATA205 M_DATA206 M_DATA207 M_IDL20 M_IDH20 M_CONF20 M_STAT20 SC_STAT20 M_DLC21 M_CTRL21 M_TIME21 M_DATA210 M_DATA211 M_DATA212 M_DATA213 M_DATA214 M_DATA215 M_DATA216 M_DATA217 M_IDL21 M_IDH21 M_CONF21 M_STAT21 SC_STAT21 M_DLC22 M_CTRL22 M_TIME22 M_DATA220 M_DATA221 M_DATA222 M_DATA223 M_DATA224 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W 8 Bits 16 Bits Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Initial Value Remark n = 2, 6, A, or E 92 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION (11/15) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit xxxxnACDH xxxxnACEH xxxxnACFH xxxxnAD0H xxxxnAD2H xxxxnAD4H xxxxnAD5H xxxxnAD6H xxxxnAE4H xxxxnAE5H xxxxnAE6H xxxxnAE8H xxxxnAE9H xxxxnAEAH xxxxnAEBH xxxxnAECH xxxxnAEDH xxxxnAEEH xxxxnAEFH xxxxnAF0H xxxxnAF2H xxxxnAF4H xxxxnAF5H xxxxnAF6H xxxxnB04H xxxxnB05H xxxxnB06H xxxxnB08H xxxxnB09H xxxxnB0AH xxxxnB0BH xxxxnB0CH xxxxnB0DH xxxxnB0EH xxxxnB0FH xxxxnB10H CAN message data register 225 CAN message data register 226 CAN message data register 227 CAN message ID register L22 CAN message ID register H22 CAN message configuration register 22 CAN message status register 22 CAN status set/clear register 22 CAN message data length register 23 CAN message control register 23 CAN message time stamp register 23 CAN message data register 230 CAN message data register 231 CAN message data register 232 CAN message data register 233 CAN message data register 234 CAN message data register 235 CAN message data register 236 CAN message data register 237 CAN message ID register L23 CAN message ID register H23 CAN message configuration register 23 CAN message status register 23 CAN status set/clear register 23 CAN message data length register 24 CAN message control register 24 CAN message time stamp register 24 CAN message data register 240 CAN message data register 241 CAN message data register 242 CAN message data register 243 CAN message data register 244 CAN message data register 245 CAN message data register 246 CAN message data register 247 CAN message ID register L24 M_DATA225 M_DATA226 M_DATA227 M_IDL22 M_IDH22 M_CONF22 M_STAT22 SC_STAT22 M_DLC23 M_CTRL23 M_TIME23 M_DATA230 M_DATA231 M_DATA232 M_DATA233 M_DATA234 M_DATA235 M_DATA236 M_DATA237 M_IDL23 M_IDH23 M_CONF23 M_STAT23 SC_STAT23 M_DLC24 M_CTRL24 M_TIME24 M_DATA240 M_DATA241 M_DATA242 M_DATA243 M_DATA244 M_DATA245 M_DATA246 M_DATA247 M_IDL24 R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 8 Bits 16 Bits Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Initial Value Remark n = 2, 6, A, or E User's Manual U14492EJ5V0UD 93 CHAPTER 3 CPU FUNCTION (12/15) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit xxxxnB12H xxxxnB14H xxxxnB15H xxxxnB16H xxxxnB24H xxxxnB25H xxxxnB26H xxxxnB28H xxxxnB29H xxxxnB2AH xxxxnB2BH xxxxnB2CH xxxxnB2DH xxxxnB2EH xxxxnB2FH xxxxnB30H xxxxnB32H xxxxnB34H xxxxnB35H xxxxnB36H xxxxnB44H xxxxnB45H xxxxnB46H xxxxnB48H xxxxnB49H xxxxnB4AH xxxxnB4BH xxxxnB4CH xxxxnB4DH xxxxnB4EH xxxxnB4FH xxxxnB50H xxxxnB52H xxxxnB54H xxxxnB55H xxxxnB56H CAN message ID register H24 CAN message configuration register 24 CAN message status register 24 CAN status set/clear register 24 CAN message data length register 25 CAN message control register 25 CAN message time stamp register 25 CAN message data register 250 CAN message data register 251 CAN message data register 252 CAN message data register 253 CAN message data register 254 CAN message data register 255 CAN message data register 256 CAN message data register 257 CAN message ID register L25 CAN message ID register H25 CAN message configuration register 25 CAN message status register 25 CAN status set/clear register 25 CAN message data length register 26 CAN message control register 26 CAN message time stamp register 26 CAN message data register 260 CAN message data register 261 CAN message data register 262 CAN message data register 263 CAN message data register 264 CAN message data register 265 CAN message data register 266 CAN message data register 267 CAN message ID register L26 CAN message ID register H26 CAN message configuration register 26 CAN message status register 26 CAN status set/clear register 26 M_IDH24 M_CONF24 M_STAT24 SC_STAT24 M_DLC25 M_CTRL25 M_TIME25 M_DATA250 M_DATA251 M_DATA252 M_DATA253 M_DATA254 M_DATA255 M_DATA256 M_DATA257 M_IDL25 M_IDH25 M_CONF25 M_STAT25 SC_STAT25 M_DLC26 M_CTRL26 M_TIME26 M_DATA260 M_DATA261 M_DATA262 M_DATA263 M_DATA264 M_DATA265 M_DATA266 M_DATA267 M_IDL26 M_IDH26 M_CONF26 M_STAT26 SC_STAT26 R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W 8 Bits 16 Bits Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Initial Value Remark n = 2, 6, A, or E 94 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION (13/15) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit xxxxnB64H xxxxnB65H xxxxnB66H xxxxnB68H xxxxnB69H xxxxnB6AH xxxxnB6BH xxxxnB6CH xxxxnB6DH xxxxnB6EH xxxxnB6FH xxxxnB70H xxxxnB72H xxxxnB74H xxxxnB75H xxxxnB76H xxxxnB84H xxxxnB85H xxxxnB86H xxxxnB88H xxxxnB89H xxxxnB8AH xxxxnB8BH xxxxnB8CH xxxxnB8DH xxxxnB8EH xxxxnB8FH xxxxnB90H xxxxnB92H xxxxnB94H xxxxnB95H xxxxnB96H xxxxnBA4H xxxxnBA5H xxxxnBA6H xxxxnBA8H CAN message data length register 27 CAN message control register 27 CAN message time stamp register 27 CAN message data register 270 CAN message data register 271 CAN message data register 272 CAN message data register 273 CAN message data register 274 CAN message data register 275 CAN message data register 276 CAN message data register 277 CAN message ID register L27 CAN message ID register H27 CAN message configuration register 27 CAN message status register 27 CAN status set/clear register 27 CAN message data length register 28 CAN message control register 28 CAN message time stamp register 28 CAN message data register 280 CAN message data register 281 CAN message data register 282 CAN message data register 283 CAN message data register 284 CAN message data register 285 CAN message data register 286 CAN message data register 287 CAN message ID register L28 CAN message ID register H28 CAN message configuration register 28 CAN message status register 28 CAN status set/clear register 28 CAN message data length register 29 CAN message control register 29 CAN message time stamp register 29 CAN message data register 290 M_DLC27 M_CTRL27 M_TIME27 M_DATA270 M_DATA271 M_DATA272 M_DATA273 M_DATA274 M_DATA275 M_DATA276 M_DATA277 M_IDL27 M_IDH27 M_CONF27 M_STAT27 SC_STAT27 M_DLC28 M_CTRL28 M_TIME28 M_DATA280 M_DATA281 M_DATA282 M_DATA283 M_DATA284 M_DATA285 M_DATA286 M_DATA287 M_IDL28 M_IDH28 M_CONF28 M_STAT28 SC_STAT28 M_DLC29 M_CTRL29 M_TIME29 M_DATA290 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W 8 Bits 16 Bits Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Initial Value Remark n = 2, 6, A, or E User's Manual U14492EJ5V0UD 95 CHAPTER 3 CPU FUNCTION (14/15) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit xxxxnBA9H xxxxnBAAH xxxxnBABH xxxxnBACH xxxxnBADH xxxxnBAEH xxxxnBAFH xxxxnBB0H xxxxnBB2H xxxxnBB4H xxxxnBB5H xxxxnBB6H xxxxnBC4H xxxxnBC5H xxxxnBC6H xxxxnBC8H xxxxnBC9H xxxxnBCAH xxxxnBCBH xxxxnBCCH xxxxnBCDH xxxxnBCEH xxxxnBCFH xxxxnBD0H xxxxnBD2H xxxxnBD4H xxxxnBD5H xxxxnBD6H xxxxnBE4H xxxxnBE5H xxxxnBE6H xxxxnBE8H xxxxnBE9H xxxxnBEAH xxxxnBEBH xxxxnBECH CAN message data register 291 CAN message data register 292 CAN message data register 293 CAN message data register 294 CAN message data register 295 CAN message data register 296 CAN message data register 297 CAN message ID register L29 CAN message ID register H29 CAN message configuration register 29 CAN message status register 29 CAN status set/clear register 29 CAN message data length register 30 CAN message control register 30 CAN message time stamp register 30 CAN message data register 300 CAN message data register 301 CAN message data register 302 CAN message data register 303 CAN message data register 304 CAN message data register 305 CAN message data register 306 CAN message data register 307 CAN message ID register L30 CAN message ID register H30 CAN message configuration register 30 CAN message status register 30 CAN status set/clear register 30 CAN message data length register 31 CAN message control register 31 CAN message time stamp register 31 CAN message data register 310 CAN message data register 311 CAN message data register 312 CAN message data register 313 CAN message data register 314 M_DATA291 M_DATA292 M_DATA293 M_DATA294 M_DATA295 M_DATA296 M_DATA297 M_IDL29 M_IDH29 M_CONF29 M_STAT29 SC_STAT29 M_DLC30 M_CTRL30 M_TIME30 M_DATA300 M_DATA301 M_DATA302 M_DATA303 M_DATA304 M_DATA305 M_DATA306 M_DATA307 M_IDL30 M_IDH30 M_CONF30 M_STAT30 SC_STAT30 M_DLC31 M_CTRL31 M_TIME31 M_DATA310 M_DATA311 M_DATA312 M_DATA313 M_DATA314 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W R/W 8 Bits 16 Bits Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Initial Value Remark n = 2, 6, A, or E 96 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION (15/15) Address Function Register Name Symbol R/W Bit Units for Manipulation 1 Bit xxxxnBEDH xxxxnBEEH xxxxnBEFH xxxxnBF0H xxxxnBF2H xxxxnBF4H xxxxnBF5H xxxxnBF6H xxxxnC00H xxxxnC02H xxxxnC04H xxxxnC0CH xxxxnC10H xxxxnC12H xxxxnC14H xxxxnC18H xxxxnC1AH CAN message data register 315 CAN message data register 316 CAN message data register 317 CAN message ID register L31 CAN message ID register H31 CAN message configuration register 31 CAN message status register 31 CAN status set/clear register 31 CAN interrupt pending register CAN global interrupt pending register CAN1 interrupt pending register CAN stop register CAN global status register CAN global interrupt enable register CAN main clock selection register CAN time stamp count register CAN message search start register CAN message search result register xxxxnC40H xxxxnC42H xxxxnC44H xxxxnC46H xxxxnC48H xxxxnC4AH xxxxnC4CH xxxxnC4EH xxxxnC50H xxxxnC52H xxxxnC54H xxxxnC56H xxxxnC58H xxxxnC5AH xxxxnC5CH CAN1 address mask 0 register L CAN1 address mask 0 register H CAN1 address mask 1 register L CAN1 address mask 1 register H CAN1 address mask 2 register L CAN1 address mask 2 register H CAN1 address mask 3 register L CAN1 address mask 3 register H CAN1 control register CAN1 definition register CAN1 information register CAN1 error count register CAN1 interrupt enable register CAN1 bus active register CAN1 bit rate prescaler register CAN1 bus diagnostic information register xxxxnC5EH CAN1 synchronization control register M_DATA315 M_DATA316 M_DATA317 M_IDL31 M_IDH31 M_CONF31 M_STAT31 SC_STAT31 CCINTP CGINTP C1INTP CSTOP CGST CGIE CGCS CGTSC CGMSS CGMSR C1MASKL0 C1MASKH0 C1MASKL1 C1MASKH1 C1MASKL2 C1MASKH2 C1MASKL3 C1MASKH3 C1CTRL C1DEF C1LAST C1ERC C1IE C1BA C1BRP C1DINF C1SYNC R/W R/W R/W R/W R/W R/W R W R R/W R/W R/W R/W R/W R/W R W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R R/W R R/W 8 Bits 16 Bits Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H 0000H 00H 00H 0000H 0100H 0A00H 7F05H 0000H 0000H 0000H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0101H 0000H 00FFH 0000H 0900H 00FFH 0000H 0000H 0218H Initial Value Remark n = 2, 6, A, or E User's Manual U14492EJ5V0UD 97 CHAPTER 3 CPU FUNCTION 3.4.10 Specific registers Specific registers are registers that are protected from being written with illegal data due to inadvertent program loop (runaway), etc. The V850E/IA1 has three specific registers, the power save control register (PSC) (refer to 8.5.2 (13) Power save control register (PSC)), clock control register (CKC) (refer to 8.3.4 Clock control register (CKC)), and flash programming mode control register (FLPMC) (refer to 16.7.12 Flash programming mode control register (FLPMC)). 3.4.11 System wait control register (VSWC) Set the value shown below to this register. This register can be read/written in 8-bit units (address: FFFFF06EH, initial value: 77H). Remark If the timing of changing the flag or count value conflicts with the timing of accessing a register when a register including a status flag that indicates the status of an on-chip peripheral function (such as ASIF0) or a register indicating the count value of a timer (such as TM0n) is accessed, a register access retry operation is performed. As a result, a longer time may be required to access the on-chip peripheral I/O register. Register Name System wait control register (VSWC) When PRM02 register = 01H When PRM02 register = 00H VSWC Set Value 12H (3 clocks are set for the wait) 15H (6 clocks are set for the wait) 3.4.12 Cautions (1) Register to be set first When using the V850E/IA1, the following registers must be set from the beginning. * System wait control register (VSWC) (See 3.4.11 System wait control register (VSWC)) * Clock control register (CKC) (See 8.3.4 Clock control register (CKC)) After setting VSWC and CKC, set other registers as required. 98 User's Manual U14492EJ5V0UD CHAPTER 3 CPU FUNCTION (2) Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1> may not be stored in a register. Instruction <1> * ld instruction: * sld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu sld.b, sld.h, sld.w, sld.bu, sld.hu * Multiplication instruction: mul, mulh, mulhi, mulu Instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 * * * not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 If the decode operation of the mov instruction User's Manual U14492EJ5V0UD 99 CHAPTER 4 BUS CONTROL FUNCTION The V850E/IA1 is provided with an external bus interface function by which external I/O and memories, such as ROM and RAM, can be connected. 4.1 Features * 16-bit/8-bit data bus sizing function * 8-space chip select function * Wait function * Programmable wait function, through which up to 7 wait states can be inserted for each memory block * External wait function via WAIT pin * Idle state insertion function * Bus hold function * External device connection enabled via bus control/port alternate function pins 4.2 Bus Control Pins The following pins are used for connection to external devices. Bus Control Pin (Function When in Control Mode) Function When in Port Mode Register for Port/Control Mode Switching Address/data bus (AD0 to AD15) Address bus (A16 to A23) Chip select (CS0 to CS7) Read/write control (LWR/UWR, RD, ASTB) PDL0 to PDL15 (Port DL) PDH0 to PDH7 (Port DH) PCS0 to PCS7 (Port CS) PCT0, PCT1, PCT4, PCT6 (Port CT) PCM0 (Port CM) PCM1 (Port CM) PCM2, PCM3 (Port CM) PMCDL PMCDH PMCCS PMCCT External wait control (WAIT) Internal system clock (CLKOUT) Bus hold control (HLDRQ, HLDAK) PMCCM Remark In the case of single-chip mode 1 and ROMless modes 0 and 1, when the system is reset, each bus control pin becomes unconditionally valid. 4.2.1 Pin status during internal ROM, internal RAM, and on-chip peripheral I/O access When the internal ROM and RAM are accessed, both the address bus and address/data bus become undefined. The external bus control signal becomes inactive. When on-chip peripheral I/O are accessed, both the address bus and address/data bus output the addresses of the on-chip peripheral I/O currently being accessed. No data is output. The external bus control signal becomes inactive. 100 User's Manual U14492EJ5V0UD CHAPTER 4 BUS CONTROL FUNCTION 4.3 Memory Block Function The 256 MB memory space is divided into memory blocks of 2 MB and 64 MB units. The programmable wait function and bus cycle operation mode can be independently controlled for each block. The area that can be used as program area is the 64 MB space of addresses 0000000H to 3FFFFFFH. FFFFFFFH FE00000H FDFFFFFH CS7, CS6, CS5 Area 3 FC00000H FBFFFFFH FA00000H F9FFFFFH F800000H F7FFFFFH CS6 C000000H BFFFFFFH Block 7 (2 MB) Block 6 (2 MB) Block 5 (2 MB) Block 4 (2 MB) FFFFFFFH On-chip peripheral I/O area (4 KB) FFFF000H FFFEFFFH Internal RAM area (12 KBNote 1) FFFC000H External memory area CS4 Area 2 8000000H 7FFFFFFH 64 MB CS3 Area 1 4000000H 3FFFFFFH 64 MB CS1 0800000H 07FFFFFH 0600000H 05FFFFFH 0400000H 03FFFFFH 0200000H 01FFFFFH 0000000H Block 3 (2 MB) Block 2 (2 MB) Block 1 (2 MB) Block 0 (2 MB) 3FFFFFFH On-chip peripheral I/O area (4 KB)Note 2 3FFF000H 3FFEFFFH Internal RAM area (12 KBNote 1) 3FFC000H External memory area Area 0 CS2, CS1, CS0 00FFFFFH Internal ROM area (1 MB)Note 3 0000000H Notes 1. 2. 3. Physical internal RAM: 10 KB Access to this area is prohibited. addresses FFFF000H to FFFFFFFH. When in single-chip mode 1 and ROMless modes 0 and 1, this becomes an external memory area. When in single-chip mode 1, addresses 0100000H to 01FFFFFH become an internal ROM area. To access the on-chip peripheral I/O in this area, specify User's Manual U14492EJ5V0UD 101 CHAPTER 4 BUS CONTROL FUNCTION 4.3.1 Chip select control function Of the 256 MB memory area, the lower 8 MB (0000000H to 07FFFFFH) and the higher 8 MB (F800000H to FFFFFFFH) can be divided into 2 MB memory blocks by chip area selection control registers 0 and 1 (CSC0, CSC1) to control the chip select signal. The memory area can be effectively used by dividing it into memory blocks using the chip select control function. The priority order is described below. (1) Chip area selection control registers 0, 1 (CSC0, CSC1) These registers can be read/written in 16-bit units and become valid by setting each bit to 1. If different chip select signal outputs are set to the same block, the priority order is controlled as follows. CSC0: CS0 > CS2 > CS1 CSC1: CS7 > CS5 > CS6 If both the CS0m and CS2m bits of the CSC0 register are set to 0, CS1 is output to the corresponding block (m = 0 to 3). Similarly, if both the CS5m and CS7m bits of the CSC1 register are set to 0, CS6 is output to the corresponding block (m = 0 to 3). Caution Write to the CSC0 and CSC1 registers after reset, and then do not change the set values. 102 User's Manual U14492EJ5V0UD CHAPTER 4 BUS CONTROL FUNCTION 15 CSC0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF060H Initial value 2C11H CS33 CS32 CS31 CS30 CS23 CS22 CS21 CS20 CS13 CS12 CS11 CS10 CS03 CS02 CS01 CS00 15 CSC1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF062H Initial value 2C11H CS43 CS42 CS41 CS40 CS53 CS52 CS51 CS50 CS63 CS62 CS61 CS60 CS73 CS72 CS71 CS70 Bit position 15 to 0 Bit name CSnm (n = 0 to 7) (m = 0 to 3) CS00 CS01 CS02 CS03 CS10 to CS13 CS20 CS21 CS22 CS23 CS30 to CS33 CS40 to CS43 CS50 CS51 CS52 CS53 CS60 to CS63 CS70 CS71 CS72 CS73 Function Chip select enabled by setting CSnm bit to 1. CSnm CS operation CS0 output during block 0 access CS0 output during block 1 access CS0 output during block 2 access CS0 output during block 3 access Note 1 CS2 output during block 0 access CS2 output during block 1 access CS2 output during block 2 access CS2 output during block 3 access Note 2 Note 3 CS5 output during block 7 access CS5 output during block 6 access CS5 output during block 5 access CS5 output during block 4 access Note 4 CS7 output during block 7 access CS7 output during block 6 access CS7 output during block 5 access CS7 output during block 4 access Notes 1. 2. 3. 4. If both the CS0m and CS2m bits have been set to 0, if area 0 is accessed, CS1 will be output regardless of the setting of the CS1m bit. When area 1 is accessed, CS3 will be output regardless of the setting of the CS3m bit. When area 2 is accessed, CS4 will be output regardless of the setting of the CS4m bit. If both the CS5m and CS7m bits have been set to 0, if area 3 is accessed, CS6 will be output regardless of the setting of the CS6m bit. User's Manual U14492EJ5V0UD 103 CHAPTER 4 BUS CONTROL FUNCTION The following diagram shows the CS signal, which is enabled for area 0 when the CSC0 register is set to 0703H. When the CSC0 register is set to 0703H, CS0 and CS2 are output to block 0 and block 1, but since CS0 has priority over CS2, CS0 is output if the addresses of block 0 and block 1 are accessed. If the address of block 3 is accessed, both the CS03 and CS23 bits of the CSC0 register are 0, and CS1 is output. Figure 4-1. Example When CSC0 Register Is Set to 0703H 3FFFFFFH 58 MB CS1 is output. 0800000H 07FFFFFH Block 3 (2 MB) 0600000H 05FFFFFH 2 MB 0400000H 03FFFFFH Block 2 (2 MB) CS2 is output. Block 1 (2 MB) 4 MB 0200000H 01FFFFFH Block 0 (2 MB) 0000000H CS0 is output. 104 User's Manual U14492EJ5V0UD CHAPTER 4 BUS CONTROL FUNCTION 4.4 Bus Cycle Type Control Function In the V850E/IA1, the following external devices can be connected directly to each memory block. * SRAM, external ROM, external I/O Connected external devices are specified by bus cycle type configuration registers 0, 1 (BCT0, BCT1). (1) Bus cycle type configuration registers 0, 1 (BCT0, BCT1) These registers can be read/written in 16-bit units. Caution Write to the BCT0 and BCT1 registers after reset, and then do not change the set values. Also, do not access an external memory area other than the one for this initialization routine until the initial setting of the BCT0 and BCT1 registers is complete. However, it is possible to access external memory areas whose initial settings are complete. 15 BCT0 ME3 14 1 13 0 12 11 10 1 9 0 8 0 7 6 5 0 4 3 2 1 0 0 0 Address FFFFF480H Initial value CCCCH 0 ME2 CS2 ME1 1 CS1 0 ME0 1 CS0 CSn signal CS3 15 BCT1 ME7 14 1 13 0 12 11 10 9 0 8 7 6 5 0 4 0 3 2 1 0 0 0 Address FFFFF482H Initial value CCCCH 0 ME6 1 CS6 0 ME5 1 CS5 ME4 1 CS4 CSn signal CS7 Bit position 15, 11, 7, 3 (BCT0), 15, 11, 7, 3 (BCT1) Bit name MEn (n = 0 to 7) MEn 0 1 Function Sets memory controller operation enable for each chip select Note . Memory controller operation enable Operation disabled Operation enabled Note Set the BCT1.ME6 and BCT1.ME5 bits to 11B (operation enable) when an external memory is connected to the CS5 area or CS6 area. Set the PMCCS register to x01xxxxxB when only CS5 is connected to the external memory and CS6 is used as a port (PCS6), and set the PMCCS register to x10xxxxxB when only CS6 is connected to the external memory and CS5 is used as a port (PCS5). User's Manual U14492EJ5V0UD 105 CHAPTER 4 BUS CONTROL FUNCTION 4.5 Bus Access 4.5.1 Number of access clocks The number of base clocks required to access each resource is shown below. Bus Cycle Status Resource (Bus Width) Internal ROM (32 bits) Internal RAM (32 bits) On-chip peripheral I/O (16 bits) Programmable peripheral I/O External memory (16 bits) 3 1 Note 1 Instruction Fetch Operand Data Access 5 1 5 5 3 Note 3 1 Note 2 - - Note 3 Note 3 Note 3 Notes 1. 2. 3. Remark This value is 2 in the case of instruction branch This value is 2 if there is contention with data access. MIN. value Unit: Clock/access 106 User's Manual U14492EJ5V0UD CHAPTER 4 BUS CONTROL FUNCTION 4.5.2 Bus sizing function The bus sizing function controls the data bus width for each CS space. The data bus width is specified by using the bus size configuration register (BSC). (1) Bus size configuration register (BSC) This register can be read/written in 16-bit units. Cautions 1. Write to the BSC register after reset, and then do not change the set values. Also, do not access an external memory area other than the one for this initialization routine until the initial setting of the BSC register is complete. However, it is possible to access external memory areas whose initial settings are complete. 2. When the data bus width is specified as 8 bits, only the signals shown below become active. LWR: When accessing SRAM, external ROM, or external I/O (write cycle) 15 BSC CSn signal 0 14 BS70 CS7 13 0 12 BS60 CS6 11 0 10 BS50 CS5 9 0 8 BS40 CS4 7 0 6 BS30 CS3 5 0 4 BS20 CS2 3 0 2 BS10 CS1 1 0 0 BS00 CS0 Address FFFFF066H Initial valueNote 0000H/5555H Note When in single-chip mode 0, 1: 5555H When in ROMless mode 0: When in ROMless mode 1: Bit position 14, 12, 10, 8, 6, 4, 2, 0 Bit name BSn0 (n = 0 to 7) BSn0 0 1 8 bits 16 bits Data bus width of CSn space 5555H 0000H Function Sets the data bus width of CSn space. 4.5.3 Word data processing format The word data in memory can be processed using the little endian method for CS space selected with a chip select signal (CS0 to CS7). User's Manual U14492EJ5V0UD 107 CHAPTER 4 BUS CONTROL FUNCTION 4.5.4 Bus width The V850E/IA1 accesses on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The following shows the operation for each type of access. Access all data in order starting from the lower side. (1) Byte access (8 bits) (a) When the data bus width is 16 bits (little endian) <1> Access to even address (2n) Address 15 <2> Access to odd address (2n + 1) Address 15 2n + 1 7 8 7 2n 7 8 7 0 Byte data 0 External data bus 0 Byte data 0 External data bus (b) When the data bus width is 8 bits (little endian) <1> Access to even address (2n) Address 7 7 2n 0 Byte data 0 External data bus <2> Access to odd address (2n + 1) Address 7 7 2n + 1 0 Byte data 0 External data bus 108 User's Manual U14492EJ5V0UD CHAPTER 4 BUS CONTROL FUNCTION (2) Halfword access (16 bits) (a) When the data bus width is 16 bits (little endian) <1> Access to even address (2n) <2> Access to odd address (2n + 1) 1st access 2nd access Address 15 2n + 1 8 7 8 7 2n 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus 8 7 8 7 2n + 2 15 Address 15 15 2n + 1 8 7 8 7 2n 0 Halfword data 0 External data bus 15 15 Address (b) When the data bus width is 8 bits (little endian) <1> Access to even address (2n) 1st access 15 Address 7 2n 0 Halfword data 0 External data bus 0 Halfword data 0 External data bus 15 Address 7 2n + 1 0 Halfword data <2> Access to odd address (2n + 1) 1st access 15 Address 7 2n + 1 0 External data bus 0 Halfword data 0 External data bus 15 Address 7 2n + 2 2nd access 2nd access 8 7 8 7 8 7 8 7 User's Manual U14492EJ5V0UD 109 CHAPTER 4 BUS CONTROL FUNCTION (3) Word access (32 bits) (a) When the data bus width is 16 bits (little endian) (1/2) <1> Access to address (4n) 1st access 31 31 2nd access 24 23 Address 15 4n + 1 8 7 8 7 4n 0 Word data 0 External data bus 24 23 Address 15 4n + 3 8 7 8 7 4n + 2 0 Word data 0 External data bus 16 15 16 15 <2> Access to address (4n + 1) 1st access 31 31 2nd access 31 3rd access 24 23 Address 15 4n + 1 8 7 8 7 24 23 Address 15 4n + 3 8 7 8 7 4n + 2 24 23 Address 15 16 15 16 15 16 15 8 7 8 7 4n + 4 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus 110 User's Manual U14492EJ5V0UD CHAPTER 4 BUS CONTROL FUNCTION (a) When the data bus width is 16 bits (little endian) (2/2) <3> Access to address (4n + 2) 1st access 31 31 2nd access 24 23 Address 15 4n + 3 8 7 8 7 4n + 2 0 Word data 0 External data bus 24 23 Address 15 4n + 5 8 7 8 7 4n + 4 0 Word data 0 External data bus 16 15 16 15 <4> Access to address (4n + 3) 1st access 31 31 2nd access 31 3rd access 24 23 Address 15 4n + 3 8 7 8 7 24 23 Address 15 4n + 5 8 7 8 7 4n + 4 24 23 Address 15 16 15 16 15 16 15 8 7 8 7 4n + 6 0 Word data 0 External data bus 0 Word data 0 External data bus 0 Word data 0 External data bus User's Manual U14492EJ5V0UD 111 CHAPTER 4 BUS CONTROL FUNCTION (b) When the data bus width is 8 bits (little endian) (1/2) <1> Access to address (4n) 1st access 31 31 2nd access 31 3rd access 31 4th access 24 23 24 23 24 23 24 23 16 15 Address 7 4n 0 Word data 0 External data bus 16 15 Address 7 4n + 1 0 Word data 0 External data bus 16 15 Address 7 4n + 2 0 Word data 0 External data bus 16 15 Address 7 4n + 3 0 Word data 0 External data bus 8 7 8 7 8 7 8 7 <2> Access to address (4n + 1) 1st access 31 31 2nd access 31 3rd access 31 4th access 24 23 24 23 24 23 24 23 16 15 Address 7 4n + 1 0 Word data 0 External data bus 16 15 Address 7 4n + 2 0 Word data 0 External data bus 16 15 Address 7 4n + 3 0 Word data 0 External data bus 16 15 Address 7 4n + 4 0 Word data 0 External data bus 8 7 8 7 8 7 8 7 112 User's Manual U14492EJ5V0UD CHAPTER 4 BUS CONTROL FUNCTION (b) When the data bus width is 8 bits (little endian) (2/2) <3> Access to address (4n + 2) 1st access 31 31 2nd access 31 3rd access 31 4th access 24 23 24 23 24 23 24 23 16 15 Address 7 4n + 2 0 Word data 0 External data bus 16 15 Address 7 4n + 3 0 Word data 0 External data bus 16 15 Address 7 4n + 4 0 Word data 0 External data bus 16 15 Address 7 4n + 5 0 Word data 0 External data bus 8 7 8 7 8 7 8 7 <4> Access to address (4n + 3) 1st access 31 31 2nd access 31 3rd access 31 4th access 24 23 24 23 24 23 24 23 16 15 Address 7 4n + 3 0 Word data 0 External data bus 16 15 Address 7 4n + 4 0 Word data 0 External data bus 16 15 Address 7 4n + 5 0 Word data 0 External data bus 16 15 Address 7 4n + 6 0 Word data 0 External data bus 8 7 8 7 8 7 8 7 User's Manual U14492EJ5V0UD 113 CHAPTER 4 BUS CONTROL FUNCTION 4.6 Wait Function 4.6.1 Programmable wait function (1) Data wait control registers 0, 1 (DWC0, DWC1) To facilitate interfacing with low-speed memory or with I/Os, it is possible to insert up to 7 data wait states in the starting bus cycle for each CS space. The number of wait states can be specified by program using data wait control registers 0 and 1 (DWC0, DWC1). Just after system reset, all blocks have 3 data wait states inserted. These registers can be read/written in 16-bit units. Cautions 1. The internal ROM area and internal RAM area are not subject to programmable waits and ordinarily no wait access is carried out. The on-chip peripheral I/O area is also not subject to programmable wait states, with wait control performed by each peripheral function only. 2. Write to the DWC0 and DWC1 registers after reset, and then do not change the set values. Also, do not access an external memory area other than the one for this initialization routine until the initial setting of the DWC0 and DWC1 registers is complete. However, it is possible to access external memory areas whose initial settings are complete. 15 DWC0 CSn signal 15 DWC1 CSn signal 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF484H Initial value 3333H 0 DW32 DW31 DW30 0 DW22 DW21 DW20 0 DW12 DW11 DW10 0 DW02 DW01 DW00 CS3 14 13 12 11 10 CS2 9 8 7 6 CS1 5 4 3 2 CS0 1 0 0 DW72 DW71 DW70 0 DW62 DW61 DW60 0 DW52 DW51 DW50 0 DW42 DW41 DW40 CS7 CS6 CS5 CS4 Address FFFFF486H Initial value 3333H Bit position 14 to 12, 10 to 8, 6 to 4, 2 to 0 Bit name DWn2 to DWn0 (n = 0 to 7) Function Specifies the number of wait states inserted in the CSn space. DWn2 0 0 0 0 1 1 1 1 DWn1 0 0 1 1 0 0 1 1 DWn0 0 1 0 1 0 1 0 1 Number of wait states inserted in CSn space Not inserted 1 2 3 4 5 6 7 114 User's Manual U14492EJ5V0UD CHAPTER 4 BUS CONTROL FUNCTION (2) Address wait control register (AWC) In the V850E/IA1, address setup wait and address hold wait states can be inserted before and after the T1 cycle, respectively. These wait states can be set for each CS space via the AWC register. This register can be read/written in 16-bit units. Caution Write to the AWC register after reset, and then do not change the set values. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF488H Initial value 0000H AWC AHW7 ASW7 AHW6 ASW6 AHW5 ASW5 AHW4 ASW4 AHW3 ASW3 AHW2 ASW2 AHW1 ASW1 AHW0 ASW0 CSn signal CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 Bit position 15, 13, 11, 9, 7, 5, 3, 1 Bit name AHWn (n = 0 to 7) Function Sets the insertion of an address hold wait state in each CSn space after the T1 cycle. 0: Address hold wait state not inserted 1: Address hold wait state inserted Sets the insertion of an address setup wait state in each CSn space before the T1 cycle. 0: Address setup wait state not inserted 1: Address setup wait state inserted 14, 12, 10, 8, 6, 4, 2, 0 ASWn (n = 0 to 7) User's Manual U14492EJ5V0UD 115 CHAPTER 4 BUS CONTROL FUNCTION 4.6.2 External wait function When an extremely slow device, I/O, or asynchronous system is connected, an arbitrary number of wait states can be inserted in the bus cycle by the external wait pin (WAIT) for synchronization with the external device. Just as with programmable waits, accessing internal ROM, internal RAM, and on-chip peripheral I/O areas cannot be controlled by external waits. The external WAIT signal can be input asynchronously to CLKOUT and is sampled at the falling edge of the CLKOUT signal in the T2 and TW states of a bus cycle. If the setup/hold time in the sampling timing is not satisfied, the wait state may or may not be inserted in the next state. 4.6.3 Relationship between programmable wait and external wait A wait cycle is inserted as the result of an OR operation between the wait cycle specified by the set value of the programmable wait and the wait cycle controlled by the WAIT pin. Programmable wait Wait control Wait by WAIT pin For example, if the timings of the programmable wait and the WAIT pin signal are as illustrated below, three wait states will be inserted in the bus cycle. Figure 4-2. Example of Wait Insertion T2 CLKOUT TW TW TW T3 WAIT pin Wait by WAIT pin Programmable wait Wait control Remark The circles indicate the sampling timing. 116 User's Manual U14492EJ5V0UD CHAPTER 4 BUS CONTROL FUNCTION 4.7 Idle State Insertion Function To facilitate interfacing with low-speed memory devices, a set number of idle states (TI) can be inserted into the starting bus cycle after the T3 state to secure the data output float delay time (tDF) of the memory when each CS space is read accessed. The bus cycle following the T3 state starts after the inserted idle state(s). Idle states are inserted at the following timing. * After the read cycle for SRAM, external I/O, or external ROM. The idle state insertion setting can be specified using the bus cycle control register (BCC). Idle state insertion is automatically programmed for all memory blocks immediately after a system reset. (1) Bus cycle control register (BCC) This register can be read/written in 16-bit units. Cautions 1. Idle states cannot be inserted in internal ROM, internal RAM, on-chip peripheral I/O, or programmable peripheral I/O areas. 2. Write to the BCC register after reset, and then do not change the set values. Also, do not access an external memory area other than the one for this initialization routine until the initial setting for this register is complete. However, it is possible to access external memory areas whose initial settings are complete. 15 BCC BC71 CSn signal CS7 14 0 13 BC61 CS6 12 0 11 BC51 CS5 10 0 9 BC41 CS4 8 0 7 BC31 CS3 6 0 5 BC21 CS2 4 0 3 BC11 CS1 2 0 1 BC01 CS0 0 0 Address FFFFF48AH Initial value AAAAH Bit position 15, 13, 11, 9, 7, 5, 3, 1 Bit name BCn1 (n = 0 to 7) Function Specifies the insertion of idle states after the T3 state in each CSn space. 0: Idle state not inserted 1: Idle state inserted User's Manual U14492EJ5V0UD 117 CHAPTER 4 BUS CONTROL FUNCTION 4.8 Bus Hold Function 4.8.1 Function outline If pins PCM2 and PCM3 are specified in the control mode, the HLDAK and HLDRQ functions become valid. If it is determined that the HLDRQ pin has become active (low level) as a bus mastership request from another bus master, the external address/data bus and each strobe pin are shifted to high impedance and then released (bus hold state). If the HLDRQ pin becomes inactive (high level) and the bus mastership request is canceled, driving of these pins begins again. During the bus hold period, the internal operations of the V850E/IA1 continue until the external memory or on-chip peripheral I/O register is accessed. The bus hold state can be known by the HLDAK pin becoming active (low level). The period from when the HLDRQ pin becomes active (low level) to when the HLDAK pin becomes active (low level) is at least 2 clocks. In a multiprocessor configuration, etc., a system with multiple bus masters can be configured. 4.8.2 Bus hold procedure The procedure of the bus hold function is illustrated below. <1> HLDRQ = 0 accepted <2> All bus cycle start requests held pending <3> End of current bus cycle <4> Transition to bus idle state <5> HLDAK = 0 Bus hold state Normal state <6> HLDRQ = 1 accepted <7> HLDAK = 1 <8> Releases pending bus cycle start request <9> Start of bus cycle Normal state HLDRQ (input) HLDAK (output) <1> <2> <3><4> <5> <6> <7><8><9> 118 User's Manual U14492EJ5V0UD CHAPTER 4 BUS CONTROL FUNCTION 4.8.3 Operation in power save mode In the software STOP or IDLE mode, the internal system clock is stopped. Consequently, the bus hold state is not accepted and set since the HLDRQ pin cannot be accepted even if it becomes active. In the HALT mode, the HLDAK pin immediately becomes active when the HLDRQ pin becomes active, and the bus hold state is set. When the HLDRQ pin becomes inactive after that, the HLDAK pin also becomes inactive. As a result, the bus hold state is cleared and the HALT mode is set again. 4.8.4 Bus hold timing T2 CLKOUT (output) T3 TH TH TH TH TI T1 HLDRQ (input) HLDAK (output) A16 to A23 (output) Address Undefined Address AD0 to AD15 (I/O) Address Data Undefined Address ASTB (output) RD (output) LWR, UWR (output) CSn (output) WAIT (input) Remarks 1. The circles indicate the sampling timing. 2. The broken lines indicate the high-impedance state. 3. n = 0 to 7 User's Manual U14492EJ5V0UD 119 CHAPTER 4 BUS CONTROL FUNCTION 4.9 Bus Priority Order There are four external bus cycles: bus hold, DMA cycle, operand data access, and instruction fetch. In order of priority, bus hold is the highest, followed by DMA cycle, operand data access, and instruction fetch, in that order. An instruction fetch may be inserted between a read access and write access during a read modify write access. Also, an instruction fetch may be inserted between bus accesses when the CPU bus is locked. Table 4-1. Bus Priority Order Priority Order High Bus hold DMA cycle Operand data access Low Instruction fetch External device DMA controller CPU CPU External Bus Cycle Bus Master 4.10 Boundary Operation Conditions 4.10.1 Program space (1) Branching to the on-chip peripheral I/O area or successive fetches from the internal RAM area to the on-chip peripheral I/O area are prohibited. If the above is performed (branching or successive fetch), a data to be fetched is undefined and the operation is not guaranteed. (2) If a branch instruction exists at the upper limit of the internal RAM area, a prefetch operation (invalid fetch) that straddles over the on-chip peripheral I/O area does not occur. 4.10.2 Data space The V850E/IA1 is provided with an address misalign function. Through this function, regardless of the data format (word data or halfword data), data can be allocated to all addresses. However, in the case of word data and halfword data, if the data is not subject to boundary alignment, the bus cycle will be generated at least 2 times and bus efficiency will drop. (1) In the case of halfword-length data access When the address's LSB is 1, the byte-length bus cycle will be generated 2 times. (2) In the case of word-length data access (a) When the address's LSB is 1, bus cycles will be generated in the order of byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle. (b) When the address's lowest 2 bits are 10, the halfword-length bus cycle will be generated 2 times. 120 User's Manual U14492EJ5V0UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.1 SRAM, External ROM, External I/O Interface 5.1.1 Features * SRAM is accessed in a minimum of 2 states. * A maximum of 7 programmable data wait states can be inserted according to DWC0 and DWC1 register settings. * Data waits can be controlled by WAIT pin input. * An idle state (1 state) can be inserted after a read/write cycle by setting the BCC register. * An address hold wait state or address setup wait state can be inserted by setting the AWC register. User's Manual U14492EJ5V0UD 121 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.1.2 SRAM, external ROM, external I/O access Figure 5-1. SRAM, External ROM, External I/O Access Timing (1/5) (a) On a read (1 wait insertion) T1 CLKOUT (Output) T2 TW T3 A16 to A23 (Output) Address AD0 to AD15 (I/O) Address Data ASTB (Output) RD (Output) UWR, LWR (Output) H CSn (Output) WAIT (Input) Remarks 1. The circles indicate the sampling timing. 2. Broken lines indicate high impedance. 3. n = 0 to 7 122 User's Manual U14492EJ5V0UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-1. SRAM, External ROM, External I/O Access Timing (2/5) (b) On a read (0 wait, address setup wait, address hold wait state insertion) TASW CLKOUT (Output) T1 TAHW T2 T3 A16 to A23 (Output) Address AD0 to AD15 (I/O) Address Data ASTB (Output) RD (Output) UWR, LWR (Output) H CSn (Output) WAIT (Input) Remarks 1. The circles indicate the sampling timing. 2. Broken lines indicate high impedance. 3. n = 0 to 7 User's Manual U14492EJ5V0UD 123 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-1. SRAM, External ROM, External I/O Access Timing (3/5) (c) On a write (1 wait insertion) T1 CLKOUT (Output) T2 TW T3 A16 to A23 (Output) Address AD0 to AD15 (I/O) Address DataNote ASTB (Output) RD (Output) H UWR, LWR (Output) CSn (Output) WAIT (Input) Note AD0 to AD7 output invalid data when accessed to odd-numbered address byte data. AD8 to AD15 output invalid data when accessed to even-numbered address byte data. Remarks 1. The circles indicate the sampling timing. 2. Broken lines indicate high impedance. 3. n = 0 to 7 124 User's Manual U14492EJ5V0UD CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-1. SRAM, External ROM, External I/O Access Timing (4/5) (d) On a write (0 wait insertion, for 8-bit data bus) T1 CLKOUT (Output) T2 T3 A16 to A23 (Output) Address AD8 to AD15 (I/O) Address AD0 to AD7 (I/O) Address DataNote ASTB (Output) RD (Output) H UWR, LWR (Output) CSn (Output) WAIT (Input) Note AD0 to AD7 output invalid data when accessed to odd-numbered address byte data. Remarks 1. The circles indicate the sampling timing. 2. Broken lines indicate high impedance. 3. n = 0 to 7 User's Manual U14492EJ5V0UD 125 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-1. SRAM, External ROM, External I/O Access Timing (5/5) (e) Bus hold timing T2 CLKOUT (Output) T3 TH TH TH TH TI T1 HLDRQ (Input) HLDAK (Output) A16 to A23 (Output) Note 1 Undefined Address AD0 to AD15 (I/O) Note 2 Undefined Undefined Address ASTB (Output) RD (Output) UWR, LWR (Output) CSn (Output) WAIT (Input) Notes 1. 2. On a read: Undefined On a write: Address On a read: Data On a write: Undefined Remarks 1. The circles indicate the sampling timing. 2. Broken lines indicate high impedance. 3. n = 0 to 7 126 User's Manual U14492EJ5V0UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) The V850E/IA1 includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfer between memory and peripheral I/O, among memories or among peripheral I/Os, based on DMA requests issued by the on-chip peripheral I/O (such as serial interface, timer/counter, and A/D converter), or software triggers (memory refers to internal RAM or external memory). 6.1 Features * 4 independent DMA channels * Transfer units: 8/16 bits * Maximum transfer count: 65,536 (216) * Transfer type: Two-cycle transfer * Three transfer modes * Single transfer mode * Single-step transfer mode * Block transfer mode * Transfer requests * Request by interrupts from on-chip peripheral I/O (such as serial interface, timer/counter, A/D converter) * Requests by software trigger * Transfer targets * Memory peripheral I/O * Memory memory * Peripheral I/O peripheral I/O * Next address setting function User's Manual U14492EJ5V0UD 127 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.2 Configuration Internal RAM On-chip peripheral I/O Internal bus On-chip peripheral I/O bus CPU Data control Address control DMA source address register (DSAnH/DSAnL) DMA destination address register (DDAnH/DDAnL) Count control DMA transfer count register (DBCn) DMA channel control register (DCHCn) DMA addressing control register (DADCn) Channel control DMA disable status register (DDIS) DMA restart register (DRST) DMA trigger factor register n (DTFRn) DMAC Bus interface External bus V850E/IA1 External I/O External RAM External ROM Remark n = 0 to 3 128 User's Manual U14492EJ5V0UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3 Control Registers 6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3) These registers are used to set the DMA source addresses (28 bits each) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DSAnH and DSAnL. Since these registers are 2-stage FIFO buffer registers, a new source address for DMA transfer can be specified during DMA transfer (refer to 6.8 Next Address Setting Function). In this case, if a new DSAn register is set, the value set will be transferred to the slave register and enabled only if DMA transfer ends normally, and the TCn bit of DMA channel control register n (DCHCn) has been set to 1 or the INITn bit of the DCHCn register has been set to 1 (n = 0 to 3). (1) DMA source address registers 0H to 3H (DSA0H to DSA3H) These registers can be read/written in 16-bit units. Be sure to set bits 12 to 14 to 0. If they are set to 1, the operation is not guaranteed. Cautions 1. When setting an address of an on-chip peripheral I/O register for the source address, be sure to specify an address between FFFF000H and FFFFFFFH. An address of the onchip peripheral I/O register image (3FFF000H to 3FFFFFFH) must not be specified. 2. Do not set the DSAnH register when DMA transfer has been suspended. 15 DSA0H IR 14 0 13 0 12 0 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF082H Initial value Undefined SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 DSA1H IR 0 0 0 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 FFFFF08AH Undefined DSA2H IR 0 0 0 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 FFFFF092H Undefined DSA3H IR 0 0 0 SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 FFFFF09AH Undefined Bit position 15 IR Bit name Specifies the DMA source address. Function 0: External memory, on-chip peripheral I/O 1: Internal RAM 11 to 0 SA27 to SA16 Sets the DMA source addresses (A27 to A16). During DMA transfer, it stores the next DMA transfer source address. User's Manual U14492EJ5V0UD 129 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) DMA source address registers 0L to 3L (DSA0L to DSA3L) These registers can be read/written in 16-bit units. 15 DSA0L 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF080H Initial value Undefined SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 DSA1L SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 FFFFF088H Undefined DSA2L SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 FFFFF090H Undefined DSA3L SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 FFFFF098H Undefined Bit position 15 to 0 Bit name SA15 to SA0 Function Sets the DMA source addresses (A15 to A0). During DMA transfer, it stores the next DMA transfer source address. 130 User's Manual U14492EJ5V0UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3) These registers are used to set the DMA destination address (28 bits each) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DDAnH and DDAnL. Since these registers are 2-stage FIFO buffer registers, a new destination address for DMA transfer can be specified during DMA transfer (refer to 6.8 Next Address Setting Function). In this case, if a new DDAn register is set, the value set will be transferred to the slave register and enabled only if DMA transfer ends normally, and the TCn bit of DMA channel control register n (DCHCn) has been set to 1 or the INITn bit of the DCHCn register has been set to 1 (n = 0 to 3). (1) DMA destination address registers 0H to 3H (DDA0H to DDA3H) These registers can be read/written in 16-bit units. Be sure to set bits 12 to 14 to 0. If they are set to 1, the operation is not guaranteed. Cautions 1. When setting an address of an on-chip peripheral I/O register for the destination address, be sure to specify an address between FFFF000H and FFFFFFFH. An address of the on-chip peripheral I/O register image (3FFF000H to 3FFFFFFH) must not be specified. 2. Do not set the DDAnH register when DMA transfer has been suspended. 15 DDA0H IR 14 0 13 0 12 0 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF086H Initial value Undefined DA27 DA26 DA25 DA24 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16 DDA1H IR 0 0 0 DA27 DA26 DA25 DA24 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16 FFFFF08EH Undefined DDA2H IR 0 0 0 DA27 DA26 DA25 DA24 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16 FFFFF096H Undefined DDA3H IR 0 0 0 DA27 DA26 DA25 DA24 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16 FFFFF09EH Undefined Bit position 15 Bit name IR Specifies the DMA destination address. Function 0: External memory, on-chip peripheral I/O 1: Internal RAM 11 to 0 DA27 to DA16 Sets the DMA destination addresses (A27 to A16). During DMA transfer, it stores the next DMA transfer destination address. User's Manual U14492EJ5V0UD 131 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) DMA destination address registers 0L to 3L (DDA0L to DDA3L) These registers can be read/written in 16-bit units. 15 DDA0L 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF084H Initial value Undefined DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DDA1L DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FFFFF08CH Undefined DDA2L DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FFFFF094H Undefined DDA3L DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 FFFFF09CH Undefined Bit position 15 to 0 Bit name DA15 to DA0 Function Sets the DMA destination addresses (A15 to A0). During DMA transfer, it stores the next DMA transfer destination address. 132 User's Manual U14492EJ5V0UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3) These 16-bit registers are used to set the byte transfer counts for DMA channel n (n = 0 to 3). They store the remaining transfer counts during DMA transfer. Since these registers are 2-stage FIFO buffer registers, a new DMA byte transfer count for DMA transfer can be specified during DMA transfer (refer to 6.9 Next Address Setting Function). In this case, if a new DBCn register is set, the value set will be transferred to the slave register and enabled only if DMA transfer ends normally, and the TCn bit of DMA channel control register n (DCHCn) has been set to 1 or the INITn bit of the DCHCn register has been set to 1 (n = 0 to 3). These registers are decremented by 1 per transfer. Transfer is terminated if a borrow occurs. These registers can be read/written in 16-bit units. Cautions 1. When performing 2-cycle transfer from the internal RAM, do not set the transfer count to 2 (by setting the DBCn register to 0001H). If it is required to perform DMA transfer twice, be sure to perform DMA transfer for which the transfer count is set to 1 (by setting the DBCn register to 0000H) twice. 2. Do not set the DBCn register when DMA transfer has been suspended. Remark If the DBCn register is read after a terminal count has occurred during DMA transfer without the value of the DBCn register being rewritten, the value set immediately before DMA transfer is read (0000H is not read even after completion of transfer). 15 DBC0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF0C0H Initial value Undefined BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 DBC1 BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 FFFFF0C2H Undefined DBC2 BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 FFFFF0C4H Undefined DBC3 BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 FFFFF0C6H Undefined Bit position 15 to 0 Bit name BC15 to BC0 Function Sets the byte transfer count. It stores the remaining byte transfer count during DMA transfer. DBCn (n = 0 to 3) 0000H 0001H : FFFFH States Byte transfer count 1 or remaining byte transfer count Byte transfer count 2 or remaining byte transfer count : Byte transfer count 65,536 (2 ) or remaining byte transfer count 16 User's Manual U14492EJ5V0UD 133 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) These 16-bit registers are used to control the DMA transfer modes for DMA channel n (n = 0 to 3). These registers cannot be accessed during DMA operation. These registers can be read/written in 16-bit units. Be sure to set bits 0, 1, and 8 to 13 to 0. If they are set to 1, the operation is not guaranteed. Cautions 1. The DS1 and DS0 bits are used to set how many bits of data are transferred. When 8-bit data (DS1, DS0 bits = 00) is set, the lower data bus (AD0 to AD7) is not necessarily used. When the transfer data size is set to 16 bits, the transfer must start from an address with bit 1 of the lower address aligned to "0". In this case, the transfer cannot start from an odd address. 2. Set the DADCn register when the corresponding channel is in one of the following periods (the operation is not guaranteed if set at another timing). * Time from system reset to generation of the first DMA transfer request * Time from DMA transfer end (after terminal count) to generation of the next DMA transfer request * Time from the forcible termination of DMA transfer (after the INITn bit of DMA channel control register n (DCHCn) has been set to 1) to generation of the next DMA transfer request (1/2) 15 DADC0 14 13 0 12 0 11 0 10 0 9 0 8 7 6 5 4 3 2 1 0 0 0 Address FFFFF0D0H Initial value 0000H DS1 DS0 0 SAD1 SAD0 DAD1 DAD0 TM1 TM0 DADC1 DS1 DS0 0 0 0 0 0 0 SAD1 SAD0 DAD1 DAD0 TM1 TM0 0 0 FFFFF0D2H 0000H DADC2 DS1 DS0 0 0 0 0 0 0 SAD1 SAD0 DAD1 DAD0 TM1 TM0 0 0 FFFFF0D4H 0000H DADC3 DS1 DS0 0 0 0 0 0 0 SAD1 SAD0 DAD1 DAD0 TM1 TM0 0 0 FFFFF0D6H 0000H Bit position 15, 14 Bit name DS1, DS0 Function Sets the transfer data size for DMA transfer. DS1 0 0 1 1 DS0 0 1 0 1 8 bits 16 bits Setting prohibited Setting prohibited Transfer data size For the on-chip peripheral I/O and programmable peripheral I/O registers, ensure the transfer size matches the access size. 134 User's Manual U14492EJ5V0UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2/2) Bit position 7, 6 Bit name SAD1, SAD0 Function Sets the count direction of the source address for DMA channel n (n = 0 to 3). SAD1 0 0 1 1 SAD0 0 1 0 1 Increment Decrement Fixed Setting prohibited Count direction 5, 4 DAD1, DAD0 Sets the count direction of the destination address for DMA channel n (n = 0 to 3). DAD1 0 0 1 1 DAD0 0 1 0 1 Increment Decrement Fixed Setting prohibited Count direction 3, 2 TM1, TM0 Sets the transfer mode during DMA transfer. TM1 0 0 1 1 TM0 0 1 0 1 Single transfer mode Single-step transfer mode Setting prohibited Block transfer mode Transfer mode User's Manual U14492EJ5V0UD 135 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) These 8-bit registers are used to control the DMA transfer operating mode for DMA channel n (n = 0 to 3). These registers can be read/written in 8-bit or 1-bit units. (However, bit 7 is read only and bits 2 and 1 are write only. If bits 2 and 1 are read, the read value is always 0.) Be sure to set bits 4 to 6 to 0. If they are set to 1, the operation is not guaranteed. Cautions 1. If transfer is completed with the MLEn bit set to 1, and the next transfer request is executed with the DMA transfer (hardware DMA) started by an interrupt from the on-chip peripheral I/O, the next transfer will be executed if the TCn bit is set to 1 (will not be automatically cleared to 0). 2. Set the MLEn bit when the corresponding channel is in one of the following periods (the operation is not guaranteed if set at another timing). * Time from system reset to generation of the first DMA transfer request * Time from DMA transfer end (after terminal count) to generation of the next DMA transfer request * Time from the forcible termination of DMA transfer (after the INITn bit has been set to 1) to generation of the next DMA transfer request 3. If DMA transfer is forcibly terminated in the last transfer cycle with the MLEn bit set to 1, the same operations as transfer completion (setting of the TCn bit to 1) are performed (the Enn bit will be cleared to 0 in forcible termination regardless of the value of the MLEn bit). In this case, at the next DMA transfer request, the Enn bit must be set to 1 and the TCn bit must be read (cleared to 0). 4. During DMA transfer completion (terminal count), each bit is updated in the order of clearing the Enn bit to 0 and setting the TCn bit to 1. For this reason, if the TCn bit and Enn bit are in the polling mode, the value indicating "transfer not completed, and transfer prohibited" (TCn bit = 0, and Enn bit = 0) may be read in some cases if the DCHCn register is read while each of the above bits is being updated (this is not an error). 5. Do not set the Enn and STGn bits when DMA transfer has been suspended; otherwise the operation cannot be guaranteed. 136 User's Manual U14492EJ5V0UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) <7> DCHC0 TC0 6 0 5 0 4 0 <3> MLE0 <2> INIT0 <1> STG0 <0> E00 Address FFFFF0E0H Initial value 00H DCHC1 TC1 0 0 0 MLE1 INIT1 STG1 E11 FFFFF0E2H 00H DCHC2 TC2 0 0 0 MLE2 INIT2 STG2 E22 FFFFF0E4H 00H DCHC3 TC3 0 0 0 MLE3 INIT3 STG3 E33 FFFFF0E6H 00H Bit position 7 Bit name TCn Function This status bit indicates whether DMA transfer through DMA channel n has ended or not. This bit is read-only. It is set to 1 when DMA transfer ends and cleared (to 0) when it is read. 0: DMA transfer had not ended. 1: DMA transfer had ended. 3 MLEn When this bit is set to 1 when DMA transfer ends (at terminal count output), the Enn bit is not cleared to 0 and the DMA transfer enable state is retained. When the next DMA transfer start trigger is an interrupt from the on-chip peripheral I/O (hardware DMA), the DMA transfer request can be accepted even when the TCn bit is not read. When the next DMA transfer start trigger is the setting of the STGn bit to 1 (software DMA), the DMA transfer request can be accepted by reading and clearing the TCn bit to 0. When this bit is cleared to 0 when DMA transfer ends (at terminal count output), the Enn bit is cleared to 0 and the DMA transfer disable state is entered. At the next DMA transfer request, the setting of the Enn bit to 1 and the reading of the TCn bit are required. 2 INITn When this bit is set to 1 during DMA transfer or DMA transfer suspension, DMA transfer is forcibly terminated (refer to 6.12.1 Restrictions related to DMA transfer forcible termination). 1 STGn If this bit is set to 1 in the DMA transfer enable state (TCn bit = 0, Enn bit = 1), DMA transfer is started. 0 Enn Specifies whether DMA transfer through DMA channel n is to be enabled or disabled. This bit is cleared to 0 when DMA transfer ends. It is also cleared to 0 when DMA transfer is forcibly suspended or terminated by means of setting the INITn bit to 1 or by NMI input. 0: DMA transfer disabled 1: DMA transfer enabled Caution After the Enn bit is set (1), do not set the Enn bit again until the number of DMA transfers set by the DBCn register are complete or DMA transfer is forcibly terminated using the INITn bit. Remark n = 0 to 3 User's Manual U14492EJ5V0UD 137 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.6 DMA disable status register (DDIS) This register holds the contents of the Enn bit of the DCHCn register during forcible interruption by NMI input (n = 0 to 3). This register is read-only, in 8-bit units. Be sure to set bits 4 to 7 to 0. If they are set to 1, the operation is not guaranteed. 7 DDIS 0 6 0 5 0 4 0 3 CH3 2 CH2 1 CH1 0 CH0 Address FFFFF0F0H Initial value 00H Bit position 3 to 0 Bit name CH3 to CH0 Function Reflects the contents of the Enn bit of the DCHCn register during forcible interruption by NMI input. The contents of this register are held until the next forcible interruption by NMI input or until the system is reset. 6.3.7 DMA restart register (DRST) The ENn bit of the DRST register and the Enn bit of the DCHCn register are linked to each other, the Enn bit can also be used to set the enabling or disabling of DMA transfer independently for four channels, and the DRST register can be used to set the enabling or disabling of DMA transfer for four channels at the same time (n = 0 to 3). This register can be read/written in 8-bit units. Be sure to set bits 4 to 7 to 0. If they are set to 1, the operation is not guaranteed. 7 DRST 0 6 0 5 0 4 0 3 EN3 2 EN2 1 EN1 0 EN0 Address FFFFF0F2H Initial value 00H Bit position 3 to 0 Bit name EN3 to EN0 Function Specifies whether DMA transfer through DMA channel n is to be enabled or disabled. This bit is cleared to 0 when DMA transfer is completed in accordance with the terminal count output (n = 0 to 3). It is also cleared to 0 when DMA transfer is forcibly terminated by setting the INITn bit of the DCHCn register to 1 or by NMI input. 0: DMA transfer disabled 1: DMA transfer enabled 138 User's Manual U14492EJ5V0UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.8 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) These 8-bit registers are used to control the DMA transfer start trigger through interrupt requests from on-chip peripheral I/O. The interrupt requests set with these registers serve as DMA transfer start factors. These registers can be read/written in 8-bit units. Only bit 7 (DFn) can be read/written in 1-bit units, and bits 5 to 0 (IFCn5 to IFCn0) can be read/written in 8-bit units (n = 0 to 3). Be sure to set bit 6 to 0. If it is set to 1, the operation is not guaranteed. Cautions 1. Be sure to stop DMA operation before making changes to DTFRn register settings. 2. An interrupt request input in a standby mode (IDLE or software STOP mode) cannot be used as a DMA transfer start factor except for INTP0 to INTP6 and INTP20 to INTP25 (when the noise elimination by analog filter is selected). 3. If the start factor for DMA transfer is changed using the IFCn5 to IFCn0 bits, be sure to clear (0) the DFn bit with the instruction immediately after the change. (1/2) <7> DTFR0 DF0 <7> DTFR1 DF1 <7> DTFR2 DF2 <7> DTFR3 DF3 6 0 6 0 6 0 6 0 5 IFC05 5 IFC15 5 IFC25 5 IFC35 4 IFC04 4 IFC14 4 IFC24 4 IFC34 3 IFC03 3 IFC13 3 IFC23 3 IFC33 2 IFC02 2 IFC12 2 IFC22 2 IFC32 1 IFC01 1 IFC11 1 IFC21 1 IFC31 0 IFC00 0 IFC10 0 IFC20 0 IFC30 FFFFF816H 00H FFFFF814H 00H FFFFF812H 00H Address FFFFF810H Initial value 00H Bit position 7 Bit name DFn Function This is a DMA transfer request flag. Only 0 can be written to this flag. 0: No DMA transfer request 1: DMA transfer request If an interrupt that causes DMA transfer occurs while DMA transfer is disabled (including if it has been suspended by an NMI or forcibly terminated by software), and if this DMA transfer request must be cleared, stop the operation causing the interrupt (e.g., disable reception if serial reception is in progress), and then clear the DFn bit. If it is clear in the application that the interrupt will not occur again until DMA transfer is resumed next, it is not necessary to stop the operation causing the interrupt. Sets the interrupt source that serves as the DMA transfer start factor. IFCn5 0 0 0 0 0 0 IFCn4 0 0 0 0 0 0 IFCn3 0 0 0 0 0 0 IFCn2 0 0 0 0 1 1 IFCn1 0 0 1 1 0 0 IFCn0 0 1 0 1 0 1 Interrupt Source DMA request from on-chip peripheral I/O disabled INTP0 INTP1 INTP2 INTP3 INTP4 5 to 0 IFCn5 to IFCn0 Remark n = 0 to 3 User's Manual U14492EJ5V0UD 139 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2/2) Bit position 5 to 0 Bit name IFCn5 to IFCn0 Function IFCn5 IFCn4 IFCn3 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 Other than above IFCn2 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 IFCn1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 IFCn0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Interrupt source INTP5 INTP6 INTDET0 INTDET1 INTTM00 INTCM003 INTTM01 INTCM013 INTP100/INTCC100 INTP101/INTCC101 INTCM100 INTCM101 INTP110/INTCC110 INTP111/INTCC111 INTCM110 INTCM111 INTTM20 INTTM21 INTP20/INTCC20 INTP21/INTCC21 INTP22/INTCC22 INTP23/INTCC23 INTP24/INTCC24 INTP25/INTCC25 INTTM3 INTP30/INTCC30 INTP31/INTCC31 INTCM4 INTDMA0 INTDMA1 INTDMA2 INTDMA3 INTCREC INTCTRX INTCERR INTCMAC INTCSI0 INTCSI1 INTSR0 INTST0 INTSER0 INTSR1 INTST1 INTSR2 INTST2 INTAD0 INTAD1 Note NBDAD Note NBDREW Setting prohibited Note PD70F3116 only Remark n = 0 to 3 140 User's Manual U14492EJ5V0UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) The relationship between the interrupt source and the DMA transfer trigger is as follows (n = 0 to 3). Interrupt source Selector Internal DMA request signal IFCn0 to IFCn5 Caution An interrupt request will be generated when DMA transfer starts. To prevent an interrupt from being generated, mask the interrupt by setting the interrupt request control register. transfer starts even if an interrupt is masked. DMA User's Manual U14492EJ5V0UD 141 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.4 Transfer Mode 6.4.1 Single transfer mode In single transfer mode, the DMAC releases the bus at each byte/halfword transfer. If there is a subsequent DMA transfer request, transfer is performed again once. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence. However, if a lower priority DMA transfer request is generated within one clock after the end of a single transfer, even if the previous higher priority DMA transfer request signal stays active, this request is not prioritized, and the next DMA transfer after the bus is released for the CPU is a transfer based on the newly generated, lower priority DMA transfer request. Figures 6-1 to 6-4 show examples of single transfer. Figure 6-1. Single Transfer Example 1 DMARQ3 (Internal signal) Note CPU Note Note CPU CPU CPU CPU Note CPU DMA3 CPU DMA3 CPU CPU CPU CPU DMA3 CPU DMA3 CPU DMA3 CPU DMA channel 3 terminal count Note The bus is always released. Figure 6-2 shows a single transfer mode example in which a higher priority DMA transfer request is generated. DMA channels 0 to 2 are used for a block transfer, and channel 3 is used for a single transfer. Figure 6-2. Single Transfer Example 2 DMARQ0 (Internal signal) DMARQ1 (Internal signal) DMARQ2 (Internal signal) DMARQ3 (Internal signal) Note CPU CPU CPU DMA3 CPU DMA0 DMA0 Note Note Note CPU DMA3 CPU DMA1 DMA1 CPU DMA2 DMA2 CPU DMA3 DMA channel 0 terminal count DMA channel 1 terminal count DMA channel 2 terminal count DMA channel 3 terminal count Note The bus is always released. 142 User's Manual U14492EJ5V0UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-3 shows a single transfer mode example in which a lower priority DMA transfer request is generated within one clock after the end of a single transfer. DMA channels 0 and 3 are used for a single transfer. When two DMA transfer request signals are activated at the same time, the two DMA transfers are performed alternately. Figure 6-3. Single Transfer Example 3 DMARQ0 (Internal signal) DMARQ3 (Internal signal) Note CPU Note Note Note Note Note Note CPU CPU DMA0 CPU DMA0 CPU DMA3 CPU DMA0 CPU DMA3 CPU DMA0 CPU DMA0 CPU DMA0 CPU DMA channel 3 terminal count DMA channel 0 terminal count Note The bus is always released. Figure 6-4 shows a single transfer mode example in which two or more lower priority DMA transfer requests are generated within one clock after the end of a single transfer. DMA channels 0, 2, and 3 are used for a single transfer. When three or more DMA transfer request signals are activated at the same time, the two highest priority DMA transfers are performed alternately. Figure 6-4. Single Transfer Example 4 DMARQ0 (Internal signal) DMARQ2 (Internal signal) DMARQ3 (Internal signal) Note Note Note Note Note Note Note Note Note CPU CPU CPU DMA3 CPU DMA3 CPU DMA2 CPU DMA0 CPU DMA2 CPU DMA0 CPU DMA2 CPU DMA3 CPU DMA2 CPU DMA3 DMA channel 0 terminal count DMA channel 2 terminal count DMA channel 3 terminal count Note The bus is always released. User's Manual U14492EJ5V0UD 143 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.4.2 Single-step transfer mode In single-step transfer mode, the DMAC releases the bus at each byte/halfword transfer. Once a DMA transfer request signal is received, transfer is performed again. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence. The following shows examples of single-step transfer. Figure 6-6 shows a single-step transfer mode example in which a higher priority DMA transfer request is generated. DMA channels 0 and 1 are used for the single-step transfer. Figure 6-5. Single-Step Transfer Example 1 DMARQ1 (Internal signal) Note CPU CPU Note Note CPU CPU CPU CPU CPU CPU CPU DMA1 CPU DMA1 CPU DMA1 CPU DMA1 CPU DMA channel 1 terminal count Note The bus is always released. Figure 6-6. Single-Step Transfer Example 2 DMARQ0 (Internal signal) DMARQ1 (Internal signal) Note CPU CPU Note Note Note Note Note DMA1 CPU CPU DMA1 CPU DMA1 CPU DMA0 CPU DMA0 CPU DMA0 CPU DMA1 CPU DMA channel 0 terminal count DMA channel 1 terminal count Note The bus is always released. 144 User's Manual U14492EJ5V0UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.4.3 Block transfer mode In the block transfer mode, once transfer starts, the DMAC continues the transfer operation without releasing the bus until a terminal count occurs. No other DMA requests are acknowledged during block transfer. After the block transfer ends and the DMAC releases the bus, another DMA transfer can be acknowledged. The following shows an example of block transfer in which a higher priority DMA request is issued. DMA channels 2 and 3 are in the block transfer mode. Figure 6-7. Block Transfer Example DMARQ2 (internal signal) DMARQ3 (internal signal) CPU CPU CPU DMA3 DMA3 DMA3 DMA3 DMA3 DMA3 DMA3 DMA3 CPU DMA2 DMA2 DMA2 DMA2 DMA2 The bus is always released. DMA channel 3 terminal count 6.5 Transfer Types 6.5.1 Two-cycle transfer In two-cycle transfer, data transfer is performed in two cycles, a read cycle (source to DMAC) and a write cycle (DMAC to destination). In the first cycle, the source address is output and reading is performed from the source to the DMAC. In the second cycle, the destination address is output and writing is performed from the DMAC to the destination. Caution An idle cycle of 1 to 2 clocks is always inserted between the read cycle and write cycle. User's Manual U14492EJ5V0UD 145 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.6 Transfer Target 6.6.1 Transfer type and transfer target Table 6-1 shows the relationship between the transfer type and transfer target (: transfer enabled, x: transfer disabled). Table 6-1. Relationship Between Transfer Type and Transfer Target Destination Internal ROM x x x x x On-Chip Peripheral I/O On-chip peripheral I/O Source External I/O Internal RAM External memory Internal ROM Note Note Internal RAM x x External Memory, External I/O x x Note If the transfer target is the on-chip peripheral I/O, only the single transfer mode can be used. Cautions 1. The operation is not guaranteed for combinations of transfer destination and source marked with "x" in Table 6-1. 2. Addresses between 3FFF000H and 3FFFFFFH cannot be specified for the source and destination address of DMA transfer. Be sure to specify an address between FFFF000H and FFFFFFFH. Remark If the target of the DMA transfer is an on-chip peripheral I/O register (transfer source/transfer destination), be sure to specify the same transfer size as the register size. For example, in the case of DMA transfer to an 8-bit register, be sure to specify byte (8-bit) transfer. <16-bit transfer> * Transfer from a 16-bit bus to an 8-bit bus A read cycle (16 bits) is generated and then a write cycle (8 bits) is generated twice successively. * Transfer from an 8-bit bus to a 16-bit bus A read cycle (8 bits) is generated twice successively and then a write cycle (16 bits) is generated. Data is written to the transfer destination from the lowest byte in little-endian mode, and the highest byte in big-endian mode. <8-bit transfer> * Transfer from a 16-bit bus to an 8-bit bus A read cycle (the higher 8 bits go into a high-impedance state) is generated and then a write cycle (8 bits) is generated. * Transfer from an 8-bit bus to a 16-bit bus A read cycle (8 bits) is generated and then a write cycle (the higher 8 bits go into a high-impedance state) is generated. Data is written to the transfer destination from the lowest byte in little-endian mode, and the highest byte in big-endian mode. 146 User's Manual U14492EJ5V0UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.6.2 External bus cycles during DMA transfer (two-cycle transfer) The external bus cycles during DMA transfer (two-cycle transfer) are shown below. Table 6-2. External Bus Cycles During DMA Transfer (Two-Cycle Transfer) Transfer Target On-chip peripheral I/O, internal RAM External memory, external I/O None Yes External Bus Cycle - SRAM, external ROM, external I/O access cycle 6.7 DMA Channel Priorities The DMA channel priorities are fixed as follows. DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3 In the block transfer mode, the channel used for transfer is never switched. In the single-step transfer mode, if a higher priority DMA transfer request is issued while the bus is released, the higher priority DMA transfer request is acknowledged. Caution Do not start more than one DMA channel using the same start factor. If more than one DMA channel is started, a lower priority DMA channel may be acknowledged prior to a higher priority DMA channel. 6.8 Next Address Setting Function The DMA source address registers (DSAnH, DSAnL), DMA destination address registers (DDAnH, DDAnL), and DMA transfer count register (DBCn) are 2-stage FIFO buffer registers configured with a master register and slave register (n = 0 to 3). When the terminal count is issued, these registers are automatically rewritten with the value that was set immediately before. If new DMA transfer setting is made to these registers during DMA transfer, therefore, the values of the registers are automatically updated to the new value after completion of transferNote. Note Before making another DMA transfer setting, confirm that DMA transfer has started. If new settings are made before DMA transfer starts, the set values are overwritten to both the master and slave registers, preventing the DMA transfer based on the set value immediately before from being correctly performed. User's Manual U14492EJ5V0UD 147 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-8 shows the configuration of the buffer register. Figure 6-8. Buffer Register Configuration Data read Internal bus Data write Master register Slave register Address/ count controller The actual DMA transfer is performed based on the settings of the slave register. The settings incorporated in the master and slave registers differ as follows according to the timing (time) at which the settings were made. (1) Time from system reset to generation of first DMA transfer request The settings made are incorporated in both the master and slave registers. (2) During DMA transfer (time from generation of DMA transfer request to end of DMA transfer) The settings made are incorporated in only the master register, and not in the slave register (the slave register maintains the value set for the next DMA transfer). However, the contents of the master register are automatically overwritten in the slave register after DMA transfer ends. The value of the slave register is read if the value of each register is read during this period. To check that DMA transfer has been started, confirm that the first transfer has been executed by reading the DBCn register (n = 0 to 3). (3) Time from DMA transfer end to start of next DMA transfer The settings made are incorporated in both the master and slave registers. Remark "DMA transfer end" means one of the following. * Completion of DMA transfer (terminal count) * Forcible termination of DMA transfer (the INITn bit of the DCHCn register is set to 1) 148 User's Manual U14492EJ5V0UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.9 DMA Transfer Start Factors There are two types of DMA transfer start factors, as shown below. Cautions 1. Do not use two or more start factors ((1) and (2)) in combination for the same channel (if two or more start factors are generated at the same time, only one of them is valid, but the valid start factor cannot be identified). The operation is not guaranteed if two or more start factors are used in combination. 2. If DMA transfer is started via software and if the software does not correctly detect whether the expected DMA transfer operation has been completed through manipulation (setting to 1) of the STGn bit of the DCHCn register, it cannot be guaranteed whether the next (second) manipulation of the STGn bit corresponds to the start of "the next DMA transfer expected by software" (n = 0 to 3). For example, suppose single transfer is started by manipulating the STGn bit. Even if the STGn bit is manipulated next (the second time) without checking by software whether the single transfer has actually been executed, the next (second) DMA transfer is not always executed. This is because the STGn bit may be manipulated the second time before the first DMA transfer is started or completed because, for example, DMA transfer with a higher priority had already been started when the STGn bit was manipulated for the first time. It is therefore necessary to manipulate the STGn bit next time (the second time) after checking whether DMA transfer started by the first manipulation of the STGn bit has been completed. Completion of DMA transfer can be checked by checking the contents of the DBCn register. (1) Request from software If the STGn, Enn, and TCn bits of the DCHCn register are set as follows, DMA transfer starts (n = 0 to 3). * STGn bit = 1 * Enn bit = 1 * TCn bit = 0 (2) Request from on-chip peripheral I/O If, when the Enn and TCn bits of the DCHCn register are set as shown below, an interrupt request is issued from the on-chip peripheral I/O that is set in the DTFRn register, DMA transfer starts (n = 0 to 3). * Enn bit = 1 * TCn bit = 0 User's Manual U14492EJ5V0UD 149 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.10 Forcible Interruption DMA transfer can be forcibly interrupted by NMI input during DMA transfer. At such a time, the DMAC clears the Enn bit of the DCHCn register of all channels to 0 and the DMA transfer disabled state is entered. An NMI request can then be acknowledged after the DMA transfer executed during NMI input is terminated (n = 0 to 3). If DMA transfer has been forcibly interrupted, perform forcible termination of the DMA using the INITn bit of the DCHCn register and then initialize. 6.11 DMA Transfer End When DMA transfer ends and the TCn bit of the DCHCn register is set to 1, a DMA transfer end interrupt (INTDMAn) is issued to the interrupt controller (INTC) (n = 0 to 3). 150 User's Manual U14492EJ5V0UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.12 Forcible Termination In addition to the forcible interruption operation by means of NMI input, DMA transfer can be forcibly terminated by the INITn bit of the DCHCn register (n = 0 to 3). An example of forcible termination by the INITn bit of the DCHCn register is illustrated below (n = 0 to 3). Figure 6-9. Example of Forcible Termination of DMA Transfer (a) Block transfer via DMA channel 3 is started during block transfer via DMA channel 2 DSA2, DDA2, DBC2, DADC2, DCHC2 Register set DMARQ2 (internal signal) E22 bit = 1 TC2 bit = 0 DSA3, DDA3, DBC3, DADC3, DCHC3 Register set DMARQ3 (internal signal) E33 bit = 1 TC3 bit = 0 E33 bit 0 TC3 bit 1 DCHC2 (INIT2 bit = 1) Register set E22 bit 0 TC2 bit = 0 CPU CPU CPU CPU DMA2 DMA2 DMA2 DMA2 DMA2 CPU DMA3 DMA3 DMA3 DMA3 CPU CPU CPU DMA channel 3 terminal count DMA channel 3 transfer start Forcible termination of DMA channel 2 transfer, bus released (b) When transfer is suspended during DMA channel 1 block transfer, and transfer under another condition is executed DSA1, DDA1, DBC1, DADC1, DCHC1 Register set DMARQ1 (internal signal) E11 bit = 1 TC1 bit = 0 DSA1, DDA1, DBC1 Register set DCHC1 (INIT1 bit = 1) DADC1, DCHC1 Register set E11 bit 0 TC1 bit 1 Register set E11 bit 0 TC1 bit = 0 E11 bit 1 TC1 bit = 0 CPU CPU CPU CPU DMA1 DMA1 DMA1 DMA1 DMA1 DMA1 CPU CPU CPU CPU DMA1 DMA1 DMA1 CPU Forcible termination of DMA channel 1 transfer, bus released DMA channel 1 terminal count Remark The values of the DSAn, DDAn, and DBCn registers (n = 0 to 3) are retained even when DMA transfer is forcibly terminated, because these registers are FIFO-format buffer registers. The next transfer condition can be set to these registers even while DMA transfer is in progress. On the other hand, the setting of the DADCn and DCHCn registers is invalid during DMA transfer because these registers are not buffer registers (see 6.8 Next Address Setting Function, 6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3), and 6.3.5 registers 0 to 3 (DCHC0 to DCHC3)). DMA channel control User's Manual U14492EJ5V0UD 151 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.12.1 Restriction related to DMA transfer forcible termination When terminating a DMA transfer by setting the INITn bit of the DCHCn register, the transfer may not be terminated, but just suspended, even though the INITn bit is set to 1. As a result, when the DMA transfer of a channel that should have been terminated is resumed, the DMA transfer will terminate after an unexpected number of transfers are completed and a DMA transfer completion interrupt may occur. [Preventive measures] This problem can be avoided by implementing any of the following workarounds. (1) Stop all the transfers from DMA channels temporarily. The following measure is effective if the program does not assume that the TCn bit of the DCHCn register is 1 except for the following workaround processing. (Since the TCn bit of the DCHCn register is cleared to 0 when it is read, execution of the following procedure (ii) under step <5> clears this bit.) <1> Disable interrupts (DI state). <2> Read the DMA restart register (DRST) and transfer the ENn bit of each channel to a general-purpose register (value A). <3> Write 00H to the DMA restart register (DRST) twiceNote. By executing twice, the DMA transfer is definitely stopped before proceeding to <4>. <4> Set the INITn bit of the DCHCn register of the channel to be forcibly terminated to 1. <5> Perform the following operations for value A read in step <2>. (Value B) (i) Clear the bit of the channel to be forcibly terminated to 0 (ii) If the TCn of the DCHCn register and ENn bit of the DRST register of the channel that is not terminated forcibly are 1 (AND makes 1), clear the bit of the channel to 0. <6> Write value B in <5> to the DRST register. <7> Enable interrupts (EI state). Note Execute three times if the transfer target (transfer source or transfer destination) is the internal RAM. Caution Be sure to execute step <5> to prevent the ENn bit of the DRST register from being set illegally for channels that are terminated normally during the period of steps <2> and <3>. Remark n = 0 to 3 152 User's Manual U14492EJ5V0UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) Repeat setting the INITn bit of the DCHCn register until forcible termination of DMA transfer is completed normally The procedure is shown below. <1> Copy the initial transfer count of the channel to be forcibly terminated to a general-purpose register. <2> Set the INITn bit of the DCHCn register of the channel to be forcibly terminated to 1. <3> Read the value of DMA transfer count register n (DBCn) of the channel to be forcibly terminated, and compare that value with the value copied in step <1>. If the two values do not match, repeat steps <2> and <3>. Cautions 1. If the DBCn register is read in step <3>, and if DMA transfer is stopped due to trouble, the remaining number of transfers will be read. If DMA transfer has been forcibly terminated correctly, the initial number of transfers will be read. 2. With this procedure, it may take some time for the channel in question to be forcibly terminated in an application in which DMA transfer of a channel other than that to be forcibly terminated is frequently executed. Remark n = 0 to 3 6.13 Times Related to DMA Transfer The overhead before and after DMA transfer and minimum execution clock for DMA transfer are shown below. Table 6-3. Number of Minimum Execution Clocks in DMA Cycle DMA Cycle <1> Time to respond to DMA request <2> Memory access Internal RAM access On-chip peripheral I/O register access 4 clocks Note 1 Number of Minimum Execution Clocks 2 clocks Note 2 4 clocks + number of waits set by VSWC register Notes 1. 2. If an external interrupt (INTPn) is specified as a factor of starting DMA transfer, noise elimination time is added (n = 0 to 6, 100, 101, 110, 111, 20 to 25, 30, or 31). Two clocks are required for the DMA cycle. The minimum execution clock in the DMA cycle in each transfer mode is as follows. Single transfer: Block transfer: DMA response time (<1>) + Transfer source memory access (<2>) + 1Note + Transfer destination memory access (<2>) DMA response time (<1>) + (Transfer source memory access (<2>) + 1 destination memory access (<2>)) x Number of transfers Note One clock is always inserted between the read cycle and write cycle of DMA transfer. Note + Transfer User's Manual U14492EJ5V0UD 153 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.14 Precautions (1) Memory boundary The transfer operation is not guaranteed if the source or the destination address exceeds the area of DMA targets (external memory, internal RAM, or on-chip peripheral I/O) during DMA transfer. (2) Transfer of misaligned data DMA transfer of 16-bit bus width misaligned data is not supported. If the source or the destination address is set to an odd address, the LSB of the address is forcibly handled as "0". (3) Bus arbitration for CPU When an external device is targeted for DMA transfer, the CPU can access the internal ROM and internal RAM (if they are not subject to DMA transfer). When DMA transfer is executed between the on-chip peripheral I/O and internal RAM, the CPU can access the internal ROM. (4) DMA start factor Do not start two or more DMA channels with the same factor. If two or more DMA channels are started with the same factor, the DMA channel with a lower priority may be acknowledged before the DMA channel with a higher priority. Operation is not guaranteed in this case. (5) Program execution and DMA transfer with internal RAM Do not execute DMA transfer to/from the internal RAM and an instruction in the internal RAM simultaneously. (6) Restrictions related to automatic clearing of TCn bit of DCHCn register The TCn bit of the DCHCn register is automatically cleared to 0 when it is read. When DMA transfer is executed to transfer data to or from the internal RAM when two or more DMA transfer channels are simultaneously used, the TCn bit may not be cleared even if it is read after completion of DMA transfer (n = 0 to 3). Caution This restriction does not apply if one of the following conditions is satisfied. * Only one channel of DMA transfer is used. * DMA is not executed to transfer data to or from the internal RAM. [Preventive measures] To read the TCn bit of the DCHCn register of the DMA channel that is used to transfer data to or from the internal RAM, be sure to read the TCn bit three times in a row. This can accurately clear the TCn bit to 0. 154 User's Manual U14492EJ5V0UD CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (7) Read values of DSAn and DDAn registers If the values of the DSAn and DDAn registers are read during DMA transfer, the values in the middle of being updated may be read (n = 0 to 3). For example, if the DSAnH register and the DSAnL register are read in that order when the value of the DMA transfer source address (DSAn register) is "0000FFFFH" and the counting direction is incremental (when the SADn1 and SADn0 bits of the DADCn register = 00), the value of the DSAnL register differs as follows depending on whether DMA transfer is executed immediately after the DSAnH register has been read. (a) If DMA transfer does not occur while the DSAn register is being read <1> Reading DSAnH register: DSAnH = 0000H <2> Reading DSAnL register: DSAnL = FFFFH (b) If DMA transfer occurs while the DSAn register is being read <1> Reading DSAnH register: DSAnH = 0000H <2> Occurrence of DMA transfer <3> Incrementing DSAn register : DSAn = 00010000H <4> Reading DSAnL register: DSAnL = 0000H 6.14.1 Interrupt factors DMA transfer is interrupted if a bus hold is issued. If the factor (bus hold) interrupting DMA transfer disappears, DMA transfer promptly restarts. User's Manual U14492EJ5V0UD 155 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V850E/IA1 is provided with an interrupt controller (INTC) that can process a total of 53 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution. The V850E/IA1 can process interrupt requests from the on-chip peripheral hardware and external sources. Moreover, exception processing can be started by the TRAP instruction (software exception) or by generation of an exception event (i.e. fetching of an illegal opcode) (exception trap). Eight levels of software-programmable priorities can be specified for each interrupt request. Interrupt servicing starts after no fewer than 4 system clocks (80 ns (@ 50 MHz)) following the generation of an interrupt request. 7.1 Features Interrupts * Non-maskable interrupts: 1 source Caution P00 alternately functions as NMI, and is fixed to input. P00 and NMI cannot be switched. If the P00 bit of the P0 register is read, the level of the P00/NMI pin is read. Set the valid edge of the NMI pin using the ESN0 bit of the INTM0 register (default value: falling edge detection). * Maskable interrupts: 52 sources * 8 levels of programmable priorities (maskable interrupts) * Multiple interrupt control according to priority * Masks can be specified for each maskable interrupt request. * Noise eliminationNote, edge detection, and valid edge specification for external interrupt request signals. Note For details of the noise eliminator, refer to 14.5 Noise Eliminator. Exceptions * Software exceptions: 32 sources * Exception traps: 2 sources (illegal opcode exception and debug trap) Interrupt/exception sources are listed in Table 7-1. 156 User's Manual U14492EJ5V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt/Exception Source List (1/2) Type Classification Name Interrupt/Exception Source Controlling Register Reset Interrupt RESET NMI0 TRAP0nNote TRAP1n ILGOP/ DBG0 Maskable Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTDET0 INTDET1 INTTM00 INTCM003 INTTM01 INTCM013 INTP100/ INTCC100 Interrupt INTP101/ INTCC101 Interrupt Interrupt Interrupt INTCM100 INTCM101 INTP110/ INTCC110 Interrupt INTP111/ INTCC111 Interrupt Interrupt Interrupt Interrupt Interrupt INTCM110 INTCM111 INTTM20 INTTM21 INTP20/ INTCC20 Interrupt INTP21/ INTCC21 Interrupt INTP22/ INTCC22 Interrupt INTP23/ INTCC23 Interrupt INTP24/ INTCC24 Interrupt INTP25/ INTCC25 Interrupt INTTM3 TM3IC0 CC2IC5 CC2IC4 CC2IC3 INTP23 pin/ CC23 match INTP24 pin/ CC24 match INTP25 pin/ CC25 match TM3 overflow TM3 29 0250H 00000250H nextPC CC2IC2 INTP22 pin/CC22 match CC2IC1 INTP21 pin/CC21 match Pin/ TM20/TM21 Pin/ TM20/TM21 Pin/ TM20/TM21 Pin/ TM20/TM21 Pin/TM21 28 0240H 00000240H nextPC 27 0230H 00000230H nextPC 26 0220H 00000220H nextPC 25 0210H 00000210H nextPC 24 0200H 00000200H nextPC CM11IC0 CM11IC1 TM2IC0 TM2IC1 CC2IC0 CC11IC1 CM10IC0 CM10IC1 CC11IC0 CC10IC1 P0IC0 P0IC1 P0IC2 P0IC3 P0IC4 P0IC5 P0IC6 DETIC0 DETIC1 TM0IC0 CM03IC0 TM0IC1 CM03IC1 CC10IC0 Note Default Exception Generating Priority Unit - - - - - Pin Pin Pin Pin Pin Pin Pin ADC0 ADC1 TM00 TM00 TM01 TM01 Pin/TM10 - - - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Code Handler Address Restored PC Generating Source - - - - - RESET input NMI input TRAP instruction TRAP instruction Illegal opcode/ DBTRAP instruction INTP0 pin INTP1 pin INTP2 pin INTP3 pin INTP4 pin INTP5 pin INTP6 pin AD0 voltage detection AD1 voltage detection TM00 underflow CM003 match TM01 underflow CM013 match INTP100 pin/ CC100 match Pin Pin 0000H 0010H 00000000H Undefined 00000010H nextPC Non-maskable Interrupt Software exception Exception trap Exception Exception Exception 004nHNote 1 00000040H nextPC 005nHNote 1 00000050H nextPC 0060H 0080H 0090H 00A0H 00B0H 00C0H 00D0H 00E0H 00F0H 0100H 0110H 0120H 0130H 0140H 0150H 00000060H nextPC 00000080H nextPC 00000090H nextPC 000000A0H nextPC 000000B0H nextPC 000000C0H nextPC 000000D0H nextPC 000000E0H nextPC 000000F0H nextPC 00000100H nextPC 00000110H nextPC 00000120H nextPC 00000130H nextPC 00000140H nextPC 00000150H nextPC INTP101/INTP100 pinNote 2/ Pin/TM10 CC101 match CM100 match CM101 match INTP110 pin/ CC110 match INTP111/INTP110 pinNote 2/ Pin/TM11 CC111 match CM110 match CM111 match TM20 overflow TM21 overflow INTP20 pin/CC20 match TM11 TM11 TM20 TM21 Pin/TM20 TM10 TM10 Pin/TM10 14 0160H 00000160H nextPC 15 16 17 0170H 0180H 0190H 00000170H nextPC 00000180H nextPC 00000190H nextPC 18 01A0H 000001A0H nextPC 19 20 21 22 23 01B0H 01C0H 01D0H 01E0H 01F0H 000001B0H nextPC 000001C0H nextPC 000001D0H nextPC 000001E0H nextPC 000001F0H nextPC Notes 1. 2. n = 0 to FH Select using the CSL10 and CSL11 registers. User's Manual U14492EJ5V0UD 157 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt/Exception Source List (2/2) Type Classification Name Interrupt/Exception Source Controlling Register Maskable Interrupt INTP30/ INTCC30 Interrupt INTP31/ INTCC31 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt INTCM4 INTDMA0 INTDMA1 INTDMA2 INTDMA3 INTCREC INTCTRX CM4IC0 DMAIC0 DMAIC1 DMAIC2 DMAIC3 CANIC0 CANIC1 CM4 match signal End of DMA0 transfer End of DMA1 transfer End of DMA2 transfer End of DMA3 transfer TM4 DMA DMA DMA DMA 32 33 34 35 36 37 38 0280H 0290H 02A0H 02B0H 02C0H 02D0H 02E0H 00000280H nextPC 00000290H nextPC 000002A0H nextPC 000002B0H nextPC 000002C0H nextPC 000002D0H nextPC 000002E0H nextPC CC3IC1 INTP31 pin/CC31 match Pin/TM3 31 0270H 00000270H nextPC CC3IC0 INTP30 pin/CC30 match Generating Source Default Exception Generating Priority Unit Pin/TM3 30 0260H 00000260H nextPC Code Handler Address Restored PC CAN1 reception complete FCAN CAN1 transmission complete FCAN Interrupt INTCERR CANIC2 CAN1 communication error FCAN 39 02F0H 000002F0H nextPC Interrupt Interrupt INTCMAC INTCSI0 CANIC3 CSIIC0 CAN illegal write CSI0 transmission/ reception complete FCAN CSI0 40 41 0300H 0310H 00000300H nextPC 00000310H nextPC Interrupt INTCSI1 CSIIC1 CSI1 transmission/ reception complete CSI1 42 0320H 00000320H nextPC Interrupt INTSR0 SRIC0 UART0 reception complete UART0 43 0330H 00000330H nextPC Interrupt INTST0 STIC0 UART0 transmission complete UART0 44 0340H 00000340H nextPC Interrupt Interrupt INTSER0 INTSR1 SEIC0 SRIC1 UART0 reception error UART1 reception complete UART0 UART1 45 46 0350H 0360H 00000350H nextPC 00000360H nextPC Interrupt INTST1 STIC1 UART1 transmission complete UART1 47 0370H 00000370H nextPC Interrupt INTSR2 SRIC2 UART2 reception complete UART2 48 0380H 00000380H nextPC Interrupt INTST2 STIC2 UART2 transmission complete UART2 49 0390H 00000390H nextPC Interrupt Interrupt INTAD0 INTAD1 ADIC0 ADIC1 End of AD0 conversion End of AD1 conversion ADC0 ADC1 50 51 03A0H 03B0H 000003A0H nextPC 000003B0H nextPC 158 User's Manual U14492EJ5V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Remarks 1. Default priority: Restored PC: The priority order when two or more maskable interrupt requests are generated at the same time. The highest priority is 0. The value of the program counter (PC) saved to EIPC, FEPC, or DBPC of CPU when interrupt servicing is started. Note, however, that the restored PC when a non-maskable or maskable interrupt is acknowledged while one of the following instructions is being executed does not become the nextPC. (If an interrupt is acknowledged during instruction execution, execution stops, and then resumes after the interrupt servicing has finished. In this case, the address of the aborted instruction is the restore PC.) * Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W) * Division instructions (DIV, DIVH, DIVU, DIVHU) * PREPARE, DISPOSE instructions (only if an interrupt is generated before the stack pointer is updated) nextPC: The PC value that starts the processing following interrupt/exception processing. 2. The execution address of the illegal instruction when an illegal opcode exception occurs is calculated by (Restored PC - 4). User's Manual U14492EJ5V0UD 159 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2 Non-Maskable Interrupt A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupts. A non-maskable interrupt request is input from the NMI pin. When the valid edge specified by bit 0 (ESN0) of the external interrupt mode register 0 (INTM0) is detected on the NMI pin, the interrupt occurs. While the service program of the non-maskable interrupt is being executed, another non-maskable interrupt request is held pending. The pending NMI is acknowledged after the original service program of the non-maskable interrupt under execution has been terminated (by the RETI instruction). Note that if two or more NMI requests are input during the execution of the service program for an NMI, the number of NMIs that will be acknowledged after the RETI instruction is executed is only one. 160 User's Manual U14492EJ5V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.1 Operation If a non-maskable interrupt is generated by NMI input, the CPU performs the following processing, and transfers control to the handler routine. (1) Saves the restored PC to FEPC. (2) Saves the current PSW to FEPSW. (3) Writes exception code 0010H to the higher halfword (FECC) of ECR. (4) Sets the NP and ID bits of the PSW and clears the EP bit. (5) Sets the handler address (00000010H) corresponding to the non-maskable interrupt to the PC, and transfers control. The servicing configuration of a non-maskable interrupt is shown in Figure 7-1. Figure 7-1. Servicing Configuration of Non-Maskable Interrupt NMI input INTC acknowledged Non-maskable interrupt request CPU processing PSW.NP 0 FEPC FEPSW ECR.FECC PSW.NP PSW.EP PSW.ID PC restored PC PSW 0010H 1 0 1 00000010H Interrupt request held pending 1 Interrupt servicing User's Manual U14492EJ5V0UD 161 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-2. Acknowledging Non-Maskable Interrupt Request (a) If a new NMI request is generated while an NMI service program is being executed Main routine (PSW.NP = 1) NMI request NMI request NMI request held pending regardless of the value of the NP bit of the PSW Pending NMI request processed (b) If a new NMI request is generated twice while an NMI service program is being executed Main routine NMI request NMI request Held pending because NMI service program is being processed NMI request Held pending because NMI service program is being processed Only one NMI request is acknowledged even though two NMI requests are generated 162 User's Manual U14492EJ5V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.2 Restore Execution is restored from the non-maskable interrupt servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. (1) Restores the values of the PC and the PSW from FEPC and FEPSW, respectively, because the EP bit of the PSW is 0 and the NP bit of the PSW is 1. (2) Transfers control back to the address of the restored PC and PSW. Figure 7-3 illustrates how the RETI instruction is processed. Figure 7-3. RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 0 1 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Original processing restored Caution When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction during nonmaskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 1 using the LDSR instruction immediately before the RETI instruction. The solid lines show the CPU processing flow. Remark User's Manual U14492EJ5V0UD 163 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.3 Non-maskable interrupt status flag (NP) The NP flag is a status flag that indicates that non-maskable interrupt (NMI) servicing is under execution. This flag is set when an NMI interrupt has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged. 31 PSW 876543210 Initial value 00000020H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z Bit position 7 NP Bit name Function Indicates whether NMI interrupt servicing is in progress. 0: No NMI interrupt servicing 1: NMI interrupt currently being serviced 7.2.4 Edge detection function (1) External interrupt mode register 0 (INTM0) External interrupt mode register 0 (INTM0) is a register that specifies the valid edge of a non-maskable interrupt (NMI). The NMI valid edge can be specified to be either the rising edge or the falling edge by the ESN0 bit. This register can be read/written in 8-bit or 1-bit units. 7 INTM0 0 6 0 5 0 4 0 3 0 2 0 1 0 <0> ESN0 Address FFFFF880H Initial value 00H Bit position 0 Bit name ESN0 Specifies the NMI pin's valid edge. 0: Falling edge 1: Rising edge Function 164 User's Manual U14492EJ5V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3 Maskable Interrupts The V850E/IA1 has 52 maskable Maskable interrupt requests can be masked by interrupt control registers. interrupt sources. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority. In addition to the default priority, eight levels of priorities can be specified by using the interrupt control registers (programmable priority control). When an interrupt request has been acknowledged, the acknowledgment of other maskable interrupt requests is disabled and the interrupt disabled (DI) status is set. When the EI instruction is executed in an interrupt servicing routine, the interrupt enabled (EI) status is set, which enables servicing of interrupts having a higher priority than the interrupt request in progress (specified by the interrupt control register). Note that only interrupts with a higher priority will have this capability; interrupts with the same priority level cannot be nested. However, if multiple interrupts are executed, the following processing is necessary. <1> Save EIPC and EIPSW in memory or a general-purpose register before executing the EI instruction. <2> Execute the DI instruction before executing the RETI instruction, then reset EIPC and EIPSW with the values saved in <1>. 7.3.1 Operation If a maskable interrupt occurs by INT input, the CPU performs the following processing, and transfers control to a handler routine. (1) Saves the restored PC to EIPC. (2) Saves the current PSW to EIPSW. (3) Writes an exception code to the lower halfword of ECR (EICC). (4) Sets the ID bit of the PSW and clears the EP bit. (5) Sets the handler address corresponding to each interrupt to the PC, and transfers control. The servicing configuration of a maskable interrupt is shown in Figure 7-4. User's Manual U14492EJ5V0UD 165 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-4. Servicing Configuration of Maskable Interrupt INT input INTC acknowledged xxIF = 1 Yes xxMK = 0 Yes Priority higher than that of interrupt currently being serviced? No No Is the interrupt mask released? No Yes Priority higher than that of other interrupt request? No Yes Highest default priority of interrupt requests with the same priority? No Yes Maskable interrupt request CPU processing PSW.NP 0 PSW.ID 0 EIPC EIPSW ECR.EICC PSW.EP PSW.ID Corresponding bit of ISPRNote PC restored PC PSW exception code 0 1 1 handler address Interrupt request held pending 1 1 Interrupt request held pending Interrupt servicing Note For the ISPR register, see 7.3.6 In-service priority register (ISPR). The INT input masked by the interrupt controllers and the INT input that occurs while another interrupt is being serviced (when PSW.NP = 1 or PSW.ID = 1) are held pending internally by the interrupt controller. In such case, if the interrupts are unmasked, or when PSW.NP = 0 and PSW.ID = 0 as set by the RETI and LDSR instructions, input of the pending INT starts the new maskable interrupt servicing. 166 User's Manual U14492EJ5V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.2 Restore Recovery from maskable interrupt servicing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. (1) Restores the values of the PC and the PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and the NP bit of the PSW is 0. (2) Transfers control to the address of the restored PC and PSW. Figure 7-5 illustrates the processing of the RETI instruction. Figure 7-5. RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 0 PC PSW Corresponding bit of ISPRNote EIPC EIPSW 0 PC PSW FEPC FEPSW 1 Restores original processing Note For the ISPR register, see 7.3.6 In-service priority register (ISPR). Caution When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 0 using the LDSR instruction immediately before the RETI instruction. The solid lines show the CPU processing flow. Remark User's Manual U14492EJ5V0UD 167 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.3 Priorities of maskable interrupts The V850E/IA1 provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn). When two or more interrupts having the same priority level specified by the xxPRn bit are generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt request type (default priority level) beforehand. For more information, refer to Table 7-1 Interrupt/Exception Source List. The programmable priority control customizes interrupt requests into eight levels by setting the priority level specification flag. Note that when an interrupt request is acknowledged, the ID flag of PSW is automatically set to 1. Therefore, when multiple interrupts are to be used, clear the ID flag to 0 beforehand (for example, by placing the EI instruction in the interrupt service program) to set the interrupt enable mode. Remark xx: Identification name of each peripheral unit (refer to Table 7-2) n: Peripheral unit number (refer to Table 7-2) 168 User's Manual U14492EJ5V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-6. Example of Servicing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Serviced (1/2) Main routine Servicing of a EI Interrupt request a (level 3) Interrupt request b (level 2) EI Interrupt request b is acknowledged because the priority of b is higher than that of a and interrupts are enabled. Servicing of b Servicing of c Interrupt request c (level 3) Interrupt request d (level 2) Servicing of d Although the priority of interrupt request d is higher than that of c, d is held pending because interrupts are disabled. Servicing of e EI Interrupt request e (level 2) Interrupt request f (level 3) Interrupt request f is held pending even if interrupts are enabled because its priority is lower than that of e. Servicing of f Servicing of g EI Interrupt request g (level 1) Interrupt request h (level 1) Interrupt request h is held pending even if interrupts are enabled because its priority is the same as that of g. Servicing of h Caution The values of the EIPC and EIPSW registers must be saved before executing multiple interrupts. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. Remarks 1. a to u in the figure are the temporary names of interrupt requests shown for the sake of explanation. 2. The default priority in the figure indicates the relative priority between two interrupt requests. User's Manual U14492EJ5V0UD 169 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-6. Example of Servicing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Serviced (2/2) Main routine Servicing of i EI Interrupt request i (level 2) EI Interrupt request j (level 3) Interrupt request k (level 1) Servicing of k Interrupt request j is held pending because its priority is lower than that of i. k that occurs after j is acknowledged because it has the higher priority. Servicing of j Servicing of l Interrupt request m (level 3) Interrupt request n (level 1) Servicing of n Interrupt requests m and n are held pending because servicing of l is performed in the interrupt disabled status. Interrupt request l (level 2) Pending interrupt requests are acknowledged after servicing of interrupt request l. At this time, interrupt requests n is acknowledged first even though m has occurred first because the priority of n is higher than that of m. Servicing of m Interrupt request o (level 3) Interrupt request p (level 2) Servicing of o Servicing of p EI Servicing of q EI Servicing of r EI Interrupt request q Interrupt (level 1) request r (level 0) If levels 3 to 0 are acknowledged Servicing of s Interrupt request t (level 2) Interrupt request u (level 2) Pending interrupt requests t and u are acknowledged after servicing of s. Because the priorities of t and u are the same, u is acknowledged first because it has the higher default priority, regardless of the order in which the interrupt requests have been generated. Interrupt request s (level 1) Note 1 Note 2 Servicing of u Notes 1. Servicing of t Lower default priority Higher default priority 2. Caution The values of the EIPC and EIPSW registers must be saved before executing multiple interrupts. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. 170 User's Manual U14492EJ5V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-7. Example of Servicing Interrupt Requests Generated Simultaneously Main routine EI Interrupt request a (level 2) Interrupt request b (level 1) Interrupt request c (level 1) Servicing of interrupt request b . . Default priority a>b>c Servicing of interrupt request c Interrupt requests b and c are acknowledged first according to their priorities. Because the priorities of b and c are the same, b is acknowledged first according to the default priority. Servicing of interrupt request a Caution The values of the EIPC and EIPSW registers must be saved before executing multiple interrupts. When returning from multiple interrupt servicing, restore the values of EIPC and EIPSW after executing the DI instruction. Remark a to c in the figure are the temporary names of interrupt requests shown for the sake of explanation. User's Manual U14492EJ5V0UD 171 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.4 Interrupt control register (xxICn) An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read/written in 8-bit or 1-bit units. Caution Read the xxIFn bit of the xxICn register in the interrupt disabled (DI) state. Otherwise if the timing of interrupt acknowledgment and bit reading conflict, normal values may not be read. <7> xxICn xxIFn <6> xxMKn 5 0 4 0 3 0 <2> xxPRn2 <1> xxPRn1 <0> xxPRn0 Address Initial value FFFFF110H to 47H FFFFF176H Bit position 7 Bit name xxIFn This is an interrupt request flag. 0: Interrupt request not issued 1: Interrupt request issued Function The flag xxlFn is reset automatically by the hardware if an interrupt request is acknowledged. 6 xxMKn This is an interrupt mask flag. 0: Enables interrupt servicing 1: Disables interrupt servicing (pending) 2 to 0 xxPRn2 to xxPRn0 xxPRn2 0 0 0 0 1 1 1 1 xxPRn1 0 0 1 1 0 0 1 1 xxPRn0 0 1 0 1 0 1 0 1 Interrupt priority specification bit Specifies level 0 (highest). Specifies level 1. Specifies level 2. Specifies level 3. Specifies level 4. Specifies level 5. Specifies level 6. Specifies level 7 (lowest). 8 levels of priority order are specified for each interrupt. Remark xx: Identification name of each peripheral unit (refer to Table 7-2) n: Peripheral unit number (refer to Table 7-2) The address and bit of each interrupt control register are as follows. 172 User's Manual U14492EJ5V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-2. Addresses and Bits of Interrupt Control Registers (1/2) Address Register <7> FFFFF110H FFFFF112H FFFFF114H FFFFF116H FFFFF118H P0IC0 P0IC1 P0IC2 P0IC3 P0IC4 P0IF0 P0IF1 P0IF2 P0IF3 P0IF4 P0IF5 P0IF6 DETIF0 DETIF1 TM0IF0 <6> P0MK0 P0MK1 P0MK2 P0MK3 P0MK4 P0MK5 P0MK6 DETMK0 DETMK1 TM0MK0 CM03MK0 TM0MK1 CM03MK1 CC10MK0 CC10MK1 CM10MK0 CM10MK1 CC11MK0 CC11MK1 CM11MK0 CM11MK1 TM2MK0 TM2MK1 CC2MK0 CC2MK1 CC2MK2 CC2MK3 CC2MK4 CC2MK5 TM3MK0 CC3MK0 CC3MK1 CANMK2 DMAMK0 DMAMK1 DMAMK2 DMAMK3 CANMK0 CANMK1 CANMK2 CANMK3 CSIMK0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 <2> P0PR02 P0PR12 P0PR22 P0PR32 P0PR42 P0PR52 P0PR62 DETPR02 DETPR12 TM0PR02 <1> P0PR01 P0PR11 P0PR21 P0PR31 P0PR41 P0PR51 P0PR61 DETPR01 DETPR11 TM0PR01 <0> P0PR00 P0PR10 P0PR20 P0PR30 P0PR40 P0PR50 P0PR60 DETPR00 DETPR10 TM0PR00 FFFFF11AH P0IC5 FFFFF11CH P0IC6 FFFFF11EH DETIC0 FFFFF120H FFFFF122H FFFFF124H FFFFF126H FFFFF128H DETIC1 TM0IC0 CM03IC0 CM03IF0 TM0IC1 TM0IF1 CM03PR02 CM03PR01 CM03PR00 TM0PR12 TM0PR11 TM0PR10 CM03IC1 CM03IF1 CM03PR12 CM03PR11 CM03PR10 CC10PR02 CC10PR01 CC10PR00 CC10PR12 CC10PR11 CC10PR10 CM10PR02 CM10PR01 CM10PR00 CM10PR12 CM10PR11 CM10PR10 CC11PR02 CC11PR01 CC11PR00 CC11PR12 CC11PR11 CC11PR10 CM11PR02 CM11PR01 CM11PR00 CM11PR12 CM11PR11 CM11PR10 TM2PR02 TM2PR12 CC2PR02 CC2PR12 CC2PR22 CC2PR32 CC2PR42 CC2PR52 TM3PR02 CC3PR02 CC3PR12 CM4PR02 DMAPR02 DMAPR12 DMAPR22 DMAPR32 CANPR02 CANPR12 CANPR22 CANPR32 CSIPR02 TM2PR01 TM2PR11 CC2PR01 CC2PR11 CC2PR21 CC2PR31 CC2PR41 CC2PR51 TM3PR01 CC3PR01 CC3PR11 CM4PR01 DMAPR01 DMAPR11 DMAPR21 DMAPR31 CANPR01 CANPR11 CANPR21 CANPR31 CSIPR01 TM2PR00 TM2PR10 CC2PR00 CC2PR10 CC2PR20 CC2PR30 CC2PR40 CC2PR50 TM3PR00 CC3PR00 CC3PR10 CM4PR00 DMAPR00 DMAPR10 DMAPR20 DMAPR30 CANPR00 CANPR10 CANPR20 CANPR30 CSIPR00 FFFFF12AH CC10IC0 CC10IF0 FFFFF12CH CC10IC1 CC10IF1 FFFFF12EH CM10IC0 CM10IF0 FFFFF130H FFFFF132H FFFFF134H FFFFF136H FFFFF138H CM10IC1 CM10IF1 CC11IC0 CC11IF0 CC11IC1 CC11IF1 CM11IC0 CM11IF0 CM11IC1 CM11IF1 TM2IF0 TM2IF1 CC2IF0 CC2IF1 CC2IF2 CC2IF3 CC2IF4 CC2IF5 TM3IF0 CC3IF0 CC3IF1 CM4IF0 DMAIF0 DMAIF1 DMAIF2 DMAIF3 CANIF0 CANIF1 CANIF2 CANIF3 CSIIF0 FFFFF13AH TM2IC0 FFFFF13CH TM2IC1 FFFFF13EH CC2IC0 FFFFF140H FFFFF142H FFFFF144H FFFFF146H FFFFF148H CC2IC1 CC2IC2 CC2IC3 CC2IC4 CC2IC5 FFFFF14AH TM3IC0 FFFFF14CH CC3IC0 FFFFF14EH CC3IC1 FFFFF150H FFFFF152H FFFFF154H FFFFF156H FFFFF158H CM4IC0 DMAIC0 DMAIC1 DMAIC2 DMAIC3 FFFFF15AH CANIC0 FFFFF15CH CANIC1 FFFFF15EH CANIC2 FFFFF160H FFFFF162H CANIC3 CSIIC0 User's Manual U14492EJ5V0UD 173 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-2. Addresses and Bits of Interrupt Control Registers (2/2) Address Register <7> FFFFF164H FFFFF166H FFFFF168H CSIIC1 SRIC0 STIC0 CSIIF1 SRIF0 STIF0 SEIF0 SRIF1 STIF1 SRIF2 STIF2 ADIF0 ADIF1 <6> CSIMK1 SRMK0 STMK0 SEMK0 SRMK1 STMK1 SRMK2 STMK2 ADMK0 ADMK1 5 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 Bit 3 0 0 0 0 0 0 0 0 0 0 <2> CSIPR12 SRPR02 STPR02 SEPR02 SRPR12 STPR12 SRPR22 STPR22 ADPR02 ADPR12 <1> CSIPR11 SRPR01 STPR01 SEPR01 SRPR11 STPR11 SRPR21 STPR21 ADPR01 ADPR11 <0> CSIPR10 SRPR00 STPR00 SEPR00 SRPR10 STPR10 SRPR20 STPR20 ADPR00 ADPR10 FFFFF16AH SEIC0 FFFFF16CH SRIC1 FFFFF16EH STIC1 FFFFF170H FFFFF172H FFFFF174H FFFFF176H SRIC2 STIC2 ADIC0 ADIC1 174 User's Manual U14492EJ5V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) These registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to IMR3 registers is equivalent to the xxMKn bit of the xxICn register. IMRm can be read/written in 16-bit units (m = 0 to 3). When the IMRm register is divided into two registers: higher 8 bits (IMRmH register) and lower 8 bits (IMRmL register), these registers can be read/written in 8-bit or 1-bit units. Caution The device file defines the xxMKn bit of the xxICn register as a reserved word. rewritten (as a result, the IMRm register is also rewritten). If a bit is manipulated with the name xxMKn, therefore, the xxICn register, rather than the IMRm register, is <15> <14> <13> <12> <11> <10> <9> <8> Address FFFFF100H Initial value FFFFH IMR0 CM10MK0 CC10MK1 CC10MK0 CM03MK1 TM0MK1 CM03MK0 TM0MK0 DETMK1 <7> DETMK0 <6> P0MK6 <5> P0MK5 <4> P0MK4 <3> P0MK3 <2> P0MK2 <1> P0MK1 <0> P0MK0 <15> <14> <13> <12> <11> <10> <9> <8> Address FFFFF102H Initial value FFFFH IMR1 CC3MK1 CC3MK0 TM3MK0 CC2MK5 CC2MK4 CC2MK3 CC2MK2 CC2MK1 <7> <6> <5> <4> <3> <2> <1> <0> CC2MK0 TM2MK1 TM2MK0 CM11MK1 CM11MK0 CC11MK1 CC11MK0 CM10MK1 <15> IMR2 STMK1 <7> <14> SRMK1 <6> <13> SEMK0 <5> <12> STMK0 <4> <11> SRMK0 <3> <10> CSIMK1 <2> <9> <8> Address FFFFF104H Initial value FFFFH CSIMK0 CANMK3 <1> <0> CANMK2 CANMK1 CANMK0 DMAMK3 DMAMK2 DMAMK1 DMAMK0 CM4MK0 15 IMR3 1 7 1 14 1 6 1 13 1 5 1 12 1 4 1 11 1 <3> ADMK1 10 1 <2> ADMK0 9 1 <1> STMK2 8 1 <0> SRMK2 Address FFFFF106H Initial value FFFFH Bit position 15 to 0 (IMR0 to 2), 0 to 3 (IMR3) Bit name xxMKn Function Interrupt mask flag 0: Interrupt servicing enabled 1: Interrupt servicing disabled (pending) Remark xx: Identification name of each peripheral unit (refer to Table 7-2) n: Peripheral unit number (refer to Table 7-2) User's Manual U14492EJ5V0UD 175 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.6 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced. When the RETI instruction is executed, the bit corresponding to the interrupt request having the highest priority is automatically cleared to 0 by hardware. However, it is not cleared to 0 when execution is returned from non-maskable interrupt servicing or exception processing. This register is read-only, in 8-bit or 1-bit units. Caution In the interrupt enabled (EI) state, if an interrupt is acknowledged during the reading of the ISPR register, the value of the ISPR register may be read after the bit is set to 1 by this interrupt acknowledgment. To read the value of the ISPR register properly before interrupt acknowledgment, read it in the interrupt disabled (DI) state. <7> ISPR ISPR7 <6> ISPR6 <5> ISPR5 <4> ISPR4 <3> ISPR3 <2> ISPR2 <1> ISPR1 <0> ISPR0 Address FFFFF1FAH Initial value 00H Bit position 7 to 0 Bit name ISPR7 to ISPR0 Function Indicates priority of interrupt currently acknowledged 0: Interrupt request with priority n not acknowledged 1: Interrupt request with priority n acknowledged Remark n = 0 to 7 (priority level) 176 User's Manual U14492EJ5V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.7 Maskable interrupt status flag (ID) The ID flag is bit 5 of the PSW and this controls the maskable interrupt's operating state, and stores control information regarding enabling or disabling of interrupt requests. 31 PSW 876543210 Initial value 00000020H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z Bit position 5 ID Bit name Function Indicates whether maskable interrupt servicing is enabled or disabled. 0: Maskable interrupt request acknowledgment enabled 1: Maskable interrupt request acknowledgment disabled (pending) This bit is set to 1 by the DI instruction and reset to 0 by the EI instruction. Its value is also modified by the RETI instruction or LDSR instruction when referencing the PSW. Non-maskable interrupt requests and exceptions are acknowledged regardless of this flag. When a maskable interrupt is acknowledged, the ID flag is automatically set to 1 by hardware. The interrupt request generated during the acknowledgment disabled period (ID = 1) is acknowledged when the xxIFn bit of xxICn register is set to 1, and the ID flag is reset to 0. 7.3.8 Interrupt trigger mode selection The valid edge of the INTPn, ADTRG0, ADTRG1, TIUD10, TIUD11, TCUD10, TCUD11, TCLR10, TCLR11, TCLR3, and TI3 pins can be selected by program. The edge that can be selected as the valid edge is one of the following (n = 0 to 6, 20 to 25, 30, 31, 100, 101, 110, 111). * Rising edge * Falling edge * Both the rising and falling edges When the INTPn, ADTRG0, ADTRG1, TIUD10, TIUD11, TCUD10, TCUD11, TCLR10, TCLR11, TCLR3, and TI3 signals are edge-detected, they become an interrupt source or capture/trigger. The valid edge is specified by external interrupt mode registers 1 and 2 (INTM1 and INTM2), signal edge selection registers 10 and 11 (SESA10 and SESA11), the valid edge selection register (SESC), and TM2 input filter mode registers 0 to 5 (FEM0 to FEM5). User's Manual U14492EJ5V0UD 177 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) External interrupt mode registers 1, 2 (INTM1, INTM2) These registers specify the valid edge for external interrupt requests (INTP0 to INTP6), input via external pins. The correspondence between each register and the external interrupt requests that register controls is shown below. * INTM1: INTP0, INTP1, INTP2/ADTRG0, INTP3/ADTRG1 * INTM2: INTP4 to INTP6 INTP2 and INTP3 function alternately as ADTRG0 and ADTRG1 (A/D converter external trigger input). Therefore, if the external trigger mode has been set by the TRG0 to TRG2 bits of A/D converter mode register n0 (ADSCMn0), setting the ES20 and ES21, and ES30 and ES31 bits of INTM1 also specifies the valid edge of the external trigger input (ADTRG0 and ADTRG1) (n = 0, 1). The valid edge can be specified independently for each pin (rising edge, falling edge, or both rising and falling edges). These registers can be read/written in 8-bit or 1-bit units. 7 INTM1 ES31 6 ES30 5 ES21 4 ES20 3 ES11 2 ES10 1 ES01 0 ES00 Address FFFFF882H Initial value 00H INTP3/ADTRG1 7 INTM2 0 6 0 INTP2/ADTRG0 5 ES61 4 ES60 3 INTP1 2 ES50 1 INTP0 0 ES40 Address FFFFF884H Initial value 00H ES51 ES41 INTP6 INTP5 INTP4 Bit position 7 to 0 (INTM1), 5 to 0 (INTM2) Bit name ESn1, ESn0 (n = 0 to 6) ESn1 0 0 1 1 ESn0 0 1 0 1 Function Specifies the valid edge of the INTPn, ADTRG0 and ADTRG1 pins. Operation Falling edge Rising edge Setting prohibited Both rising and falling edges 178 User's Manual U14492EJ5V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Signal edge selection registers 10, 11 (SESA10, SESA11) These registers specify the valid edge of external interrupt requests (INTP100, INTP101, INTP110, INTP111, TIUD10, TIUD11, TCUD10, TCUD11, TCLR10, and TCLR11), input via external pins. The correspondence between each register and the external interrupt requests that register controls is shown below. * SESA10: TIUD10, TCUD10, TCLR10, INTP100, INTP101 * SESA11: TIUD11, TCUD11, TCLR11, INTP110, INTP111 The valid edge can be specified independently for each pin (rising edge, falling edge, or both rising and falling edges). These registers can be read/written in 8-bit or 1-bit units. Cautions 1. The bits of the SESA1n register cannot be changed during TM1n operation (TM1CEn bit of timer control registers 10, 11 (TMC10, TMC11) = 1). 2. The TM1CEn bit must be set (1) before using the TCUD10/INTP100, TCLR10/INTP101, TCUD11/INTP110, and TCLR11/INTP111 pins as INTP100, INTP101, INTP110, and INTP111, even if not using timer 1. 3. Before setting the INTP100, INTP101, INTP110, INTP111, TIUD10, TIUD11, TCUD10, TCUD11, TCLR10, and TCLR11 pins to the trigger mode, set the PMC1 register. If the PMC1 register is set after the SESA10 and SESA11 registers have been set, an illegal interrupt may occur as soon as the PMC1 register is set. User's Manual U14492EJ5V0UD 179 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1/2) 7 6 5 4 3 2 1 0 Address FFFFF5EDH Initial value 00H SESA10 TESUD01 TESUD00 CESUD01 CESUD00 IES1011 IES1010 IES1001 IES1000 TIUD10, TCUD10 7 6 5 TCLR10 4 3 INTP101 2 IES1110 1 IES1101 INTP100 0 IES1100 Address FFFFF60DH Initial value 00H SESA11 TESUD11 TESUD10 CESUD11 CESUD10 IES1111 TIUD11, TCUD11 TCLR11 INTP111 INTP110 Bit position 7, 6 Bit name TESUDn1, TESUDn0 TESUDn1 0 0 1 1 TESUDn0 0 1 0 1 Function Specifies the valid edge of the TIUD10, TIUD11, TCUD10, and TCUD11 pins. Valid edge Falling edge Rising edge Setting prohibited Both rising and falling edges Cautions 1. The values set to the TESUDn1 and TESUDn0 bits are valid only in UDC mode A Note 1 and UDC mode B Note 1 . Note 2 2. If TM1n operation has been specified in mode 4 TCUD1n pins is invalid. 5, 4 CESUDn1, CESUDn0 CESUDn1 0 0 1 1 CESUDn0 0 1 0 1 Falling edge Rising edge Low level High level Valid edge Specifies the valid edge of the TCLR10 and TCLR11 pins. , the valid edge specification (TESUDn1 and TESUDn0 bits) for the TIUD1n and The setting values of the CESUDn1 and CESUDn0 bits and the operation of TM1n are as follows. 00: TM1n cleared after detection of TCLR1n rising edge 01: TM1n cleared after detection of TCLR1n falling edge 10: TM1n holds cleared status while TCLR1n input is low level 11: TM1n holds cleared status while TCLR1n input is high level Caution The values set to the CESUDn1 and CESUDn0 bits are valid only in UDC mode A Note 1 . Remark Notes 1. 2. n = 0, 1 See 9.2.4 (2) Timer unit mode registers 0, 1 (TUM0, TUM1) See 9.2.4 (6) Prescaler mode registers 10, 11 (PRM10, PRM11) 180 User's Manual U14492EJ5V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2/2) Bit position 3, 2 Bit name IES1n11, IES1n10 Function Specifies the valid edge of the pin selected using the CSLn bit of the CSL1n register (INTP1n1, INTP1n0). IES1n11 0 0 1 1 IES1n10 0 1 0 1 Falling edge Rising edge Setting prohibited Valid edge Both rising and falling edges 1, 0 IES1n01, IES1n00 Specifies the valid edge of the INTP100 and INTP110 pins. IES1n01 0 0 1 1 IES1n00 0 1 0 1 Falling edge Rising edge Setting prohibited Valid edge Both rising and falling edges Remark n = 0, 1 User's Manual U14492EJ5V0UD 181 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) Valid edge selection register (SESC) This register specifies the valid edge for external interrupt requests (INTP30, INTP31, TCLR3, and TI3), input via external pins. The valid edge can be specified independently for each pin (rising edge, falling edge, or both rising and falling edges). This register can be read/written in 8-bit or 1-bit units. Cautions 1. The TM3CAE and TM3CE bits of timer control register 30 (TMC30) must be set (1) before using the TI3/TCLR3/INTP30 and TO3/INTP31 pins as INTP30 and INTP31, even if not using timer 3. 2. Before setting the INTP30, INTP31, TCLR3, and TI3 pins to the trigger mode, set the PMC2 register. If the PMC2 register is set after the SESC register has been set, an illegal interrupt may occur as soon as the PMC2 register is set. 7 SESC TES31 TI3 6 TES30 5 CES31 4 CES30 3 IES311 2 IES310 1 IES301 0 IES300 Address FFFFF689H Initial value 00H TCLR3 INTP31 INTP30 Bit position 7, 6 Bit name TES31, TES30 Function Specifies the valid edge of the INTP30, INTP31, TCLR3, and TI3 pins. 5, 4 CES31, CES30 xESn1 0 0 xESn0 0 1 0 1 Falling edge Rising edge Setting prohibited Operation 3, 2 IES311, IES310 1 1 Both rising and falling edges Remark 1, 0 TES301, TES300 n = 3, 30, 31 182 User's Manual U14492EJ5V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (4) Timer 2 input filter mode registers 0 to 5 (FEM0 to FEM5) These registers specify the valid edge for external interrupt requests input to timer 2 (INTP20 to INTP25). The correspondence between each register and the external interrupt request that register controls is shown below. * FEM0: INTP20 * FEM1: INTP21 * FEM2: INTP22 * FEM3: INTP23 * FEM4: INTP24 * FEM5: INTP25 The valid edge can be specified independently for each pin (rising edge, falling edge, or both rising and falling edges). These registers can be read/written in 8-bit or 1-bit units. Cautions 1. The STFTE bit of timer 2 clock stop register 0 (STOPTE0) must be cleared (0) before using the TI2/INTP20, TO21/INTP21, TO22/INTP22, TO23/INTP23, TO24/INTP24, and TCLR2/INTP25 pins as INTP20, INTP21, INTP22, INTP23, INTP24, and INTP25, even if not using timer 2. 2. Before setting the INTP2n pin to the trigger mode, set the PMC2 register. If the PMC2 register is set after the FEMn register has been set, an illegal interrupt may occur as soon as the PMC2 register is set (n = 0 to 5). 3. The noise elimination function starts operating by setting the CEEn bit of the TCRE0 register to 1 (enabling count operations). User's Manual U14492EJ5V0UD 183 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1/2) 7 FEM0 DFEN00 6 0 5 0 4 0 3 2 1 0 TMS000 Address FFFFF630H Initial value 00H EDGE010 EDGE000 TMS010 INTP20 7 FEM1 DFEN01 6 0 5 0 4 0 3 2 1 0 TMS001 Address FFFFF631H Initial value 00H EDGE011 EDGE001 TMS011 INTP21 7 FEM2 DFEN02 6 0 5 0 4 0 3 2 1 0 TMS002 Address FFFFF632H Initial value 00H EDGE012 EDGE002 TMS012 INTP22 7 FEM3 DFEN03 6 0 5 0 4 0 3 2 1 0 TMS003 Address FFFFF633H Initial value 00H EDGE013 EDGE003 TMS013 INTP23 7 FEM4 DFEN04 6 0 5 0 4 0 3 2 1 0 TMS004 Address FFFFF634H Initial value 00H EDGE014 EDGE004 TMS014 INTP24 7 FEM5 DFEN05 6 0 5 0 4 0 3 2 1 0 TMS005 Address FFFFF635H Initial value 00H EDGE015 EDGE005 TMS015 INTP25 Bit position 7 Bit name DFEN0n Specifies the filter of the INTP2n pin. 0: Analog filter 1: Digital filter Function Caution When the DFEN0n bit = 1, the sampling clock of the digital filter is fXXTM2 (clock of TM20 and TM21 selected by PRM02 register). 3, 2 EDGE01n, EDGE00n EDGE01n 0 0 1 1 EDGE00n 0 1 0 1 Operation Interrupt by INTCC2n Rising edge Falling edge Both rising and falling edges Note Specifies the valid edge of the INTP2n pin. Note Set when INTCC2n is selected by a match between TM20, TM21 and the subchannel compare register (specified by the TMS01n, TMS00n bits) (n = 0 to 5). Remark n = 0 to 5 184 User's Manual U14492EJ5V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2/2) Bit position 1, 0 Bit name TMS01n, TMS00n TMS01n 0 0 1 1 TMS00n 0 1 0 1 Used as a pin Digital filter (noise eliminator specification) Timer-based capture to sub-channel 1 Timer-based capture to sub-channel 2 Operation Selects the capture input Note Function . Note Selection of capture input based on INTCM100 and INTCM101 is valid only for the FEM1 and FEM2 registers. Set the TMS01m and TMS00m bits of the FEMm register to 00B or 01B. All other settings are prohibited (m = 1, 3 to 5). Sub-channels 1 and 2 of timer 2 can be captured by INTP21, INTP22, and INTCM100, INTCM101. An example is given below. (a) When sub-channel 1 is captured by INTCM101 FEM1 register = xxxxxx10B TMIC0 register = 00000010B (b) When sub-channel 2 is captured by INTCM101 FEM2 register = xxxxxx11B TMIC0 register = 00001000B Remark n = 0 to 5 User's Manual U14492EJ5V0UD 185 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can be always acknowledged. 7.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine. (1) Saves the restored PC to EIPC. (2) Saves the current PSW to EIPSW. (3) Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source). (4) Sets the EP and ID bits of the PSW. (5) Sets the handler address (00000040H or 00000050H) corresponding to the software exception to the PC, and transfers control. Figure 7-8 illustrates the processing of a software exception. Figure 7-8. Software Exception Processing TRAP instructionNote CPU processing EIPC EIPSW ECR.EICC PSW.EP PSW.ID PC restored PC PSW exception code 1 1 handler address Exception processing Note TRAP instruction format: TRAP vector (the vector is a value from 00H to 1FH.) The handler address is determined by the TRAP instruction's operand (vector). If the vector is 00H to 0FH, it becomes 00000040H, and if the vector is 10H to 1FH, it becomes 00000050H. 186 User's Manual U14492EJ5V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4.2 Restore Recovery from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC's address. (1) Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1. (2) Transfers control to the address of the restored PC and PSW. Figure 7-9 illustrates the processing of the RETI instruction. Figure 7-9. RETI Instruction Processing RETI instruction 1 PSW.EP 0 PSW.NP 0 1 PC PSW EIPC EIPSW PC PSW FEPC FEPSW Original processing restored Caution When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during the software exception processing, in order to restore the PC and PSW correctly during recovery by the RETI instruction, it is necessary to set PSW.EP back to 1 using the LDSR instruction immediately before the RETI instruction. The solid lines show the CPU processing flow. Remark User's Manual U14492EJ5V0UD 187 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4.3 Exception status flag (EP) The EP flag is bit 6 of PSW, and is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. 31 PSW 876543210 Initial value 00000020H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z Bit position 6 EP Bit name Function Shows that exception processing is in progress. 0: Exception processing not in progress. 1: Exception processing in progress. 188 User's Manual U14492EJ5V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.5 Exception Trap An exception trap is an interrupt that is requested when an illegal execution of an instruction takes place. In the V850E/IA1, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 7.5.1 Illegal opcode definition The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B, and a sub-opcode (bit 16) of 0B. instruction is executed. An exception trap is generated when an instruction applicable to this illegal 15 11 10 54 0 31 27 26 23 22 16 0 xxxxx x: Arbitrary 111111 xxxxxxxxxx 0111 to 1111 xxxxxx Caution Since it is possible to assign this instruction to an illegal opcode in the future, it is recommended that it not be used. (1) Operation If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler routine. (1) Saves the restored PC to DBPC. (2) Saves the current PSW to DBPSW. (3) Sets the NP, EP, and ID bits of the PSW. (4) Sets the handler address (00000060H) corresponding to the exception trap to the PC, and transfers control. Figure 7-10 illustrates the processing of the exception trap. User's Manual U14492EJ5V0UD 189 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-10. Exception Trap Processing Exception trap (ILGOP) occurs CPU processing DBPC DBPSW PSW.NP PSW.EP PSW.ID PC restored PC PSW 1 1 1 00000060H Exception processing (2) Restore Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC. (1) Loads the restored PC and PSW from DBPC and DBPSW. (2) Transfers control to the address indicated by the restored PC and PSW. Figure 7-11 illustrates the restore processing from an exception trap. Figure 7-11. Restore Processing from Exception Trap DBRET instruction PC PSW DBPC DBPSW Jump to address of restored PC 190 User's Manual U14492EJ5V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.5.2 Debug trap The debug trap is an exception that can be acknowledged every time and is generated by execution of the DBTRAP instruction. When the debug trap is generated, the CPU performs the following processing. (1) Operation (1) Saves the restored PC to DBPC. (2) Saves the current PSW to DBPSW. (3) Sets the NP, EP and ID bits of the PSW. (4) Sets the handler address (00000060H) corresponding to the debug trap to the PC and transfers control. Figure 7-12 illustrates the processing of the debug trap. Figure 7-12. Debug Trap Processing DBTRAP instruction CPU processing DBPC DBPSW PSW.NP PSW.EP PSW.ID PC restored PC PSW 1 1 1 00000060H Debug monitor routine processing User's Manual U14492EJ5V0UD 191 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restore Restoration from a debug trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC. (1) Loads the restored PC and PSW from DBPC and DBPSW. (2) Transfers control to the address indicated by the restored PC and PSW. Caution DBPC and DBPSW can be accessed during the period between when the DBTRAP is executed and when the DBRET instruction is executed. Figure 7-13 illustrates the processing for restoring from a debug trap. Figure 7-13. Processing for Restoring from Debug Trap DBRET instruction PC PSW DBPC DBPSW Jump to address of restored PC 192 User's Manual U14492EJ5V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.6 Multiple Interrupt Servicing Control Multiple interrupt servicing control is a process by which an interrupt request that is currently being serviced can be interrupted during servicing if there is an interrupt request with a higher priority level, and the higher priority interrupt request is acknowledged and serviced first. If there is an interrupt request with a lower priority level than the interrupt request currently being serviced, that interrupt request is held pending. Maskable interrupt multiple servicing control is executed when interrupts are enabled (ID = 0). Thus, if multiple interrupts are executed, it is necessary for interrupts to be enabled (ID = 0) even during an interrupt servicing routine. If a maskable interrupt or a software exception is generated in a maskable interrupt or software exception service program, it is necessary to save EIPC and EIPSW. This is accomplished by the following procedure. (1) Acknowledgement of maskable interrupts in service program Service program of maskable interrupt or exception ... ... * EIPC saved to memory or register * EIPSW saved to memory or register * EI instruction (interrupt acknowledgment enabled) ... ... ... ... * DI instruction (interrupt acknowledgment disabled) * Saved value restored to EIPSW * Saved value restored to EIPC * RETI instruction Maskable interrupt acknowledgment User's Manual U14492EJ5V0UD 193 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Generation of exception in service program Service program of maskable interrupt or exception ... ... * EIPC saved to memory or register * EIPSW saved to memory or register ... * TRAP instruction ... * Saved value restored to EIPSW * Saved value restored to EIPC * RETI instruction Exception such as TRAP instruction acknowledged. The priority order for multiple interrupt servicing control has 8 levels, from 0 to 7 for each maskable interrupt request (0 is the highest priority), but it can be set as desired via software. Setting of the priority order level is done using the xxPRn0 to xxPRn2 bits of the interrupt request control register (xxlCn), which is provided for each maskable interrupt request. After system reset, an interrupt request is masked by the xxMKn bit and the priority order is set to level 7 by the xxPRn0 to xxPRn2 bits. The priority order of maskable interrupts is as follows. (High) Level 0 > Level 1 > Level 2 > Level 3 > Level 4 > Level 5 > Level 6 > Level 7 (Low) Interrupt servicing that has been suspended as a result of multiple servicing control is resumed after the servicing of the higher priority interrupt has been completed and the RETI instruction has been executed. A pending interrupt request is acknowledged after the current interrupt servicing has been completed and the RETI instruction has been executed. Caution In a non-maskable interrupt servicing routine (time until the RETI instruction is executed), maskable interrupts are suspended and not acknowledged. 7.7 Interrupt Response Time The following table describes the V850E/IA1 interrupt response time (from interrupt generation to start of interrupt servicing). 194 User's Manual U14492EJ5V0UD CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-14. Pipeline Operation at Interrupt Request Acknowledgement (Outline) 4 system clocks Internal clock Interrupt request Instruction 1 Instruction 2 Interrupt acknowledgment operation Instruction (start instruction of interrupt servicing routine) IF IF IFX ID EX DF WB IFX IDX INT1 INT2 INT3 INT4 IF IF ID EX Interleave accessNote Note For details of interleave access, refer to 8.1.2 2-clock branch in V850E1 Architecture User's Manual (U14559E). Remark INT1 to INT4: Interrupt acknowledgment processing IFX: IDX: Invalid instruction fetch Invalid instruction decode Condition INTP100, INTP101, INTP110, INTP111 INTP30, INTP31 Minimum 4 4+ analog delay time Maximum 7 Note 2 Interrupt response time (internal system clock (fXX)) Internal interrupt INTP0 to INTP6, INTP20 to INTP25 4+ digital noise filter 7+ digital noise filter External interrupt INTP20 to INTP25 4 + Note 1 + digital noise filter 7 + Note 1 + digital noise filter The following cases are exceptions. * In IDLE/software STOP mode * External bus access * Two or more interrupt request non-sampling instructions are executed in succession * Access to on-chip peripheral I/O register * Access to programmable peripheral I/O register 7+ analog delay time Notes 1. The number of internal system clocks are as follows. * For timers 10, 11 (TM10, TM11) using INTP100, INTP101, INTP110, and INTP111 as external interrupt inputs (see 9.2.4 (1) Timer 1/timer 2 clock selection register (PRM02)): fCLK = fXX/2 (PRM2 bit = 1): 2 fCLK = fXX/4 (PRM2 bit = 0): 4 * For timer 3 (TM3) using INTP30 and INTP31 as external interrupt inputs (see 9.4.4 (1) Timer 3 clock selection register (PRM03)): fCLK = fXX (PRM3 bit = 1): 2 fCLK = fXX/2 (PRM3 bit = 0): 4 2. When LD instruction is executed to internal ROM (during align access) User's Manual U14492EJ5V0UD 195 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.8 Periods in Which CPU Does Not Acknowledge Interrupts However, no interrupt will be The CPU acknowledges an interrupt while an instruction is being executed. pending). The interrupt request non-sampling instructions are as follows. * EI instruction * DI instruction * LDSR reg2, 0x5 instruction (for PSW) * The store instruction for the command register (PRCMD) acknowledged between an interrupt request non-sampling instruction and the next instruction (interrupt is held * The store instructions or bit manipulation instructions of SET1, CLR1, and NOT1 instructions for the following registers: * Interrupt-related registers: Interrupt control register (xxICn), interrupt mask registers 0 to 3 (IMR0 to IMR3) * Power save control register (PSC) * CSI-related registers: Clocked serial interface mode registers 0, 1 (CSIM0, CSIM1) Clocked serial interface clock selection registers 0, 1 (CSIC0, CSIC1) Clocked serial interface receive buffer registers 0, 1 (SIRB0, SIRB1) Clocked serial interface receive buffer registers L0, L1 (SIRBL0, SIRBL1) Clocked serial interface transmit buffer registers 0, 1 (SOTB0, SOTB1) Clocked serial interface transmit buffer registers L0, L1 (SOTBL0, SOTBL1) Clocked serial interface read-only receive buffer registers 0, 1 (SIRBE0, SIRBE1) Clocked serial interface read-only receive buffer registers L0, L1 (SIRBEL0, SIRBEL1) Clocked serial interface initial transmit buffer registers 0, 1 (SOTBF0, SOTBF1) Clocked serial interface initial transmit buffer registers L0, L1 (SOTBFL0, SOTBFL1) Serial I/O shift registers 0, 1 (SIO0, SIO1) Serial I/O shift registers L0, L1 (SIOL0, SIOL1) Prescaler mode register (PRSM3) Prescaler compare register (PRSCM3) * FCAN clock selection register (PRM04) Remark xx: Identification name of each peripheral unit (refer to Table 7-2) n: Peripheral unit number (refer to Table 7-2) 196 User's Manual U14492EJ5V0UD CHAPTER 8 CLOCK GENERATION FUNCTION The clock generator (CG) generates and controls the internal system clock (fXX) that is supplied to each internal unit, such as the CPU. 8.1 Features * Multiplier function using a phase locked loop (PLL) synthesizer * Clock sources * Oscillation by connecting a resonator * External clock * Power saving modes * HALT mode * IDLE mode * Software STOP mode * Internal system clock output function 8.2 Configuration X1 (fX) fXX X2 CKSEL Clock generator (CG) CPU, on-chip peripheral I/O CLKOUT Time base counter (TBC) Remark fX: External resonator or external clock frequency fXX: Internal system clock User's Manual U14492EJ5V0UD 197 CHAPTER 8 CLOCK GENERATION FUNCTION 8.3 Input Clock Selection The clock generator consists of an oscillator and a PLL synthesizer. For example, connecting a 5.0 MHz crystal resonator or ceramic resonator to pins X1 and X2 enables a 50 MHz internal system clock (fXX) to be generated when the multiplier is 10. Also, an external clock can be input directly to the oscillator. In this case, the clock signal should be input only to pin X1 (pin X2 should be left open). Two basic operation modes are provided for the clock generator. These are PLL mode and direct mode. The operation mode is selected by the CKSEL pin. The input to this pin is latched on reset. CKSEL 0 1 Operating Mode PLL mode Direct mode Caution The input level for the CKSEL pin must be fixed. malfunction may occur. If it is switched during operation, a 8.3.1 Direct mode In direct mode, an external clock is divided by two and the divided clock is supplied as the internal system clock. The maximum frequency that can be input in direct mode is 50 MHz. The V850E/IA1 is mainly used in application systems in which operates at relatively low frequencies. Caution In direct mode, an external clock must be input (an external resonator should not be connected). 8.3.2 PLL mode In PLL mode, an external resonator is connected or external clock is input and multiplied by the PLL synthesizer. The multiplied PLL output is divided by the division ratio specified by the clock control register (CKC) to generate a system clock that is 10, 5, 2.5, or 1 times the frequency (fX) of the external resonator or external clock. After reset, an internal system clock (fXX) that is 1 time the frequency (1 x fX) of the input clock frequency (fX) is generated. When a frequency that is 10 times (10 x fX) the input clock frequency (fX) is generated, a system with low noise and low power consumption can be realized because a frequency of up to 50 MHz is obtained based on a 5 MHz external resonator or external clock. In PLL mode, if the clock supply from an external resonator or external clock source stops, operation of the internal system clock (fXX) based on the self-propelled frequency of the clock generator's internal voltage controlled oscillator (VCO) continues. In this case, fXX is undefined. However, do not devise an application method expecting to use this self-propelled frequency. Example: Clocks when PLL mode (fXX = 10 x fX) is used Internal System Clock Frequency (fXX) 50.000 MHz 40.000 MHz External Resonator or External Clock Frequency (fX) 5.0000 MHz 4.0000 MHz 198 User's Manual U14492EJ5V0UD CHAPTER 8 CLOCK GENERATION FUNCTION Caution When using the PLL mode, only an fX (4 to 5 MHz) value for which 10 x fX does not exceed the system clock maximum frequency (50 MHz) can be used for the oscillation frequency or external clock frequency. When 5 x fX, 2.5 x fX, or 1 x fX is used, a frequency of 4 to 6.4 MHz can be used. Remark Note the following when PLL mode is selected (fXX = 5 x fX, fXX = 2.5 x fX, or fXX = 1 x fX) If the V850E/IA1 need not be operated at high frequency, use fXX = 5 x fX, fXX = 2.5 x fX, or fXX = 1 x fX to reduce the power consumption by lowering the system clock frequency using software. 8.3.3 Peripheral command register (PHCMD) This is an 8-bit register that is used to set protection for writing to registers that can significantly affect the system so that the application system is not halted unexpectedly due to erroneous program execution. This register can be written only in 8-bit units (when it is read, undefined data is read out). Writing to the first specific register (CKC or FLPMC register) is only valid after first writing to the PHCMD register. Because of this, the register value can be overwritten only with the specified sequence, preventing an illegal write operation from being performed. 7 PHCMD REG7 6 REG6 5 REG5 4 REG4 3 REG3 2 REG2 1 REG1 0 REG0 Address Initial value FFFFF800H Undefined Bit position 7 to 0 Bit name REG7 to REG0 Function Registration code (arbitrary 8-bit data) The specific registers targeted are as follows. * Clock control register (CKC) * Flash programming mode control register (FLPMC) The generation of an illegal store operation can be checked with the PRERR bit of the peripheral status register (PHS). User's Manual U14492EJ5V0UD 199 CHAPTER 8 CLOCK GENERATION FUNCTION 8.3.4 Clock control register (CKC) The clock control register is an 8-bit register that controls the internal system clock (fXX) in PLL mode. It can be written to only by a specific sequence combination so that it cannot easily be overwritten by mistake due to erroneous program execution. This register can be read/written in 8-bit units. Caution Do not change bits CKDIV2 to CKDIV0 in direct mode. 7 CKC 0 6 0 5 TBCS 4 CESEL 3 0 2 CKDIV2 1 CKDIV1 0 CKDIV0 Address FFFFF822H Initial value 00H Bit position 5 Bit name TBCS Selects the time base counter clock. 0: fX/2 1: fX/2 8 9 Function For details, see 8.6.2 Time base counter (TBC). 4 CESEL Specifies the functions of the X1 and X2 pins. 0: A resonator is connected to the X1 and X2 pins 1: An external clock is connected to the X1 pin When CESEL = 1, the oscillator feedback loop is disconnected to prevent current leak in software STOP mode. 2 to 0 CKDIV2 to CKDIV0 CKDIV2 CKDIV1 CKDIV0 0 0 0 1 0 0 1 1 0 1 1 1 fX 2.5 x fX 5 x fX 10 x fX Setting prohibited Internal system clock (fXX) Sets the internal system clock frequency (fXX) when PLL mode is used. Other than above Caution When changing the internal system clock during operation, be sure to set the clock to be changed after setting the CKDIV2 to CKDIV0 bits to 000 (fX). Example Clock generator settings Operation Mode Direct mode PLL mode High-level input Low-level input CKSEL Pin CKDIV2 0 0 0 0 1 Other than above CKC Register CKDIV1 0 0 0 1 1 CKDIV0 0 0 1 1 1 16 MHz 5 MHz 5 MHz 5 MHz 5 MHz Setting prohibited Input Clock (fX) Internal System Clock (fXX) 8 MHz 5 MHz 12.5 MHz 25 MHz 50 MHz Setting prohibited 200 User's Manual U14492EJ5V0UD CHAPTER 8 CLOCK GENERATION FUNCTION Data is set in the clock control register (CKC) according to the following sequence. <1> <2> <3> <4> <5> Disable interrupts (set the NP bit of PSW to 1). Prepare data in any one of the general-purpose registers to set in the specific register. Write arbitrary data to the peripheral command register (PHCMD). Set the clock control register (CKC) (with the following instructions). * Store instruction (ST/SST instruction) Insert five or more NOP instructions (5 instructions (<5> to <9>)) <10> Release the interrupt disabled state (set the NP bit of PSW to 0). [Sample coding] <1> LDSR <2> MOV <3> ST.B <4> ST.B <5> NOP <6> NOP <7> NOP <8> NOP <9> NOP <10> LDSR Remark rX: Value written to PSW rY: Value returned to PSW No special sequence is required to read the specific register. Cautions 1. If an interrupt is acknowledged between the issuing of data to the PHCMD (<3>) and writing to the specific register immediately after (<4>), the write operation to the specific register is not performed and a protection error (the PRERR bit of the PHS register = 1) may occur. Therefore, set the NP bit of the PSW to 1 (<1>) to disable interrupt acknowledgment. Also disable interrupt acknowledgment as well when selecting a bit manipulation instruction for the specific register setting. 2. Although the data written to the PHCMD register is dummy data however, use the same register as the general-purpose register used in specific register setting (<4>) for writing to the PHCMD register (<3>). The same method should be applied when using a generalpurpose register for addressing. 3. Before executing this processing, complete all DMA transfer operations. rY, 5 rX, 5 0x07, r10 r10, PHCMD [r0] r10, CKC [r0] User's Manual U14492EJ5V0UD 201 CHAPTER 8 CLOCK GENERATION FUNCTION 8.3.5 Peripheral status register (PHS) If a write operation is not performed in the correct sequence including access to the command register for the protection-targeted internal registers, writing is not performed and a protection error is generated, setting the status flag (PRERR) to 1. This flag is a cumulative flag. After checking the PRERR flag, it is cleared to 0 by an instruction. This register can be read/written in 8-bit or 1-bit units. 7 PHS 0 6 0 5 0 4 0 3 0 2 0 1 0 <0> PRERR Address FFFFF802H Initial value 00H Bit position 0 Bit name PRERR Protection error 0: Protection error does not occur 1: Protection error occurs Function The operation conditions of the PRERR flag are as follows. Set conditions: <1> If the operation of the relevant store instruction for the on-chip peripheral I/O is not a write operation for the PHCMD register, but the peripheral specific register is written to. <2> If the first store instruction operation after the write operation to the PHCMD register is for memory other than the specific registers and on-chip peripheral I/O. Reset conditions: <1> If the PRERR flag of the PHS register is set to 0. <2> If the system is reset 202 User's Manual U14492EJ5V0UD CHAPTER 8 CLOCK GENERATION FUNCTION 8.4 PLL Lockup The lockup time (frequency stabilization time) is the time from when the power is turned on or the software STOP mode is released until the phase locks at the prescribed frequency. The state until this stabilization occurs is called a lockup state, and the stabilized state is called a lock state. (1) Lock register (LOCKR) The lock register (LOCKR) has a LOCK flag that reflects the stabilized state of the PLL frequency. This register is read-only, in 8-bit or 1-bit units. Caution When the PLL is locked, the LOCK flag is 0. If the system then enters an unlocked state due to a standby, the LOCK flag becomes 1. If anything other than a standby causes the system to enter an unlocked state, the LOCK flag is not affected (LOCK = 0). 7 LOCKR 0 6 0 5 0 4 0 3 0 2 0 1 0 <0> LOCK Address Initial value FFFFF824H 0000000xB Bit position 0 Bit name LOCK Function This is a read-only flag that indicates the PLL state. This flag holds the value 0 as long as a lockup state is maintained and is not initialized by a system reset. 0: Indicates that the PLL is locked. 1: Indicates that the PLL is not locked (UNLOCK state). If the clock stops, the power fails, or some other factor operates to cause an unlock state to occur, for control processing that depends on software execution speed, such as real-time processing, be sure to judge the LOCK flag using software immediately after operation begins so that processing does not begin until after the clock stabilizes. On the other hand, static processing such as the setting of internal hardware or the initialization of register data or memory data can be executed without waiting for the LOCK flag to be reset. The relationship between the oscillation stabilization time (the time from when the resonator starts to oscillate until the input waveform stabilizes) when a resonator is used, and the PLL lockup time (the time until frequency stabilizes) is shown below. Oscillation stabilization time < PLL lockup time User's Manual U14492EJ5V0UD 203 CHAPTER 8 CLOCK GENERATION FUNCTION 8.5 Power Save Control 8.5.1 Overview The power save function has the following three modes. (1) HALT mode In this mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the CPU's operation clock stops. Since the supply of clocks to on-chip peripheral functions other than the CPU continues, operation continues. The power consumption of the overall system can be reduced by intermittent operation that is achieved due to a combination of HALT mode and normal operation mode. The system is switched to HALT mode by a specific instruction (the HALT instruction). (2) IDLE mode In this mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the supply of internal system clocks is stopped, which causes the overall system to stop. When the system is released from IDLE mode, it can be switched to normal operation mode quickly because the oscillator's oscillation stabilization time need not be secured. The system is switched to IDLE mode according to the PSMR register setting. IDLE mode is located midway between software STOP mode and HALT mode in relation to the clock stabilization time and current consumption. It is used for situations in which a low current consumption mode is to be used and the clock stabilization time is to be eliminated after the mode is released. (3) Software STOP mode In this mode, the overall system is stopped by stopping the clock generator (oscillator and PLL synthesizer). The system enters an ultra-low power consumption state in which only leak current is lost. The system is switched to software STOP mode according to a PSMR register setting. (a) PLL mode The system is switched to software STOP mode by setting the register according to software. The PLL synthesizer's clock output is stopped at the same time that the oscillator is stopped. After software STOP mode is released, the oscillator's oscillation stabilization time must be secured until the system clock stabilizes. Also, PLL lockup time may be required depending on the program. When a resonator or external clock is connected, following the release of the software STOP mode, execution of the program is started after the count time of the time base counter has elapsed. (b) Direct mode To stop the clock, set the X1 pin to low level. After the release of software STOP mode, execution of the program is started after the count time of the time base counter has elapsed. 204 User's Manual U14492EJ5V0UD CHAPTER 8 CLOCK GENERATION FUNCTION Table 8-1 shows the operation of the clock generator in normal operation mode, HALT mode, IDLE mode, and software STOP mode. An effective low power consumption system can be realized by combining these modes and switching modes according to the required use. Figure 8-1. Power Save Mode State Transition Diagram Release according to RESET, NMI, or maskable interrupt Normal operation mode Set HALT mode Release according to RESET, NMI, or maskable interrupt Note Set STOP mode Release according to RESET, NMI, or maskable interrupt Note Set IDLE mode HALT mode Software STOP mode IDLE mode Note INTPn (n = 0 to 6, 20 to 25) However, when a digital filter using clock sampling is selected as the noise eliminator for INTP20 to INTP25, the software STOP or IDLE mode cannot be released. User's Manual U14492EJ5V0UD 205 CHAPTER 8 CLOCK GENERATION FUNCTION Table 8-1. Clock Generator Operation Using Power Save Control Clock Source Power Save Mode Oscillator PLL Synthesizer Clock Supply to Peripheral I/O PLL mode Oscillation with resonator Normal operation HALT mode IDLE mode Software STOP mode External clock Normal operation HALT mode IDLE mode Software STOP mode Direct mode External clock Normal operation HALT mode IDLE mode Software STOP mode - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Clock Supply to CPU Remark : Operating -: Stopped 206 User's Manual U14492EJ5V0UD CHAPTER 8 CLOCK GENERATION FUNCTION 8.5.2 Control registers (1) Power save mode register (PSMR) This is an 8-bit register that controls power save mode. It is effective only when the STB bit of the PSC register is set to 1. Writing to the PSMR register is executed by the store instruction (ST/SST instruction) and a bit manipulation instruction (SET1/CLR1/NOT1 instruction). This register can be read/written in 8-bit or 1-bit units. 7 PSMR 0 6 0 5 0 4 0 3 0 2 0 1 0 <0> PSM Address FFFFF820H Initial value 00H Bit position 0 Bit name PSM Function Specifies IDLE mode or software STOP mode. 0: Switches the system to IDLE mode 1: Switches the system to software STOP mode (2) Command register (PRCMD) This is an 8-bit register that is used to set protection for write operations to registers that can significantly affect the system so that the application system is not halted unexpectedly due to erroneous program execution. Writing to the first specific register (power save control register (PSC)) is only valid after first writing to the PRCMD register. Because of this, the register value can be overwritten only by the specified sequence, preventing an illegal write operation from being performed. This register can only be written in 8-bit units. The undefined data is read out if read. 7 PRCMD REG7 6 REG6 5 REG5 4 REG4 3 REG3 2 REG2 1 REG1 0 REG0 Address Initial value FFFFF1FCH Undefined Bit position 7 to 0 Bit name REG7 to REG0 Function Registration code (arbitrary 8-bit data) The specific register targeted is the power save control register (PSC). User's Manual U14492EJ5V0UD 207 CHAPTER 8 CLOCK GENERATION FUNCTION (3) Power save control register (PSC) This is an 8-bit register that controls the power save function. If releasing of interrupts are enabled by the setting of the NMIM and INTM bits, the software STOP mode can be released by an interrupt request (except when interrupt servicing is disabled by the interrupt mask registers (IMR0 to IMR3)). The software STOP mode is specified by the setting of the STB bit. This register, which is one of the specific registers, is effective only when accessed by a specific sequence during a write operation. This register can be read/written in 8-bit or 1-bit units. Be sure to clear bits 7 and 6 to 0. If they are set to 1, the operation is not guaranteed. Caution It is impossible to set STB bit and NMIM or INTM bit at the same time. Be sure to set STB bit after setting NMIM or INTM bit. 7 PSC 0 6 0 <5> NMIM <4> INTM 3 0 2 0 <1> STB 0 0 Address FFFFF1FEH Initial value 00H Bit position 5 Bit name NMIM Note Function This is the enable/disable setting bit for standby mode release using valid edge input of NMI . 0: Enables NMI cancellation 1: Disables NMI cancellation 4 INTM This is the enable/disable setting for standby mode release using an unmasked maskable interrupt (INTPn) (n = 0 to 6, 20 to 25, 30, 31, 100, 101, 110, 111) 0: Enables maskable interrupt cancellation 1: Disables maskable interrupt cancellation Note . 1 STB Indicates the standby mode status. If 1 is written to this bit, the system enters IDLE or software STOP mode (set by the PSM bit of the PSMR register). When standby mode is released, this bit is automatically reset to 0. 0: Standby mode is released 1: Standby mode is in effect Note Setting these bits is valid only in the IDLE/software STOP mode. Data is set in the power save control register (PSC) according to the following sequence. <1> Set the power save mode register (PSMR) (with the following instructions). * Store instruction (ST/SST instruction) * Bit manipulation instruction (SET1/CLR1/NOT1 instruction) <2> Prepare data in any one of the general-purpose registers to set in the specific register. <3> Write arbitrary data to the command register (PRCMD). <4> Set the power save control register (PSC) (with the following instructions). * Store instruction (ST/SST instruction) * Bit manipulation instruction (SET1/CLR1/NOT1 instruction) <5> Insert the NOP instructions (5 instructions (<5> to <9>). 208 User's Manual U14492EJ5V0UD CHAPTER 8 CLOCK GENERATION FUNCTION [Sample coding] <1> ST.B <2> MOV <3> ST.B <4> ST.B <5> NOP <6> NOP <7> NOP <8> NOP <9> NOP (next instruction) r11, PSMR [r0] 0x07, r10 r10, PRCMD [r0] r10, PSC [r0] ; Set PSMR register ; Prepare data for setting specific register in arbitrary general-purpose register ; Write PRCMD register ; Set PSC register ; Dummy instruction ; Dummy instruction ; Dummy instruction ; Dummy instruction ; Dummy instruction ; Execution routine after software STOP mode and IDLE mode release No special sequence is required to read the specific register. Cautions 1. A store instruction for the command register does not acknowledge interrupts. This coding is made on assumption that <3> and <4> above are executed by the program with consecutive store instructions. If another instruction is set between <3> and <4>, the above sequence may become in effective when the interrupt is acknowledged by that instruction, and a malfunction of the program may result. 2. Although the data written to the PRCMD register is dummy data, use the same register as the general-purpose register used in specific register setting (<4>) for writing to the PRCMD register (<3>). The same method should be applied when using a general-purpose register for addressing. 3. At least 5 NOP instructions must be inserted after executing a store instruction to the PSC register to set software STOP or IDLE mode. 4. Before executing this processing, complete all DMA transfer operations. User's Manual U14492EJ5V0UD 209 CHAPTER 8 CLOCK GENERATION FUNCTION 8.5.3 HALT mode (1) Setting and operation status In HALT mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the operation clock of the CPU is stopped. Since the supply of clocks to on-chip peripheral I/O units other than the CPU continues, operation continues. The power consumption of the overall system can be reduced by setting the system to HALT mode while the CPU is idle. The system is switched to HALT mode by the HALT instruction. Although program execution stops in HALT mode, the contents of all registers, internal RAM, and ports are maintained in the state they were in immediately before HALT mode began. Also, operation continues for all on-chip peripheral I/O units (other than ports) that do not depend on CPU instruction processing. Table 8-2 shows the status of each hardware unit in HALT mode. Table 8-2. Operation Status in HALT Mode Function Clock generator Internal system clock CPU Ports On-chip peripheral I/O (excluding ports) Internal data Operating Operating Stopped Maintained Operating All internal data such as CPU registers, statuses, data, and the contents of internal RAM are maintained in the state they were in immediately before HALT mode began. AD0 to AD15 A16 to A23 RD, ASTB UWR, LWR CS0 to CS7 HLDRQ HLDAK WAIT CLKOUT Clock output Operating Operation Status 210 User's Manual U14492EJ5V0UD CHAPTER 8 CLOCK GENERATION FUNCTION (2) Release of HALT mode HALT mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request (INTPn), or RESET pin input (n = 0 to 6, 20 to 25, 30, 31, 100, 101, 110, 111). (a) Release by a non-maskable interrupt request or an unmasked maskable interrupt request HALT mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt request regardless of the priority. However, if the system is set to HALT mode during an interrupt servicing routine, operation will differ as follows. (i) If an interrupt request is generated with a lower priority than that of the interrupt request that is currently being serviced, HALT mode is released, but the newly generated interrupt request is not acknowledged. The new interrupt request is held pending. (ii) If an interrupt request (including non-maskable interrupt requests) is generated with a higher priority than that of the interrupt request that is currently being serviced, HALT mode is released and the newly generated interrupt request is acknowledged. Table 8-3. Operation After HALT Mode Is Released by Interrupt Request Release Source Non-maskable interrupt request Maskable interrupt request Enable Interrupt (EI) Status Branch to handler address Branch to handler address or execute next instruction Execute next instruction Disable Interrupt (DI) Status (b) Release by RESET pin input This is the same as a normal reset operation. User's Manual U14492EJ5V0UD 211 CHAPTER 8 CLOCK GENERATION FUNCTION 8.5.4 IDLE mode (1) Setting and operation status In IDLE mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the supply of internal system clocks is stopped which causes the overall system to stop. When IDLE mode is released, the system can be switched to normal operation mode quickly because the oscillator's oscillation stabilization time or the PLL lockup time need not be secured. The system is switched to IDLE mode by setting the PSC or PSMR register using a store instruction (ST or SST instruction) or a bit manipulation instruction (SET1, CLR1, or NOT1 instruction) (see 8.5.2 Control registers). In IDLE mode, program execution is stopped, and the contents of all registers, internal RAM, and ports are maintained in the state they were in immediately before execution stopped. peripheral I/O units (excluding ports) also is stopped. Table 8-4 shows the status of each hardware unit in IDLE mode. Table 8-4. Operation Status in IDLE Mode Function Clock generator Internal system clock CPU Ports On-chip peripheral I/O (excluding ports) Internal data Operating Stopped Stopped Maintained Stopped (CSI0 and CSI1 are operable in slave mode) Note The operation of on-chip Operation Status All internal data such as CPU registers, statuses, data, and the contents of internal RAM are maintained in the state they were in immediately before IDLE mode began. AD0 to AD15 A16 to A23 RD UWR, LWR CS0 to CS7 HLDAK HLDRQ WAIT ASTB CLKOUT High impedance High-level output High impedance Input (no sampling) High-level output Low-level output Note NBD cannot be used in IDLE mode. 212 User's Manual U14492EJ5V0UD CHAPTER 8 CLOCK GENERATION FUNCTION (2) Release of IDLE mode IDLE mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request (INTPn)Note, or RESET pin input (n = 0 to 6, 20 to 25). Note When a digital filter using clock sampling is selected as the noise eliminator for INTP20 to INTP25, the IDLE mode cannot be released. (a) Release by a non-maskable interrupt request or an unmasked maskable interrupt request The IDLE mode can be released by an interrupt request only when transition to IDLE mode is performed with the INTM and NMIM bits of the PSC register set to 0. IDLE mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt request (INTPn) regardless of the priority (n = 0 to 6, 20 to 25). The operation after release is as follows. Caution When the NMIM and INTM bits of the PSC register = 1, the IDLE mode cannot be released by the non-maskable interrupt request signal and unmasked maskable interrupt request signal. Table 8-5. Operation After IDLE Mode Is Released by Interrupt Request Release Source Non-maskable interrupt request Maskable interrupt request Enable Interrupt (EI) Status Branch to handler address Branch to handler address or execute next instruction Execute next instruction Disable Interrupt (DI) Status If the system is set to IDLE mode during a maskable interrupt servicing routine, operation will differ as follows. (i) If an interrupt request is generated with a lower priority than that of the interrupt request that is currently being serviced, IDLE mode is released, but the newly generated interrupt request is not acknowledged. The new interrupt request is held pending. (ii) If an interrupt request (including non-maskable interrupt requests) is generated with a higher priority than that of the interrupt request that is currently being serviced, IDLE mode is released and the newly generated interrupt request is acknowledged. If the system is set to IDLE mode during an NMI servicing routine, IDLE mode is released, but the interrupt is not acknowledged (interrupt is held pending). Interrupt servicing that is started when IDLE mode is released by NMI pin input is handled in the same way as normal NMI interrupt servicing that occurs during an emergency (because the NMI interrupt handler address is unique). Therefore, when a program must be able to distinguish between these two situations, a software status must be prepared in advance and that status must be set before setting the PSMR register using a store instruction or a bit manipulation instruction. By checking for this status during NMI interrupt servicing, an ordinary NMI can be distinguished from the processing that is started when IDLE mode is released by NMI pin input. (b) Release by RESET pin input This is the same as a normal reset operation. User's Manual U14492EJ5V0UD 213 CHAPTER 8 CLOCK GENERATION FUNCTION 8.5.5 Software STOP mode (1) Setting and operation status In software STOP mode, the clock generator (oscillator and PLL synthesizer) is stopped. The overall system is stopped, and ultra-low power consumption is achieved in which only leak current is lost. The system is switched to software STOP mode by using a store instruction (ST or SST instruction) or bit manipulation instruction (SET1, CLR1, or NOT1 instruction) to set the PSC and PSMR registers (see 8.5.2 Control registers). When PLL mode and resonator connection mode (CESEL bit of CKC register = 0) are used, the oscillator's oscillation stabilization time must be secured after software STOP mode is released. In both PLL and direct modes, following the release of software STOP mode, execution of the program is started after the count time of the time base counter has elapsed. Although program execution stops in software STOP mode, the contents of all registers, internal RAM, and ports are maintained in the state they were in immediately before software STOP mode began. operation of all on-chip peripheral I/O units (excluding ports) is also stopped. Table 8-6 shows the status of each hardware unit in software STOP mode. Table 8-6. Operation Status in Software STOP Mode Function Clock generator Internal system clock CPU Ports On-chip peripheral I/O (excluding ports) Internal data Stopped Stopped Stopped Retained Note 1 The Operation Status Stopped (CSI0 and CSI1 are operable in slave mode) Note 2 All internal data such as CPU registers, statuses, data, and the contents of internal RAM are retained in the state before Note 1 software STOP mode has been set . AD0 to AD15 A16 to A23 RD UWR, LWR CS0 to CS7 HLDAK HLDRQ WAIT ASTB CLKOUT High impedance High-level output High impedance Input (no sampling) High-level output Low-level output Notes 1. When the VDD5 value is within the operable range. However, even if it drops below the minimum operable voltage, as long as the data retention voltage VDDDR is maintained, the contents of only the internal RAM will be retained. 2. NBD cannot be used in software STOP mode. 214 User's Manual U14492EJ5V0UD CHAPTER 8 CLOCK GENERATION FUNCTION (2) Release of software STOP mode Software STOP mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request (INTPn)Note, or RESET pin input. Also, to release software STOP mode when PLL mode (CKSEL pin = low level) and resonator connection mode (CESEL bit of CKC register = 0) are used, the oscillator's oscillation stabilization time must be secured (n = 0 to 6, 20 to 25). Moreover, PLL lockup time may be required depending on the program. See 8.4 PLL Lockup for details. Note When a digital filter using clock sampling is selected as the noise eliminator for INTP20 to INTP25, the software STOP mode cannot be released. (a) Release by a non-maskable interrupt request or an unmasked maskable interrupt request The software STOP mode can be released by an interrupt request only when transition to software STOP mode is performed with the INTM and NMIM bits of the PSC register set to 0. Software STOP mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt request (INTPn) regardless of the priority (n = 0 to 6, 20 to 25). The operation after release is as follows. Caution When the NMIM and INTM bits of the PSC register = 1, the software STOP mode cannot be released by the non-maskable interrupt request signal and unmasked maskable interrupt request signal. Table 8-7. Operation After Software STOP Mode Is Released by Interrupt Request Release Source Non-maskable interrupt request Maskable interrupt request Enable Interrupt (EI) Status Branch to handler address Branch to handler address or execute next instruction Execute next instruction Disable Interrupt (DI) Status If the system is set to software STOP mode during a maskable interrupt servicing routine, operation will differ as follows. (i) If an interrupt request is generated with a lower priority than that of the interrupt request that is currently being serviced, software STOP mode is released, but the newly generated interrupt request is not acknowledged. The new interrupt request is held pending. (ii) If an interrupt request (including non-maskable interrupt requests) is generated with a higher priority than that of the interrupt request that is currently being serviced, software STOP mode is released and the newly generated interrupt request is acknowledged. If the system is set to software STOP mode during an NMI servicing routine, software STOP mode is released, but the interrupt is not acknowledged (interrupt is held pending). Interrupt servicing that is started when software STOP mode is released by NMI pin input is handled in the same way as normal NMI interrupt servicing that occurs during an emergency (because the NMI interrupt handler address is unique). Therefore, when a program must be able to distinguish between these two situations, a software status must be prepared in advance and that status must be set before setting the PSMR register using a store instruction or a bit manipulation instruction. By checking for this status during NMI interrupt servicing, an ordinary NMI can be distinguished from the servicing that is started when software STOP mode is released by NMI pin input. (b) Release by RESET pin input This is the same as a normal reset operation. User's Manual U14492EJ5V0UD 215 CHAPTER 8 CLOCK GENERATION FUNCTION 8.6 Securing Oscillation Stabilization Time 8.6.1 Oscillation stabilization time security specification Two specification methods can be used to secure the time from when software STOP mode is released until the stopped oscillator stabilizes. (1) Securing the time using an on-chip time base counter Software STOP mode is released when a valid edge is input to the NMI pin or a maskable interrupt request is input (INTPn). When a valid edge is input to the pin causing the start of oscillation, the time base counter (TBC) starts counting, and the time until the clock output from the oscillator stabilizes is secured during that counting time (n = 0 to 6, 20 to 25). Oscillation stabilization time = TBC counting time After a fixed time, internal system clock output begins, and processing branches to the NMI interrupt or maskable interrupt (INTPn) handler address. Set software STOP mode Oscillation waveform (X2) Internal main clock CLKOUT (output) STOP state NMI (input)Note Oscillator is stopped Time base counter's counting time Note Valid edge: When specified as the rising edge. The NMI pin should usually be set to an inactive level (for example, high level when the valid edge is specified as the falling edge) in advance. Software STOP mode is immediately released if an operation is performed according to NMI valid edge input or maskable interrupt request input (INTPn) timing in which software STOP mode is set until the CPU acknowledges the interrupt. If direct mode or external clock connection mode (CESEL bit of CKC register = 1) is used, program execution begins after the count time of the time base counter has elapsed. Also, even if PLL mode and resonator connection mode (CESEL bit of CKC register = 0) are used, program execution begins after the oscillation stabilization time is secured according to the time base counter. 216 User's Manual U14492EJ5V0UD CHAPTER 8 CLOCK GENERATION FUNCTION (2) Securing the time according to the signal level width (RESET pin input) Software STOP mode is released due to falling edge input to the RESET pin. The time until the clock output from the oscillator stabilizes is secured according to the low level width of the signal that is input to the pin. The supply of internal system clocks begins after a rising edge is input to the RESET pin, and processing branches to the handler address used for a system reset. Set software STOP mode Oscillation waveform (X2) Internal main clock Undefined CLKOUT (output) STOP state RESET (input) Internal system reset signal Oscillator is stopped Undefined Oscillation stabilization time secured by RESET 8.6.2 Time base counter (TBC) The time base counter (TBC) is used to secure the oscillator's oscillation stabilization time when software STOP mode is released. When an external clock is connected (CESEL bit of CKC register = 1) or a resonator is connected (PLL mode and CESEL bit of CKC register = 0), the TBC counts the oscillation stabilization time after software STOP mode is released, and program execution begins after the count is completed. The TBC count clock is selected according to the TBCS bit of the CKC register, and the next counting time can be set. Table 8-8. Counting Time Examples (fXX = 10 x fX) TBCS Bit Count Clock fX = 4.0000 MHz 0 1 fX/2 fX/2 8 Counting Time fX = 5.0000 MHz 13.2 ms 26.3 ms 16.4 ms 32.8 ms 9 fXX: Internal system clock fX: External oscillation frequency User's Manual U14492EJ5V0UD 217 CHAPTER 9 TIMER/COUNTER FUNCTION 9.1 Timer 0 9.1.1 Features (timer 0) Timers 00, 01 (TM00, TM01) are 16-bit timer/counters that are ideal for controlling high-speed inverters such as motors. * 3-phase PWM output function PWM mode 0 (symmetric triangular wave) PWM mode 1 (asymmetric triangular wave) PWM mode 2 (sawtooth wave) * Interrupt culling function Culling ratios (1/1, 1/2, 1/4, 1/8, 1/16) * Forcible 3-phase PWM output stop function 3-phase PWM output can be forcibly stopped by inputting a signal from external signal input pin ESOn during anomalies. This function can also be used when the clock is stopped. * Real-time output function 3-phase PWM output or rectangular wave output can be selected at the desired timing. * Output of positive phase and negative phase or positive phase and in-phase of 3-phase PWM output 218 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.2 Function overview (timer 0) * * * * * 16-bit timer (TM0n) for 3-phase PWM inverter control: 2 channels Compare registers: 4 registers x 2 channels 12-bit dead-time timers (DTMn0 to DTMn2): 3 timers x 2 channels Count clock division selectable by prescaler (set the frequency of the count clock to 40 MHz or less) Base clock (fCLK): 2 types (set fCLK to 40 MHz or less) fXX and fXX/2 can be selected * Prescaler division ratio The following division ratios can be selected according to the base clock (fCLK). Division Ratio Base Clock (fCLK) fXX Selected 1/1 1/2 1/4 1/8 1/16 1/32 fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/2 Selected fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 * Interrupt request sources * Compare-match interrupt request: 2 types INTCM0n3 generated by CM0n3 match signal * Underflow interrupt request: 2 types INTTM0n generated by underflow * External pulse output (TO0n0 to TO0n5): 6 x 2 channels Remark fXX: Internal system clock n = 0, 1 User's Manual U14492EJ5V0UD 219 CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.3 Basic configuration The basic configuration is shown below. Figure 9-1. Block Diagram of Timer 0 (Mode 0: Symmetric Triangular Wave, Mode 1: Asymmetric Triangular Wave) BFCMn3 fXX fXX/2 1/1 1/2 1/4 fCLK 1/8 1/16 1/32 BFCMn0 Selector CM0n3 16 TM0n S/R 16 INTCM0n3 INTTM0n Output control by external input (ESOn), TM0n timer operation 6 DTRRn 12 ALVTO Underflow CM0n0 R S DTMn0 R S R S TO0n0 (U phase) TO0n1 (U phase) ALVUB BFCMn1 CM0n1 R DTMn1 S Underflow R S R S TO0n2 (V phase) TO0n3 (V phase) ALVVB BFCMn2 CM0n2 R S DTMn2 Underflow R S R S ALVWB TO0n4 (W phase) TO0n5 (W phase) Remarks 1. TM0n: CM0n0 to CM0n3: DTRRn: DTMn0 to DTMn2: ALVTO: ALVUB: ALVVB: ALVWB: S/R: 2. n = 0, 1 Timer register Compare registers Dead-time timer reload register Dead-time timers Bit 7 of TOMRn register Bit 6 of TOMRn register Bit 5 of TOMRn register Bit 4 of TOMRn register Set/Reset BFCMn0 to BFCMn3: Buffer registers 3. fXX: Internal system clock 4. fCLK: Base clock (40 MHz (MAX.)) 220 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-2. Block Diagram of Timer 0 (Mode 2: Sawtooth Wave) BFCMn3 fXX fXX/2 1/1 1/2 1/4 fCLK 1/8 1/16 1/32 BFCMn0 Selector CM0n3 16 TM0n 16 Clear INTCM0n3 Output control by external input (ESOn), TM0n timer operation DTRRn R S 12 Underflow ALVTO CM0n0 DTMn0 R S R S TO0n0 (U phase) TO0n1 (U phase) ALVUB BFCMn1 CM0n1 R DTMn1 S Underflow R S R S TO0n2 (V phase) TO0n3 (V phase) ALVVB BFCMn2 CM0n2 R S DTMn2 Underflow R S R S ALVWB TO0n4 (W phase) TO0n5 (W phase) Remarks 1. TM0n: CM0n0 to CM0n3: BFCMn0 to BFCMn3: DTRRn: DTMn0 to DTMn2: ALVTO: ALVUB: ALVVB: ALVWB: 2. n = 0, 1 Timer register Compare registers Buffer registers Dead-time timer reload register Dead-time timers Bit 7 of TOMRn register Bit 6 of TOMRn register Bit 5 of TOMRn register Bit 4 of TOMRn register 3. fXX: Internal system clock 4. fCLK: Base clock (40 MHz (MAX.)) User's Manual U14492EJ5V0UD 221 CHAPTER 9 TIMER/COUNTER FUNCTION (1) Timers 00, 01 (TM00, TM01) TM0n operates as a 16-bit up/down timer or up timer. The cycle is controlled by compare register 0n3 (CM0n3) (n = 0, 1). TM0n start/stop is controlled by the TM0CEn bit of timer control register 0n (TMC0n). Division by the prescaler can be selected for the count clock from among fCLK, fCLK/2, fCLK/4, fCLK/8, fCLK/16, fCLK/32 with the PRM02 to PRM00 bits of the TMC0n register (fCLK: base clock, see 9.1.4 (1) Timer 0 clock selection register (PRM01)). The conditions when TM0n becomes 0000H are as follows. * Reset input * TM0CEn bit = 0 * TM0n register and compare register 0n3 (CM0n3) match (PWM mode 2 (sawtooth wave) only) * Immediately after overflow or underflow The TM0n timer has 3 operation modes, shown in Table 9-1. The operation mode is selected with timer control register 0n (TMC0n). Table 9-1. Timer 0 Operation Modes Operation Mode Count Operation Timer Clear Source Interrupt Source BFCMn3 CM0n3 Transfer Timing BFCMn0 to BFCMn2 CM0n0 to CM0n2 Transfer Timing INTTM0n PWM mode 0 (symmetric triangular wave) PWM mode 1 (asymmetric triangular wave) PWM mode 2 (sawtooth wave) Up/down - INTTM0n INTCM0n3 INTTM0n Up/down - INTTM0n INTCM0n3 INTTM0n INTTM0n INTCM0n3 Up INTCM0n3 INTCM0n3 INTCM0n3 INTCM0n3 Caution An interrupt does not occur and the operation of timer 0 is not affected even if TM0ICn, CM03ICn, or the interrupt mask flag of the IMR0 register (TM0MKn or CM03MKn) is set (interrupts disabled) as the interrupt source. Remark n = 0, 1 222 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (2) Dead-time timers 00 to 02, 10 to 12 (DTM00 to DTM02, DTM10 to DTM12) DTMn0 to DTMn2 are dedicated 12-bit down timers that generate dead time suitable for inverter control application. DTMn0 to DTMn2 operate as one-shot timers. Counting by a dead-time timer is enabled or disabled by the TM0CEDn bit of timer control register 0n (TMC0n) and cannot be controlled by software. Dead-time timer count start and stop is controlled by hardware. A dead-time timer starts counting down when the value of the dead-time timer reload register n (DTRRn) is transferred in synchronization with the compare match timing of CM0n0 to CM0n2. When the value of a dead-time timer changes from 000H to FFFH, the dead-time timer generates an underflow signal, and the timer stops at the value FFFH. If the value of a dead-time timer matches the value of the corresponding compare register before underflow of the dead-time timer takes place, the value of DTRRn is transferred to the dead-time timer again, and the timer starts down counting. The count clock of the dead-time timer is fixed to the base clock (fCLK), and the dead-time width is (set value of DTRRn + 1)/base clock (fCLK). If TM0n operates in PWM mode 0, PWM mode 1 with the dead-time timer count operation disabled, an inverted signal without dead time is output to TO0n0 and TO0n1, TO0n2 and TO0n3, and TO0n4 and TO0n5. (3) Dead-time timer reload registers 0, 1 (DTRR0, DTRR1) DTRRn register is a 12-bit register used to set the values of the three dead-time timers (DTMn0 to DTMn2 registers) (n = 0, 1). However, a value is transferred from the DTRRn register to each dead-time register independently. DTRRn can be read/written in 16-bit units. All 0s are read for the higher 4 bits when 16-bit read access is performed to the DTRRn register. 15 DTRR0 0 14 0 13 0 12 0 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF570H Initial value 0FFFH 15 DTRR1 0 14 0 13 0 12 0 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF5B0H Initial value 0FFFH Cautions 1. Changing the value of the DTRRn register during TM0n operation (TM0CEn bit of TMC0n register = 1) is prohibited. 2. Be sure to write 0 to the higher 4 bits. (4) Compare registers 000 to 002, 010 to 012 (CM000 to CM002, CM010 to CM012) CM0n0 to CM0n2 are 16-bit registers that always compare their own values with the value of TM0n. If the value of a compare register matches the value of TM0n, the compare register outputs a trigger signal, and changes the contents of the flip-flop (F/F) connected to the compare register. Each of CM0n0 to CM0n2 is provided with a buffer register (BFCMn0 to BFCMn2), so that the contents of the buffer are transferred to CM0n0 to CM0n2 at the next transfer timing. Transfer is enabled or disabled by the BFTEN bit of the TMC0n register. User's Manual U14492EJ5V0UD 223 CHAPTER 9 TIMER/COUNTER FUNCTION (5) Compare registers 003, 013 (CM003, CM013) CM0n3 is a 16-bit register that always compare its value with the value of TM0n. If the values match, CM0n3 outputs an interrupt signal (INTCM0n3). CM0n3 controls the maximum count value of TM0n, and if the values match, it performs the following operations at the next timer count clock. * * In triangular wave setting mode (PWM modes 0, 1): Sawtooth wave setting mode (PWM mode 2): Switches TM0n operation from up count to down count Clears the count value of TM0n CM0n3 also has a buffer register (BFCMn3) and transfers the buffer contents at the timing of the next transfer to CM0n3. Transfer enable or disable is controlled by the BFTE3 bit of the TMC0n register. (6) Buffer registers CM00 to CM02, CM10 to CM12 (BFCM00 to BFCM02, BFCM10 to BFCM12) BFCMn0 to BFCMn2 are 16-bit registers that transfer data to the compare register (CM0n0 to CM0n2) corresponding to each buffer register when an interrupt signal (INTCM0n3/INTTM0n) is generated. BFCMn0 to BFCMn2 can be read/written in 16-bit units. Caution The set values of the BFCMn0 to BFCMn2 registers are transferred to the CM0n0 to CM0n2 registers in the following timing (n = 0, 1). * When TM0CEn bit of TMC0n register = 0: Transfer at next operation timing after writing to BFCMn0 to BFCMn2 registers * When TM0CEn bit of TMC0n register = 1: Value of BFCMn0 to BFCMn2 registers is transferred to CM0n0 to CM0n2 registers upon occurrence of INTTM0n or INTCM0n3. At this time, transfer enable or disable is controlled by the BFTEN bit of the timer control register (TMC0n). 15 BFCM00 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF572H Initial value FFFFH 15 BFCM10 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF5B2H Initial value FFFFH 15 BFCM01 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF574H Initial value FFFFH 15 BFCM11 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF5B4H Initial value FFFFH 15 BFCM02 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF576H Initial value FFFFH 15 BFCM12 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF5B6H Initial value FFFFH 224 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (7) Buffer registers CM03, CM13 (BFCM03, BFCM13) BFCMn3 is a 16-bit register that transfers data to the compare register at any timing. Transfer enable or disable is controlled by the BFTE3 bit of the TMC0n register. BFCMn3 can be read/written in 16-bit units. Cautions 1. The set value of the BFCMn3 register is transferred to the CM0n3 register in the following timing (n = 0, 1). * When TM0CEn bit of TMC0n register = 0: Transfer at next operation timing after writing to BFCMn3 register * When TM0CEn bit of TMC0n register = 1: Value of BFCMn3 register is transferred to CM0n3 register upon occurrence of INTTM0n. At this time, transfer enable or disable is controlled by the BFTE3 bit of the timer control register (TMC0n). 2. Setting the BFCMn3 register to 0000H is prohibited. 15 BFCM03 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF578H Initial value FFFFH 15 BFCM13 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF5B8H Initial value FFFFH User's Manual U14492EJ5V0UD 225 CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.4 Control registers (1) Timer 0 clock selection register (PRM01) The PRM01 register is used to select the base clock (fCLK) of timer 0 (TM0n). It can be read/written in 8-bit or 1-bit units. Caution Always set this register before using the timer. 7 PRM01 0 6 0 5 0 4 0 3 0 2 0 1 0 0 PRM1 Address FFFFF5D0H Initial value 00H Bit position 0 Bit name PRM1 Function Specifies the base clock (fCLK) of timer 0 (TM0n) (See Figure 9-3). 0: fXX/2 (When fXX > 40 MHz) 1: fXX (When fXX 40 MHz) Remark fXX: Internal system clock Figure 9-3. Timer 00 and Timer 01 Clock Timer 00 fXX Select fXX/2 fCLK Timer 01 PRM1 Remarks 1. fXX: Internal system clock 2. fCLK: Base clock 226 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (2) Timer control registers 00, 01 (TMC00, TMC01) TMC0n register is a 16-bit register that sets the operation of timer 0 (TM0n). The TMC0n register can be read/written in 16-bit units. If the higher 8 bits of the TMC0n register are used as the TMC0nH register and the lower 8 bits as the TMC0nL register, the register can be read/written in 8-bit or 1-bit units. Caution To operate timer 0, first set TM0CEn = 0 and then set TM0CEn = 1. (1/4) <15> <14> 13 12 11 10 9 8 7 0 6 <5> 4 3 2 1 0 Address FFFFF57AH Initial value 0508H TMC00 TM0CE0 STINT0 CUL02 CUL01 CUL00 PRM02 PRM01 PRM00 0 TM0CED0 BFTE3 BFTEN MBFTE MOD01 MOD00 <15> <14> 13 12 11 10 9 8 7 0 6 <5> 4 3 2 1 0 Address FFFFF5BAH Initial value 0508H TMC01 TM0CE1 STINT1 CUL02 CUL01 CUL00 PRM02 PRM01 PRM00 0 TM0CED1 BFTE3 BFTEN MBFTE MOD01 MOD00 Bit position 15 Bit name TM0CEn Specifies the operation of TM0n. Function 0: Count disabled (stops after all count values are cleared) 1: Count enabled Caution When TM0CEn = 0, TO0n0 to TO0n5 output becomes high impedance. 14 STINTn Specifies interrupt during TM0n timer start. 0: Don't generate interrupt at operation start 1: Generate interrupt at operation start When STINTn bit = 1, an interrupt is generated immediately after the rising edge of the TM0CEn signal. When the MOD01 bit = 0 (triangular wave mode), the INTTM0n interrupt (see Figure 9-4) is generated, and when the MOD01 bit = 1 (sawtooth wave mode), the INTCM0n3 interrupt is generated. Caution Changing the STINTn bit during TM0n operation (TM0CEn bit = 1) is prohibited. 13 to 11 CUL02 to CUL00 Specifies the interrupt culling ratio. CUL02 0 0 0 0 1 CUL01 0 0 1 1 0 CUL00 0 1 0 1 0 Interrupt culling ratio 1/1 1/2 1/4 1/8 1/16 Culling is not performed Other than above Remark n = 0, 1 User's Manual U14492EJ5V0UD 227 CHAPTER 9 TIMER/COUNTER FUNCTION (2/4) Bit position 13 to 11 Bit name CUL02 to CUL00 Function Cautions 1. INTTM0n and INTCM0n3 interrupts can be culled with the same culling ratio (1/1, 1/2, 1/4, 1/8, 1/16). 2. Even when BFTE3 bit = 1, BFTEN bit = 1 (settings to transfer data from BFCMn0 to BFCMn3 registers to CM0n0 to CM0n3 registers), transfer is not performed with the generation timing of culled INTTM0n and INTCM0n3 interrupts if the MBFTE bit = 0. 3. If the culling ratio is changed during count operation, the new culling ratio is applied after an interrupt has occurred with the culling ratio prior to the change (see Figure 9-5). 10 to 8 PRM02 to PRM00 Specifies the count clock for TM0n. PRM02 0 0 0 0 1 1 PRM01 0 0 1 1 0 0 PRM00 0 1 0 1 0 1 Count clock fCLK fCLK/2 fCLK/4 fCLK/8 fCLK/16 fCLK/32 Setting prohibited Other than above Caution The division ratio switch timing is from when the TM0n value has become 0000H and an INTTM0n interrupt has occurred. Therefore, in the timing that corresponds to interrupt culling, the division ratio is not switched. Remark For the base clock (fCLK), see 9.1.4 (1) Timer 0 clock selection register (PRM01). 5 TM0CEDn Specifies the operation of DTMn0 to DTMn2 timers. 0: DTMn0 to DTMn2 perform count operation 1: DTMn0 to DTMn2 stopped Cautions 1. Changing the TM0CEDn bit during TM0n operation (TM0CEn = 1) is prohibited. 2. If TM0n is operated when the TM0CEDn bit = 1, a signal without dead time is output to the TO0n0 to TO0n5 pins. Remark n = 0, 1 228 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (3/4) Bit position 4 Bit name BFTE3 Function Specifies transfer of data from BFCMn3 register to CM0n3 register. 0: Transfer disabled 1: Transfer enabled The transfer timing from the BFCMn3 register to the CM0n3 register is as follows. BFTE3 0 1 1 1 TM0n operation mode All modes PWM mode 0 (symmetric triangular wave) PWM mode 1 (asymmetric triangular wave) PWM mode 2 (sawtooth wave) BFCMn3 CM0n3 transfer timing Don't transfer INTTM0n INTTM0n INTCM0n3 When the BFTE3 bit = 1, the value of the BFCMn3 register is transferred to the CM0n3 register upon occurrence of an INTTM0n or INTCM0n3 interrupt. 3 BFTEN Specifies transfer of data from BFCMn0 to BFCMn2 registers to CM0n0 to CM0n2 registers. 0: Transfer disabled 1: Transfer enabled BFTEN 0 1 1 1 TM0n operation mode All modes PWM mode 0 (symmetric triangular wave) PWM mode 1 (asymmetric triangular wave) PWM mode 2 (sawtooth wave) BFCMn0 to BFCMn2 CM0n0 to CM0n2 transfer timing Don't transfer INTTM0n INTTM0n, INTCM0n3 INTCM0n3 When the BFTEN bit = 1, the values of the BFCMn0 to BFCMn2 registers are transferred to the CM0n0 to CM0n2 registers upon occurrence of an INTTM0n or INTCM0n3 interrupt. 2 MBFTE When culling of INTTM0n and INTCM0n3 interrupts is set with the CUL02 to CUL00 bits, specifies whether enable or disable the BFTE3 and BFTEN bit settings upon occurrence of an interrupt for culling. 0: Disable the set values of BFTE3, BFTEN bits upon occurrence of a culling interrupt 1: Enable the set values of BFTE3, BFTEN bits upon occurrence of a culling interrupt The various combinations are as follows. MBFTE BFTEN 0 Operation upon occurrence of interrupt for culling 0 BFCMn0 to BFCMn2 CM0n0 to CM0n2 transfer disabled BFCMn0 to BFCMn2 CM0n0 to CM0n2 transfer disabled BFCMn3 CM0n3 transfer disabled BFCMn3 CM0n3 transfer disabled 1 BFCMn0 to BFCMn2 CM0n0 to CM0n2 transfer disabled BFCMn0 to BFCMn2 CM0n0 to CM0n2 transfer enabled BFCMn3 CM0n3 transfer disabled BFCMn3 CM0n3 transfer enabled 1 BFTE3 0 1 . Remark n = 0, 1 User's Manual U14492EJ5V0UD 229 CHAPTER 9 TIMER/COUNTER FUNCTION (4/4) Bit position 1, 0 Bit name MOD01, MOD00 Specifies the operation mode of TM0n. MOD 01 MOD 00 Operation mode TM0n operation Timer clear source BFCMn3 BFCMn0 to BFCMn2 CM0n3 CM0n0 to timing CM0n2 timing INTTM0n INTTM0n Function 0 0 Up/down PWM mode 0 (symmetric triangular wave) Up/down PWM mode 1 (asymmetric triangular wave) Up PWM mode 2 (sawtooth wave) Setting prohibited - 0 1 - INTTM0n INTTM0n, INTCM0n3 INTCM0n3 1 1 0 1 INTCM0n3 INTCM0n3 Caution Changing the value of the MOD01, MOD00 bits during TM0n operation (TM0CEn bit = 1) is prohibited. Remark n = 0, 1 Figure 9-4. Specification of INTTM0n Interrupt During PWM Mode 0 (Symmetric Triangular Wave), PWM Mode 1 (Asymmetric Triangular Wave) (MOD01, MOD00 Bits of TMC0n Register = 0n) CM0n3 TM0n count value 0000H Timer operation stopped TM0CEn Specification from occurrence of INTTM0n at first start after reset is possible with STINTn bit INTTM0n occurrence INTTM0n occurrence can be specified with STINTn bit INTTM0n occurrence Remark n = 0, 1 230 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-5. Interrupt Culling Processing (a) PWM mode 0 (symmetric triangular wave) CM0n3 TM0n count value 0000H Interrupt request INTTM0n occurrence INTTM0n occurrence INTTM0n occurrence INTTM0n occurrence CUL02 to CUL00 000 001 Interrupt culling 1/1 cycle Interrupt culling 1/2 cycle Remark n = 0, 1 (b) PWM mode 1 (asymmetric triangular wave) CM0n3 TM0n count value 0000H Interrupt request INTCM0n3 INTTM0n INTCM0n3 INTTM0n INTCM0n3 occurrence occurrence occurrence occurrence occurrence INTTM0n INTCM0n3 occurrence occurrence INTTM0n occurrence CUL02 to CUL00 000 001 Interrupt culling 1/1 cycle Interrupt culling 1/2 cycle Remark n = 0, 1 (c) PWM mode 2 (sawtooth wave) CM0n3 TM0n count value 0000H Interrupt request CUL02 to CUL00 INTCM0n3 occurrence INTCM0n3 occurrence INTCM0n3 occurrence INTCM0n3 occurrence 000 001 Interrupt culling 1/1 cycle Interrupt culling 1/2 cycle Remark n = 0, 1 User's Manual U14492EJ5V0UD 231 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-6. Interrupt Culling Ratio Change Timing (Relationship Between STINTn Bit Setting and CUL Bit Change): PWM Mode 1 (Asymmetric Triangular Wave) TM0CEn bit CM0n3 TM0n count value 0000H STINTn = 1 INTTM0n INTTM0n INTTM0n INTTM0n CUL02 to CUL00 bits 000 Interrupt culling 1/1 cycle INTCM0n3 INTCM0n3 INTCM0n3 INTCM0n3 INTTM0n INTCM0n3 INTTM0n INTCM0n3 INTTM0n INTCM0n3 INTTM0n INTCM0n3 001 Interrupt culling 1/2 cycle 010 Interrupt culling 1/4 cycle TM0CEn bit CM0n3 TM0n count value 0000H STINTn = 1 CUL02 to CUL00 bits INTTM0n INTCM0n3 INTTM0n INTCM0n3 INTTM0n INTCM0n3 INTTM0n INTTM0n INTTM0n INTTM0n INTCM0n3 INTCM0n3 INTCM0n3 INTCM0n3 001 Interrupt culling 1/2 cycle 010 Interrupt culling 1/4 cycle 000 Interrupt culling 1/1 cycle TM0CEn bit CM0n3 TM0n count value 0000H STINTn = 1 CUL02 to CUL00 bits 001 Interrupt culling 1/2 cycle INTTM0n INTCM0n3 INTTM0n INTCM0n3 INTCM0n3 INTTM0n INTTM0n INTTM0n INTTM0n INTTM0n INTCM0n3 INTCM0n3 INTCM0n3 INTCM0n3 010 Interrupt culling 1/4 cycle 000 Interrupt culling 1/1 cycle Caution If, in TM0n, to realize the INTTM0n and INTCM0n3 culling function, the culling ratio is set to a value other than 1/1 with bits CUL02 to CUL00 and counting is started, the subsequent interrupt output sequence will differ due to the set value of the STINTn bit at count start. Remark n = 0, 1 232 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (3) Timer unit control registers 00, 01 (TUC00, TUC01) TUC0n register is an 8-bit register that controls TO0n0 to TO0n5 outputs. TUC0n can be read/written in 8-bit or 1-bit units. However, bit 0 is read-only. 7 TUC00 0 6 0 5 0 4 0 3 0 2 0 <1> TORS0 <0> TOSTA0 Address FFFFF57CH Initial value 01H 7 TUC01 0 6 0 5 0 4 0 3 0 2 0 <1> TORS1 <0> TOSTA1 Address FFFFF5BCH Initial value 01H Bit position 1 Bit name TORSn Function Flag that restarts TO0n0 to TO0n5 pin output that was forcibly stopped by ESOn pin input. Causes output to resume by writing "1" to TORSn bit. Cautions 1. If the level is set for the ESOn pin input level (TOMR register TOEDG1 bit = 1, TOEDG0 bit = 0 or 1), the output disabled state is not released (TOSTAn bit = 1) even if "1" is written to the TORSn bit while the output is disabled (TOSTAn bit = 1). If the input level is inactive, the output disabled state is released (TOSTAn bit = 0). The value of the TORSn bit is held. 2. If the edge is set for the ESOn pin input (TOEDG1 bit = 0, TOEDG0 bit = 0 or 1), the output disabled state is released (TOSTAn bit = 0) by writing "1" to the TORSn bit while the output is disabled (TOSTAn bit = 1). 3. After reset, be sure to write "1" to the TORSn bit prior to starting output of TO0n0 to TO0n5. "0" is read when the TORSn bit is read. 0 TOSTAn TO0n0 to TO0n5 pin output status flag through ESOn pin input 0: Output enabled status 1: Output disabled status Remark n = 0, 1 User's Manual U14492EJ5V0UD 233 CHAPTER 9 TIMER/COUNTER FUNCTION (4) Timer output mode registers 0, 1 (TOMR0, TOMR1) The TOMRn register controls timer output from the TO0n0 to TO0n5 pins. To prevent abnormal output from pins TO0n0 to TO0n5 due to illegal access, data write to the TOMRn register consists of the following two sequences. (a) Write access to the TOMR write enable register (SPECn), followed by (b) Write access to the TOMRn register Write is not enabled hardware-wise unless these two sequences are implemented. TOMRn can be read/written in 8-bit units. Caution When interrupt requests are generated during write access to the TOMRn register (after write access to the SPECn register and prior to write to the TOMRn register), write processing to the TOMRn register may not be performed normally if access to other addresses is performed using the internal bus during servicing of these interrupts. Add one of the following processing items during the TOMRn register write routine. * Prior to write access to the TOMRn register, disable acknowledge of all interrupts of CPU. * Following write access to the TOMRn register, check that write was performed normally. (1/2) 7 TOMR0 ALVTO 6 ALVUB 5 ALVVB 4 ALVWB 3 TOSP 2 0 1 0 Address FFFFF57DH Initial value 00H TOEDG1 TOEDG0 7 TOMR1 ALVTO 6 ALVUB 5 ALVVB 4 ALVWB 3 TOSP 2 0 1 0 Address FFFFF5BDH Initial value 00H TOEDG1 TOEDG0 Bit position 7 Bit name ALVTO Function Specifies the active level of TO0n0, TO0n2, and TO0n4 pins. 0: Active level is low level 1: Active level is high level Caution Changing the ALVTO bit during TM0n operation (TM0CEn = 1) is prohibited. 6 ALVUB Specifies the output level of the TO0n1 pin. 0: Inverted level of active level set by ALVTO bit 1: Active level set by ALVTO bit When the ALVUB bit = 1, the output level of the TO0n1 output is the same as TO0n0. Caution Changing the ALVUB bit during TM0n operation (TM0CEn = 1) is prohibited. Remark n = 0, 1 234 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position 5 Bit name ALVVB Function Specifies the output level of the TO0n3 pin. 0: Inverted level of active level set by ALVTO bit 1: Active level set by ALVTO bit When the ALVVB bit = 1, the output level of the TO0n3 output is the same as TO0n2. Caution Changing the ALVVB bit during TM0n operation (TM0CEn = 1) is prohibited. 4 ALVWB Specifies the output level of the TO0n5 pin. 0: Inverted level of active level set by ALVTO bit 1: Active level set by ALVTO bit When the ALVWB bit = 1, the output level of the TO0n5 output is the same as TO0n4. Caution Changing the ALVWB bit during TM0n operation (TM0CEn = 1) is prohibited. 3 TOSP Controls TO0n0 to TO0n5 pin output stop through ESOn pin input. 0: Enables ESOn pin input 1: Disables ESOn pin input Cautions 1. The output stop status can be released by writing "1" to the TORSn bit of the TUC0n register. The operation continues even if output is prohibited for all timers and counters. 2. Before changing the ESOn pin input status from disable to enable (changing TOSP bit from 1 to 0), write "1" to the TORSn bit of the TUC0n register to reset the ESOn pin input status. 1, 0 TOEDG1, TOEDG0 These bits select the valid edge or level when setting forcible stop of TO0n0 to TO0n5 output through ESOn pin input with the TOSP bit. TOEDG1 0 0 1 1 TOEDG0 0 1 0 1 Rising edge Falling edge Low level High level Operation Cautions 1. Changing the TOEDG1, TOEDG0 bits during TM0n operation (TM0CEn = 1) is prohibited. 2. Before changing the settings of bits TOEDG1 and TOEDG0, write "1" to the TORSn bit of the TUC0n register to reset the ESOn pin input status. Remark n = 0, 1 User's Manual U14492EJ5V0UD 235 CHAPTER 9 TIMER/COUNTER FUNCTION Examples of the output waveforms of TO000 and TO001 when the higher 4 bits (ALVTO, ALVUB, ALVVB, and ALVWB) of the TOMRn register are set in PWM mode 0 (symmetric triangular waves) are shown below. Figure 9-7. Output Waveforms of TO000 and TO001 in PWM Mode 0 (Symmetric Triangular Waves) (Without Dead Time (TM0CED0 Bit = 1)) (a) TOMR0 register value = 80H TM00 = CM000 TO000 TM00 = CM000 TO001 (b) TOMR0 register value = 00H TM00 = CM000 TO000 TM00 = CM000 TO001 (c) TOMR0 register value = C0H TM00 = CM000 TO000 TM00 = CM000 TO001 (d) TOMR0 register value = 40H TM00 = CM000 TO000 TM00 = CM000 TO001 236 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-8. Output Waveforms of TO000 and TO001 in PWM Mode 0 (Symmetric Triangular Waves) (With Dead Time (TM0CED0 Bit = 0)) (a) TOMR0 register value = 80H TM00 = CM000 TM00 = CM000 TO000 TO001 Dead time period Dead time period (b) TOMR0 register value = 00H TM00 = CM000 TM00 = CM000 TO000 TO001 Dead time period Dead time period (c) TOMR0 register value = C0H TM00 = CM000 TM00 = CM000 TO000 TO001 Dead time period Dead time period (d) TOMR0 register value = 40H TM00 = CM000 TM00 = CM000 TO000 TO001 Dead time period Dead time period User's Manual U14492EJ5V0UD 237 CHAPTER 9 TIMER/COUNTER FUNCTION Data setting to timer output mode registers 0, 1 (TOMR0, TOMR1) is done in the following sequence. <1> Prepare the data to be set to timer output mode registers 0, 1 (TOMR0, TOMR1) in a general-purpose register. <2> Write data to the TOMR write enable registers 0, 1 (SEPC0, SPEC1). <3> Set timer output mode registers 0, 1 (TOMR0, TOMR1) (performed with the following instructions). * Store instruction (ST/SST instructions) * Bit manipulation instruction (SET1/CLR1/NOT1 instructions) [Description example] <1> MOV <2> ST.B <3> ST.B Remark n = 0, 1 To read the TOMRn register, no special sequence is required. Cautions 1. Disable interrupts between SPECn issue (<2>) and TOMRn register write that immediately follows (<3>). 2. The data written to the SPECn register is dummy data; use the same register as the generalpurpose register used to set the TOMRn register (<3> in the above example) for SPECn register write (<2> in the above example). The same applies when using a general-purpose register for addressing. 3. Do not write to the SPECn register or TOMRn register via DMA transfer. 0x04, r10 r10, SPECn [r0] r10, TOMRn [r0] 238 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (5) PWM output enable registers 0, 1 (POER0, POER1) The POERn register is used to make the external pulse output (TO0n0 to TO0n5) status inactive by software. POERn can be read/written in 8-bit or 1-bit units. 7 POER0 0 6 0 <5> OE210 <4> OE200 <3> OE110 <2> OE100 <1> OE010 <0> OE000 Address FFFFF57FH Initial value 00H 7 POER1 0 6 0 <5> OE211 <4> OE201 <3> OE111 <2> OE101 <1> OE011 <0> OE001 Address FFFFF5BFH Initial value 00H Bit position 5 Bit name OE21n Specifies output status of TO0n5 pin. Function 0: TO0n5 output status is high impedance. 1: TO0n5 output status is controlled by TM0CEn bit of TMC0n register and TORTOn bit of PSTOn register and ESOn pin. 4 OE20n Specifies output status of TO0n4 pin. 0: TO0n4 output status is high impedance. 1: TO0n4 output status is controlled by TM0CEn bit of TMC0n register and TORTOn bit of PSTOn register and ESOn pin. 3 OE11n Specifies output status of TO0n3 pin. 0: TO0n3 output status is high impedance. 1: TO0n3 output status is controlled by TM0CEn bit of TMC0n register and TORTOn bit of PSTOn register and ESOn pin. 2 OE10n Specifies output status of TO0n2 pin. 0: TO0n2 output status is high impedance. 1: TO0n2 output status is controlled by TM0CEn bit of TMC0n register and TORTOn bit of PSTOn register and ESOn pin. 1 OE01n Specifies output status of TO0n1 pin. 0: TO0n1 output status is high impedance. 1: TO0n1 output status is controlled by TM0CEn bit of TMC0n register and TORTOn bit of PSTOn register and ESOn pin. 0 OE00n Specifies output status of TO0n0 pin. 0: TO0n0 output status is high impedance. 1: TO0n0 output status is controlled by TM0CEn bit of TMC0n register and TORTOn bit of PSTOn register and ESOn pin. Remark n = 0, 1 User's Manual U14492EJ5V0UD 239 CHAPTER 9 TIMER/COUNTER FUNCTION (6) PWM software timing output registers 0, 1 (PSTO0, PSTO1) The PSTOn register is used to perform settings to output the desired waveforms to the external pulse output pins (TO0n0 to TO0n5) by software. PSTOn can be read/written in 8-bit or 1-bit units. Cautions 1. When the value of the TORTOn bit has been changed from 0 to 1 during timer output (setting changed to software output), the timing is delayed by the dead-time portion when the output level differs from the timer output signal during output due to the settings of the UPORTn, VPORTn, and WPORTn bits. When the output level is the same as the timer output signal during output due to the settings of the UPORTn, VPORTn, and WPORTn bits, output is performed maintaining the same output level. 2. If software output is enabled (TORTOn bit = 1), the INTTM0n and INTCM0n3 interrupts and TO0n0 to TO0n5 output statuses are as follows during TM0n operation (TM0CEn bit = 1). INTTM0n and INTCM0n3 interrupts: Continue occurring at each timing in accordance with timer and compare operations. TO0n0 to TO0n5 outputs: Software output has priority. 3. If the TORTOn bit is changed from 1 to 0 during TM0n operation (TM0CEn bit = 1), the software output state is retained for the TO0n0 to TO0n5 outputs until one of the set/reset condition of the flip-flop for the TO0n0 to TO0n5 outputs shown in (a) below is generated. (a) Set/reset conditions of flip-flop for TO0n0 to TO0n5 outputs Output Status Set Timer output Operation Mode Triangular wave mode (PWM mode 0, 1) Sawtooth wave mode (PWM mode 2) Software output Reset Timer output - Triangular wave mode (PWM mode 0, 1) Sawtooth wave mode (PWM mode 2) Software output - Match between TM0n and CM0n3 registers Conditions Compare match while TM0n is counting up Set (to 1) UPORTn, VPORTn, and WPORTn bits Compare match while TM0n is counting down Compare match with TM0n Clear (to 0) UPORTn, VPORTn, and WPORTn bits Remark n = 0, 1 4. If the same value is written to the UPORTn (VPORTn, WPORTn) bit when TORTOn = 1, the TO0n0 and TO0n1 outputs (TO0n2 and TO0n3, TO0n4 and TO0n5) are not changed. 240 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (1/2) <7> PSTO0 TORTO0 6 0 5 0 4 0 3 0 <2> <1> <0> Address FFFFF57EH Initial value 00H UPORT0 VPORT0 WPORT0 <7> PSTO1 TORTO1 6 0 5 0 4 0 3 0 <2> <1> <0> Address FFFFF5BEH Initial value 00H UPORT1 VPORT1 WPORT1 Bit position 7 Bit name TORTOn Function Specifies TO0n0 to TO0n5 output control. 0: Timer output 1: Software output The change of the TO0n0 to TO0n5 signals during software output occurs when the TORTOn bit is set (to 1) and a value is written to the UPORTn, VPORTn, and WPORTn bits. A dead-time timer can also be used. 2 UPORTn Specifies the TO0n0 (U phase)/TO0n1 (U phase) pin output value. UPORTn 0 TO0n0 TO0n1 Operation Inverted level of ALVTO bit setting When ALVUB = 0 When ALVUB = 1 1 TO0n0 TO0n1 Level of ALVTO bit setting Inverted level of ALVTO bit setting Level of ALVTO bit setting When ALVUB = 0 When ALVUB = 1 Inverted level of ALVTO bit setting Level of ALVTO bit setting Caution If the UPORTn bit setting value is changed when TORTOn = 1, the dead-time setting becomes valid for the TO0n0/TO0n1 output signal in the same way as during normal timer operation. 1 VPORTn Specifies the TO0n2 (V phase)/TO0n3 (V phase) pin output value. VPORTn 0 TO0n2 TO0n3 Operation Inverted level of ALVTO bit setting When ALVVB = 0 When ALVVB = 1 1 TO0n2 TO0n3 Level of ALVTO bit setting Inverted level of ALVTO bit setting Level of ALVTO bit setting When ALVVB = 0 When ALVVB = 1 Inverted level of ALVTO bit setting Level of ALVTO bit setting Caution If the VPORTn bit setting value is changed when TORTOn = 1, the dead-time setting becomes valid for the TO0n2/TO0n3 output signal in the same way as during normal timer operation. Remark n = 0, 1 ALVTO bit: Bit 7 of the TOMRn register ALVUB bit: Bit 6 of the TOMRn register ALVVB bit: Bit 5 of the TOMRn register User's Manual U14492EJ5V0UD 241 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position 0 Bit name WPORTn Function Specifies the TO0n4 (W phase)/TO0n5 (W phase) pin output value. WPORTn 0 TO0n4 TO0n5 Operation Inverted level of ALVTO bit setting When ALVWB = 0 When ALVWB = 1 1 TO0n4 TO0n5 Level of ALVTO bit setting Inverted level of ALVTO bit setting Level of ALVTO bit setting When ALVWB = 0 When ALVWB = 1 Inverted level of ALVTO bit setting Level of ALVTO bit setting Caution If the WPORTn bit setting value is changed when TORTOn = 1, the dead-time setting becomes valid for the TO0n4/TO0n5 output signal in the same way as during normal timer operation. Remark n = 0, 1 ALVTO bit: Bit 7 of the TOMRn register ALVWB bit: Bit 4 of the TOMRn register The TO0n0 to TO0n5 pins can be set to timer output by a match between TM0n and the compare register or to software output using the PSTOn register (TORTOn bit = 1). Software output has the priority over timer output. Consequently, when the setting changes from TM0CEn = 1 (timer operation enabled), TORTOn = 1 (software output enabled) to TM0CEn = 1 (timer operation enabled), TORTOn = 0 (software output disabled), the TO0n0 to TO0n5 pins continue to perform software output until the occurrence of the first F/F set/reset due to a match between TM0n and the compare register after the TORTOn bit setting changes. The relationship between the settings of the TORTOn and TM0CEn bits when ALVTO = 1 and the output of TO0n0 (positive phase side) is shown on the following pages (the negative phase side (TO0n1, TO0n3, and TO0n5) is dependent on the ALVUB, ALVVB, and ALVWB bits, so refer to the explanations of each of these bits). 242 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-9. When UPORTn = 1 Is Set Immediately Before TORTOn = 0 (Switched by Active Value) CM0n3 TM0n Count value 0000H Note 1 Note 2 CM0n3 CM0n3 CM0n3 Note 3 Note 2 Note 1 Note 2 F/F INTCM0n3 Note 4 INTTM0n TO0n0 TM0CEn TORTOn UPORTn Timer output Software output P1 T1 Timer output Notes 1. 2. 3. 4. Remark F/F set by compare match during up count F/F reset by compare match during down count F/F set by writing UPORTn bit F/F reset by writing UPORTn bit n = 0, 1 If the setting of the TORTOn bit changes from 1 to 0 while the UPORTn bit is set to 1 in the P1 period in Figure 9-9 above, the F/F continues to hold the TORTOn bit setting of "1" until the T1 timing. However, because the F/F is reset at the T1 timing (by a compare match of TM0n during down counting), the TO0n0 output changes from 1 to 0. User's Manual U14492EJ5V0UD 243 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-10. When UPORTn = 0 Is Set Immediately Before TORTOn = 0 (Switched by Inactive Value) CM0n3 TM0n Count value 0000H Note 1 Note 2 CM0n3 CM0n3 CM0n3 Note 3 Note 1 Note 2 F/F INTCM0n3 Note 4 INTTM0n TO0n0 TM0CEn TORTOn UPORTn Timer output Software output P1 Timer output T2 Notes 1. 2. 3. 4. Remark F/F set by compare match during up count F/F reset by compare match during down count F/F set by writing UPORTn bit F/F reset by writing UPORTn bit n = 0, 1 If the setting of the TORTOn bit changes from 1 to 0 while the UPORTn bit is set to 0 in the P1 period in Figure 910 above, the F/F continues to hold the TORTOn bit setting of "0" until the T2 timing. However, because the F/F is set at the T2 timing (by a compare match of TM0n during up counting), the TO0n0 output changes from 1 to 0. Note that TO0n0 to TO0n5 output will stop if the TORTOn bit setting is changed from 1 to 0 while the TM0CEn bit is 0. 244 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-11. When UPORTn = 0 Is Set Immediately Before TORTOn = 1 CM0n3 TM0n Count value 0000H Note 1 Note 2 CM0n3 CM0n3 CM0n3 Note 1 Note 3 Note 1 Note 2 F/F INTCM0n3 Note 4 INTTM0n TO0n0 TM0CEn TORTOn UPORTn Timer output T3 Software output Timer output Notes 1. 2. 3. 4. Remark F/F set by compare match during up count F/F reset by compare match during down count F/F set by writing UPORTn bit F/F reset by writing UPORTn bit n = 0, 1 If the setting of the TORTOn bit changes from 0 to 1 while the UPORTn bit is set to 0 during TM0n operation (TM0CEn = 1), the TO0n0 output changes from 1 to 0 because the F/F is reset at the T3 timing. Examples of the software output waveforms of TO000 and TO001 based on the settings of the TORTOn, UPORTn, VPORTn, and WPORTn bits are shown on the following pages. User's Manual U14492EJ5V0UD 245 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-12. Software Output Waveforms of TO000 and TO001 (Without Dead Time (TM0CED0 = 1)) (a) TOMR0 register value = 80H UPORT0 1 TO000 UPORT0 0 TO001 (b) TOMR0 register value = 00H UPORT0 1 TO000 UPORT0 0 TO001 (c) TOMR0 register value = C0H UPORT0 1 TO000 UPORT0 0 TO001 (d) TOMR0 register value = 40H UPORT0 1 TO000 UPORT0 0 TO001 246 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-13. Software Output Waveforms of TO000 and TO001 (With Dead Time (TM0CED0 = 0)) (a) TOMR0 register value = 80H UPORT0 1 UPORT0 0 TO000 TO001 Dead-time period Dead-time period (b) TOMR0 register value = 00H UPORT0 1 UPORT0 0 TO000 TO001 Dead-time period Dead-time period (c) TOMR0 register value = C0H UPORT0 1 UPORT0 0 TO000 TO001 Dead-time period Dead-time period (d) TOMR0 register value = 40H UPORT0 1 UPORT0 0 TO000 TO001 Dead-time period Dead-time period User's Manual U14492EJ5V0UD 247 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-14. Software Output Waveforms of TO000 and TO001 When "1" Is Written to UPORT0 Bit While TORTO0 = 1 (When TOMR0 Register Value = 80H) (a) Without dead time (TM0CED0 = 1) UPORT0 1 UPORT0 0 UPORT0 1 TO000 TO001 (b) With dead time (TM0CED0 = 0) UPORT0 1 UPORT0 0 UPORT0 1 TO000 TO001 Dead-time period Dead-time period The following table shows the output status of external pulse output (in the case of TO0n0). Table 9-2. Output Status of External Pulse Output (In Case of TO0n0) OE00n Bit 0 1 TORTOn, UPORTn Bits 0/1 0 TM0CEn Bit 0/1 0 1 1 0/1 TO0n0 High impedance High impedance Timer output Output by UPORTn bit Remarks 1. OE00n bit: Bit 0 of POERn register TORTOn bit: Bit 7 of PSTOn register UPORTn bit: Bit 2 of PSTOn register TM0CEn bit: Bit 15 of TMC0n register 2. n = 0, 1 248 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (7) TOMR write enable registers 0, 1 (SPEC0, SPEC1) The SPECn register enables write to the TOMRn register. Unless write to the TOMRn register is performed following immediately after write to the SPECn register (any data can be written), write processing to the TOMRn register is not performed normally. Normally, 0000H is read. The SPECn register can be read/written in 16-bit units. Remark n = 0, 1 15 SPEC0 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Address FFFFF580H Initial value 0000H 15 SPEC1 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Address FFFFF5C0H Initial value 0000H User's Manual U14492EJ5V0UD 249 CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.5 Operation Remarks 1. In the description of the operation in 9.1.5, it is assumed that each bit that affects the output of TO0n0 to TO0n5 is set as follows. ALVTO = 1, ALVUB = 0, ALVVB = 0, ALVWB = 0, TORTOn = 0 2. F/F mentioned in 9.1.5 is a flip-flop that controls output of the TO0n0 to TO0n5 pins. (1) Basic operation Timer 0 (TM0n) is a 16-bit interval timer that operates as an up/down timer or as an up timer. The cycle is controlled by compare register 0n3 (CM0n3) (n = 0, 1). All TM0n bits are cleared (0) by RESET input and count operation is stopped. Count operation enable/disable is controlled by the TM0CEn bit of timer control register 0n (TMC0n). The count operation is started by setting the TM0CEn bit to 1 by software. Resetting the TM0CEn bit to 0 clears TM0n and stops the count operation. When the value of compare register 0n3 (CM0n3) set beforehand and the value of the TM0n counter match, a match interrupt (INTCM0n3) is generated. The count clock to TM0n can be selected from among 6 internal clocks with the TMC0n register. If the TM0n has been set as an up/down timer, an underflow interrupt (INTTM0n) is generated when TM0n becomes 0000H during down counting. The TM0n has the following three operation modes, which are selected with timer control register 0n (TMC0n). * PWM mode 0: Triangular wave modulation (Right-left symmetric waveform control) * PWM mode 1: Triangular wave modulation (Right-left asymmetric waveform control) * PWM mode 2: Sawtooth wave modulation control Table 9-3. Timer 0 (TM0n) Operation Modes TMC0n Register MOD01 MOD00 0 0 PWM mode 0 (symmetric triangular wave) 0 1 PWM mode 1 (asymmetric triangular wave) 1 0 PWM mode 2 (sawtooth wave) Setting prohibited Up INTCM0n3 Up/down - Operation Mode TM0n Operation Timer Clear Source Interrupt Source BFCMn3 CM0n3 Timing INTTM0n BFCMn0 to BFCMn2 CM0n0 to CM0n2 Timing INTTM0n Up/down - INTTM0n INTCM0n3 INTTM0n INTCM0n3 INTTM0n INTTM0n INTCM0n3 INTCM0n3 INTCM0n3 INTCM0n3 1 1 Caution Remark Changing bits MOD01, MOD00 during TM0n operation (TM0CEn = 1) is prohibited. n = 0, 1 The various operation modes are described below. 250 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (2) PWM mode 0: Triangular wave modulation (right-left symmetric waveform control) [Setting procedure] (a) Set PWM mode 0 (symmetric triangular wave) with bits MOD01 and MOD00 of the TMC0n register. Also set the active level of pins TO0n0 to TO0n5 with the ALVTO bit of the TOMRn register (n = 0, 1). (b) Set the count clock of TM0n with bits PRM02 to PRM00 of the TMC0n register. The transfer operation from BFCMn3 to CM0n3 is set with bit BFTE3, and the transfer operation from BFCMn0 to BFCMn2 to CM0n0 to CM0n2 is set with bit BFTEN. (c) Set the initial values. (i) Specify the interrupt culling ratio with bits CUL02 to CUL00 of the TMC0n register. (ii) Set the half-cycle width of the PWM cycle in BFCMn3. * PWM cycle = BFCMn3 value x 2 x TM0n count clock (The TM0n count clock is set with the TMC0n register.) (iii) Set the dead-time width in DTRRn. * Dead-time width = (DTRRn + 1)/fCLK fCLK: Base clock (iv) Set the set/reset timing of the F/F used in the PWM cycle in BFCMn0 to BFCMn2. (d) Clear (0) the TM0CEDn bit of the TMC0n register to enable dead-time timer operation. Set TM0CEDn = 1 when not using dead time. (e) Setting (1) the TM0CEn bit of the TMC0n register starts TM0n counting, and a 6-channel PWM signal is output from pins TO0n0 to TO0n5. Cautions 1. Setting CM0n3 to 0000H is prohibited. 2. Setting BFCMnx > BFCMn3 is prohibited when the TM0CEn bit of the TMC0n register = 0 because output of the TO0n0 to TO0n5 pins is inverted from the setting (x = 0 to 2). In addition, setting BFCMnx > BFCMn3 is also prohibited when the TM0CEn bit of the TMC0n register = 1 and the CM0nx register = 0. Remark The TM0CEn bit of the TMC0n register indicates transfer operation under the following conditions. * When TM0CEn bit of TMC0n register is 0 Transfer to the CM0n0 to CM0n2 registers is performed at the next base clock (fCLK) after writing to registers BFCMn0 to BFCMn2. * When TM0CEn bit of TMC0n register is 1 The value of the BFCMn0 to BFCMn2 registers is transferred to the CM0n0 to CM0n2 registers upon occurrence of the INTTM0n interrupt. Transfer enable/disable at this time is controlled by bit BFTEN of the TMC0n register. User's Manual U14492EJ5V0UD 251 CHAPTER 9 TIMER/COUNTER FUNCTION [Operation] In PWM mode 0, TM0n performs up/down count operation. When TM0n = 0000H during down counting, an underflow interrupt (INTTM0n) is generated, and when TM0n = CM0n3 during up counting, a match interrupt (INTCM0n3) is generated (n = 0, 1). Switching from up counting to down counting is performed when TM0n and CM0n3 match (INTCM0n3), and switching from down counting to up counting is performed when TM0n underflow occurs after TM0n becomes 0000H. The PWM cycle in this mode is (BFCMn3 value x 2 x TM0n count clock). Concerning setting of data to BFCMn3, the next PWM cycle width is set to BFCMn3. The data of BFCMn3 is automatically transferred by hardware to CM0n3 upon generation of the INTTM0n interrupt. Furthermore, calculation is performed by software processing started by INTTM0n, and the data for the next cycle is set to BFCMn3. Data setting to CM0n0 to CM0n2, which control the PWM duty, is explained next. Setting of data to CM0n0 to CM0n2 consists in setting the duty output from BFCMn0 to BFCMn2. The values of BFCMn0 to BFCMn2 are automatically transferred by hardware to CM0n0 to CM0n2 upon generation of the INTTM0n interrupt. Furthermore, software processing is started up and calculation performed, and set/reset timing of the F/F for the next cycle is set to BFCMn0 to BFCMn2. The PWM cycle and the PWM duty are set in the above procedure. The F/F set/reset conditions upon match of CM0n0 to CM0n2 are as follows. * Set: CM0n0 to CM0n2 match detection during TM0n up-count operation * Reset: CM0n0 to CM0n2 match detection during TM0n down-count operation In this mode, the F/F set/reset timing is performed in the same timing (right-left symmetric control). The values of DTRRn are transferred to the corresponding dead-time timers (DTMn0 to DTMn2) in synchronization with the set/reset timing of the F/F, and down counting is started. DTMn0 to DTMn2 count down to 000H, and stop when they count down further to FFFH. DTMn0 to DTMn2 can automatically generate a width (dead time) at which the active levels of the positive phase (TO0n0, TO0n2, TO0n4) and negative phase (TO0n1, TO0n3, TO0n5) do not overlap. In this way, software processing is started by an interrupt (INTTM0n) that occurs once during every PWM cycle after initial setting has been performed, and by setting the PWM cycle and PWM duty to be used in the next cycle, it is possible to automatically output a PWM waveform to TO0n0 to TO0n5 pins taking into consideration the dead-time width (in case of interrupt culling ratio of 1/1). 252 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION [Output waveform width in respect to set value] * PWM cycle = BFCMn3 x 2 x TTM0n * Dead-time width TDnm = (DTRRn + 1)/fCLK * Active width of positive phase (TO0n0, TO0n2, TO0n4 pins) = { (CM0n3 - CM0nXup) + (CM0n3 - CM0nXdown) } x TTM0n - TDnm * Active width of negative phase (TO0n1, TO0n3, TO0n5 pins) = (CM0nXdown + CM0nXup) x TTM0n - TDnm * In this mode, CM0nXup = CM0nXdown (However, within the same PWM cycle). Since CM0nXup and CM0nXdown in the negative phase formula are prepared in a separate PWM cycle, CM0nXup CM0nXdown. fCLK: TTM0n: CM0nXup: Base clock TM0n count clock Set value of CM0n0 to CM0n2 while TM0n is counting up CM0nXdown: Set value of CM0n0 to CM0n2 while TM0n is counting down The pin level when the TO0n0 to TO0n5 pins are reset is the high impedance state. When the control mode is selected thereafter, the following levels are output until the TM0n is started. * TO0n0, TO0n2, TO0n4... When low active High level When high active Low level * TO0n1, TO0n3, TO0n5... When low active Low level When high active High level The active level is set with the ALVTO bit of the TOMRn register. The default is low active. Caution If a value such that the positive phase or negative phase active width is "0" or a negative value in the above formula, the TO0n0 to TO0n5 pins output a waveform fixed to the inactive level waveform with active width "0". Remark m = 0 to 2 n = 0, 1 User's Manual U14492EJ5V0UD 253 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-15. Operation Timing in PWM Mode 0 (Symmetric Triangular Wave) CM0n3 (d) a TM0n count value 0000H CM0nx match CM0nx match CM0nx match CM0n3 (e) a b b CM0nx match BFCMnx a b c CM0nx a b c BFCMn3 d e f CM0n3 Interrupt request F/F d INTCM0n3 INTTM0n e INTCM0n3 f INTTM0n DTMnx Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) t t t t Remarks 1. The above figure shows the timing chart when BFTE3 and BFTEN of the TMC0n register are 1, and transfer from BFCMn3 to CM0n3, or from BFCMnx to CM0nx is enabled. Transfer is not performed when BFTE3 = 0 or BFTEN = 0. 2. n = 0, 1 3. x = 0 to 2 4. t: Dead time = (DTRRn + 1)/fCLK (fCLK: Base clock) 5. To not use dead time, set the TM0CEDn bit of the TMC0n register to 1. 6. The above figure shows an active high case. Figure 9-16 shows the overall operation image. 254 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-16. Overall Operation Image of PWM Mode 0 (Symmetric Triangular Wave) CM0n3 CM0n2 CM0n2 CM0n1 CM0n2 CM0n1 CM0n3 CM0n2 CM0n1 CM0n0 TM0n count value 0000H TO0n0 output TO0n1 output TO0n2 output Without dead time TO0n3 output TO0n4 output TO0n5 output TO0n0 output TO0n1 output TO0n2 output With dead time TO0n3 output TO0n4 output TO0n5 output CM0n1 CM0n0 CM0n0 CM0n0 Remark n = 0, 1 User's Manual U14492EJ5V0UD 255 CHAPTER 9 TIMER/COUNTER FUNCTION Next, an example of the operation timing, which depends on the values set to CM0n0 to CM0n2 (BFCMn0 to BFCMn2) is shown. (a) When CM0nx (BFCMnx) CM0n3 is set Figure 9-17. Operation Timing in PWM Mode 0 (Symmetric Triangular Wave, BFCMnx CM0n3) CM0n3 a TM0n count value 0000H CM0nx match CM0nx match CM0n3 a BFCMnx a BFCMnx CM0n3 BFCMnx CM0n3 CM0nx Interrupt request F/F a INTCM0n3 INTTM0n BFCMnx CM0n3 INTCM0n3 INTTM0n DTMnx Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) t t Remarks 1. n = 0, 1 2. x = 0 to 2 3. t: Dead time = (DTRRn + 1)/fCLK (fCLK: Base clock) 4. The above figure shows an active high case. When a value greater than CM0n3 is set to BFCMnx, the positive phase side (TO0n0, TO0n2, TO0n4 pins) outputs a low level, and the negative phase side (TO0n1, TO0n3, TO0n5 pins) continues to output a high level. This feature is effective for outputting a low-level or high-level width exceeding the PWM cycle in an application such as inverter control. Furthermore, if CM0nx = CM0n3 is set, matching of TM0n and CM0nx is detected during down counting by TM0n, so that the F/F remains reset as is, and does not get set. The above explanation applies to an active high case. In an active low case, the levels of positive and negative phases are merely inverted and other operations remain the same. 256 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (b) When CM0nx (BFCMnx) = 0000H is set Figure 9-18. Operation Timing in PWM Mode 0 (Symmetric Triangular Wave, BFCMnx = 0000H) CM0n3 a TM0n count value 0000H CM0nx match CM0nx match CM0nx match CM0n3 a BFCMnx a 0000H 0000H CM0nx Interrupt request F/F a INTCM0n3 INTTM0n 0000H INTCM0n3 INTTM0n DTMnx Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) t t t Remarks 1. n = 0, 1 2. x = 0 to 2 3. t: Dead time = (DTRRn + 1)/fCLK (fCLK: Base clock) 4. The above figure shows an active high case. Since TM0n = CM0nx = 0000H match is detected during up counting by TM0n, the F/F is just set and does not get reset. Even when the setting value is 0000H, F/F is changed in the cycle during which transfer is performed from BFCMnx to CM0nx similarly to when the setting value is other than 0000H. Figure 9-19 shows the change timing from the 100% duty state. User's Manual U14492EJ5V0UD 257 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-19. Change Timing from 100% Duty State (PWM Mode 0) CM0n3 TM0n count value a a CM0n3 CM0n3 b CM0n3 b CM0nx match CM0nx match CM0nx match CM0nx match CM0nx match CM0nx match BFCM0nx a 0000H 0000H b c CM0nx Interrupt request a 0000H 0000H b INTTM0n INTTM0n INTTM0n INTTM0n INTCM0n3 INTCM0n3 INTCM0n3 INTCM0n3 Note F/F DTMnx Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) t t t t t t Note F/F is reset upon INTTM0n occurrence. Remarks 1. n = 0, 1 2. x = 0 to 2 3. t: Dead time = (DTRRn + 1)/fCLK (fCLK: Base clock) 4. The above figure shows an active high case. 258 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (3) PWM mode 1: Triangular wave modulation (right-left asymmetric waveform control) [Setting procedure] (a) Set PWM mode 1 (asymmetric triangular wave) with bits MOD01 and MOD00 of the TMC0n register. Also set the active level of pins TO0n0 to TO0n5 with the ALVTO bit of the TOMRn register (n = 0, 1). (b) Set the count clock of TM0n with bits PRM02 to PRM00 of the TMC0n register. The transfer operation from BFCMn3 to CM0n3 is set with bit BFTE3, and the transfer operation from BFCMn0 to BFCMn2 to CM0n0 to CM0n2 is set with bit BFTEN. (c) Set the initial values. (i) Specify the interrupt culling ratio with bits CUL02 to CUL00 of the TMC0n register. (ii) Set the half-cycle width of the PWM cycle in BFCMn3. * PWM cycle = BFCMn3 value x 2 x TM0n count clock (The TM0n count clock is set with the TMC0n register.) (iii) Set the dead-time width in DTRRn. * Dead-time width = (DTRRn + 1)/fCLK fCLK: Base clock (iv) Set the set timing of the F/F used in the PWM cycle in BFCMn0 to BFCMn2. (d) Clear (0) the TM0CEDn bit of the TMC0n register to enable dead-time timer operation. Set TM0CEDn = 1 when not using dead time. (e) Setting (1) the TM0CEn bit of the TMC0n register starts TM0n counting, and a 6-channel PWM signal is output from pins TO0n0 to TO0n5. Caution Remark Setting CM0n3 to 0000H is prohibited. The TM0CEn bit of the TMC0n register indicates transfer operation under the following conditions. * When TM0CEn bit of TMC0n register is 0 Transfer to the CM0n0 to CM0n2 registers is performed at the next base clock (fCLK) after writing to registers BFCMn0 to BFCMn2. * When TM0CEn bit of TMC0n register is 1 The value of the BFCMn0 to BFCMn2 registers is transferred to the CM0n0 to CM0n2 registers upon occurrence of the INTTM0n or INTCM0n3 interrupt. Transfer enable/disable at this time is controlled by bit BFTEN of the TMC0n register. User's Manual U14492EJ5V0UD 259 CHAPTER 9 TIMER/COUNTER FUNCTION [Operation] In PWM mode 1, TM0n performs up/down count operation. When TM0n = 0000H during down counting, an underflow interrupt (INTTM0n) is generated, and when TM0n = CM0n3 during up counting, a match interrupt (INTCM0n3) is generated (n = 0, 1). Switching from up counting to down counting is performed when TM0n and CM0n3 match (INTCM0n3), and switching from down counting to up counting is performed by INTTM0n. The PWM cycle in this mode is (BFCMn3 value x 2 x TM0n count clock). Concerning setting of data to BFCMn3, the next PWM cycle width is set to BFCMn3. The data of BFCMn3 is automatically transferred by hardware to CM0n3 upon generation of the INTTM0n interrupt. Furthermore, calculation is performed by software processing started by INTTM0n, and the data for the next cycle is set to BFCMn3. Data setting to CM0n0 to CM0n2, which control the PWM duty, is explained next. Setting of data to CM0n0 to CM0n2 consists in setting the duty output from BFCMn0 to BFCMn2. The values of BFCMn0 to BFCMn2 are automatically transferred by hardware to CM0n0 to CM0n2 upon generation of the INTTM0n and INTCM0n3 (TM0n and CM0n3 match interrupts). Furthermore, software processing is started up and calculation performed, and the set/reset timing of the F/F after a half cycle is set in BFCMn0 to BFCMn2. The PWM cycle and the PWM duty are set in the above procedure. The F/F set/reset conditions upon match of CM0n0 to CM0n2 are as follows. * Set: CM0n0 to CM0n2 match detection during TM0n up-count operation * Reset: CM0n0 to CM0n2 match detection during TM0n down-count operation The values of DTRRn are transferred to the corresponding dead-time timers (DTMn0 to DTMn2) in synchronization with the set/reset timing of the F/F, and down counting is started. DTMn0 to DTMn2 count down to 000H, and stop when they count down further to FFFH. DTMn0 to DTMn2 can automatically generate a width (dead time) at which the active levels of the positive phase (TO0n0, TO0n2, TO0n4) and negative phase (TO0n1, TO0n3, TO0n5) do not overlap. In this way, software processing is started by two interrupts (INTTM0n and INTCM0n3) that occur during every PWM cycle after initial setting has been performed, and by setting the PWM cycle and PWM duty to be used after a half cycle, it is possible to automatically output a PWM waveform to TO0n0 to TO0n5 pins taking into consideration the dead-time width (in case of interrupt culling ratio of 1/1). The difference between right-left symmetric waveform control and control in this mode (right-left asymmetric waveform control) is that BFCMn0 to BFCMn2 are transferred to CM0n0 to CM0n2, and that the interrupt signals that start software processing consist just of INTTM0n (generated once per PWM cycle) in the case of right-left symmetric waveform control, and INTTM0n and INTCM0n3 (generated twice per PWM cycle, or once per half cycle) in the case of right-left asymmetric waveform control. 260 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION [Output waveform width in respect to set value] * PWM cycle = BFCMn3 x 2 x TTM0n * Dead-time width TDnm = (DTRRn + 1)/fCLK * Active width of positive phase (TO0n0, TO0n2, TO0n4 pins) = { (CM0n3 - CM0nXup) + (CM0n3 - CM0nXdown) } x TTM0n - TDnm * Active width of negative phase (TO0n1, TO0n3, TO0n5 pins) = (CM0nXdown + CM0nXup) x TTM0n - TDnm fCLK: TTM0n: CM0nXup: Base clock TM0n count clock Set value of CM0n0 to CM0n2 while TM0n is counting up CM0nXdown: Set value of CM0n0 to CM0n2 while TM0n is counting down The pin level when the TO0n0 to TO0n5 pins are reset is the high impedance state. When the control mode is selected thereafter, the following levels are output until the TM0n is started. * TO0n0, TO0n2, TO0n4... When low active High level When high active Low level * TO0n1, TO0n3, TO0n5... When low active Low level When high active High level The active level is set with the ALVTO bit of the TOMRn register. The default is low active. Caution If a value such that the positive phase or negative phase active width is "0" or a negative value in the above formula, the TO0n0 to TO0n5 pins output a waveform fixed to the inactive level waveform with active width "0". Remark m = 0 to 2 n = 0, 1 User's Manual U14492EJ5V0UD 261 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-20. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave) CM0n3 (f) a TM0n count value 0000H CM0nx match CM0nx match CM0n3 (g) c b d CM0nx match CM0nx match BFCMnx a b c d e CM0nx a b c d e BFCMn3 f g h CM0n3 Interrupt request F/F f INTCM0n3 INTTM0n g INTCM0n3 h INTTM0n DTMnx Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) t t t t Remarks 1. The above figure shows the timing chart when BFTE3 and BFTEN of the TMC0n register are 1, and transfer from BFCMn3 to CM0n3, or from BFCMnx to CM0nx is enabled. Transfer is not performed when BFTE3 = 0 or BFTEN = 0. 2. n = 0, 1 3. x = 0 to 2 4. t: Dead time = (DTRRn + 1)/fCLK (fCLK: Base clock) 5. To not use dead time, set the TM0CEDn bit of the TMC0n register to 1. 6. The above figure shows an active high case. Figure 9-21 shows the overall operation image. 262 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-21. Overall Operation Image of PWM Mode 1 (Asymmetric Triangular Wave) CM0n3 CM0n2 CM0n2 CM0n1 CM0n0 CM0n0 CM0n2 CM0n1 CM0n3 CM0n2 CM0n1 CM0n0 TM0n count value 0000H TO0n0 output TO0n1 output TO0n2 output Without dead time TO0n3 output TO0n4 output TO0n5 output TO0n0 output TO0n1 output TO0n2 output With dead time TO0n3 output TO0n4 output TO0n5 output CM0n1 CM0n0 Remark n = 0, 1 User's Manual U14492EJ5V0UD 263 CHAPTER 9 TIMER/COUNTER FUNCTION (a) When BFCMnx CM0n3 is set in software processing started by INTCM0n3 Figure 9-22. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx CM0n3) CM0n3 a TM0n count value 0000H CM0nx match CM0nx match CM0n3 b BFCMnx a b c c c CM0nx Interrupt request F/F a INTCM0n3 b INTTM0n c INTCM0n3 c c INTTM0n DTMnx Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) t t Remarks 1. n = 0, 1 2. x = 0 to 2 3. c CM0n3 4. t: Dead time = (DTRRn + 1)/fCLK (fCLK: Base clock) 5. The above figure shows an active high case. When a value greater than CM0n3 is set to BFCMnx, the positive phase side (TO0n0, TO0n2, TO0n4 pins) outputs a low level, and the negative phase side (TO0n1, TO0n3, TO0n5 pins) continues to output a high level. This feature is effective for outputting a low-level or high-level width exceeding the PWM cycle in an application such as inverter control. Furthermore, if CM0nx = CM0n3 is set, matching of TM0n and CM0nx is detected during down counting by TM0n, so that the F/F remains reset as is, and does not get set. The above explanation applies to an active high case. In an active low case, the levels of positive and negative phases are merely inverted and other operations remain the same. 264 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (b) When BFCMnx > CM0n3 is set in software processing started by INTTM0n Figure 9-23. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx > CM0n3) CM0n3 a TM0n count value 0000H CM0nx match CM0n3 BFCMnx a b b b b CM0nx Interrupt request F/F a INTCM0n3 b INTTM0n b INTCM0n3 b b INTTM0n DTMnx Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) t Remarks 1. n = 0, 1 2. x = 0 to 2 3. b > CM0n3 4. t: Dead time = (DTRRn + 1)/fCLK (fCLK: Base clock) 5. The above figure shows an active high case. When a value greater than CM0n3 is set to BFCMnx, the positive phase side (TO0n0, TO0n2, TO0n4 pins) outputs a high level, and the negative phase side (TO0n1, TO0n3, TO0n5 pins) continues to output a low level. This feature is effective for outputting a low-level or high-level width exceeding the PWM cycle in an application such as inverter control. The above explanation applies to an active high case. In an active low case, the levels of positive and negative phases are merely inverted and other operations remain the same. Figure 9-24 shows the change timing from the 100% duty state. User's Manual U14492EJ5V0UD 265 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-24. Change Timing from 100% Duty State (PWM Mode 1) CM0n3 TM0n count value 0000H CM0nx match CM0n3 CM0n3 c CM0n3 d a CM0nx match CM0nx match BFCM0nx b b b b b c d e CM0nx Interrupt request a b b b b b c d e INTCM0n3 INTTM0n INTCM0n3 INTTM0n INTCM0n3 INTTM0n INTCM0n3 INTTM0n F/F Note DTMnx Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) t t t t Note F/F is reset upon INTTM0n occurrence. Remarks 1. n = 0, 1 2. x = 0 to 2 3. b > CM0n3 4. t: Dead time = (DTRRn + 1)/fCLK (fCLK: Base clock) 5. The above figure shows an active high case. 266 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (c) When BFCMnx = 0000H is set in software processing started by INTCM0n3 Figure 9-25. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx = 0000H) (1) CM0n3 a TM0n count value 0000H CM0nx match CM0nx match CM0n3 b BFCMnx a b 0000H 0000H 0000H CM0nx Interrupt request F/F a INTCM0n3 b INTTM0n 0000H INTCM0n3 0000H 0000H INTTM0n DTMnx Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) t t t Remarks 1. n = 0, 1 2. x = 0 to 2 3. t: Dead time = (DTRRn + 1)/fCLK (fCLK: Base clock) 4. The above figure shows an active high case. Since TM0n = CM0nx = 0000H match is detected during up counting by TM0n, the F/F is just set and does not get reset. Moreover, the F/F gets set upon match detection in the cycle when 0000H is transferred to CM0nx by INTTM0n interrupt. Figure 9-26 shows the change timing from the 100% duty state. User's Manual U14492EJ5V0UD 267 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-26. Change Timing from 100% Duty State (1) (PWM Mode 1) CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx match match match CM0n3 b CM0n3 CM0n3 c d a CM0nx match CM0nx match BFCM0nx b 0000H 0000H 0000H 0000H c d e CM0nx Interrupt request a b 0000H 0000H 0000H 0000H c d e INTCM0n3 INTTM0n INTCM0n3 INTTM0n INTCM0n3 INTTM0n INTCM0n3 INTTM0n F/F Note DTMnx Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) t t t t t t Note F/F is reset upon INTTM0n occurrence. Remarks 1. n = 0, 1 2. x = 0 to 2 3. t: Dead time = (DTRRn + 1)/fCLK (fCLK: Base clock) 4. The above figure shows an active high case. 268 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (d) When BFCMnx = 0000H is set in software processing started by INTTM0n Figure 9-27. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx = 0000H) (2) CM0n3 a TM0n count value 0000H CM0nx match CM0n3 BFCMnx a 0000H 0000H 0000H 0000H CM0nx Interrupt request F/F a INTCM0n3 0000H INTTM0n 0000H INTCM0n3 0000H 0000H INTTM0n DTMnx Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) t Remarks 1. n = 0, 1 2. x = 0 to 2 3. t: Dead time = (DTRRn + 1)/fCLK (fCLK: Base clock) 4. The above figure shows an active high case. Since TM0n = CM0nx = 0000H match is detected during up counting by TM0n, the F/F is just set and does not get reset. Therefore, the positive phase side (TO0n0, TO0n2, TO0n4 pins) outputs a high level, and the negative phase side (TO0n1, TO0n3, TO0n5 pins) continues to output a low level. The above explanation applies to an active high case. In an active low case, the levels of positive and negative phases are merely inverted and other operations remain the same. Figure 9-28 shows the change timing from the 100% duty state. User's Manual U14492EJ5V0UD 269 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-28. Change Timing from 100% Duty State (2) (PWM Mode 1) CM0n3 TM0n count value 0000H CM0nx match CM0n3 CM0n3 b CM0n3 c a CM0nx match CM0nx match BFCM0nx 0000H 0000H 0000H 0000H 0000H b c d CM0nx Interrupt request a 0000H 0000H 0000H 0000H 0000H b c d INTCM0n3 INTTM0n INTCM0n3 INTTM0n INTCM0n3 INTTM0n INTCM0n3 INTTM0n F/F Note DTMnx Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) t t t t Note F/F is reset upon INTTM0n occurrence. Remarks 1. n = 0, 1 2. x = 0 to 2 3. t: Dead time = (DTRRn + 1)/fCLK (fCLK: Base clock) 4. The above figure shows an active high case. 270 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (e) When BFCMnx = CM0n3 is set in software processing started by INTTM0n Figure 9-29. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx = CM0n3) CM0n3 a TM0 count value 0000H CM0nx CM0nx match match CM0n3 BFCMnx a b b b b CM0nx Interrupt request F/F a INTCM0n3 b INTTM0n b INTCM0n3 b INTTM0n b DTMnx Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) t t Remarks 1. n = 0, 1 2. x = 0 to 2 3. b = CM0n3 4. t: Dead time = (DTRRn + 1)/fCLK (fCLK: Base clock) 5. The above figure shows an active high case. Since TM0n and CM0nx match is detected during count down of TM0n when BFCMnx = CM0n3 has been set, the F/F remains reset as is and does not get set. Therefore, the positive phase side (TO0n0, TO0n2, TO0n4 pins) outputs a low level, and the negative phase side (TO0n1, TO0n3, TO0n5 pins) continues to output a high level. Moreover, the timing of matching with TM0n with CM0nx = CM0n3 is the cycle when transfer is performed from BFCMnx to CM0nx by INTCM0n3. The above explanation applies to an active high case. In an active low case, the levels of positive and negative phases are merely inverted and other operations remain the same. User's Manual U14492EJ5V0UD 271 CHAPTER 9 TIMER/COUNTER FUNCTION (4) PWM mode 2: Sawtooth wave modulation [Setting procedure] (a) Set PWM mode 2 (sawtooth wave) with bits MOD01 and MOD00 of the TMC0n register. Also set the active level of pins TO0n0 to TO0n5 with the ALVTO bit of the TOMRn register. (b) Set the count clock of TM0n with bits PRM02 to PRM00 of the TMC0n register. The transfer operation from BFCMn3 to CM0n3 is set with bit BFTE3, and the transfer operation from BFCMn0 to BFCMn2 to CM0n0 to CM0n2 is set with bit BFTEN. (c) Set the initial values. (i) Specify the interrupt culling ratio with bits CUL02 to CUL00 of the TMC0n register. (ii) Set the cycle width of the PWM cycle in BFCMn3. * PWM cycle = (BFCMn3 value + 1) x TM0n count clock (The TM0n count clock is set with the TMC0n register.) (iii) Set the dead-time width in DTRRn. * Dead-time width = (DTRRn + 1)/fCLK fCLK: Base clock (iv) Set the set/reset timing of the F/F used in the PWM cycle in BFCM0n0 to BFCM0n2. (d) Clear (0) the TM0CEDn bit of the TMC0n register to enable dead-time timer operation. Set TM0CEDn = 1 when not using dead time. (e) Setting (1) the TM0CEn bit of the TMC0n register starts TM0n counting, and a 6-channel PWM signal is output from pins TO0n0 to TO0n5. Caution Setting CM0n3 to 0000H is prohibited. 272 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION [Operation] In PWM mode 2, TM0n performs up-count operation, and when it matches the value of CM0n3, match interrupt INTCM0n3 is generated and TM0n is cleared (n = 0, 1). The PWM cycle in this mode is ((BFCMn3 value + 1) x TM0n count clock). Concerning setting of data to CM0n3, the next PWM cycle width is set to BFCMn3. The data of BFCMn3 is automatically transferred by hardware to CM0n3 upon generation of the INTCM0n3 interrupt. Furthermore, calculation is performed by software processing started by INTCM0n3, and the data for the next cycle is set to BFCMn3. Data setting to CM0n0 to CM0n2, which control the PWM duty, is explained next. Setting of data to CM0n0 to CM0n2 consists in setting the duty output from BFCMn0 to BFCMn2. The values of BFCMn0 to BFCMn2 are automatically transferred by hardware to CM0n0 to CM0n2 upon generation of the INTCM0n3 interrupt. Furthermore, software processing is started up and calculation performed, and reset timing of the F/F for the next cycle is set to BFCMn0 to BFCMn2. The PWM cycle and the PWM duty are set in the above procedure. The F/F set/reset conditions upon match of CM0n0 to CM0n2 are as follows. * Set: TM0n and CM0n3 match detection and rising edge of TM0CEn bit of TMC0n register * Reset: TM0n and CM0n0 to CM0n2 match detection The values of DTRRn are transferred to the corresponding dead-time timers (DTMn0 to DTMn2) in synchronization with the set/reset timing of the F/F, and down counting is started. DTMn0 to DTMn2 count down to 000H, and stop when they count down further to FFFH. DTMn0 to DTMn2 can automatically generate a width (dead time) at which the active levels of the positive phase (TO0n0, TO0n2, TO0n4) and negative phase (TO0n1, TO0n3, TO0n5) do not overlap. In this way, software processing is started by an interrupt (INTCM0n3) that occurs once during every PWM cycle after initial setting has been performed, and by setting the PWM cycle and PWM duty to be used in the next cycle, it is possible to automatically output a PWM waveform to TO0n0 to TO0n5 pins taking into consideration the dead-time width (in case of interrupt culling ratio of 1/1). User's Manual U14492EJ5V0UD 273 CHAPTER 9 TIMER/COUNTER FUNCTION [Output waveform width in respect to set value] * PWM cycle = (BFCMn3 + 1) x TTM0n * Dead-time width TDnm = (DTRRn + 1)/fCLK * Active width of positive phase (TO0n0, TO0n2, TO0n4 pins) = (CM0nX + 1) x TTM0n - TDnm * Active width of negative phase (TO0n1, TO0n3, TO0n5 pins) = (CM0n3 - CM0nX) x TTM0n - TDnm fCLK: TTM0n: CM0nX: Base clock TM0n count clock Set value of CM0n0 to CM0n2 The pin level when the TO0n0 to TO0n5 pins are reset is the high impedance state. When the control mode is selected thereafter, the following levels are output until the TM0n is started. * TO0n0, TO0n2, TO0n4... When low active High level When high active Low level * TO0n1, TO0n3, TO0n5... When low active Low level When high active High level The active level is set with the ALVTO bit of the TOMRn register. The default is low active. Caution If a value such that the positive phase or negative phase active width is "0" or a negative value in the above formula, the TO0n0 to TO0n5 pins output a waveform fixed to the inactive level waveform with active width "0". Remark m = 0 to 2 n = 0, 1 274 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-30. Operation Timing in PWM Mode 2 (Sawtooth Wave) CM0n3 (d) b TM0n count value 0000H CM0nx match CM0nx match CM0n3 (e) a BFCMnx b c CM0nx a b c BFCMn3 e f CM0n3 Interrupt request F/F d INTCM0n3 e f INTCM0n3 Set by rising edge of TM0CEn bit DTMnx Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) t t t t t Remarks 1. The above figure shows the timing chart when BFTE3 and BFTEN of the TMC0n register are 1, and transfer from BFCMn3 to CM0n3, or from BFCMnx to CM0nx is enabled. Transfer is not performed when BFTE3 = 0 or BFTEN = 0. 2. n = 0, 1 3. x = 0 to 2 4. t: Dead time = (DTRRn + 1)/fCLK (fCLK: Base clock) 5. The above figure shows an active high case. Figure 9-31 shows the overall operation image. User's Manual U14492EJ5V0UD 275 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-31. Overall Operation Image of PWM Mode 2 (Sawtooth Wave) CM0n3 CM0n2 CM0n2 CM0n1 CM0n0 CM0n3 TM0n count value 0000H TO0n0 output TO0n1 output TO0n2 output Without dead time TO0n3 output TO0n4 output TO0n5 output TO0n0 output TO0n1 output TO0n2 output With dead time TO0n3 output TO0n4 output TO0n5 output CM0n1 CM0n0 Remarks 1. n = 0, 1 2. The above figure shows an active low case. Since the F/F is set at the rising edge of the TM0CEn bit of the TMC0n register in the first cycle, the PWM signal can be output. 276 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (a) When BFCMnx > CM0n3 is set Figure 9-32. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx > CM0n3) CM0n3 a CM0n3 CM0n3 TM0n count value 0000H CM0nx match BFCMnx b b b CM0nx Interrupt request F/F a INTCM0n3 b INTCM0n3 b INTCM0n3 Set by rising edge of TM0CEn bit DTMnx Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) t t t Remarks 1. n = 0, 1 2. x = 0 to 2 3. b > CM0n3 4. t: Dead time = (DTRRn + 1)/fCLK (fCLK: Base clock) 5. The above figure shows an active high case. When a value greater than CM0n3 is set to BFCMnx, the positive phase side (TO0n0, TO0n2, TO0n4 pins) outputs a high level, and the negative phase side (TO0n1, TO0n3, TO0n5 pins) continues to output a low level. Since TM0n and CM0nx match does not occur, the F/F does not get reset. This feature is effective for outputting a low-level or high-level width exceeding the PWM cycle in an application such as inverter control. The above explanation applies to an active high case. In an active low case, the levels of positive and negative phases are merely inverted and other operations remain the same. Figure 9-33 shows the change timing from the 100% duty state. User's Manual U14492EJ5V0UD 277 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-33. Change Timing from 100% Duty State (PWM Mode 2) CM0n3 TM0n count value 0000H CM0nx match CM0n3 CM0n3 c CM0n3 a CM0nx match BFCM0nx a b b c d CM0nx Interrupt request F/F a INTCM0n3 b INTCM0n3 b INTCM0n3 Note c INTCM0n3 DTMnx Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) t t t t t Note F/F is reset upon occurrence of match with CM0nx. Remarks 1. n = 0, 1 2. x = 0 to 2 3. b > CM0n3 4. t: Dead time = (DTRRn + 1)/fCLK (fCLK: Base clock) 5. The above figure shows an active high case. The timing at which the F/F is reset is upon occurrence of match with CM0nx as normal. 278 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (b) When BFCMnx = CM0n3 is set Figure 9-34. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = CM0n3) CM0n3 a CM0n3 CM0n3 TM0n count value 0000H CM0nx match BFCMnx a b b b CM0nx Interrupt request F/F a INTCM0n3 b INTCM0n3 b INTCM0n3 Set by rising edge of TM0CEn bit DTMnx Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) t t t t Remarks 1. n = 0, 1 2. x = 0 to 2 3. b = CM0n3 4. t: Dead time = (DTRRn + 1)/fCLK (fCLK: Base clock) 5. The above figure shows an active high case. If match signal INTCM0n3 for TM0n and CM0n3 and the match signal for TM0n and CM0nx conflict, reset of the F/F takes precedence, so that the F/F does not get set following match of CM0nx (= CM0n3) with TM0n. User's Manual U14492EJ5V0UD 279 CHAPTER 9 TIMER/COUNTER FUNCTION (c) When BFCMnx = 0000H is set Figure 9-35. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = 0000H) CM0n3 CM0n3 CM0n3 TM0n count value 0000H a CM0nx match CM0nx match CM0nx match CM0nx match BFCMnx a b b b CM0nx Interrupt request F/F Note DTMnx a INTCM0n3 b INTCM0n3 b INTCM0n3 W W W Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) t t Note Set by rising edge of TM0CEn bit Remarks 1. n = 0, 1 2. x = 0 to 2 3. t: Dead time = (DTRRn + 1)/fCLK (fCLK: Base clock) 4. The above figure shows an active high case. 5. W: Width between CM0n3 match and CM0nx match (timer count clock) If CM0nx = 0000H has been set, the output waveform resulting from the TM0n count clock rate and the DTRRn set value differ. 280 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (d) When BFCMnx = 0000H is set while DTMnx = 000H or TM0CEDn bit = 1 A pulse equivalent to one count clock of the timer is output. Figure 9-36. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = 0000H While DTMnx = 000H or TM0CEDn Bit = 1) CM0n3 CM0n3 CM0n3 TM0n count value 0000H a CM0nx match BFCMnx a b CM0nx match b CM0nx match b CM0nx match CM0nx Interrupt request F/F Note DTMnx L a INTCM0n3 b INTCM0n3 b INTCM0n3 W W W Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) Note Set at the rising edge of the TM0CEn bit. Remarks 1. n = 0, 1 2. x = 0 to 2 3. The above figure shows an active-high case. 4. W: Width of a pulse equivalent to one count clock of the timer from CM0n3 match User's Manual U14492EJ5V0UD 281 CHAPTER 9 TIMER/COUNTER FUNCTION (e) When BFCMnx = CM0n3 = a is set Figure 9-37. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = CM0n3 = a) (When DTRRn = 0000H, TM0CEDn Bit of TMC0n Register = 1, ALVTO Bit of TOMRn Register = 1 (PWM Driving, Active Level = High) Are Set) CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx match BFCMnx a a CM0nx match CM0nx match CM0nx Interrupt request F/F a INTCM0n3 a INTCM0n3 a INTCM0n3 a DTMnx L Positive phase (TO0n0, TO0n2, TO0n4) Negative phase (TO0n1, TO0n3, TO0n5) Remarks 1. n = 0, 1 2. x = 0 to 2 3. The above figure shows an active-high case. 4. For the timing including the dead time, refer to Figure 9-35. 282 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-38. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = CM0n3 = a) (When DTRRn = 0000H, TM0CEDn Bit of TMC0n Register = 1, ALVTO Bit of TOMRn Register = 0 (PWM Driving, Active Level = Low) Are Set) CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx match BFCMnx a a CM0nx match CM0nx match CM0nx Interrupt request F/F a INTCM0n3 a INTCM0n3 a INTCM0n3 a DTMnx L Positive phase (TO0n0, TO0n2, TO0n4) H Negative phase (TO0n1, TO0n3, TO0n5) L Remarks 1. n = 0, 1 2. x = 0 to 2 3. The above figure shows an active-low case. 4. For the timing including the dead time, refer to Figure 9-35. User's Manual U14492EJ5V0UD 283 CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.6 Operation timing (1) TM0CEn bit write and TM0n timer operation timing Figure 9-39 shows the timing from write of the TM0CEn bit of the TMC0n register until the TM0n timer starts operating. Figure 9-39. TM0CEn Bit Write and TM0n Timer Operation Timing fCLK TM0CEn bit write timing Register write timing TM0n 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H Caution Remark The operation of TM0n starts 2fCLK after the register write timing. fCLK: Base clock 284 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (2) Interrupt generation timing The interrupt generation timing with the count clock setting (PRM02 to PRM00 bits of the TMC0n register) to TM0n in the various modes is described below. Figure 9-40. Interrupt Generation Timing in PWM Mode 0 (Symmetric Triangular Wave), PWM Mode 1 (Asymmetric Triangular Wave) (a) When count clock = fCLK CM0n3 0002H TM0n 0001H 0002H 0001H 0000H 0001H 0002H 0001H 0000H 0001H 0002H 0001H 0000H 0001H 0002H 0001H 0000H 0001H 0002H 0001H 0000H fCLK INTCM0n3 INTTM0n (b) When count clock = fCLK/4 CM0n3 0002H TM0n 0000H 0001H 0002H 0001H 0000H fCLK INTCM0n3 INTTM0n Cautions 1. INTCM0n3 is generated at the next fCLK after detection of TM0n and CM0n3 match. 2. INTTM0n is generated at the next fCLK after detection of TM0n and 0000H match. 3. INTTM0n is generated at the next fCLK after detection of TM0n and 0000H match, even if the count clock is 1/2, 1/8, 1/16, or 1/32. Remarks 1. n = 0, 1 2. fCLK: Base clock User's Manual U14492EJ5V0UD 285 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-41. Interrupt Generation Timing in PWM Mode 2 (Sawtooth Wave) (a) When count clock = fCLK CM0n3 0002H TM0n 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H fCLK INTCM0n3 (b) When count clock = fCLK/4 CM0n3 0002H TM0n 0000H 0001H 0002H 0000H 0001H fCLK INTCM0n3 Cautions 1. INTCM0n3 is generated at the next fCLK after detection of TM0n and CM0n3 match. count clock is 1/2, 1/8, 1/16, or 1/32. 2. INTCM0n3 is generated at the next fCLK after detection of TM0n and CM0n3 match even if the Remarks 1. n = 0, 1 2. fCLK: Base clock 286 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (3) Relationship between interrupt generation and STINTn bit of TMC0n register The interrupt generation timing for the setting of the STINTn bit of the TMC0n register and the interrupt culling ratio setting (bits CUL02 to CUL00) in the various modes is described below. If, to realize the INTTM0n and INTCM0n3 interrupt culling function for TM0n, bits CUL02 to CUL00 of the TMC0n register are set for a culling ratio other than 1/1, and count operation is started, the interrupt output order differs according to the setting of the STINTn bit when counting starts. Figure 9-42. Interrupt Generation Timing in PWM Mode 0 (Symmetric Triangular Wave), PWM Mode 1 (Asymmetric Triangular Wave): In Case of Interrupt Culling Ratio of 1/1 (a) When STINTn bit = 0 TM0CEn bit CM0n3 0004H TM0n 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H fCLK INTCM0n3 INTTM0n (b) When STINTn bit = 1 TM0CEn bit CM0n3 0004H TM0n 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H fCLK INTCM0n3 INTTM0n Remarks 1. n = 0, 1 2. fCLK: Base clock User's Manual U14492EJ5V0UD 287 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-43. Interrupt Generation Timing in PWM Mode 0 (Symmetric Triangular Wave), PWM Mode 1 (Asymmetric Triangular Wave): In Case of Interrupt Culling Ratio of 1/2 (a) When STINTn bit = 0 TM0CEn bit CM0n3 0004H TM0n 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H fCLK INTCM0n3 INTTM0n (b) When STINTn bit = 1 TM0CEn bit CM0n3 0004H TM0n 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H fCLK INTCM0n3 INTTM0n Remarks 1. n = 0, 1 2. fCLK: Base clock 288 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-44. Interrupt Generation Timing in PWM Mode 2 (Sawtooth Wave): In Case of Interrupt Culling Ratio of 1/1 (a) When STINTn bit = 0 TM0CEn bit CM0n3 0004H TM0n 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H fCLK INTCM0n3 (b) When STINTn bit = 1 TM0CEn bit CM0n3 0004H TM0n 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H fCLK INTCM0n3 Remarks 1. n = 0, 1 2. fCLK: Base clock User's Manual U14492EJ5V0UD 289 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-45. Interrupt Generation Timing in PWM Mode 2 (Sawtooth Wave): In Case of Interrupt Culling Ratio of 1/2 (a) When STINTn bit = 0 TM0CEn bit CM0n3 0004H TM0n 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H fCLK INTCM0n3 (b) When STINTn bit = 1 TM0CEn bit CM0n3 0004H TM0n 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H fCLK INTCM0n3 Remarks 1. n = 0, 1 2. fCLK: Base clock 290 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (4) TO0n0 to TO0n5 output timing Figure 9-46. TO0n0 to TO0n5 Output Timing in PWM Mode 0 (Symmetric Triangular Wave), PWM Mode 1 (Asymmetric Triangular Wave) TM0CEn bit CM0n3 0008H CM0nx 0003H TM0n 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0007H 0006H 0005H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H DTRRn 0002H DTMnx FFFFH 0002H 0001H 0000H FFFFH 0002H 0001H 0000H FFFFH fCLK Match signal F/F TO0n0, TO0n2, TO0n4 TO0n1, TO0n3, TO0n5 Remarks 1. The above figure shows the timing until the compare register and the TM0n timer match and the TO0n0 to TO0n5 outputs change. 2. x = 0 to 2 3. n = 0, 1 4. fCLK: Base clock User's Manual U14492EJ5V0UD 291 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-47. TO0n0 to TO0n5 Output Timing in PWM Mode 2 (Sawtooth Wave) TM0CEn bit CM0n3 000AH CM0nx 0005H TM0n 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 0000H 0001H 0002H 0003H 0004H 0005H 0006H DTRRn 0002H DTMnx FFFFH 0002H 0001H 0000H FFFFH 0002H 0001H 0000H FFFFH 0002H 0001H 0000H FFFFH fCLK Match signal F/F TO0n0, TO0n2, TO0n4 TO0n1, TO0n3, TO0n5 Remarks 1. The above figure shows the timing until the compare register and the TM0n timer match and the TO0n0 to TO0n5 outputs change. 2. x = 0 to 2 3. n = 0, 1 4. fCLK: Base clock 292 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.2 Timer 1 9.2.1 Features (timer 1) Timers 10, 11 (TM10, TM11) are 16-bit up/down counters that perform the following operations. * General-purpose timer mode (See 9.2.5 (1) Operation in general-purpose timer mode.) Free-running timer PWM output * Up/down counter mode (See 9.2.5 (2) Operation in UDC mode.) UDC mode A (mode 1, mode 2, mode 3, mode 4) UDC mode B (mode 1, mode 2, mode 3, mode 4) 9.2.2 Function overview (timer 1) * * * * 16-bit 2-phase encoder input up/down counter & general-purpose timer (TM1n): 2 channels Compare register: 2 x 2 channels Capture/compare register: 2 x 2 channels Interrupt request source * Capture/compare match interrupt: 2 types x 2 channels * Compare match interrupt request: 2 types x 2 channels * Capture request signal: 2 types x 2 channels * The TM1n value can be latched using the valid edge of the INTP1n0, INTP1n1 pins corresponding to the capture/compare register as the capture trigger. * Count clocks selectable through division by prescaler (set the frequency of the count clock to 8 MHz or less) * Base clock (fCLK): 2 types (set fCLK to 16 MHz or less) fXX/2 and fXX/4 can be selected * Prescaler division ratio The following division ratios can be selected according to the base clock (fCLK). Division Ratio Base Clock (fCLK) fXX/2 Selected fXX/4 Selected fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 1/2 1/4 1/8 1/16 1/32 1/64 1/128 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 User's Manual U14492EJ5V0UD 293 CHAPTER 9 TIMER/COUNTER FUNCTION * PWM output function In the general-purpose timer mode, 16-bit resolution PWM output can be output from the TO1n pin. * Timer clear The following timer clear operations are performed according to the mode that is used. (a) General-purpose timer mode: Timer clear operation is possible upon occurrence of match with CM1n0 set value. (b) Up/down counter mode: The timer clear operation can be selected from among the following four conditions. (i) Timer clear performed upon occurrence of match with CM1n0 set value during TM1n up-count operation, and timer clear performed upon occurrence of match with CM1n1 set value during TM1n down-count operation. (ii) Timer clear performed only by external input. (iii) Timer clear performed upon occurrence of match between TM1n count value and CM1n0 set value. (iv) Timer clear performed upon occurrence of external input and match between TM1n count value and CM1n0 set value. * External pulse output (TO1n): 1 x 2 channels Remark fXX: Internal system clock n = 0, 1 294 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.2.3 Basic configuration The basic configuration is shown below. Table 9-4. Timer 1 Configuration List Timer Count Clock Note 1 Timer 1 fXX/4, fXX/8, fXX/16, fXX/32, fXX/64, fXX/128, fXX/256 Note 2 fXX/8, fXX/16, fXX/32, fXX/64, fXX/128, fXX/256, fXX/512 CM101 CC100 CC101 Read/write Read/write Read/write INTCM101 INTCC100 INTCC101 - INTCM110 INTCM111 INTCC110 INTCC111 TM10 CM100 Read/write Read/write Register Read/Write Generated Interrupt Signal - INTCM100 Capture Trigger - - - INTP100 INTP100 or INTP101 - - - INTP110 INTP110 or INTP111 TM11 CM110 CM111 CC110 CC111 Read/write Read/write Read/write Read/write Read/write Notes 1. 2. Remark When fXX/2 is selected as the base clock to TM1n. When fXX/4 is selected as the base clock to TM1n. fXX: Internal system clock Figure 9-48 shows the block diagram of timer 1. User's Manual U14492EJ5V0UD 295 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-48. Block Diagram of Timer 1 Internal bus Edge detector Selector CC1n0 CC1n1 TM1UBDn CMD Selector INTP1n0/ INTCC1n0 INTP1n1Note/ INTCC1n1 Edge detector Edge detector Edge detector Clock control fCLK Edge detector 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128 SELCLK Selector Clear TM10 clear controller TCLR1n/ INTP1n1 TCUD1n/ INTP1n0 fXX/2 fXX/4 TIUD1n TCLR TM1OVFn TM1UDFn TM1n Output control TO1n INTCM1n0 INTCM1n1 CM1n0 ENMD MSEL ALVT10 CM1n1 RLEN CLR1, CLR0 Internal bus Note The INTP1n1 interrupt is the signal of the capture trigger signal from the INTP1n1 pin or the capture trigger signal from the INTP1n0 pin, selected by the CSLn bit of the CSL1n register. Remarks 1. n = 0, 1 2. fXX: Internal system clock 3. fCLK: Base clock (16 MHz (MAX.)) 296 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (1) Timers 10, 11 (TM10, TM11) TM1n is a general-purpose timer (in general-purpose mode) and 2-phase encoder input up/down counter (in UDC mode). This timer counts up in the general-purpose timer mode and counts up/down in the UDC mode. TM1n can be read/written in 16-bit units. Cautions 1. Write to TM1n is enabled only when the TM1CEn bit of the TMC1n register is "0" (count operation disabled). 2. Continuous reading of TM1n is prohibited. If TM1n is continuously read, the second read value may differ from the actual value. If TM1n must be read twice, be sure to read another register between the first and the second read operation. Correct usage example TM10 read TM11 read TM10 read TM11 read Incorrect usage example TM10 read TM10 read TM11 read TM11 read 3. Writing the same value to the TM1n, CC1n0, and CC1n1 registers, and the STATUSn register is prohibited. Writing the same value to the CCRn, TUMn, TMC1n, SESA1n, and PRM1n registers, and CM1n0 and CM1n1 registers is permitted (writing the same value is guaranteed even during a count operation). 15 TM10 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF5E0H Initial value 0000H 15 TM11 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF600H Initial value 0000H TM1n start and stop is controlled by the TM1CEn bit of timer control register 1n (TMC1n). The TM1n operation consists of the following two modes. (a) General-purpose timer mode In the general-purpose timer mode, TM1n operates as a 16-bit interval timer, free-running timer, or for PWM output. Counting is performed based on the clock selected by software. Division by the prescaler can be selected for the count clock from among fCLK/2, fCLK/4, fCLK/8, fCLK/16, fCLK/32, fCLK/64, or fCLK/128 with bits PRM12 to PRM10 of prescaler mode register 1n (PRM1n). (fCLK: base clock, refer to 9.2.4 (1) Timer 1/timer 2 clock selection register (PRM02)). User's Manual U14492EJ5V0UD 297 CHAPTER 9 TIMER/COUNTER FUNCTION (b) Up/down counter mode (UDC mode) In the UDC mode, TM1n functions as a 16-bit up/down counter, counting based on the TCUD1n and TIUD1n input signals. This mode is divided into the UDC mode A and UDC mode B, depending on the condition of clearing TM1n. The conditions for clearing the TM1n are classified as follows depending on the operation mode. Table 9-5. Timer 1 (TM1n) Clear Conditions Operation Mode TUMn Register CMD Bit General-purpose timer mode UDC mode A 0 MSEL Bit 0 TMC1n Register ENMD Bit 0 1 1 0 x x x x UDC mode B 1 1 x CLR1 Bit x x 0 0 CLR0 Bit x x 0 1 Clearing not performed (free-running timer) Cleared upon match with CM1n0 set value Cleared only by TCLR1n input Cleared upon match with CM1n0 set value during upcount operation 1 0 Cleared by TCLR1n input or upon match with CM1n0 set value during up-count operation 1 x 1 x Clearing not performed Cleared upon match with CM1n0 set value during upcount operation or upon match with CM1n1 set value during down-count operation Settings other than the above Setting prohibited TM1n Clear Remarks 1. n = 0, 1 2. x: Indicates that the set value of that bit is ignored. 298 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.2.4 Control registers (1) Timer 1/timer 2 clock selection register (PRM02) The PRM02 register is used to select the base clock (fCLK) of timer 1 (TM1n) and timer 2 (TM2n). This register can be read/written in 8-bit or 1-bit units. Caution Always set this register before using the timers 1 and 2. 7 PRM02 0 6 0 5 0 4 0 3 0 2 0 1 0 0 PRM2 Address FFFFF5D8H Initial value 00H Bit position 0 Bit name PRM2 Function Specifies the base clock (fCLK) of timer 1 (TM1n) and timer 2 (TM2n) 0: fCLK = fXX/4 1: fCLK = fXX/2 Note . Note Set the VSWC register to 15H when the PRM2 bit of the timer 1/timer 2 clock selection register (PRM02) = 0B (fCLK = fXX/4), and set the VSWC register to 12H when the PRM2 bit = 1B (fCLK = fXX/2). Remark fXX: Internal system clock n = 0, 1 User's Manual U14492EJ5V0UD 299 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Timer unit mode registers 0, 1 (TUM0, TUM1) The TUMn register is an 8-bit register used to specify the TM1n operation mode or to control the operation of the PWM output pin. TUMn can be read/written in 8-bit or 1-bit units. Cautions 1. Changing the value of the TUMn register during TM1n operation (TM1CEn bit of TMCn register = 1) is prohibited. 2. When the CMD bit = 0 (general-purpose timer mode), setting MSEL bit = 1 (UDC mode B) is prohibited. 7 TUM0 CMD 6 0 5 0 4 0 3 TOE10 2 ALVT10 1 0 0 MSEL Address FFFFF5EBH Initial value 00H 7 TUM1 CMD 6 0 5 0 4 0 3 TOE10 2 ALVT10 1 0 0 MSEL Address FFFFF60BH Initial value 00H Bit position 7 Bit name CMD Specifies TM1n operation mode. Function 0: General-purpose timer mode (up count) 1: UDC mode (up/down count) 3 TOE10 Specifies timer output (TO1n) enable. 0: Timer output disabled 1: Timer output enabled Caution When CMD bit = 1 (UDC mode), timer output is not performed regardless of the setting of the TOE10 bit. At this time, timer output consists of the negative phase level of the level set by the ALVT10 bit. 2 ALVT10 Specifies active level of timer output (TO1n). 0: Active level is high level 1: Active level is low level Caution When CMD bit = 1 (UDC mode), timer output is not performed regardless of the setting of the TOE10 bit. At this time, timer output consists of the negative phase level of the level set by the ALVT10 bit. 0 MSEL Specifies operation in UDC mode (up/down count). 0: UDC mode A TM1n can be cleared by setting the CLR1, CLR0 bits of the TMC1n register. 1: UDC mode B TM1n is cleared in the following cases. * Upon match with CM1n0 during TM1n up-count operation * Upon match with CM1n1 during TM1n down-count operation When UDC mode B is set, the ENMD, CLR1, and CLR0 bits of the TMC1n register becomes invalid. Remark n = 0, 1 300 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (3) Timer control registers 10, 11 (TMC10, TMC11) The TMC1n register is used to enable/disable TM1n operation and to set transfer and timer clear operations. TMC1n can be read/written in 8-bit or 1-bit units. Caution Changing the value of bits of the TMC1n register other than the TM1CEn bit during TM1n operation (TM1CEn bit = 1) is prohibited. (1/2) 7 TMC10 0 <6> TM1CE0 5 0 4 0 3 RLEN 2 ENMD 1 CLR1 0 CLR0 Address FFFFF5ECH Initial value 00H 7 TMC11 0 <6> TM1CE1 5 0 4 0 3 RLEN 2 ENMD 1 CLR1 0 CLR0 Address FFFFF60CH Initial value 00H Bit position 6 Bit name TM1CEn Enables/disables TM1n operation. 0: Disable TM1n count operation 1: Enable TM1n count operation Function 3 RLEN Enables/disables transfer from CM1n0 to TM1n. 0: Disable transfer 1: Enable transfer Cautions 1. When RLEN = 1, the value set to CM1n0 is transferred to TM1n upon occurrence of TM1n underflow. 2. The RLEN bit is valid only in UDC mode A (CMD bit of TUMn register = 1 and MSEL bit = 0). In the general-purpose timer mode (CMD bit = 0) and UDC mode B (CMD bit = 1, MSEL bit = 1), a transfer operation is not executed even if the RLEN bit is set to 1. 2 ENMD Enables/disables clearing of TM1n in general-purpose timer mode (CMD bit of TUMn register = 0). 0: Disable clear (free-running mode) Clearing is not performed even when TM1n and CM1n0 values match. 1: Enable clear Clearing is performed when TM1n and CM1n0 values match. Caution The ENMD bit setting becomes invalid in UDC mode (CMD bit of TUMn register = 1). Remark n = 0, 1 User's Manual U14492EJ5V0UD 301 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position 1, 0 Bit name CLR1, CLR0 Function Controls TM1n clear operation in UDC mode A. CLR1 0 0 CLR0 0 1 Specify TM1n clear source Clear only by external input (TCLR1n) Clear upon match of TM1n count value and CM1n0 set value 1 0 Clear by TCLR1n input or upon match of TM1n count value and CM1n0 set value 1 1 Don't clear Cautions 1. Clearing by match of the TM1n count value and CM1n0 set value is valid only during TM1n up-count operation (TM1n is not cleared during TM1n down-count operation). 2. The CLR1 and CLR0 bit settings are invalid in general-purpose timer mode (CMD bit of TUMn register = 0). 3. The CLR1 and CLR0 bit settings are invalid in UDC mode B (MSEL bit of TUMn register = 1). 4. When clearing by TCLR1n has been enabled with bits CLR1 and CLR0, clearing is performed whether the value of the TM1CEn bit is 1 or 0. Remark n = 0, 1 302 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (4) Capture/compare control registers 0, 1 (CCR0, CCR1) The CCRn register specifies the operation mode of the capture/compare registers (CC1n0, CC1n1). CCRn can be read/written in 8-bit or 1-bit units. Caution Overwriting the CCRn register during TM1n operation (TM1CEn bit = 1) is prohibited. 7 CCR0 0 6 0 5 0 4 0 3 0 2 0 1 CMS1 0 CMS0 Address FFFFF5EAH Initial value 00H 7 CCR1 0 6 0 5 0 4 0 3 0 2 0 1 CMS1 0 CMS0 Address FFFFF60AH Initial value 00H Bit position 1 Bit name CMS1 Specifies operation mode of CC1n1. 0: Capture register 1: Compare register Function 0 CMS0 Specifies operation mode of CC1n0. 0: Capture register 1: Compare register Remark n = 0, 1 User's Manual U14492EJ5V0UD 303 CHAPTER 9 TIMER/COUNTER FUNCTION (5) Signal edge selection registers 10, 11 (SESA10, SESA11) The SESA1n register is used to specify the valid edge of external interrupt requests from external pins (INTP100, INTP101, INTP110, INTP111, TIUD10, TIUD11, TCUD10, TCUD11, TCLR10, TCLR11). The correspondences between each register and the external interrupt requests it controls are as follows. * SESA10: TIUD10, TCUD10, TCLR10, INTP100, INTP101 * SESA11: TIUD11, TCUD11, TCLR11, INTP110, INTP111 The valid edge (rising edge, falling edge, or both edges) can be specified independently for each pin. SESA1n can be read/written in 8-bit or 1-bit units. Cautions 1. Changing the values of the SESA1n register bits during TM1n operation (TM1CEn bit = 1) is prohibited. 2. Be sure to set (to 1) the TM1CEn bit of timer control registers 10, 11 (TMC10, TMC11) even when timer 1 is not used and the TCUD10/INTP100, TCLR10/INTP101, TCUD11/INTP110, and TCLR11/INTP111 pins are used as INTP100, INTP101, INTP110, and INTP111. (1/2) 7 6 5 4 3 2 1 0 Address FFFFF5EDH Initial value 00H SESA10 TESUD01 TESUD00 CESUD01 CESUD00 IES1011 IES1010 IES1001 IES1000 TIUD10, TCUD10 7 6 5 TCLR10 4 3 INTP101 2 1 INTP100 0 Address FFFFF60DH Initial value 00H SESA11 TESUD11 TESUD10 CESUD11 CESUD10 IES1111 IES1110 IES1101 IES1100 TIUD11, TCUD11 TCLR11 INTP111 INTP110 Bit position 7, 6 Bit name TESUDn1, TESUDn0 Function Specifies valid edge of pins TIUD10, TIUD11, TCUD10, TCUD11. TESUDn1 0 0 1 1 TESUDn0 0 1 0 1 Falling edge Rising edge Setting prohibited Valid edge Both rising and falling edges Cautions 1. The set values of the TESUDn1 and TESUDn0 bits are only valid in UDC mode A and UDC mode B. 2. If mode 4 is specified as the operation mode of TM1n (specified with PRM12 to PRM10 bits of PRM1n register), the valid edge specifications for pins TIUD1n and TCUD1n (bits TESUDn1 and TESUDn0) are not valid. Remark n = 0, 1 304 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position 5, 4 Bit name CESUDn1, CESUDn0 CESUDn1 0 0 1 1 CESUDn0 0 1 0 1 Falling edge Rising edge Low level High level Valid edge Function Specifies valid edge of pins TCLR10, TCLR11. The set values of bits CESUDn1 and CESUDn0 and the TM1n operation are related as follows. 00: TM1n cleared after detection of falling edge of TCLR1n 01: TM1n cleared after detection of rising edge of TCLR1n 10: TM1n cleared status held while TCLR1n input is low level 11: TM1n cleared status held while TCLR1n input is high level Caution The set values of the CESUDn1 and CESUDn0 bits are valid only in UDC mode A. 3, 2 IES1n11, IES1n10 Specifies valid edge of the pin (INTP1n1/INTP1n0) selected by the CSLn bit of the CSL1n register. IES1n11 0 0 1 1 IES1n10 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges Valid edge 1, 0 IES1n01, IES1n00 Specifies valid edge of pins INTP100, INTP110. IES1n01 0 0 1 1 IES1n00 0 1 0 1 Falling edge Rising edge Setting prohibited Both rising and falling edges Valid edge Remark n = 0, 1 User's Manual U14492EJ5V0UD 305 CHAPTER 9 TIMER/COUNTER FUNCTION (6) Prescaler mode registers 10, 11 (PRM10, PRM11) The PRM1n register is used to perform the following selections. * Selection of count clock in the general-purpose timer mode (CMD bit of TUMn register = 0) * Selection of count operation mode in the UDC mode (CMD bit = 1) PRM1n can be read/written in 8-bit or 1-bit units. Cautions 1. Overwriting the PRM1n register during TM1n operation (TM1CEn bit = 1) is prohibited. 2. Clearing the PRM12 bit to 0 is prohibited in UDC mode (CMD bit of TUMn register = 1). 3. When TM1n is in mode 4, specification of the valid edge for the TIUD1n and TCUD1n pins is invalid. 7 PRM10 0 6 0 5 0 4 0 3 0 2 PRM12 1 PRM11 0 PRM10 Address FFFFF5EEH Initial value 07H 7 PRM11 0 6 0 5 0 4 0 3 0 2 PRM12 1 PRM11 0 PRM10 Address FFFFF60EH Initial value 07H Bit position 2 to 0 Bit name PRM12 to PRM10 Function Specifies the up/down count operation mode during input of the clock rate when the internal clock of the TM1n is used, or during external clock (TIUD1n) input. PRM12 PRM11 PRM10 CMD = 0 Count clock CMD = 1 Count clock UDC mode 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Setting prohibited fCLK/2 fCLK/4 fCLK/8 fCLK/16 fCLK/32 fCLK/64 fCLK/128 Setting prohibited TIUD1n Mode 1 Mode 2 Mode 3 Mode 4 Remarks 1. fCLK: Base clock 2. n = 0, 1 306 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (a) In general-purpose timer mode (CMD bit of TUMn register = 0) The count clock is specified with the PRM12 to PRM10 bits. (b) UDC mode (CMD bit of TUMn register = 1) The TM1n count sources in the UDC mode are as follows. Operation Mode Mode 1 Down count when TCUD1n = high level Up count when TCUD1n = low level Up count upon detection of valid edge of TIUD1n input Down count upon detection of valid edge of TCUD1n input Mode 3 Up count upon detection of valid edge of TIUD1n input when TCUD1n = high level Down count upon detection of valid edge of TIUD1n input when TCUD1n = low level Mode 4 Automatic judgment upon detection of both edges of TIUD1n input and both edges of TCUD1n input TM1n Operation Mode 2 User's Manual U14492EJ5V0UD 307 CHAPTER 9 TIMER/COUNTER FUNCTION (7) Status registers 0, 1 (STATUS0, STATUS1) The STATUSn register indicates the operating status of TM1n. STATUSn is read-only, in 8-bit or 1-bit units. 7 STATUS0 0 6 0 5 0 4 0 3 0 <2> <1> <0> Address FFFFF5EFH Initial value 00H TM1UDF0 TM1OVF0 TM1UBD0 7 STATUS1 0 6 0 5 0 4 0 3 0 <2> <1> <0> Address FFFFF60FH Initial value 00H TM1UDF1 TM1OVF1 TM1UBD1 Bit position 2 Bit name TM1UDFn TM1n underflow flag 0: No TM1n count underflow 1: TM1n count underflow Function Caution The TM1UDFn bit is cleared (to "0") upon completion of read access to the STATUSn register from the CPU. 1 TM1OVFn TM1n overflow flag 0: No TM1n count overflow 1: TM1n count overflow Caution The TM1OVFn bit is cleared (to "0") upon completion of read access to the STATUSn register from the CPU. 0 TM1UBDn Indicates the operating status of TM1n up/down count. 0: TM1n up count in progress 1: TM1n down count in progress Caution The state of the TM1UBDn bit differs according to the mode as follows. * The TM1UBDn bit is fixed to 0 in general-purpose timer mode (CMD bit of TUMn register = 0). * The TM1UBDn bit indicates the TM1n up-/down-count status in UDC mode (CMD bit of TUMn register = 1). Remark n = 0, 1 308 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (8) CC101 capture input selection register (CSL10) The CSL10 register is used to select the INTP101 or INTP100 pin to input a capture signal when the CC101 register is used as a capture register. CSL10 can be read/written in 8-bit or 1-bit units. 7 CSL10 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CSL0 Address FFFFF5F6H Initial value 00H Bit position 0 Bit name CSL0 Specifies capture input to CC101. 0: INTP101 1: INTP100 Function (9) CC111 capture input selection register (CSL11) The CSL11 register is used to select the INTP111 or INTP110 pin to input a capture signal when the CC111 register is used as a capture register. CSL11 can be read/written in 8-bit or 1-bit units. 7 CSL11 0 6 0 5 0 4 0 3 0 2 0 1 0 0 CSL1 Address FFFFF616H Initial value 00H Bit position 0 Bit name CSL1 Specifies capture input to CC111. 0: INTP111 1: INTP110 Function User's Manual U14492EJ5V0UD 309 CHAPTER 9 TIMER/COUNTER FUNCTION (10) Compare registers 100, 110 (CM100, CM110) CM1n0 is a 16-bit register that always compares its value with the value of TM1n. When the value of a compare register matches the value of TM1n, an interrupt signal is generated. The interrupt generation timing in the various modes is described below. * In the general-purpose timer mode (CMD bit of TUMn register = 0) and UDC mode A (MSEL bit of TUMn register = 0), an interrupt signal (INTCM1n0) is generated upon occurrence of a match. * In UDC mode B (MSEL bit of TUMn register = 1), an interrupt signal (INTCM1n0) is generated only upon occurrence of a match during up-count operation. CM1n0 can be read/written in 16-bit units. Caution When the TM1CEn bit of the TMC1n register is "1", it is prohibited to overwrite the value of the CM1n0 register. 15 CM100 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF5E2H Initial value 0000H 15 CM110 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF602H Initial value 0000H (11) Compare registers 101, 111 (CM101, CM111) CM1n1 is a 16-bit register that always compares its value with the value of TM1n. When the value of a compare register matches the value of TM1n, an interrupt signal is generated. The interrupt generation timing in the various modes is described below. * In the general-purpose timer mode (CMD bit of TUMn register = 0) and UDC mode A (MSEL bit of TUMn register = 0), an interrupt signal (INTCM1n1) is generated upon occurrence of a match. * In UDC mode B (MSEL bit of TUMn register = 1), an interrupt signal (INTCM1n1) is generated only upon occurrence of a match during down count operation. CM1n1 can be read/written in 16-bit units. Caution When the TM1CEn bit of the TMC1n register is "1", it is prohibited to overwrite the value of the CM1n1 register. 15 CM101 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF5E4H Initial value 0000H 15 CM111 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF604H Initial value 0000H 310 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (12) Capture/compare registers 100, 110 (CC100, CC110) CC1n0 is a 16-bit register. It can be used as a capture register or as a compare register through specification with capture/compare control register n (CCRn). CC1n0 can be read/written in 16-bit units. Cautions 1. When used as a capture register (CMS0 bit of CCRn register = 0), write access is prohibited. 2. When used as a compare register (CMS0 bit of CCRn register = 1) during TM1n operation (TM1CEn bit of TMC1n register = 1), overwriting the CC1n0 register values is prohibited. 3. When TM1n has been stopped (TM1CEn bit of TMC1n register = 0), the capture trigger is disabled. 4. When the operation mode is changed from capture register to compare register, newly set a compare value. 5. Continuous reading of CC1n0 is prohibited. If CC1n0 is continuously read, the second read value may differ from the actual value. If CC1n0 must be read twice, be sure to read another register between the first and the second read operation. Correct usage example CC100 read CC110 read CC100 read CC110 read Remark n = 0, 1 Incorrect usage example CC100 read CC100 read CC110 read CC110 read 15 CC100 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF5E6H Initial value 0000H 15 CC110 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF606H Initial value 0000H (a) When set as a capture register When CC1n0 is set as a capture register, the valid edge of the corresponding external interrupt signal (INTP1n0) is detected as the capture trigger. TM1n latches the count value in synchronization with the capture trigger (capture operation). The latched value is held in the capture register until the next capture operation. The valid edge of external interrupts (rising edge, falling edge, both rising and falling edges) is selected with signal edge selection register 1n (SESA1n). When the CC1n0 register is specified as a capture register, interrupts are generated upon detection of the valid edge of the INTP1n0 signal. (b) When set as a compare register When CC1n0 is set as a compare register, it always compares its own value with the value of TM1n. If the value of CC1n0 matches the value of the TM1n, CC1n0 generates an interrupt signal (INTCC1n0). User's Manual U14492EJ5V0UD 311 CHAPTER 9 TIMER/COUNTER FUNCTION (13) Capture/compare registers 101, 111 (CC101, CC111) CC1n1 is a 16-bit register. It can be used as a capture register or as a compare register through specification with capture/compare control register n (CCRn). CC1n1 can be read/written in 16-bit units. Cautions 1. When used as a capture register (CMS1 bit of CCRn register = 0), write access is prohibited. 2. When used as a compare register (CMS1 bit of CCRn register = 1) during TM1n operation (TM1CEn bit of TMC1n register = 1), overwriting the CC1n1 register values is prohibited. 3. When TM1n has been stopped (TM1CEn bit of TMC1n register = 0), the capture trigger is disabled. 4. When the operation mode is changed from capture register to compare register, newly set a compare value. 5. Continuous reading of CC1n1 is prohibited. If CC1n1 is continuously read, the second read value may differ from the actual value. If CC1n1 must be read twice, be sure to read another register between the first and the second read operation. Correct usage example CC101 read CC111 read CC101 read CC111 read Remark n = 0, 1 Incorrect usage example CC101 read CC101 read CC111 read CC111 read 15 CC101 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF5E8H Initial value 0000H 15 CC111 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF608H Initial value 0000H (a) When set as a capture register When CC1n1 is set as a capture register, the valid edge of either corresponding external interrupt signal (INTP1n0 or INTP1n1) is selected with the selector, and the valid edge of the selected external interrupt signal is detected as the capture trigger. TM1n latches the count value in synchronization with the capture trigger (capture operation). The latched value is held in the capture register until the next capture operation. The valid edge of external interrupts (rising edge, falling edge, both rising and falling edges) is selected with signal edge selection register 1n (SESA1n). When the CC1n1 register is specified as a capture register, interrupts are generated upon detection of the valid edge of either the INTP1n0 or INTP1n1 signal. (b) When set as a compare register When CC1n1 is set as a compare register, it always compares its own value with the value of TM1n. If the value of CC1n1 matches the value of the TM1n, CC1n1 generates an interrupt signal (INTCC1n1). 312 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.2.5 Operation (1) Operation in general-purpose timer mode TM1n can perform the following operations in the general-purpose timer mode. (a) Interval operation (when ENMD bit of TMC1n register = 1) TM1n and CM1n0 always compare their values and the INTCM1n0 interrupt is generated upon occurrence of a match. TM1n is cleared (0000H) at the count clock following the match. Furthermore, when one more count clock is input, TM1n counts up to 0001H. The interval time can be calculated with the following formula. Interval time = (CM1n0 value + 1) x TM1n count clock rate (b) Free-running operation (when ENMD bit of TMC1n register = 0) TM1n performs full count operation from 0000H to FFFFH, and after the TM1OVFn bit of the STATUSn register is set (to "1"), TM1n is cleared to 0000H at the next count clock and resumes counting. The free-running cycle can be calculated with the following formula. Free-running cycle = 65536 x TM1n count clock rate (c) Compare function TM1n connects two compare register (CM1n0, CM1n1) channels and two capture/compare register (CC1n0, CC1n1) channels. When the TM1n count value and the set value of one of the compare registers match, a match interrupt (INTCM1n0, INTCM1n1, INTCC1n0Note, INTCC1n1Note) is output. Particularly in the case of interval operation, TM1n is cleared upon generation of the INTCM1n0 interrupt. Note This match interrupt is generated when CC1n0 and CC1n1 are set to the compare register mode. (d) Capture function TM1n connects two capture/compare register (CC1n0, CC1n1) channels. When CC1n0 and CC1n1 are set to the capture register mode, the value of TM1n is captured in synchronization with the corresponding capture trigger signal. Furthermore, an interrupt request signal (INTCC1n0, INTCC1n1) is generated by the valid edge of the INTP1n0, INTP1n1 input signals specified as the capture trigger signals. User's Manual U14492EJ5V0UD 313 CHAPTER 9 TIMER/COUNTER FUNCTION Table 9-6. Capture Trigger Signal (TM1n) to 16-Bit Capture Register Capture Register CC1n0 CC1n1 Capture Trigger Signal INTP1n0 INTP1n0 or INTP1n1 Remarks 1. CC1n0 and CC1n1 are capture/compare registers. Which of these registers is used is specified with capture/compare control register n (CCRn). 2. n = 0, 1 The valid edge of the capture trigger is specified by signal edge selection register 1n (SESA1n). If both the rising edge and the falling edge are selected as the capture triggers, it is possible to measure the input pulse width from external. If a single edge is selected as the capture trigger, the input pulse cycle can be measured. (e) PWM output operation PWM output operation is performed from the TO1n pin by setting TM1n to the general-purpose timer mode (CMD bit = 0) using timer unit mode register n (TUMn). The resolution is 16 bits, and the count clock can be selected from among seven internal clocks (fCLK/2, fCLK/4, fCLK/8, fCLK/16, fCLK/32, fCLK/64, fCLK/128). Figure 9-49. TM1n Block Diagram (During PWM Output Operation) fCLK/2 fCLK/4 fCLK/8 fCLK/16 fCLK/32 fCLK/64 fCLK/128 TM1n (16 bits) 16 Compare register (CM1n0) 16 Compare register (CM1n1) S Q TO1n R INTCM1n1 Clear INTCM1n0 ALVT10 TUMn register Caution Be sure to set the count clock of TM1n to 8 MHz or lower. Remarks 1. fCLK: Base clock 2. n = 0, 1 314 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (i) Description of operation The CM1n0 register is a compare register used to set the PWM output cycle. When the value of this register matches the value of TM1n, the INTCM1n0 interrupt is generated. Compare match is saved by hardware, and TM1n is cleared at the next count clock after the match. The CM1n1 register is a compare register used to set the PWM output duty. Set the duty required for the PWM cycle. Figure 9-50. PWM Signal Output Example (When ALVT10 Bit = 0 Is Set) CM1n0 set value TM1n CM1n1 set value TO1n INTCM1n0 INTCM1n1 Cautions 1. Changing the values of the CM1n0 and CM1n1 registers is prohibited during TM1n operation (TM1CEn bit of TMC1n register = 1). 2. Changing the value of the ALVT10 bit of the TUMn register is prohibited during TM1n operation. 3. PWM signal output is performed from the second PWM cycle after the TM1CEn bit is set (to "1"). User's Manual U14492EJ5V0UD 315 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Operation in UDC mode (a) Overview of operation in UDC mode The count clock input to TM1n in the UDC mode (CMD bit of TUMn register = 1) can only be external input from the TIUD1n and TCUD1n pins. Up/down count judgment in the UDC mode is determined based on the phase difference of the TIUD1n and TCUD1n pin inputs according to the PRM1n register setting (there is a total of four choices). Table 9-7. List of Count Operations in UDC Mode PRM1n Register PRM12 1 PRM11 0 PRM10 0 Operation Mode Mode 1 TM1n Operation Down count when TCUD1n = high level Up count when TCUD1n = low level 1 0 1 Mode 2 Up count upon detection of valid edge of TIUD1n input Down count upon detection of valid edge of TCUD1n input 1 1 0 Mode 3 Up count upon detection of valid edge of TIUD1n input when TCUD1n = high level Down count upon detection of valid edge of TIUD1n input when TCUD1n = low level 1 1 1 Mode 4 Automatic judgment upon detection of both edges of TIUD1n input and both edges of TCUD1n input The UDC mode is further divided into two modes according to the TM1n clear conditions (count operation is performed only with TIUD1n, TCUD1n input in both modes). * UDC mode A (TUMn register's CMD bit = 1, MSEL bit = 0) The TM1n clear source can be selected as only external clear input (TCLR1n), a match signal between the TM1n count value and the CM1n0 set value during up-count operation, or logical sum (OR) of the two signals, using bits CLR1 and CLR0 of the TMC1n register. TM1n can transfer the value of CM1n0 upon occurrence of TM1n underflow. * UDC mode B (TUMn register's CMD bit = 1, MSEL bit = 1) The status of TM1n after match of the TM1n count value and CM1n0 set value is as follows. <1> In the case of up-count operation, TM1n is cleared (0000H), and the INTCM1n0 interrupt is generated. <2> In the case of down-count operation, the TM1n count value is decremented (-1). The status of TM1n after match of the TM1n count value and CM1n1 set value is as follows. <1> In the case of up-count operation, the TM1n count value is incremented (+1). <2> In the case of down-count operation, TM1n is cleared (0000H), and the INTCM1n1 interrupt is generated. 316 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (b) Up/down count operation in UDC mode TM1n up/down count judgment in the UDC mode is determined based on the phase difference of the TIUD1n and TCUD1n pin inputs according to the PRM1n register setting. (i) Mode 1 (PRM1n register's PRM12 bit = 1, PRM11 bit = 0, PRM10 bit = 0) In mode 1, the following count operations are performed based on the level of the TCUD1n pin upon detection of the valid edge of the TIUD1n pin. * TM1n down-count operation when TCUD1n pin = high level * TM1n up-count operation when TCUD1n pin = low level Figure 9-51. Mode 1 (When Rising Edge Is Specified as Valid Edge of TIUD1n Pin) TIUD1n TCUD1n TM1n 0007H 0006H 0005H 0004H 0005H 0006H Up count 0007H Down count Remark n = 0, 1 User's Manual U14492EJ5V0UD 317 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-52. Mode 1 (When Rising Edge Is Specified as Valid Edge of TIUD1n Pin): In Case of Simultaneous TIUD1n, TCUD1n Pin Edge Timing TIUD1n TCUD1n TM1n 0007H 0006H 0005H 0004H 0005H 0006H Up count 0007H Down count Remark n = 0, 1 (ii) Mode 2 (PRM1n register's PRM12 bit = 1, PRM11 bit = 0, PRM10 bit = 1) The count conditions in mode 2 are as follows. * TM1n up-count upon detection of valid edge of TIUD1n pin * TM1n down-count upon detection of valid edge of TCUD1n pin Caution If the count clock is simultaneously input to the TIUD1n pin and the TCUD1n pin, count operation is not performed and the immediately preceding value is held. Figure 9-53. Mode 2 (When Rising Edge Is Specified as Valid Edge of TIUD1n, TCUD1n Pins) TIUD1n TCUD1n TM1n 0006H 0007H Up count 0008H Hold value 0007H 0006H 0005H Down count Remark n = 0, 1 318 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (iii) Mode 3 (PRM1n register's PRM12 = 1, PRM11 = 1, PRM10 = 0) In mode 3, when two signals 90 degrees out of phase are input to the TIUD1n and TCUD1n pins, the level of the TCUD1n pin is sampled at the input of the valid edge of the TIUD1n pin (refer to Figure 9-54). If the TCUD1n pin level sampled at the valid edge input to the TIUD1n pin is low, TM1n counts down when the valid edge is input to the TIUD1n pin. If the TCUD1n pin level sampled at the valid edge input to the TIUD1n pin is high, TM1n counts up when the valid edge is input to the TIUD1n pin. Figure 9-54. Mode 3 (When Rising Edge Is Specified as Valid Edge of TIUD1n Pin) TIUD1n TCUD1n TM1n 0007H 0008H 0009H 000AH 0009H 0008H 0007H Up count Down count Remark n = 0, 1 Figure 9-55. Mode 3 (When Rising Edge Is Specified as Valid Edge of TIUD1n Pin): In Case of Simultaneous TIUD1n, TCUD1n Pin Edge Timing TIUD1n TCUD1n TM1n 0007H 0008H 0009H 000AH 0009H 0008H 0007H Up count Down count Remark n = 0, 1 User's Manual U14492EJ5V0UD 319 CHAPTER 9 TIMER/COUNTER FUNCTION (iv) Mode 4 (PRM1n register's PRM12 = 1, PRM11 = 1, PRM10 = 1) In mode 4, when two signals out of phase are input to the TIUD1n and TCUD1n pins, up/down operation is automatically judged and counting is performed according to the timing shown in Figure 9-56. In mode 4, counting is executed at both the rising and falling edges of the two signals input to the TIUD1n and TCUD1n pins. Therefore, TM1n counts four times per cycle of an input signal (x 4 count). Figure 9-56. Mode 4 TIUD1n TCUD1n TM1n 0003H 0004H 0005H 0006H 0007H 0008H 0009H Up count 000AH 0009H 0008H 0007H 0006H 0005H Down count Cautions 1. When mode 4 is specified as the operation mode of TM1n, the valid edge specifications for pins TIUD1n and TCUD1n are not valid. 2. If the TIUD1n pin edge and TCUD1n pin edge are input simultaneously in mode 4, TM1n continues the same count operation (up or down) it was performing immediately before the input. 320 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (c) Operation in UDC mode A (i) Interval operation The operations at the count clock following match of the TM1n count value and the CM1n0 set value are as follows. * In case of up-count operation: TM1n is cleared (0000H) and the INTCM1n0 interrupt is generated. * In case of down-count operation: The TM1n count value is decremented (-1) and the INTCM1n0 interrupt is generated. Remark The interval operation can be combined with the transfer operation. (ii) Transfer operation If TM1n becomes 0000H during down counting when the RLEN bit of the TMC1n register is 1, the CM1n0 register set value is transferred to TM1n at the next count clock. Remarks 1. Transfer enable/disable can be set with the RLEN bit of the TMC1n register. 2. The transfer operation can be combined with the interval operation. Figure 9-57. Example of TM1n Operation When Interval Operation and Transfer Operation Are Combined CM1n0 set value TM1n count value 0000H TM1n and CM1n0 match & timer clear TM1n underflow & CM1n0 data transfer Up count Down count Remark n = 0, 1 (iii) Compare function TM1n connects two compare register (CM1n0, CM1n1) channels and two capture/compare register (CC1n0, CC1n1) channels. When the TM1n count value and the set value of one of the compare registers match, a match interrupt (INTCM1n0, INTCM1n1, INTCC1n0Note, INTCC1n1Note) is output. Note This match interrupt is generated when CC1n0 and CC1n1 are set to the compare register mode. (iv) Capture function TM1n connects two capture/compare register (CC1n0, CC1n1) channels. When CC1n0 and CC1n1 are set to the capture register mode, the value of TM1n is captured in synchronization with the corresponding capture trigger signal. INTCC1n1) is generated upon detection of the valid edge. A capture interrupt (INTCC1n0, User's Manual U14492EJ5V0UD 321 CHAPTER 9 TIMER/COUNTER FUNCTION (d) Operation in UDC mode B (i) Basic operation The operations at the next count clock after the count value of TM1n and the CM1n0 set value match when TM1n is in UDC mode B are as follows. * In case of up-count operation: TM1n is cleared (0000H) and the INTCM1n0 interrupt is generated. * In case of down-count operation: The TM1n count value is decremented (-1). The operations at the next count clock after the count value of TM1n and the CM1n1 set value match when TM1n is in UDC mode B are as follows. * In case of up-count operation: The TM1n count value is incremented (+1). * In case of down-count operation: TM1n is cleared (0000H) and the INTCM1n1 interrupt is generated. Figure 9-58. Example of TM1n Operation in UDC Mode CM1n0 set value TM1n not cleared if count clock counts up following match Clear TM1n count value Clear TM1n not cleared if count clock counts down following match CM1n1 set value Remark n = 0, 1 (ii) Compare function TM1n connects two compare register (CM1n0, CM1n1) channels and two capture/compare register (CC1n0, CC1n1) channels. When the TM1n count value and the set value of one of the compare registers match, a match interrupt (INTCM1n0 (only during up-count operation), INTCM1n1 (only during down-count operation), INTCC1n0Note, INTCC1n1Note) is output. Note This match interrupt is generated when CC1n0 and CC1n1 are set to the compare register mode. (iii) Capture function TM1n connects two capture/compare register (CC1n0, CC1n1) channels. When CC1n0 and CC1n1 are set to the capture register mode, the value of TM1n is captured in synchronization with the corresponding capture trigger signal. INTCC1n1) is generated upon detection of the valid edge. A capture interrupt (INTCC1n0, 322 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.2.6 Supplementary description of internal operation (1) Clearing of count value in UDC mode B When TM1n is in UDC mode B, the conditions to clear the count value are as follows. * In case of TM1n up-count operation: TM1n count value is cleared upon match with the CM1n0 register * In case of TM1n down-count operation: TM1n count value is cleared upon match with the CM1n1 register Figure 9-59. Clear Operation After Match of CM1n0 Register Set Value and TM1n Count Value (a) Up count Up count TM1n cleared Count clock (Rising edge set as valid edge) TM1n FFFEH FFFFH 0000H 0001H CM1n0 register Up count FFFFH Up count (b) Up count Down count TM1n not cleared Count clock (Rising edge set as valid edge) TM1n FFFEH FFFFH FFFEH FFFDH CM1n0 register Up count FFFFH Down count Remark n = 0, 1 User's Manual U14492EJ5V0UD 323 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-60. Clear Operation After Match of CM1n1 Register Set Value and TM1n Count Value (a) Down count Down count TM1n cleared Count clock (Rising edge set as valid edge) TM1n 00FFH 00FEH 0000H FFFFH CM1n1 register Down count 00FEH Down count (b) Down Up count TM1n not cleared Count clock (Rising edge set as valid edge) TM1n 00FFH 00FEH 00FFH 0100H CM1n1 register Down count 00FEH Up count Remark n = 0, 1 (2) Transfer operation If TM1n becomes 0000H during down counting when the RLEN bit of the TMC1n register is 1 in UDC mode A, the set value of the CM1n0 register is transferred to TM1n at the next count clock. The transfer operation is not performed during up counting. Figure 9-61. Internal Operation During Transfer Operation Transfer operation performed. Count clock (Rising edge set as valid edge) TM1n 0001H 0000H CM1n0 CM1n0 set value set value - 1 FFFFH Down count Down count CM1n0 register Remark n = 0, 1 324 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (3) Interrupt signal output upon compare match An interrupt signal is output when the count value of TM1n matches the set value of the CM1n0, CM1n1, CC1n0Note, or CC1n1Note register. The interrupt generation timing is as follows. Note When CC1n0 and CC1n1 are set to the compare register mode. Figure 9-62. Interrupt Output upon Compare Match (CM1n1 with Operation Mode Set to General-Purpose Timer Mode and Count Clock Set to fCLK/2) fCLK Count clock TM1n 0007H 0008H 0009H 000AH 000BH CM1n1 Internal match signal 0009H INTCM1n1 Remarks 1. n = 0, 1 2. fCLK: Base clock An interrupt signal such as illustrated in Figure 9-62 is output at the next count clock following a match of the TM1n count value and the set value of a corresponding compare register. (4) TM1UBDn flag (bit 0 of STATUSn register) operation In the UDC mode (CMD bit of TUMn register = 1), the TM1UBDn flag changes as follows during TM1n up/down count operation at every internal operation clock. Figure 9-63. TM1UBDn Flag Operation Count clock TM1n 0000H 0001H 0000H 0001H 0000H 0001H TM1UBDn Remark n = 0, 1 User's Manual U14492EJ5V0UD 325 CHAPTER 9 TIMER/COUNTER FUNCTION 9.3 Timer 2 9.3.1 Features (timer 2) Timers 20, 21 (TM20, TM21) are 16-bit general-purpose timer units that perform the following operations. * Pulse interval or frequency measurement and programmable pulse output * Interval timer * PWM output timer * 32-bit capture timer when 2 timer/counter channels are connected in cascade (In this case, four 32-bit capture register channels can be used.) 9.3.2 Function overview (timer 2) * 16-bit timer/counter (TM20, TM21): 2 channels * Bit length Timer 2 registers (TM20, TM21): 16 bits During cascade operation: 32 bits (higher 16 bits: TM21, lower 16 bits: TM20) * Capture/compare register In 16-bit mode: 6 In 32-bit mode: 4 (capture mode only) * Count clock division selectable by prescaler (set the frequency of the count clock to 8 MHz or less) * Base clock (fCLK): 2 types (set fCLK to 16 MHz or less) fXX/2 and fXX/4 can be selected * Prescaler division ratio The following division ratios can be selected according to the base clock (fCLK). Division Ratio Base Clock (fCLK) fXX/2 Selected 1/2 1/4 1/8 1/16 1/32 1/64 1/128 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/4 Selected fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 326 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION * Interrupt request sources * Compare-match interrupt request: 6 types Perform comparison with sub-channel n capture/compare register and generate the INTCC2n interrupt upon compare match. * Timer/counter overflow interrupt request: 2 types The INTTM20 (INTTM21) interrupt is generated when the count value of TM20 (TM21) becomes FFFFH. * Capture request The count values of TM20, TM21 can be latched using external pin (INTP2n)Notes 1, 2, TM10, TM11 interrupt signals (INTCM100, INTCM101) and interrupt requests by software as capture triggers. * PWM output function Control of the outputs of pins TO21 to TO24 in the compare mode and PWM output can be performed using the compare match timing of sub-channels 1 to 4 and the zero count signal of the timer/counter. * Timer count operation with external clock inputNote 2 Timer count operation can be performed with the pin TI2 clock input signal. * Timer count enable operationNote 3 with external pin inputNote 2 Timer count enable operation can be performed with the TCLR2 pin input signal. * Timer/counter clear operationNotes 3, 4 with external pin inputNote 2 Timer/counter clear operation can be performed with the TCLR2 pin input signal. * Up/down count controlNotes 3, 5 with external pin inputNote 2 Up/down count operation in the compare mode can be controlled with the TCLR2 pin input signal. * Output delay operation A clock-synchronized output delay can be added to the output signal of pins TO21 to TO24. This is effective as an EMI countermeasure. * Input filter An input filter can be inserted at the input stage of external pins (TI2, INTP20 to INTP25, TCLR2) and the TM10, TM11 interrupt signals (refer to 14.5.3 (1) Timer 2 input filter mode registers 0 to 5 (FEM0 to FEM5)). Notes 1. 2. 3. 4. 5. Remark For the registers used to specify the valid edge for external interrupt requests (INTP20 to INTP25) to timer 2, refer to 7.3.8 (4) Timer 2 input filter mode registers 0 to 5 (FEM0 to FEM5). The pairs TI2 and INTP20, TO21 and INTP21, TO22 and INTP22, TO23 and INTP23, TO24 and INTP24, TCLR2 and INTP25 are each alternate function pins. The count enable operation for the timer/counter through external pin input, timer/counter clear operation, and up/down count control cannot be performed combined all at the same time. In the case of 32-bit cascade connection, clear operation by external pin input (TCLR2) cannot be performed. Up/down count control using 32-bit cascade connection cannot be performed. fXX: Internal system clock n = 0 to 5 User's Manual U14492EJ5V0UD 327 CHAPTER 9 TIMER/COUNTER FUNCTION 9.3.3 Basic configuration The basic configuration is shown below. Table 9-8. Timer 2 Configuration List Timer Count Clock Note 1 Timer 2 fXX/4, fXX/8, fXX/16, fXX/32, fXX/64, fXX/128, fXX/256 Note 2 fXX/8, fXX/16, fXX/32, fXX/64, fXX/128, fXX/256, fXX/512 CVSE00 CVSE10 CVSE20 CVSE30 CVSE40 CVSE50 CVPE40 CVPE30 CVPE20 CVPE10 TM20 TM21 - - Read/write Read/write Read/write Read/write Read/write Read/write Read Read Read Read Register Read/Write Generated Interrupt Signal INTTM20 INTTM21 INTCC20 INTCC21 INTCC22 INTCC23 INTCC24 INTCC25 INTCC24 INTCC23 INTCC22 INTCC21 Capture Trigger Other Functions - - INTP20/INTP25 INTP21/INTP24 INTP22/INTP23 INTP23/INTP22 INTP24/INTP21 INTP25/INTP20 INTP24/INTP21 INTP23/INTP22 INTP22/INTP23 INTP21/INTP24 Note 3 Note 3 - Buffer/Note 4 Buffer/Note 4 Buffer/Note 4 Buffer/Note 4 - Note 4 Note 4 Note 4 Note 4 Notes 1. 2. 3. 4. Remark When fXX/2 is selected as the base clock input to TM2n When fXX/4 is selected as the base clock input to TM2n Cascade operation with TM20 and TM21 is enabled. Cascade operation using the CVSEn0 register and CVPEn0 register is enabled (n = 1 to 4). fXX: Internal system clock 328 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION The following shows the capture/compare operation sources. Table 9-9. Capture/Compare Operation Sources Register Sub-channel No. CVSE00 CVPEn0 0 n TM20 TM21 when BFEEy bit of CMSEm0 register = 0 CVSEn0 n TM20 when BFEEy bit of CMSEm0 register = 0 CVSE50 5 TM21 TM21 - TM20 TM20 when TB1Ey, TB0Ey bits of CMSEm0 register = 01 Used as buffer TM20 TM21 Timer to Be Captured Timer to Be Compared Timer Captured in 32-Bit Cascade Connection - Remark n = 1 to 4 m: m = 12 when n = 1, 2, m = 34 when n = 3, 4 y: y = 1, 2 when m = 12, y = 3, 4 when m = 34 The following shows the output level sources during timer output. Table 9-10. Output Level Sources During Timer Output TO2n Toggle Mode 0 (OTMEn1, OTMEn0 = 00) Compare match of subchannel n Toggle Mode 1 (OTMEn1, OTMEn0 = 01) Compare match of subchannel n Active output Inactive output TM20 = 0 Toggle Mode 2 (OTMEn1, OTMEn0 = 10) Compare match of subchannel n Active output Inactive output TM21 = 0 Toggle Mode 3 (OTMEn1, OTMEn0 = 11) Compare Compare Trigger match of sub- match of subchannel n channel n + 1 Active output Inactive output Output level Active output Inactive output Remarks 1. n = 1 to 4 2. OTMEn1, OTMEn0: Bits 13, 12, 9, 8, 5, 4, 1, and 0 of timer 2 output control register 0 (OCTLE0) Figure 9-64 shows the block diagram of timer 2. User's Manual U14492EJ5V0UD 329 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-64. Block Diagram of Timer 2 Selector Selector fXX/2 fXX/4 1/2, 1/4, 1/8, 1/16, 1/32, fCLK 1/64, 1/128 ECLR TCOUNTE0 edge selection CT TM20 (16-bit) CNT = MAX. CNT = 0 R INTTM20 Selector TCOUNTE1 edge selection INTCC20 TI2/ INTP20 Input filter TINE0 edge selection ED1 ED2 CVSE00 (16-bit) Sub-channel 0 INTCC21 INTP21 Input filter TINE1 edge selection ED1 ED2 CVSE10 (16-bit) CVPE10 (16-bit) Sub-channel 1 S/T RA RB RN INTCC22 INTP22 Input filter TINE2 edge selection ED1 ED2 CVSE20 (16-bit) CVPE20 (16-bit) Sub-channel 2 S/T RA RB RN INTCC23 INTP23 Input filter TINE3 edge selection ED1 ED2 CVSE30 (16-bit) CVPE30 (16-bit) Sub-channel 3 S/T RA RB RN INTCC24 INTP24 Input filter TINE4 edge selection ED1 ED2 CVSE40 (16-bit) CVPE40 (16-bit) Sub-channel 4 ED1 ED2 S/T RA RB RN Output circuit 2 RELOAD2A RELOAD2B Output circuit 1 TO21 RELOAD2A RELOAD2B TO22 RELOAD2A RELOAD2B Output circuit 3 TO23 RELOAD2A RELOAD2B Output circuit 4 TO24 TCLR2/ INTP25 Input filter TINE5 edge selection INTCC25 CVSE50 (16-bit) Timer connection selector Sub-channel 5 ECLR CT CTC CASC TM21 (16-bit) CNT = MAX. CNT = 0 R INTTM21 Remark fXX: Internal system clock fCLK: Base clock (16 MHz (MAX.)) 330 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Table 9-11. Meaning of Signals in Block Diagram Signal Name CASC CNT Note 1 Meaning TM21 count signal input in 32-bit mode Count value of timer 2 (CNT = MAX.: Maximum value count signal output of timer 2 (generated when TM2n = FFFFH), CNT = 0: Zero count signal output of timer 2 (generated when TM2n = 0000H)) CT CTC ECLR ED1, ED2 R Note 2 TM2n count signal input in 16-bit mode TM21 count signal input in 32-bit mode External control signal input from TCLR2 input Capture event signal input from edge selector Compare match signal input (sub-channel 0/5) TM20 zero count signal input (reset signal of output circuit) TM21 zero count signal input (reset signal of output circuit) TM20 zero count signal input (generated when TM20 = 0000H) TM21 zero count signal input (generated when TM21 = 0000H) Sub-channel x interrupt signal input (reset signal of output circuit) Sub-channel x interrupt signal input (set signal of output circuit) Timer 2 count enable signal input Timer 2 sub-channel m capture event signal input RA RB RELOAD2A RELOAD2B RN S/T TCOUNTE0, TCOUNTE1 TINEm Notes 1. 2. Remark TM21 performs count operation when CASC (CNT = MAX. for TM20) is generated and the rising edge of CTC is detected in the 32-bit mode. TM20/TM21 clear by sub-channel 0/5 compare match or count direction can be controlled. m = 0 to 5 n = 0, 1 x = 1 to 4 User's Manual U14492EJ5V0UD 331 CHAPTER 9 TIMER/COUNTER FUNCTION (1) Timers 20, 21 (TM20, TM21) The features of TM2n are listed below. * Free-running counter that enables counter clearing by compare match of sub-channel 0 and sub-channel 5 * Can be used as a 32-bit capture timer when TM20 and TM21 are connected in cascade. * Up/down control, counter clear, and count operation enable/disable can be controlled with external pin (TCLR2). * Counter up/down and clear operation control method can be set by software. * Stop upon occurrence of count value 0 and count operation start/stop can be controlled by software. (2) Timer 2 sub-channel 0 capture/compare register (CVSE00) The CVSE00 register is a 16-bit capture/compare register of sub-channel 0. In the capture register mode, it captures the TM20 count value. In the compare register mode, it detects match with TM20. This register can be read/written in 16-bit units. 15 CVSE00 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF660H Initial value 0000H 332 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (3) Timer 2 sub-channel n main capture/compare register (CVPEn0) (n = 1 to 4) The CVPEn0 register is a sub-channel n 16-bit main capture/compare register. In the capture register mode, this register captures the value of TM21 when the BFEEn bit of the CMSEm0 register = 0 (m = 12, 34). When the BFEEn bit = 1, this register holds the value of TM20 or TM21. In the compare register mode, a match between this register and TM2x is detected (TM2x = timer/counter selected by TB1En and TB0En bits). If the capture register mode is selected in the 32-bit mode (value of TB1En, TB0En bits of CMSEm0 register = 11B), this register captures the contents of TM21 (higher 16 bits). This register is read-only, in 16-bit units. Caution When the BFEEn bit = 1, a compare match occurs on starting the timer in the compare register mode because the values of both the TM2x and CVPEn0 registers are 0 after reset (TM2x = timer/counter selected by TB1En and TB0En bits, n = 1 to 4). After that, the value of the sub register (CVSEn0) is written to the main register (CVPEn0). 15 CVPE10 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF652H Initial value 0000H 15 CVPE20 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF656H Initial value 0000H 15 CVPE30 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF65AH Initial value 0000H 15 CVPE40 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF65EH Initial value 0000H User's Manual U14492EJ5V0UD 333 CHAPTER 9 TIMER/COUNTER FUNCTION (4) Timer 2 sub-channel n sub capture/compare register (CVSEn0) (n = 1 to 4) The CVSEn0 register is a sub-channel n 16-bit sub capture/compare register. In the compare register mode, this register can be used as a buffer. In the capture register mode, this register captures the value of TM20 when the BFEEn bit of the CMSEm0 register = 0 (m = 12, 34). If the capture register mode is selected in the 32-bit mode (value of TB1En and TB0En bits of CMSEm0 register = 11B), this register captures the contents of TM20 (lower 16 bits). The CVSEn0 register can be written only in the compare register mode. If this register is written in the capture register mode, the contents written to CVSEn0 register will be lost. This register can be read/written in 16-bit units. Caution When the BFEEn bit = 1, a compare match occurs on starting the timer in the compare register mode because the values of both the TM2x and CVPEn0 registers are 0 after reset (TM2x = timer/counter selected by TB1En and TB0En bits, n = 1 to 4). After that, the value of the sub register (CVSEn0) is written to the main register (CVPEn0). 15 CVSE10 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF650H Initial value 0000H 15 CVSE20 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF654H Initial value 0000H 15 CVSE30 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF658H Initial value 0000H 15 CVSE40 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF65CH Initial value 0000H (5) Timer 2 sub-channel 5 capture/compare register (CVSE50) The CVSE50 register is a sub-channel 5 16-bit capture/compare register. In the capture register mode, it captures the count value of TM21. In the compare register mode, it detects match with TM21. This register can be read/written in 16-bit units. 15 CVSE50 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF662H Initial value 0000H 334 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.3.4 Control registers (1) Timer 1/timer 2 clock selection register (PRM02) The PRM02 register is used to select the base clock (fCLK) of timer 1 and timer 2. This register can be read/written in 8-bit or 1-bit units. Caution Always set this register before using timer 1 and timer 2. 7 PRM02 0 6 0 5 0 4 0 3 0 2 0 1 0 0 PRM2 Address FFFFF5D8H Initial value 00H Bit position 0 Bit name PRM2 Function Specifies the base clock (fCLK) of timer 1 and timer 2 0: fCLK = fXX/4 1: fCLK = fXX/2 Note . Note Set the VSWC register to 15H when the PRM2 bit of the timer 1/timer 2 clock selection register (PRM02) = 0B (fCLK = fXX/4) and set the VSWC register to 12H when the PRM2 bit = 1B (fCLK = fXX/2). Remark fXX: Internal system clock n = 0, 1 (2) Timer 2 clock stop register 0 (STOPTE0) The STOPTE0 register is used to stop the operation clock input to timer 2. This register can be read/written in 16-bit units. When the higher 8 bits of the STOPTE0 register are used as the STOPTE0H register, and the lower 8 bits are used as the STOPTE0L register, the STOPTE0H register can be read/written in 8-bit or 1-bit units, and the STOPTE0L register is read-only, in 8-bit units. Cautions 1. Initialize timer 2 when the STFTE bit = 0. Timer 2 cannot be initialized when the STFTE bit = 1. 2. If, following initialization, the value of the STFTE bit is made "1", the initialized state is maintained. <15> 14 STOPTE0 STFTE 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Address FFFFF640H Initial value 0000H Bit position 15 Bit name STFTE Stops the operation clock to timer 2. 0: Normal operation 1: Stop operation clock to timer 2 Function User's Manual U14492EJ5V0UD 335 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Timer 2 count clock/control edge selection register 0 (CSE0) The CSE0 register is used to specify the TM2n count clock and the control valid edge (n = 0, 1). This register can be read/written in 16-bit units. When the higher 8 bits of the CSE0 register are used as the CSE0H register, and the lower 8 bits are used as the CSE0L register, they can be read/written in 8-bit or 1-bit units. (1/2) 15 CSE0 0 14 0 13 0 12 0 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF642H Initial value 0000H TES1E1 TES1E0 TES0E1 TES0E0 CESE1 CESE0 CSE12 CSE11 CSE10 CSE02 CSE01 CSE00 Bit position 11, 10, 9, 8 Bit name TESnE1, TESnE0 TESnE1 0 0 1 1 TESnE0 0 1 0 1 Function Specifies the valid edge of the TM2n internal count clock (TCOUNTEn) signal. Valid edge Falling edge Rising edge Setting prohibited Both rising and falling edges Note 7, 6 CESE1, CESE0 Specifies the valid edge of the TM2n external clear input (TCLR2). CESE1 0 0 1 1 CESE0 0 1 0 1 Falling edge Rising edge Valid edge Through input (no clear operation) Both rising and falling edges 5 to 3, 2 to 0 CSEn2, CSEn1, CSEn0 Selects internal count clock (TCOUNTEn) of TM2n. CSEn2 0 0 0 0 1 1 1 1 CSEn1 0 0 1 1 0 0 1 1 CSEn0 0 1 0 1 0 1 0 1 fCLK/2 fCLK/4 fCLK/8 fCLK/16 fCLK/32 fCLK/64 fCLK/128 Note 1 Count clock Selects input signal from external clock input pin (TI2) as clock. 336 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Note Setting the TESnE1 and TESnE0 bits to 11B and the CSEn2 to CSEn0 bits to 000B for timer 2 count clock/control edge select register 0 (CSE0) is prohibited. Caution Set the VSWC register to 15H when the PRM2 bit of the timer 1/timer 2 clock selection register (PRM02) = 0B (fCLK = fXX/4) and set the VSWC register to 12H when the PRM2 bit = 1B (fCLK = fXX/2). Remark n = 0, 1 fCLK: Base clock (4) Timer 2 sub-channel input event edge selection register 0 (SESE0) The SESE0 register specifies the valid edge of the external capture signal input (TINEn) for the sub-channel n capture/compare register performing capture (n = 0 to 5). This register can be read/written in 16-bit units. When the higher 8 bits of the SESE0 register are used as the SESE0H register, and the lower 8 bits are used as the SESE0L register, they can be read/written in 8-bit or 1-bit units. 15 SESE0 0 14 0 13 0 12 0 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF644H Initial value 0000H IESE51 IESE50 IESE41 IESE40 IESE31 IESE30 IESE21 IESE20 IESE11 IESE10 IESE01 IESE00 Bit position 11 to 0 Bit name IESEn1, IESEn0 Function Specifies the valid edge of external capture signal input (TINEn) for sub-channel n capture/compare register performing capture. IESEn1 0 0 1 1 IESEn0 0 1 0 1 Falling edge Rising edge Setting prohibited Valid edge Both rising and falling edges Remark n = 0 to 5 User's Manual U14492EJ5V0UD 337 CHAPTER 9 TIMER/COUNTER FUNCTION (5) Timer 2 time base control register 0 (TCRE0) The TCRE0 register controls the operation of TM2n (n = 0, 1). This register can be read/written in 16-bit units. When the higher 8 bits of the TCRE0 register are used as the TCRE0H register, and the lower 8 bits are used as the TCRE0L register, they can be read/written in 8-bit or 1-bit units. Cautions 1. If ECREn = 1 and ECEEn = 1 have been set, it is not possible to input an external clear signal (TCLR2) for TM2n. In this case, first set CLREn = 1, and then clear TM2n by software (n = 0, 1). 2. When clearing is performed using the ECLR signal, the TM2n counter is cleared with a delay of (1 internal count clock set with bits CSEn2 to CSEn0 of the CSE0 register) + 2 base clocks. Therefore, if external clock input is selected as the internal count clock, the counter is not cleared until the external clock (TI2) is input. 3. The ECREn bit and the ECEEn bit cannot be set to 1. 4. If the ECEEn bit is set to 1 and the ECREn bit is set to 0, a down count operation cannot be performed. 5. When UDSEn1, UDSEn0 = 01 and OSTEn = 1, the counter does not count up when the counter value is 0. Therefore, when the counter value is 0, set OSTEn = 0, and after the value of the counter ceases to be 0, set OSTEn = 1. Also, on the application, change the value of OSTEn from 0 to 1 using the sub-channels 0 and 5 interrupt signals. 6. When the TM2n count value is cleared (0) by setting CLREn to 1, the CLREn = 1 setting must be held for at least one of the internal count clocks set by the CSEn2 to CSEn0 bits of the CSE0 register. Example When timer 20 (TM20) is cleared (0) <1> Select fCLK/2 as TM20 internal count clock 15 CSE0 0 14 0 13 0 12 0 11 x 10 x 9 x 8 x 7 x 6 x 5 x 4 x 3 x 2 0 1 0 0 0 <2> Clear (0) the TM20 count value 7 TCRE0L 0 6 1 5 0 4 0 3 0 2 x 1 x 0 x <3> Set the conditions required for the TM20 count clock 15 CSE0 x 14 x 13 x 12 x 11 x 10 x 9 x 8 x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 x <4> Start the TM20 count operation 7 TCRE0L 0 6 0 5 1 4 0 3 0 2 x 1 x 0 x 338 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (1/2) 15 <14> <13> 12 11 10 9 8 7 0 <6> <5> 4 3 2 1 0 Address FFFFF646H Initial value 0000H TCRE0 CASE1 CLRE1 CEE1 ECRE1 ECEE1 OSTE1 UDSE11 UDSE10 CLRE0 CEE0 ECRE0 ECEE0 OSTE0 UDSE01 UDSE00 Bit position 15 Bit name CASE1 Function Specifies 32-bit cascade operation mode for TM21 (TM21 counts upon overflow of TM20 (carry count)). 0: Not connected in cascade Note 1 Notes 2, 3 1: 32-bit cascade operation mode Notes 1. TM21 counts at CT signal input in the count enabled state. 2. TM21 counts at CTC and CASC signal inputs in the count enabled state. 3. Only the capture register mode can be used for the capture/compare register. Cautions 1. When CASE1 = 1, set the TByE1 and TByE0 bits of the CMSEx0 register to 11 (x = 12, 34, y: When x = 12, y = 1, 2, and when x = 34, y = 3, 4). 2. When CASE1 = 0, TCOUNTE1 is selected as the count of TM21. When CASE1 = 1, TCOUNTE0 and the TM20 overflow signal are selected as the count of TM21. 14, 6 CLREn Specifies software clear for TM2n. 0: TM2n operation continued 1: TM2n count value cleared (0) Caution Do not perform the software clear and hardware clear operations simultaneously. 13, 5 CEEn Specifies TM2n count operation enable/disable. 0: Count operation stopped 1: Count operation enabled 12, 4 ECREn Specifies TM2n external clear (TCLR2) operation enable/disable via ECLR signal input. 0: TM2n external clear (TCLR2) operation not enabled 1: TM2n external clear (TCLR2) operation enabled Cautions 1. In the 32-bit cascade operation mode (CASE1 = 1), the TM2n external clear operation is not performed. 2. When the count value is cleared by inputting the ECLR signal while ECREn = 1, the ECREn = 1 setting must be held for at least one of the internal count clocks set by the CSEn2 to CSEn0 bits of the CSE0 register. 3. In the 32-bit cascade operation mode (CASE1 = 1), only TM21 is affected by the ECREn bit setting. Remark n = 0, 1 User's Manual U14492EJ5V0UD 339 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position 11, 3 Bit name ECEEn Function Specifies TM2n count operation enable/disable through ECLR signal input. 0: TM2n count operation not enabled 1: TM2n count operation enabled Cautions 1. In the 32-bit cascade operation mode (CASE1 = 1), the TM2n count operation using ECLR signal input is not performed. 2. When the ECEEn bit = 1, always set the CESE1 and CESE0 bits of the CSE0 register to 10 (through input). 3. In the 32-bit cascade operation mode (CASE1 = 1), only TM21 is affected by the ECEEn bit setting. 10, 2 OSTEn Specifies stop mode. 0: TM2n count stopped when count value is 0. 1: TM2n count not stopped when count value is 0. Caution When the TM2n count stop is cancelled when the OSTE1n bit = 1 (TM2n count is stopped when the count value is 0), TM2n counts up except when the UDSEn1, UDSEn0 bits = 10. The count direction when the UDSEn1 and UDSEn0 bits = 10 is determined by the value of ECLR. 9, 8, 1, 0 UDSEn1, UDSEn0 UDSEn1 0 UDSEn0 0 Perform only up count. Clear TM2n with compare match signal. 0 1 Count up after TM2n has become 0, and count down after a compare match occurs for sub-channels 0, 5 (triangular wave up/down count). 1 0 Selects up/down count according to the ECLR signal input. Up count when ECLR = 1 Down count when ECLR = 0 1 1 Setting prohibited Count Specifies TM2n up/down count. Cautions 1. In the 32-bit cascade operation mode (CASE1 bit = 1), set the UDSEn1 and UDSEn0 bits to 00. 2. When the UDSEn1 and UDSEn0 bits = 10, be sure to set the CESE1 and CESE0 bits of the CSE0 register to 10 (through input). 3. When the UDSEn1 and UDSEn0 bits = 10, compare match between TM2n and CVSEx0 has no effect on the TM2n count operation (x: 0 when n = 0, 5 when n = 1). Remark n = 0, 1 340 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (6) Timer 2 output control register 0 (OCTLE0) The OCTLE0 register controls timer output from the TO2n pin (n = 1 to 4). This register can be read/written in 16-bit units. When the higher 8 bits of the OCTLE0 register are used as the OCTLE0H register, and the lower 8 bits are used as the OCTLE0L register, they can be read/written in 8-bit or 1-bit units. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF648H Initial value 0000H OCTLE0 SWFE ALVE OTME OTME SWFE ALVE OTME OTME SWFE ALVE OTME OTME SWFE ALVE OTME OTME 4 4 41 40 3 3 31 30 2 2 21 20 1 1 11 10 Bit position 15, 11, 7, 3 Bit name SWFEn Function Fixes the TO2n pin output level according to the setting of ALVEn bit. 0: Don't fix output level. 1: When ALVEn = 0, fix output level to low level. When ALVEn = 1, fix output level to high level. 14, 10, 6, 2 ALVEn Specifies the active level of the TO2n pin output. 0: Active level is high level 1: Active level is low level 13, 12, 9, 8, 5, 4, 1, 0 OTMEn1, OTMEn0 Specifies toggle mode. OTMEn1 0 OTMEn0 0 Toggle mode 0: Toggle mode Reverse output level of TO2n output every time a subchannel n compare match occurs. 0 1 Toggle mode 1: Upon sub-channel n compare match, set TO2n output to active level, and when TM20 is "0", set TO2n output to inactive level. 1 0 Toggle mode 2: Upon sub-channel n compare match, set TO2n output to active level, and when TM21 is "0", set TO2n output to inactive level. 1 1 Toggle mode 3: Upon sub-channel n compare match, set TO2n output to active level, and upon sub-channel n + 1 compare match, set TO2n output to inactive level (when n = "4", n + 1 becomes "1"). Cautions 1. When the OTMEn1, OTMEn0 bits = 11 (toggle mode 3), if the same output delay operation settings are made when setting bits ODLEn2 to ODLEn0 of the ODELE0 register, two outputs change simultaneously upon 1 sub-channel n compare match. 2. If two or more signals are input simultaneously to the same output circuit, S/T signal input has a higher priority than RA, RB, and RN signal inputs. Remark n = 1 to 4 User's Manual U14492EJ5V0UD 341 CHAPTER 9 TIMER/COUNTER FUNCTION (a) Caution for PWM output change timing If the SWFEn bit is changed from 1 to 0 when the timer is operating while the internal PWM output operation is being performed, then the output level becomes active. After that, PWM output from the TO2n pin is performed upon a compare match at subchannel n. However, the first PWM output change timing varies as follows, depending on the internal output level and the SWFEn bit clear timing. Figure 9-65. PWM Output Change Timing (i) Example 1 Internal output level SWFEn bit TO2n output (ALVEn bit = 1) PWM output change timing (ii) Example 2 Internal output level SWFEn bit TO2n output (ALVEn bit = 1) PWM output change timing Remark n = 1 to 4 342 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (7) Timer 2 sub-channel 0, 5 capture/compare control register (CMSE050) The CMSE050 register controls timer 2 sub-channel 0 capture/compare register (CVSE00) and timer 2 subchannel 5 capture/compare register (CVSE50). This register can be read/written in 16-bit units. 15 CMSE050 0 14 0 13 EEVE5 12 0 11 10 9 0 8 0 7 0 6 0 5 EEVE0 4 0 3 2 1 0 0 0 Address FFFFF64AH Initial value 0000H LNKE5 CCSE5 LNKE0 CCSE0 Bit position 13, 5 Bit name EEVEn Function Enables/disables event detection by sub-channel n capture/compare register. 0: ED1 and ED2 signal inputs ignored (nothing is done even if these signals are input). 1: Operation caused by ED1 and ED2 signal inputs enabled. 11, 3 LNKEn Specifies capture event signal input from edge selection to ED1 or ED2. 0: In capture register mode, select ED1 signal input. In compare register mode, LNKEn bit has no influence. 1: In capture register mode, select ED2 signal input. In compare register mode, LNKEn bit has no influence. 10, 2 CCSEn Selects capture/compare register operation mode. 0: Operate in capture register mode. The TM20 and TM21 count statuses can be read with sub-channel 0 and sub-channel 5, respectively. 1: Operate in compare register mode. TM2m is cleared upon detection of match between sub-channel n and TM2m. Remark m = 0, 1 n = 0, 5 User's Manual U14492EJ5V0UD 343 CHAPTER 9 TIMER/COUNTER FUNCTION (8) Timer 2 sub-channel 1, 2 capture/compare control register (CMSE120) The CMSE120 register controls the timer 2 sub-channel n sub capture/compare register (CVSEn0) and the timer 2 sub-channel n main capture/compare register (CVPEn0) (n = 1, 2). This register can be read/written in 16-bit units. (1/2) 15 CMSE120 0 14 0 13 12 11 10 9 8 7 0 6 0 5 4 3 2 1 0 Address FFFFF64CH Initial value 0000H EEVE2 BFEE2 LNKE2 CCSE2 TB1E2 TB0E2 EEVE1 BFEE1 LNKE1 CCSE1 TB1E1 TB0E1 Bit position 13, 5 Bit name EEVEn Function Enables/disables event detection for CMSE120 register. 0: ED1 and ED2 signal inputs ignored (nothing is done even if these signals are input). 1: Operation caused by ED1 and ED2 signal inputs enabled. 12, 4 BFEEn Specifies the buffer operation of sub-channel n sub capture/compare register (CVSEn0). 0: Don't use sub-channel n sub capture/compare register (CVSEn0) as buffer. 1: Use sub-channel n sub capture/compare register (CVSEn0) as buffer. Caution When the BFEEn bit = 1, a compare match occurs on starting the timer in the compare register mode because the values of both the TM2x and CVPEn0 registers are 0 after reset (TM2x = timer/counter selected by TB1En and TB0En bits, n = 1 to 4). After that, the value of the sub register (CVSEn0) is written to the main register (CVPEn0). Remarks 1. The operations in the capture register mode and compare register mode when the sub-channel n sub capture/compare register (CVSEn0) is not used as a buffer are shown below. * In capture register mode: The CPU can read both the master register (CVPEn0) and slave register (CVSEn0). The next event is ignored until the CPU finishes reading the master register. TM20 capture is performed by the slave register, and TM21 capture is performed by the master register. * In compare register mode: The CPU writes to the slave register (CVSEn0), and immediately after, the same contents as those of the slave register are written to the master register (CVPEn0). 2. The operations in the capture register mode and compare register mode when the sub-channel n sub capture/compare register (CVSEn0) is used as a buffer are shown below. * In capture register mode: When the CPU reads the master register (CVPEn0), the master register updates the value held by the slave register (CVSEn0) immediately before the CPU read operation. When a capture event occurs, the timer/counter value at that time is always saved in the slave register. * In compare register mode: The CPU writes to the slave register (CVSEn0) and these contents are transferred to the master register (CVPEn0) set with the LNKEn bits. Remark n = 1, 2 344 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position 11, 3 Bit name LNKEn Function Selects capture event signal input from edge selection and specifies transfer operation in compare register mode. 0: Select ED1 signal input in capture register mode. In the compare register mode, the data of the CVSEn0 register is transferred to the CVPEn0 register upon occurrence of TM2x compare match (TM2x = timer/ counter selected with bits TB1En, TB0En). 1: Select ED2 signal input in capture register mode. In the compare register mode, the data of the CVSEn0 register is transferred to the CVPEn0 register when the TM2x count value becomes "0" (TM2x = timer/ counter selected with bits TB1En, TB0En). 10, 2 CCSEn Selects capture/compare register operation mode. 0: Capture register mode 1: Compare register mode 9, 8, 1, 0 TB1En, TB0En Sets sub-channel n timer/counter. TB1En 0 0 1 1 TB0En 0 1 0 1 Sub-channel n timer/counter Don't use sub-channel n. Set TM20 to sub-channel n. Set TM21 to sub-channel n. 32-bit mode Note (select both TM20 and TM21.) Note In the 32-bit mode, influence of the BFEEn bit is ignored. Also, the CVSEn0 register cannot be used as a buffer in this mode. Caution When the TB1En, TB0En bits are set to "11", set the CASE1 bit of the TCRE0 register to "1". Remark n = 1, 2 User's Manual U14492EJ5V0UD 345 CHAPTER 9 TIMER/COUNTER FUNCTION (9) Timer 2 sub-channel 3, 4 capture/compare control register (CMSE340) The CMSE340 register controls the timer 2 sub-channel n sub capture/compare register (CVSEn0) and the timer 2 sub-channel n main capture/compare register (CVPEn0) (n = 3, 4). This register can be read/written in 16-bit units. (1/2) 15 CMSE340 0 14 0 13 12 11 10 9 8 7 0 6 0 5 4 3 2 1 0 Address FFFFF64EH Initial value 0000H EEVE4 BFEE4 LNKE4 CCSE4 TB1E4 TB0E4 EEVE3 BFEE3 LNKE3 CCSE3 TB1E3 TB0E3 Bit position 13, 5 Bit name EEVEn Function Enables/disables event detection by CMSE340 register. 0: ED1 and ED2 signal inputs ignored (nothing is done even if these signals are input). 1: Operation caused by ED1 and ED2 signal inputs enabled. 12, 4 BFEEn Specifies the sub-channel n sub capture/compare register (CVSEn0) buffer operation. 0: Don't use sub-channel n sub capture/compare register (CVSEn0) as buffer. 1: Use sub-channel n sub capture/compare register (CVSEn0) as buffer. Caution When the BFEEn bit = 1, a compare match occurs on starting the timer in the compare register mode because the values of both the TM2x and CVPEn0 registers are 0 after reset (TM2x = timer/counter selected by TB1En and TB0En bits, n = 1 to 4). After that, the value of the sub register (CVSEn0) is written to the main register (CVPEn0). Remarks 1. The operations in the capture register mode and compare register mode when the sub-channel n sub capture/compare register (CVSEn0) is not used as a buffer are shown below. * In capture register mode: The CPU can read both the master register (CVPEn0) and slave register (CVSEn0). The next event is ignored until the CPU finishes reading the master register. TM20 capture is performed by the slave register, and TM21 capture is performed by the master register. * In compare register mode: The CPU writes to the slave register (CVSEn0), and immediately after, the same contents as those of the slave register are written to the master register (CVPEn0). 2. The operations in the capture register mode and compare register mode when the sub-channel n sub capture/compare register (CVSEn0) is used as a buffer are shown below. * In capture register mode: When the CPU reads the master register (CVPEn0), the master register updates the value held by the slave register (CVSEn0) immediately before the CPU read operation. When a capture event occurs, the timer/counter value at that time is always saved in the slave register. * In compare register mode: The CPU writes to the slave register (CVSEn0) and these contents are transferred to the master register (CVPEn0) set with the LNKEn bits. Remark n = 3, 4 346 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position 11, 3 Bit name LNKEn Function Selects capture event signal input from edge selection and specifies transfer operation in compare register mode. 0: Select ED1 signal input in capture register mode. In the compare register mode, the data of the CVSEn0 register is transferred to the CVPEn0 register upon occurrence of TM2x compare match (TM2x = timer/ counter selected with bits TB1En, TB0En). 1: Select ED2 signal input in capture register mode. In the compare register mode, the data of the CVSEn0 register is transferred to the CVPEn0 register when the TM2x count value becomes "0" (TM2x = timer/ counter selected with bits TB1En, TB0En). 10, 2 CCSEn Selects capture/compare register operation mode. 0: Capture register mode 1: Compare register mode 9, 8, 1, 0 TB1En, TB0En TB1En 0 0 1 1 TB0En 0 1 0 1 Sub-channel n timer/counter Don't use sub-channel n. Set TM20 to sub-channel n. Set TM21 to sub-channel n. 32-bit mode Note Sets sub-channel n timer/counter. (select both TM20 and TM21.) Note In the 32-bit mode, influence of the BFEEn bit is ignored. Also, the CVSEn0 register cannot be used as a buffer in this mode. Caution When the TB1En, TB0En bits are set to "11", set the CASE1 bit of the TCRE0 register to "1". Remark n = 3, 4 User's Manual U14492EJ5V0UD 347 CHAPTER 9 TIMER/COUNTER FUNCTION (10) Timer 2 time base status register 0 (TBSTATE0) The TBSTATE0 register indicates the status of TM2n (n = 0, 1). This register can be read/written in 16-bit units. When the higher 8 bits of the TBSTATE0 register are used as the TBSTATE0H register, and the lower 8 bits are used as the TBSTATE0L register, they can be read/written in 8-bit or 1-bit units. Caution The ECFEn, RSFEn, and UDFEn bits are read-only bits. 15 TBSTATE0 0 14 0 13 0 12 <11> <10> <9> <8> 0 OVFE1 ECFE1 RSFE1 UDFE1 7 0 6 0 5 0 4 0 <3> <2> <1> <0> OVFE0 ECFE0 RSFE0 UDFE0 Address FFFFF664H Initial value 0101H Bit position 11, 3 Bit name OVFEn Indicates TM2n overflow status. 0: No overflow 1: Overflow Caution Function If write access to the TBSTATE0 register is performed while overflow is not detected, the OVFEn bit is cleared (0). 10, 2 ECFEn Indicates the ECLR signal input status. 0: Low level 1: High level 9, 1 RSFEn Indicates the TM2n count status. 0: TM2n is not counting. 1: TM2n is counting (either up or down) 8, 0 UDFEn Indicates the TM2n up/down count status. 0: TM2n is in the down-count mode. 1: TM2n is in the up-count mode. Remark n = 0, 1 348 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (11) Timer 2 capture/compare 1 to 4 status register 0 (CCSTATE0) The CCSTATE0 register indicates the status of the timer 2 sub-channel sub capture/compare register (CVSEn0) and the timer 2 sub-channel main capture/compare register (CVPEn0) (n = 1 to 4). This register can be read/written in 16-bit units. When the higher 8 bits of the CCSTATE0 register are used as the CCSTATE0H register, and the lower 8 bits are used as the CCSTATE0L register, they can be read/written in 8-bit or 1-bit units. Caution The BFFEn1 and BFFEn0 bits are read-only bits. 15 <14> 13 CCSTATE0 0 12 11 <10> 9 0 8 7 0 <6> 5 4 3 0 <2> 1 0 Address FFFFF666H Initial value 0000H CEFE4 BFFE41 BFFE40 CEFE3 BFFE31 BFFE30 CEFE2 BFFE21 BFFE20 CEFE1 BFFE11 BFFE10 Bit position 14, 10, 6, 2 Bit name CEFEn Function Indicates the capture/compare event occurrence status. 0: In capture register mode: No capture operation has occurred. In compare register mode: No compare match has occurred. 1: In capture register mode: At least one capture operation has occurred. In compare register mode: At least one compare match has occurred. Caution The CEFEn bit can be cleared (0) by performing write access to the CCSTATE0 register while no capture operation or compare match occurs. When bit manipulation is performed for the CEFE1 (CEFE3) bit and the CEFE2 (CEFE4) bit, both bits are cleared. 13, 12, 9, 8, 5, 4, 1, 0 BFFEn1, BFFEn0 Indicates the capture buffer status. BFFEn1 0 0 BFFEn0 0 1 Capture buffer status No value in buffer Sub-channel n master register (CVPEn0) contains a capture value. Slave register (CVSEn0) does not contain a value. 1 0 Both sub-channel n master register (CVPEn0) and slave register (CVSEn0) contain a capture value. 1 Caution 1 Unused The BFFEn1 and BFFEn0 bits return a value only when sub-channel n sub capture/compare register (CVSEn0) buffer operation (bit BFEEn of CMSEm0 register = 1) is selected or when capture register mode (bit CCSEn of CMSEm0 register = 0) is selected. "0" is read when the compare register mode (CCSEn bit = 1) is selected. Remark m = 12, 34 n = 1 to 4 User's Manual U14492EJ5V0UD 349 CHAPTER 9 TIMER/COUNTER FUNCTION (12) Timer 2 output delay register 0 (ODELE0) The ODELE0 register sets the output delay operation synchronized with the clock to the TO2n pin's output delay circuit (n = 1 to 4). This register can be read/written in 16-bit units. When the higher 8 bits of the ODELE0 register are used as the ODELE0H register, and the lower 8 bits are used as the ODELE0L register, they can be read/written in 8-bit or 1-bit units. 15 ODELE0 0 14 13 12 11 0 10 9 8 7 0 6 5 4 3 0 2 1 0 Address FFFFF668H Initial value 0000H ODLE42 ODLE41 ODLE40 ODLE32 ODLE31 ODLE30 ODLE22 ODLE21 ODLE20 ODLE12 ODLE11 ODLE10 Bit position 14 to 12, 10 to 8, 6 to 4, 2 to 0 Bit name ODLEn2, ODLEn1, ODLEn0 Specifies output delay operation. Function ODLEn2 0 0 0 0 1 1 1 1 ODLEn1 0 0 1 1 0 0 1 1 ODLEn0 0 1 0 1 0 1 0 1 Set output delay operation Don't perform output delay operation. Set output delay of 1 system clock. Set output delay of 2 system clocks. Set output delay of 3 system clocks. Set output delay of 4 system clocks. Set output delay of 5 system clocks. Set output delay of 6 system clocks. Set output delay of 7 system clocks. Remark The ODLEn2, ODLEn1, and ODLEn0 bits are used for EMI countermeasures. Remark n = 1 to 4 350 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (13) Timer 2 software event capture register (CSCE0) The CSCE0 register sets capture operation by software in the capture register mode. This register can be read/written in 16-bit units. 15 CSCE0 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 4 3 2 1 0 Address FFFFF66AH Initial value 0000H SEVE5 SEVE4 SEVE3 SEVE2 SEVE1 SEVE0 Bit position 5 to 0 Bit name SEVEn Function Specifies capture operation by software in capture register mode. 0: Continue normal operation. 1: Perform capture operation. Cautions 1. The SEVEn bit ignores the settings of the EEVEn and the LNKEn bits of the CMSEm0 register. 2. The SEVEn bit is automatically cleared (0) at the end of an event. 3. The SEVEn bit ignores all the internal limitation statuses of the timer 2 unit. Remark m = 12, 34, 05 n = 0 to 5 User's Manual U14492EJ5V0UD 351 CHAPTER 9 TIMER/COUNTER FUNCTION 9.3.5 Operation (1) Edge detection The edge detection timing is shown below. Figure 9-66. Edge Detection Timing fCLK Note 00B 01B 10B 11B TINEx, TCLR2, TCOUNTEn MUXTB0 CT ED1, ED2 ECLR Note Set values of TESnE1, TESnE0 bits and CESE1, CESE0 bits of CSE0 register, and IESEx1, IESEx0 bits of SESE0 register. Remarks 1. fCLK: Base clock 2. CT: TM2n count signal input in the 16-bit mode ECLR: External control signal input from TCLR2 input ED1, ED2: Capture event signal input from edge selector MUXTB0: TM20 multiplex signal TCOUNTEn: Timer 2 count enable signal input TINEx: Timer 2 sub-channel x capture event signal input 3. n = 0, 1 x = 0 to 5 352 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (2) Basic operation of timer 2 Figures 9-67 to 9-70 show the basic operation of timer 2. Figure 9-67. Timer 2 Up-Count Timing (When TCRE0 Register's UDSEn1, UDSEn0 Bits = 00B, ECEEn Bit = 0, ECREn Bit = 0, CLREn Bit = 0, CASE1 Bit = 0) fCLK OSTEn bitNote 1 CEEn bitNote 1 CT CNT RNote 2 INTTM2n (output) CNT = 0 FFFDH (Stop) FFFEH FFFFH 0000H 1234H 1235H 0000H (Stop) Notes 1. 2. Bits OSTE, CEE of TCRE0 register Can control TM20/TM21 clear by sub-channel 0/5 compare match or count direction. Remarks 1. fCLK: Base clock 2. CNT: Count value of timer 2 CT: TM2n count signal input in 16-bit mode R: Compare match signal input (sub-channel 0/5) 3. n = 0, 1 User's Manual U14492EJ5V0UD 353 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-68. External Control Timing of Timer 2 (When TCRE0 Register's UDSEn1, UDSEn0 Bits = 00B, OSTEn Bit = 0, CEEn Bit = 1, CASE1 Bit = 0) fCLK CT ECEEn bitNote ECREn bitNote CLREn bitNote ECLR CNT 1234H 1235H 0000H 0001H 0000H Note Bits ECEEn, ECREn, CLREn of TCRE0 register Remarks 1. fCLK: Base clock 2. CNT: Count value of timer 2 CT: TM2n count signal input in 16-bit mode ECLR: External control signal input from TCLR2 pin input 3. n = 0, 1 354 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-69. Operation in Timer 2 Up-/Down-Count Mode (When TCRE0 Register's ECEEn Bit = 0, ECREn Bit = 0, CLREn Bit = 0, OSTEn Bit = 0, CEEn Bit = 1, CASE1 Bit = 0) fCLK CT UDSEn1, UDSEn0 bitsNote 1 ECLR RNote 2 CNT FFFEH INTTM2n (output) CNT = 0 FFFFH 0000H 0001H 0002H 0001H 0000H 0001H 0002H 0003H 0002H 01B don't care 10B Notes 1. 2. UDSEn1, UDSEn0 bits of TCRE0 register Can control TM20/TM21 clear by sub-channel 0/5 compare match or count direction. Remarks 1. fCLK: Base clock 2. CNT: Count value of timer 2 CT: TM2n count signal input in 16-bit mode ECLR: External control signal input from TCLR2 pin input R: Compare match signal input (sub-channel 0/5) 3. n = 0, 1 User's Manual U14492EJ5V0UD 355 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-70. Timing in 32-Bit Cascade Operation Mode (When TCRE0 Register's UDSEn1, UDSEn0 Bits = 00B, ECEEn Bit = 0, ECREn Bit = 0, CLREn Bit = 0, OSTEn Bit = 0, CEEn Bit = 1, CASE1 Bit = 1) fCLK CTC CASCNote[TB1] CNT[TB0] CNT[TB1] FFFBH FFFCH FFFDH FFFEH FFFFH 0000H 0001H 0002H 1235H 0003H 0004H 1234H Note If, in the 32-bit mode, CASC (CNT = MAX. for TM20) is input to TM21 and the CTC rising edge is detected, TM21 performs count operation. Remarks 1. fCLK: Base clock 2. CASC: TM21 count signal input in 32-bit mode CNT: Count value of timer 2 CTC: TM21 count signal input in 32-bit mode TB0: Count value of TM20 TB1: Count value of TM21 3. n = 0, 1 356 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (3) Operation of capture/compare register (sub-channels 1 to 4) Sub-channels 1 to 4 receive the count value of the timer 2 multiplex count generator. The multiplex count generator is an internal unit of TM2n that supplies the multiplex count value MUXCNT to sub-channels 1 to 4. The count value of TM20 is output to sub-channels 1 to 4 at the rising edge of MUXTB0, and the count value of TM21 is output to sub-channels 1 to 4 at the rising edge of MUXTB1. Figure 9-71 shows the block diagram of the timer 2 multiplex count generator, and Figure 9-72 shows the multiplex count timing. Figure 9-71. Block Diagram of Timer 2 Multiplex Count Generator fCLK Multiplex control MUXTB0 (to sub-channel m capture/compare register) MUXTB1 (to sub-channel m capture/compare register) CNT (from TM20) CNT (from TM21) Timer 2 multiplex count generator MUXCNT (to sub-channel m capture/compare register) Remarks 1. fCLK: Base clock 2. CNT: Count value of timer 2 MUXTB0, MUXTB1: Multiplex signal of TM20, TM21 MUXCNT: Count value to sub-channel m 3. m = 1 to 4 User's Manual U14492EJ5V0UD 357 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-72. Multiplex Count Timing fCLK CNT (0) CNT (1) MUXTB0 MUXTB1 MUXCNT FFFEH 1234H FFFFH 1234H FFFFH 1234H FFFFH 1234H 0000H 1235H 0000H 1235H 0000H 1235H 0001H 1235H 0001H 1235H 0001H FFFEH 1234H FFFFH 0000H 1235H 0001H TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 Remarks 1. fCLK: Base clock 2. CNT: Count value of timer 2 MUXTB0, MUXTB1: Multiplex signal of TM20, TM21 MUXCNT: Count value to sub-channel m (m = 1 to 4) TB0: Count value of TM20 TB1: Count value of TM21 Figures 9-73 to 9-78 show the operation of the capture/compare register (sub-channels 1 to 4). 358 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-73. Capture Operation: 16-Bit Buffer-Less Mode (When Operation Is Delayed Through Setting of LNKEy Bit of CMSEx0 Register, and CMSEx0 Register's CCSEy Bit = 0, BFEEy Bit = 0, EEVEy Bit = 1, and CSCE0 Register's SEVEy Bit = 0) fCLK MUXTB0 MUXTB1 MUXCNT TB0Ey bitNote 1 TB1Ey bitNote 1 LNKEy bitNote 1 ED1 ED2 CAPTURE_P CAPTURE_S READ_ENABLE_P CVPEm0 register CVSEm0 register Undefined 2 Undefined 4 11 13 Note 2 Note 2 1 6 2 7 3 8 4 9 5 10 6 11 7 12 8 13 9 14 10 5 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 Notes 1. 2. Bits TB0Ey, TB1Ey of CMSEx register If an event occurs in this timing, it is ignored. Remarks 1. fCLK: Base clock 2. CAPTURE_P: Capture trigger signal of main capture register CAPTURE_S: Capture trigger signal of sub capture register ED1, ED2: Capture event signal input from edge selector MUXCNT: Count value to sub-channel m MUXTB0, MUXTB1: Multiplex signal of TM20, TM21 READ_ENABLE_P: Read timing for CVPEm0 register TB0: Count value of TM20 TB1: Count value of TM21 3. m = 1 to 4, x = 12, 34 y: When x = 12, y = 1, 2, and when x = 34, y = 3, 4 User's Manual U14492EJ5V0UD 359 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-74. Capture Operation: Mode with 16-Bit BufferNote 1 (When CMSEx0 Register's TByE1 Bit = 0, TByE0 Bit = 1, CCSEy Bit = 0, LNKEy Bit = 0, BFEEy Bit = 1, EEVEy Bit = 1, and CSCE0 Register's SEVEy Bit = 0) fCLK MUXTB0 MUXTB1 MUXCNT ED1 Event CAPTURE_P CAPTURE_S BUFFER READ_ENABLE_P CVPEm0 register CVSEm0 register Capture Undefined Undefined 2 3 Shift 2 4 Note 3 1 6 2 7 3 8 4 9 5 10 6 11 7 12 8 13 9 14 10 5 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 Note 2 L New event 4 8 Notes 1. To operate TM2n in the mode with 16-bit buffer, perform capture at least twice at the start of operation and read the CVPEm0 register. Also, read the CVPEm0 register after performing capture at least once. 2. 3. Write operation to the CVPEn0 register is not performed at these signal inputs because the CVSEm0 register operates as a buffer. After this timing, write operation from the CVSEm0 register to the CVPEm0 register is enabled. Remarks 1. fCLK: Base clock 2. BUFFER: Timing of write operation from CVSEm0 register to CVPEm0 register CAPTURE_P: Capture trigger signal of main capture register CAPTURE_S: Capture trigger signal of sub capture register ED1: Capture event signal input from edge selector MUXCNT: Count value to sub-channel m MUXTB0, MUXTB1: Multiplex signal of TM20, TM21 READ_ENABLE_P: Read timing of CVPEm0 register TB0: Count value of TM20; TB1: Count value of TM21 3. m = 1 to 4, x = 12, 34 y: When x = 12, y = 1, 2, and when x = 34, y = 3, 4 360 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-75. Capture Operation: 32-Bit Cascade Operation Mode (When CMSEx Register's TByE1 Bit = 1, TByE0 Bit = 1, CCSEy Bit = 0, LNKEy Bit = 0, BFEEy Bit = Arbitrary, EEVEy Bit = 1, and CSCE0 Register's SEVEy Bit = 0) fCLK TCOUNTE0 = TCOUNTE1 CNT (0) CNT (1) CASCNote 1 MUXTB0 MUXTB1 MUXCNT ED1 Note 2 Note 2 FFFEH 1234H FFFFH 0000H 1235H 0001H FFFEH 1234H FFFFH 1234H FFFFH 1234H FFFFH 1234H 0000H 1235H 0000H 1235H 0000H 1235H 0001H 1235H 0001H 1235H 0001H TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 CAPTURE_S CAPTURE_P READ_ENABLE_P CVSEm0 register CVPEm0 register Undefined Undefined Enable the next capture 0000H 1235H 0001H 1235H Note 3 Note 3 Notes 1. 2. 3. TM21 performs count operation when, in the 32-bit mode, CASC (CNT = MAX. for TM20) is input to TM21 and the rising edge of CTC is detected. If an event occurs during this timing, it is ignored. CPU read access is not performed in this timing (wait status). Remarks 1. fCLK: Base clock 2. CAPTURE_P: Capture trigger signal of main capture register CAPTURE_S: Capture trigger signal of sub capture register CASC: TM21 count signal in 32-bit mode CNT: Count value of timer 2 ED1: Capture event signal input from edge selector MUXCNT: Count value to sub-channel m MUXTB0, MUXTB1: Multiplex signal of TM20, TM21 READ_ENABLE_P: Read timing of CVPEm0 register TB0: Count value of TM20 TB1: Count value of TM21 TCOUNTE0, TCOUNTE1: Count enable signal input of timer 2 3. m = 1 to 4, x = 12, 34 y: When x = 12, y = 1, 2, and when x = 34, y = 3, 4 User's Manual U14492EJ5V0UD 361 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-76. Capture Operation: Capture Control by Software and Trigger Timing (When CMSEx0 Register's TByE1 Bit = 0, TByE0 Bit = 1, CCSEy Bit = 0, LNKEy Bit = 0, BFEEy Bit = 1) fCLK MUXTB0 MUXTB1 MUXCNT EEVEy bitNote 1 SEVEy bitNote 2 ED1 CAPTURE_P CAPTURE_S BUFFER CVSEm0 register CVPEm0 register Undefined Undefined 4 4 9 L Event detection by EEVEy bit prohibited Set by software Cleared by timer 6 2 7 3 8 4 9 5 10 6 11 7 12 8 13 9 14 10 5 1 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 Notes 1. 2. EEVEy bit of CMSEx0 register SEVEy bit of CSCE0 register Remarks 1. fCLK: Base clock 2. BUFFER: Timing of write operation from CVSEm0 register to CVPEm0 register CAPTURE_P: Capture trigger signal of main capture register CAPTURE_S: Capture trigger signal of sub capture register ED1: Capture event signal input from edge selector MUXCNT: Count value to sub-channel m MUXTB0, MUXTB1: Multiplex signal of TM20, TM21 TB0: Count value of TM20 TB1: Count value of TM21 3. m = 1 to 4, x = 12, 34 y: When x = 12, y = 1, 2, and when x = 34, y = 3, 4 362 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-77. Compare Operation: Buffer-Less Mode (When CMSEx0 Register's CCSEy Bit = 1, LNKEy Bit = Arbitrary, BFEEy Bit = 0) fCLK MUXTB0 MUXTB1 MUXCNT TB0Ey bitNote 1 TB1Ey bitNote 1 WRITE_ENABLE_S RELOAD_PRIMARY CVSEm0 register CVPEm0 register RELOAD1 INTCCm Note 3 Note 3 Note 3 Note 3 Note 2 6 2 7 3 5 1 TB1 TB0 TB1 TB0 TB1 TB0 7 9 8 10 9 11 TB0 TB1 TB0 TB1 TB0 TB1 6 8 7 9 8 10 TB1 TB0 TB1 TB0 TB1 TB0 2 2 9 9 8 8 Notes 1. 2. 3. TB1Ey, TB0Ey bits of CMSEx0 register No interrupt is generated due to compare match with counter differing from TB1Ey, TB0Ey bit settings. INTCC2m is generated to match the cycle from rising edge to falling edge of MUXTB0. Remarks 1. fCLK: Base clock 2. MUXCNT: Count value to sub-channel m MUXTB0, MUXTB1: Multiplex signal of TM20, TM21 RELOAD1: Compare match signal RELOAD_PRIMARY: Timing of write operation from CVSEm0 register to CVPEm0 register WRITE_ENABLE_S: Timing of CVSEm0 register write operation TB0: Count value of TM20 TB1: Count value of TM21 3. m = 1 to 4, x = 12, 34 User's Manual U14492EJ5V0UD 363 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-78. Compare Operation: Mode with Buffer (When Operation Is Delayed Through Setting of LNKEy Bit of CMSEx0 Register, CMSEx0 Register's CCSEy Bit = 1, BFEEy Bit = 1) fCLK MUXTB0 MUXTB1 MUXCNT LNKEy bitNote WRITE_ENABLE_S RELOAD2A RELOAD1 RELOAD_PRIMARY CVSEm0 register CVPEm0 register INTCC2m (output) 4 4 7 7 1 1 6 2 7 3 8 4 9 5 10 6 11 7 12 0 13 1 14 2 5 1 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 TB1 TB0 Note LNKEy bit of CMSEx0 register Remarks 1. fCLK: Base clock 2. MUXCNT: Count value to sub-channel m MUXTB0, MUXTB1: Multiplex signal of TM20, TM21 RELOAD1: Compare match signal RELOAD2A: Zero count signal input of TM20 (occurs when TM20 = 0000H) RELOAD_PRIMARY: Timing of write operation from CVSEm0 register to CVPEm0 register WRITE_ENABLE_S: Timing of CVSEm0 register write operation TB0: Count value of TM20 (In this figure, the maximum count value is 7.) TB1: Count value of TM21 3. m = 1 to 4, x = 12, 34 y: When x = 12, y = 1, 2, and when x = 34, y = 3, 4 364 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (4) Operation of capture/compare register (sub-channels 0, 5) Figures 9-79 and 9-80 show the operation of the capture/compare register (sub-channels 0, 5). Figure 9-79. Capture Operation: Timer 2 Count Value Read Timing (When CMSE050 Register's CCSEy Bit = 0, EEVEy Bit = 1, and CSCE0 Register's SEVEy Bit = 0) fCLK CNT LNKEyNote 1 ED1 Note 2 0 1 2 3 4 5 6 7 8 9 10 ED2 CAPTURE_S READ_ENABLE_S CVSEy0 register Undefined 2 6 9 Note 2 Notes 1. 2. LNKEy bit of CMSE050 register If an event occurs in this timing, it is ignored. Remarks 1. fCLK: Base clock 2. CNT: Count value of timer 2 CAPTURE_S: Capture trigger signal of sub capture register ED1, ED2: Capture event signal inputs from edge selector READ_ENABLE_S: Read timing for CVSEy0 register 3. y = 0, 5 User's Manual U14492EJ5V0UD 365 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-80. Compare Operation: Timing of Compare Match and Write Operation to Register (When CMSE050 Register's CCSEy Bit = 1, EEVEy Bit = Arbitrary, and CSCE0 Register's SEVEy Bit = Arbitrary) fCLK CNT CPU write C/C CVSEy0 register MATCH RNote 1 Note 2 Note 2 Note 2 0 1 2 3 4 5 6 7 8 9 10 2 4 8 INTCC20, INTCC25 (output) Note 3 Note 3 Note 3 Notes 1. 2. 3. Can control TM20/TM21 clear by sub-channel 0/5 compare match or count direction. When MATCH signal occurs, the same waveform as the MATCH signal is generated. The pulse width is always 1 clock. Remarks 1. fCLK: Base clock 2. CNT: Count value of timer 2 MATCH: CVSEy0 register compare match timing R: Compare match input (sub-channel 0/5) 366 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (5) Operation of output circuit Figures 9-81 to 9-84 show the output circuit operation. Figure 9-81. Signal Output Operation: Toggle Mode 0 and Toggle Mode 1 (When OCTLE0 Register's SWFEn Bit = 0, and ODELE0 Register's ODLEn2 to ODLEn0 Bits = 0) fCLK OTMEn1, OTMEn0 bitsNote 1 S/T RA RB RN TO2n timer output (ALVEn bit = 0Note 2) TO2n timer output (ALVEn bit = 1Note 2) 00B 01B Notes 1. 2. OTMEn1, OTMEn0 bits of OCTLE0 register ALVEn bit of OCTLE0 register Remarks 1. fCLK: Base clock 2. RA: Zero count signal input of TM20 (output circuit reset signal) RB: Zero count signal input of TM21 (output circuit reset signal) RN: Interrupt signal input of sub-channel n (output circuit reset signal) S/T: Interrupt signal input of sub-channel n (output circuit set signal) 3. n = 1 to 4 User's Manual U14492EJ5V0UD 367 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-82. Signal Output Operation: Toggle Mode 2 and Toggle Mode 3 (When OCTLE0 Register's SWFEn Bit = 0, and ODELE0 Register's ODLEn2 to ODLEn0 Bits = 0) fCLK OTMEn1, OTMEn0 bitsNote 1 S/T RA RB RN TO2n timer output (ALVEn bit = 0Note 2) TO2n timer output (ALVEn bit = 1Note 2) 10B 11B Notes 1. 2. OTMEn1, OTMEn0 bits of OCTLE0 register ALVEn bit of OCTLE0 register Remarks 1. fCLK: Base clock 2. RA: Zero count signal input of TM20 (output circuit reset signal) RB: Zero count signal input of TM21 (output circuit reset signal) RN: Interrupt signal input of sub-channel n (output circuit reset signal) S/T: Interrupt signal input of sub-channel n (output circuit set signal) 3. n = 1 to 4 Figure 9-83. Signal Output Operation: During Software Control (When OCTLE0 Register's OTMEn1, OTMEn0 Bits = Arbitrary, SWFEn Bit = 1, and ODELE0 Register's ODLEn2 to ODLEn0 Bits = 0) fCLK ALVEn bitNote TO2n timer output Note ALVEn bit of OCTLE0 register Remarks 1. fCLK: Base clock 2. n = 1 to 4 368 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-84. Signal Output Operation: During Delay Output Operation (When OCTLE0 Register's OTMEn1, OTMEn0 Bits = 0, ALVEn = 0, SWFEn Bit = 0) fCLK ODELEn2 to ODELEn0 bitsNote S/T TO2n timer output 5 2 Note ODELEn2 to ODELEn0 bits of OCTLE0 register Remarks 1. fCLK: Base clock 2. n = 1 to 4 User's Manual U14492EJ5V0UD 369 CHAPTER 9 TIMER/COUNTER FUNCTION 9.3.6 PWM output operation when timer 2 operates in compare mode (1) Operation when TO2n pin performs PWM output operation in toggle mode 1 In toggle mode 1, the TO2n output (internal) becomes inactive triggered by a signal when TM20 = 0, and becomes active triggered by a sub-channel 1 (CVPEn0 register) compare match signal. In accordance with the state of this TO2n (internal), the TO2n pin outputs a high or low level depending on the OCTLE0.ALVEn bit setting. Figure 9-85. Normal Output Operation (When OCTLE0 Register's OTMEn1, OTMEn0 Bits = 01, ODELE0 Register's ODLEn2 to ODLEn0 Bits = 000) fCLK TM20 CVSE00 register CVSEn0 register TM20 = 0 CVSEn0 register match signal TO2n (internal) TO2n output (ALVEn bit = 0) TO2n output (ALVEn bit = 1) Inactive state Active state Inactive state Active state 05 06 07 00 01 02 03 04 05 06 0008H 0005H 07 00 01 02 03 04 05 06 07 00 01 Remark n = 1 to 4 370 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (2) Operation when TO2n pin output is controlled by manipulating OCTLE0.SWFEn bit in toggle mode 1 (a) When a sub-channel n compare match signal is output immediately after the SWFEn bit is cleared to 0 Figures 9-86 and 9-87 show the waveforms when output from the TO2n output pin is started or ended by manipulating the SWFEn bit in toggle mode 1. In the V850E/IA1, timer 2 outputs a level according to the ALVEn bit setting (low level when ALVEn bit = 0, and high level when ALVEn bit = 1) by fixing the TO2n output to the inactive state when the SWFEn bit is 1. When the SWFEn bit is 0, TO2n (internal) synchronizes with a trigger signal and an active or inactive level is output from the TO2n output pin. However, TO2n output is forcibly fixed to the active state when the SWFEn bit is cleared to 0, and inactive state when the SWFEn bit is set to 1. Therefore, if the sub-channel n compare match signal is output immediately after the SWFEn bit is cleared to 0, the active period from when the SWFEn bit is cleared to 0 to when the compare match signal is output will be added to the ordinary TO2n output active period, so the first active period becomes long (refer to Figure 9-86). Figure 9-86. When Output Operation Is Started/Ended Normally (When OCTLE0 Register's OTMEn1, OTMEn0 Bits = 01, ODELD0 Register's ODLEn2 to ODLEn0 Bits = 000) fCLK TM20 CVSE00 register CVSEn0 register TM20 = 0 CVSEn0 register 05 06 07 00 01 02 03 04 05 06 0008H 0005H 07 00 01 02 03 04 05 06 07 00 01 02 03 04 05 match signal SWFEn bit TO2n (internal) TO2n output (ALVEn bit = 0) TO2n output (ALVEn bit = 1) Inactive state (fixed) Active state Inactive state Active state Inactive state Inactive state (fixed) Remark n = 1 to 4 User's Manual U14492EJ5V0UD 371 CHAPTER 9 TIMER/COUNTER FUNCTION (b) When the trigger signal of TM20 = 0 is output immediately after the SWFEn bit is cleared to 0 When the trigger signal of TM20 = 0 is output immediately after the SWFEn bit is cleared to 0, from when the SWFEn bit is cleared to 0 to when the trigger signal of TM20 = 0 is output is the first active period, so a pulse shorter than the active period of the ordinary TO2n output is output. In addition, since TO2n output is forcibly fixed to the inactive level when the SWFEn bit is set to 1, the active level output period also becomes shorter if the SWFEn bit is set to 1 while an active level is being output (refer to Figure 9-87). Figure 9-87. When Output Operation Is Started/Ended Normally (When OCTLE0 Register's OTMEn1, OTMEn0 Bits = 01, ODELD0 Register's ODLEn2 to ODLEn0 Bits = 000) fCLK TM20 CVSE00 register CVSEn0 register TM20 = 0 CVSEn0 register match signal SWFEn bit TO2n (internal) TO2n output (ALVEn bit = 0) TO2n output (ALVEn bit = 1) Inactive state (fixed) Inactive state (fixed) Active state 02 03 04 05 06 07 00 01 02 03 04 05 06 07 00 01 02 03 04 05 06 07 00 0008H 0005H Active state Inactive state Active state Inactive state Remark n = 1 to 4 372 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.4 Timer 3 9.4.1 Features (timer 3) Timer 3 (TM3) is a 16-bit timer/counter that can perform the following operations. * Interval timer function * PWM output * External signal cycle measurement 9.4.2 Function overview (timer 3) * * * * 16-bit timer/counter (TM3): 1 channel Capture/compare registers: 2 Count clock division selectable by prescaler (set the frequency of the count clock to 16 MHz or less) Base clock (fCLK): 2 types (set fCLK to 32 MHz or less) fXX and fXX/2 can be selected * Prescaler division ratio The following division ratios can be selected according to the base clock (fCLK). Division Ratio Base Clock (fCLK) fXX Selected 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/2 Selected fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 * Interrupt request sources * Capture/compare match interrupt requests: 2 sources In case of capture register: INTCC3n generated by INTP3n input In case of compare register: INTCC3n generated by CC3n match signal * Overflow interrupt request: 1 source INTTM3 generated upon overflow of TM3 register * Timer/counter count clock sources: 2 types (Selection of external pulse input, internal system clock cycle) * One of two operation modes when the timer/counter overflows can be selected: free-running mode or overflow stop mode * The timer/counter can be cleared by match of timer/counter and compare register * External pulse output (TO3): 1 Remarks 1. fXX: Internal system clock 2. n = 0, 1 User's Manual U14492EJ5V0UD 373 CHAPTER 9 TIMER/COUNTER FUNCTION 9.4.3 Basic configuration Table 9-12. Timer 3 Configuration List Timer Count Clock Note 1 Timer 3 fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXX/64, fXX/128, fXX/256 Note 2 fXX/4, fXX/8, fXX/16, fXX/32, fXX/64, fXX/128, fXX/256, fXX/512 CC31 Read/write INTC31 INTP31 TO3 (R) CC30 Read/write INTCC30 INTP30 TO3 (S) TM3 Read Register Read/Write Generated Interrupt Signal INTTM3 Capture Trigger Timer Output S/R - - Notes 1. 2. Remark When fXX is selected as the base clock (fCLK) of TM3 When fXX/2 is selected as the base clock (fCLK) of TM3 fXX: Internal system clock S/R: Set/Reset Figure 9-88 shows the block diagram of timer 3. Figure 9-88. Block Diagram of Timer 3 Selector fXX Selector fCLK fXX/2 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 Clear & start TM3 (16-bit) INTTM3 Clear & start TI3/TCLR3/INTP30 INTP31 CC30 CC31 S RNote Q Q Selector TO3 INTCC30 INTCC31 Note Reset priority Remarks 1. TI3 input and TCLR3 input connected to port immediately before edge detection 2. fCLK: Base clock (32 MHz (MAX.)) fXX: Internal system clock 374 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (1) Timer 3 (TM3) TM3 functions as a 16-bit free-running timer or as an event counter for an external signal. Besides being mainly used for cycle measurement, TM3 can be used as pulse output. TM3 is read-only, in 16-bit units. Cautions 1. The TM3 register can only be read. If writing is performed to the TM3 register, the subsequent operation is undefined. 2. If the TM3CAE bit of the TMC30 register is cleared (0), a reset is performed asynchronously. 3. Continuous reading of TM3 is prohibited. If TM3 is continuously read, the second read value may differ from the actual value. Figure 9-89. Timer 3 (TM3) 15 TM3 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF680H Initial value 0000H TM3 performs the count-up operations of an internal count clock or external count clock. Timer starting and stopping are controlled by the TM3CE bit of timer control register 30 (TMC30). The internal or external count clock is selected by the ETI bit of timer control register 31 (TMC31). (a) Selection of the external count clock TM3 operates as an event counter. When the ETI bit of timer control register 31 (TMC31) is set (1), TM3 counts the valid edges of the external clock input (TI3), synchronized with the internal count clock. The valid edge is specified by valid edge selection register (SESC). Caution If the INTP30, TI3, and TCLR3 pins are used as the TI3 and TCLR3, either mask the INTP30 interrupt or set CC3n in compare mode (n = 0, 1). User's Manual U14492EJ5V0UD 375 CHAPTER 9 TIMER/COUNTER FUNCTION (b) Selection of the internal count clock TM3 operates as a free-running timer. When an internal clock is specified as a count clock by timer control register 31 (TMC31), TM3 is counted up for each input clock cycle specified by the CS2 to CS0 bits of the TMC30 register. A division by the prescaler can be selected for the count clock from among fCLK/2, fCLK/4, fCLK/8, fCLK/16, fCLK/32, fCLK/64, fCLK/128 and fCLK/256 by the TMC30 register (fCLK: base clock). An overflow interrupt can be generated if the timer overflows. Also, the timer can be stopped following an overflow by setting the OST bit of the TMC31 register to 1. Caution The count clock cannot be changed while the timer is operating. The conditions when the TM3 register becomes 0000H are shown below. (i) Asynchronous reset * TM3CAE bit of TMC30 register = 0 * Reset input (ii) Synchronous reset * TM3CE bit of TMC30 register = 0 * The CC30 register is used as a compare register, and the TM3 and CC30 registers match when clearing the TM3 register is enabled (CCLR bit of the TMC31 register = 1) 376 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (2) Capture/compare registers 30 and 31 (CC30 and CC31) These capture/compare registers 30 and 31 are 16-bit registers. They can be used as capture registers or compare registers according to the CMS1 and CMS0 bit specifications of timer control register 31 (TMC31). These registers can be read/written in 16-bit units (however, write operations can only be performed in compare mode). Caution Continuous reading of CC3n is prohibited. If CC3n is continuously read, the second read value may differ from the actual value. If CC3n must be read twice, be sure to read another register between the first and the second read operation. Correct usage example CC30 read CC31 read CC30 read CC31 read Incorrect usage example CC30 read CC30 read CC31 read CC31 read 15 CC30 15 CC31 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF682H Initial value 0000H Initial value 0000H 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF684H (a) Setting these registers to capture registers (CMS1 and CMS0 of TMC31 = 0) When these registers are set to capture registers, the valid edges of the corresponding external interrupt signals INTP30 and INTP31 are detected as capture triggers. The timer TM3 is synchronized with the capture trigger, and the value of TM3 is latched in the CC30 and CC31 registers (capture operation). The valid edge of the INTP30 pin is specified (rising, falling, or both edges) according to the IES301 and IES300 bits of the SESC register, and the valid edge of the INTP31 pin is specified according to the IES311 and IES310 bits of the SESC register. The capture operation is performed asynchronously relative to the count clock. The latched value is held in the capture register until the next capture operation is performed. When the TM3CAE bit of timer control register 30 (TMC30) is 0, 0000H is read. If these registers are specified as capture registers, an interrupt is generated by detecting the valid edge of signals INTP30 and INTP31. Caution If the capture operation and the TM3 register count prohibit setting (TM3CE bit of TMC30 register = 0) timings conflict, the captured data becomes undefined, and no INTCC3n interrupt is generated (n = 0, 1). User's Manual U14492EJ5V0UD 377 CHAPTER 9 TIMER/COUNTER FUNCTION (b) Setting these registers to compare registers (CMS1 and CMS0 of TMC31 = 1) When these registers are set to compare registers, the TM3 and register values are compared for each count clock, and an interrupt is generated by a match. If the CCLR bit of timer control register 31 (TMC31) is set (1), the TM3 value is cleared (0) at the same time as a match with the CC30 register (it is not cleared (0) by a match with the CC31 register). A compare register is equipped with a set/reset output function. The corresponding timer output (TO3) is set or reset, synchronized with the generation of a match signal. The interrupt selection source differs according to the function of the selected register. Cautions 1. To write to capture/compare registers 30 and 31 (CC30, CC31), always set the TM3CAE bit to 1 first. When the TM3CAE bit is 0, even if writing to registers CC30 and CC31, the data that is written will be invalid because the reset is asynchronous. 2. Perform a write operation to capture/compare registers 30 and 31 after setting them to compare registers according to the TMC30, TMC31 register setting. If they are set to capture registers (CMS1 and CMS0 bits of TMC31 register = 0), no data is written even if a write operation is performed to CC30 and CC31. 3. When these registers are set to compare registers, INTP30 and INTP31 cannot be used as external interrupt input pins. 378 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.4.4 Control registers (1) Timer 3 clock selection register (PRM03) The PRM03 register is used to select the base clock (fCLK) of timer 3 (TM3). This register can be read/written in 8-bit or 1-bit units. Cautions 1. Always set this register before using the timer. 2. Set fCLK to 32 MHz or less. 7 PRM03 0 6 0 5 0 4 0 3 0 2 0 1 0 0 PRM3 Address FFFFF690H Initial value 00H Bit position 0 Bit name PRM3 Function Specifies the base clock (fCLK) of timer 3 (TM3). 0: fXX/2 (when fXX > 32 MHz) 1: fXX (when fXX 32 MHz) Remark fXX: Internal system clock User's Manual U14492EJ5V0UD 379 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Timer control register 30 (TMC30) The TMC30 register controls the operation of TM3. This register can be read/written in 8-bit or 1-bit units. Cautions 1. The TM3CAE bit and other bits cannot be set at the same time. Be sure to set the TM3CAE bit and then set the other bits and the other registers of TM3. To use an external pin related to the timer function when using timer 3, be sure to set (1) the TM3CAE bit after setting the external pin to the control mode. 2. If occurrence of an overflow conflicts with writing to the TMC30 register, the value of the TM3OVF bit is the value written to the TMC30 register. (1/2) <7> TMC30 TM3OVF 6 CS2 5 CS1 4 CS0 3 0 2 0 <1> TM3CE <0> TM3CAE Address FFFFF686H Initial value 00H Bit position 7 Bit name TM3OVF Flag that indicates TM3 overflow. 0: No overflow 1: Overflow Function The TM3OVF bit becomes "1" when TM3 changes from FFFFH to 0000H. An overflow interrupt request (INTTM3) is generated at the same time. However, if CC30 is set to the compare mode (CMS0 bit of the TMC31 register = 1) and match clear during comparison of TM3 and CC30 is enabled (CCLR bit of TMC31 register = 1), and TM3 is cleared to 0000H following match at FFFFH, TM3 is considered to have been cleared and the TM3OVF bit does not become "1", nor is the INTTM3 interrupt generated. The TM3OVF bit holds a "1" until "0" is written to it or an asynchronous reset is applied while the TM3CAE bit = 0. Interrupts by overflow and the TM3OVF bit are independent, and even if the TM3OVF bit is manipulated, this does not affect the interrupt request flag for INTTM3 (TM3IF0). If an overflow occurs while the TM3OVF bit is being read, the value of the flag changes and the value is returned at the next read. 380 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position 6 to 4 Bit name CS2 to CS0 Function Selects the internal count clock for TM3. CS2 0 0 0 0 1 1 1 1 Caution CS1 0 0 1 1 0 0 1 1 CS0 0 1 0 1 0 1 0 1 fCLK/2 fCLK/4 fCLK/8 fCLK/16 fCLK/32 fCLK/64 fCLK/128 fCLK/256 Count clock Do not change the CS2 to CS0 bits during timer operation. If they are to be changed, they must be changed after setting the TM3CE bit to "0". If the CS2 to CS0 bits are overwritten during timer operation, the operation is not guaranteed. Remark fCLK: Base clock 1 TM3CE Controls the operation of TM3. 0: Disable count (timer stopped at 0000H and does not operate) 1: Perform count operation. Caution If TM3CE = 0, the external pulse output (TO3) becomes inactive level (the active level of TO3 output is set with the ALV bit of the TMC31 register). 0 TM3CAE Controls the internal count clock. 0: Asynchronously reset entire TM3 unit. Stop base clock supply to TM3 unit. 1: Supply base clock (fCLK) to TM3 unit. Cautions 1. When TM3CAE = 0 is set, the TM3 unit can be reset asynchronously. 2. When TM3CAE = 0, the TM3 unit is in a reset state. To operate TM3, first set TM3CAE = 1. 3. When the TM3CAE bit is changed from "1" to "0", all the registers of the TM3 unit are initialized. When again setting TM3CAE = 1, be sure to then again set all the registers of the TM3 unit. User's Manual U14492EJ5V0UD 381 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Timer control register 31 (TMC31) The TMC31 register controls the operation of TM3. This register can be read/written in 8-bit or 1-bit units. Cautions 1. Do not change the bits of the TMC31 register during timer operation. If they are to be changed, they must be changed after setting the TM3CE bit of the TMC30 register to "0". If the TMC31 register is overwritten during timer operation, the operation is not guaranteed. 2. If the ENT1 bit and the ALV bit are changed simultaneously, a glitch (spike-shaped noise) may be generated in the TO3 pin output. Either design the circuit that will not malfunction even if a glitch is generated, or make sure that the ENT1 bit and the ALV bit do not change at the same time. 3. TO3 output remains unchanged by external interrupt signals (INTP30, INTP31). When using the TO3 signal, set the capture/compare register to the compare register (CMS1, CMS0 bits of TMC31 register = 1). Remark A reset takes precedence for the flip-flop of the TO3 output. 382 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION 7 TMC31 OST 6 ENT1 5 ALV 4 ETI 3 CCLR 2 ECLR 1 CMS1 0 CMS0 Address FFFFF688H Initial value 20H Bit position 7 OST Bit name Function Sets the operation when TM3 overflows. 0: Continue count operation after overflow (free-running mode) 1: After overflow, timer holds 0000H and stops count operation (overflow stop mode). At this time, the TM3CE bit of TMC30 remains "1". The count operation is resumed by again writing "1" to the TM3CE bit. 6 ENT1 Enables/disables output of external pulse output (TO3). 0: Disable external pulse output. Output of inactive level of ALV bit to TO3 pin is fixed. TO3 pin level remains unchanged even if match signal from corresponding compare register is generated. 1: Enable external pulse output. Compare register match causes TO3 output to change. However, in capture mode, TO3 output does not change. An ALV bit inactive level is output from the time when timer output is enabled until a match signal is generated. Caution If either CC30 or CC31 is specified as a capture register, the ENT1 bit must be set to "0". 5 ALV Specifies active level of external pulse output (TO3). 0: Active level is low level. 1: Active level is high level. Caution The initial value of the ALV bit is "1". 4 ETI Switches count clock between external clock and internal clock. 0: Specifies input clock (internal). The count clock can be selected with bits CS2 to CS0 of TMC30. 1: Specifies external clock (TI3). Valid edge can be selected with bits TES31, TES30 of SESC. 3 CCLR Enables/disables TM3 clearing during compare operation. 0: Disable clearing. 1: Enable clearing (TM3 is cleared when CC30 and TM3 match during compare operation). 2 ECLR Enables TM3 clearing by external clear input (TCLR3). 0: Disable clearing by TCLR3. 1: Enable clearing by TCLR3 (counting resumes after clearing). 1 CMS1 Selects operation mode of capture/compare register (CC31). 0: Register operates as capture register. 1: Register operates as compare register. 0 CMS0 Selects operation mode of capture/compare register (CC30). 0: Register operates as capture register. 1: Register operates as compare register. User's Manual U14492EJ5V0UD 383 CHAPTER 9 TIMER/COUNTER FUNCTION (4) Valid edge selection register (SESC) This register specifies the valid edge of external interrupt requests (TI3, TCLR3, INTP30, INTP31) from an external pin. The rising edge, the falling edge, or both rising and falling edges can be specified as the valid edge independently for each pin. This register can be read/written in 8-bit or 1-bit units. Caution Do not change the bits of SESC register during timer operation. If they are to be changed, they must be changed after setting the TM3CE bit of the TMC30 register to "0". If the SESC register is overwritten during timer operation, the operation is not guaranteed. 7 SESC TES31 TI3 6 TES30 5 CES31 4 CES30 3 IES311 2 IES310 1 IES301 0 IES300 Address FFFFF689H Initial value 00H TCLR3 INTP31 INTP30 Bit position 7, 6 Bit name TES31, TES30 Function Specifies the valid edge of INTP30, INTP31 pins, TCLR3, and TI3 pins. 5, 4 CES31, CES30 xESn1 0 xESn0 0 1 0 1 Falling edge Rising edge Setting prohibited Operation 3, 2 IES311, IES310 0 1 1, 0 IES301, IES300 1 Both rising and falling edges Remark n = 3, 30, 31 384 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.4.5 Operation (1) Count operation Timer 3 can function as a 16-bit free-running timer or as an external signal event counter. The setting for the type of operation is specified by timer control register 3n (TMC3n) (n = 0, 1). When it operates as a free-running timer, if the CC30 or CC31 register and the TM3 count value match, an interrupt signal is generated and the timer output signal (TO3) can be set or reset. Also, a capture operation that holds the TM3 count value in the CC30 or CC31 register is performed, synchronized with the valid edge that was detected from the external interrupt request input pin as an external trigger. The capture value is held until the next capture trigger is generated. Caution If the INTP30/TI3/TCLR3 pin is used as TI3 or TCLR3, either mask the INTP30 interrupt or set the CC3n register to compare mode (n = 0, 1). Figure 9-90. Basic Operation of Timer 3 Count clock TM3 0000H 0001H 0002H 0003H Count start TM3CE 1 FBFEH FBFFH 0000H 0001H 0002H Count disabled TM3CE 0 Count start TM3CE 1 User's Manual U14492EJ5V0UD 385 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Overflow When the TM3 register has counted the count clock from FFFFH to 0000H, the TM3OVF bit of the TMC30 register is set (1), and an overflow interrupt (INTTM3) is generated at the same time. However, if the CC30 register is set to compare mode (CMS0 bit = 1) and to the value FFFFH when match clearing is enabled (CCLR bit = 1), then the TM3 register is considered to be cleared and the TM3OVF bit is not set (1) when the TM3 register changes from FFFFH to 0000H. Also, the overflow interrupt (INTTM3) is not generated. When the TM3 register is changed from FFFFH to 0000H because the TM3CE bit changes from 1 to 0, the TM3 register is considered to be cleared, but the TM3OVF bit is not set (1) and no INTTM3 interrupt is generated. Also, timer operation can be stopped after an overflow by setting the OST bit of the TMC31 register to 1. When the timer is stopped due to an overflow, the count operation is not restarted until the TM3CE bit of the TMC30 register is set (1). Operation is not affected even if the TM3CE bit is set (1) during a count operation. Figure 9-91. Operation After Overflow (When OST = 1) Overflow FFFFH Overflow FFFFH Count start TM3 0 OST 1 INTTM3 TM3CE 1 TM3CE 1 386 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (3) Capture operation The TM3 register has two capture/compare registers. These are the CC30 register and the CC31 register. A capture operation or a compare operation is performed according to the settings of both the CMS1 and CMS0 bits of the TMC31 register. If the CMS1 and CMS0 bits of the TMC31 register are set to 0, the register operates as a capture register. A capture operation that captures and holds the TM3 count value asynchronously relative to the count clock is performed synchronized with an external trigger. The valid edge that is detected from an external interrupt request input pin (INTP30 or INTP31) is used as an external trigger (capture trigger). The TM3 count value during counting is captured and held in the capture register, synchronized with that capture trigger signal. The capture register value is held until the next capture trigger is generated. Also, an interrupt request (INTCC30 or INTCC31) is generated by INTP30 or INTP31 signal input. The valid edge of the capture trigger is set by valid edge selection register (SESC). If both the rising and falling edges are set as capture triggers, the input pulse width from an external source can be measured. Also, if only one of the edges is set as the capture trigger, the input pulse cycle can be measured. Figure 9-92. Capture Operation Example n TM3 0 TM3CE CC31 (Capture register) n INTP31 (Capture trigger) (Capture trigger) Remarks 1. When the TM3CE bit is 0, no capture operation is performed even if INTP31 is input. 2. Valid edge of INTP31: Rising edge User's Manual U14492EJ5V0UD 387 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-93. TM3 Capture Operation Example (When Both Edges Are Specified) (TM3 count values) D1 D0 TM3 Count start TM3CE 1 Overflow TM3OVF 1 D2 Interrupt request (INTP31) Capture register (CC31) D0 D1 D2 Remark D0 to D2: TM3 count values 388 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (4) Compare operation The TM3 register has two capture/compare registers. These are the CC30 register and the CC31 register. A capture operation or a compare operation is performed according to the settings of both the CMS1 and CMS0 bits of the TMC31 register. If 1 is set in the CMS1 and CMS0 bits of the TMC31 register, the register operates as a compare register. A compare operation that compares the value that was set in the compare register and the TM3 count value is performed. If the TM3 count value matches the value of the compare register, which had been set in advance, a match signal is sent to the output controller. The match signal causes the timer output pin (TO3) to change and an interrupt request signal (INTCC30, INTCC31) to be generated at the same time. If the CC30 or CC31 register is set to 0000H, the 0000H after the TM3 register counts up from FFFFH to 0000H is judged as a match. In this case, the value of the TM3 register is cleared to 0 at the next count timing, but 0000H is not judged as a match at that time. 0000H when the TM3 register begins counting is not judged as a match either. If match clearing is enabled (CCLR bit = 1) for the CC30 register, the TM3 register is cleared when a match with the TM3 register occurs during a compare operation. Figure 9-94. Compare Operation Example (1/2) (a) If CCLR bit = 1 and CC30 is value other than 0000H Count up TM3 n-1 n 0000H 0001H Compare register (CC30) n TO3 (output) Match detection (INTCC30) Remarks 1. The match is detected immediately after the count up, and the match detection signal is generated. 2. n 0000H User's Manual U14492EJ5V0UD 389 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-94. Compare Operation Example (2/2) (b) If CCLR bit = 1 and CC30 is 0000H Count up TM3 FFFFH 0000H 0000H 0001H Compare register (CC30) 0000H INTTM3 TO3 (output) Match detection (INTCC30) Remark The match is detected immediately after the count up, and the match detection signal is generated. 390 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (5) External pulse output Timer 3 has one timer output pin (TO3). An external pulse output (TO3) is generated when a match of the two compare registers (CC30 and CC31) and the TM3 register is detected. If a match is detected when the TM3 count value and the CC30 value are compared, the output level of the TO3 pin is set. Also, if a match is detected when the TM3 count value and the CC31 value are compared, the output level of the TO3 pin is reset. The output level of the TO3 pin can be specified by the TMC31 register. Table 9-13. TO3 Output Control ENT1 ALV External Pulse Output 0 0 1 0 1 0 Disable Disable Enable High level Low level When the CC30 register is matched: Low level When the CC31 register is matched: High level 1 1 Enable When the CC30 register is matched: High level When the CC31 register is matched: Low level TO3 Output Output Level Figure 9-95. TM3 Compare Operation Example (Set/Reset Output Mode) CC30 CC30 CC31 TM3 count value 0 Count start TM3CE1 1 Interrupt request (INTCC31) CC31 CC31 Clear & start Clear & start Interrupt request (INTCC30) TO3 pin ENT1 1 ALV 0 User's Manual U14492EJ5V0UD 391 CHAPTER 9 TIMER/COUNTER FUNCTION 9.4.6 Application examples (1) Interval timer By setting the TMC30 and TMC31 registers as shown in Figure 9-96, timer 3 operates as an interval timer that repeatedly generates interrupt requests with the value that was set in advance in the CC30 register as the interval. When the counter value of the TM3 register matches the setting value of the CC30 register, the TM3 register is cleared (0000H) and an interrupt request signal (INTCC30) is generated at the same time that the count operation resumes. Figure 9-96. Contents of Register Settings When Timer 3 Is Used as Interval Timer TM3OVF CS2 TMC30 0/1 0/1 CS1 0/1 CS0 0/1 0 0 TM3CETM3CAE 1 1 Supply input clocks to internal units Enable count operation OST ENT1 TMC31 0 0/1 ALV 0/1 ETI 0/1 CCLR ECLR CMS1 CMS0 1 0/1 0/1 1 Use CC30 register as compare register Clear TM3 register due to match with CC30 register Continue counting after TM3 register overflows Remark 0/1: Set to 0 or 1 as necessary 392 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-97. Interval Timer Operation Timing Example t Count clock TM3 register 0000H 0001H p 0000H 0001H p 0000H 0001H p Count start CC30 register INTCC30 interrupt Interval time p Clear p Clear p p Interval time Interval time Remark p: Setting value of CC30 register (0000H to FFFFH) t: Count clock cycle Interval time = (p + 1) x t User's Manual U14492EJ5V0UD 393 CHAPTER 9 TIMER/COUNTER FUNCTION (2) PWM output By setting the TMC30 and TMC31 registers as shown in Figure 9-98, timer 3 can output a PWM of the frequency determined by the setting of the CS2 to CS0 bits of the TMC30 register with the values that were set in advance in the CC30 and CC31 registers as the intervals. When the counter value of the TM3 register matches the setting value of the CC30 register, the TO3 output becomes active. Then, when the count value of the TM3 register matches the setting value of the CC31 register, the TO3 output becomes inactive. The TM3 register continues counting, and when an overflow occurs, clears the count value to 0000H and continues counting. This enables a PWM of the frequency determined by the setting of the CS2 to CS0 bits of the TMC30 register to be output. When the setting value of the CC30 register and the setting value of the CC31 register are the same, the TO3 output remains inactive and does not change. The active level of TO3 output can be set by the ALV bit of the TMC31 register. Figure 9-98. Contents of Register Settings When Timer 3 Is Used for PWM Output TM3OVF CS2 TMC30 0/1 0/1 CS1 0/1 CS0 0/1 0 0 TM3CETM3CAE 1 1 Supply input clocks to internal units Enable count operation OST ENT1 TMC31 0 1 ALV 0/1 ETI 0/1 CCLR ECLR CMS1 CMS0 0 0/1 1 1 Use CC30 register as compare register Use CC31 register as compare register Disable clearing of TM3 register due to match with CC30 register Enable external pulse output (TO3) Continue counting after TM3 register overflows Remark 0/1: Set to 0 or 1 as necessary 394 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-99. PWM Output Operation Timing Example t Count clock TM3 register 0000H 0001H Count start CC30 register CC31 register INTCC30 interrupt INTCC31 interrupt TO3 (output) p p p p q FFFFH 0000H 0001H Clear p p p q q q q q q Remarks 1. p: Setting value of CC30 register (0000H to FFFFH) q: Setting value of CC31 register (0000H to FFFFH) pq t: Count clock cycle PWM cycle = 65536 x t Duty = q-p 65536 2. In this example, the active level of TO3 output is set to high level. User's Manual U14492EJ5V0UD 395 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Cycle measurement By setting the TMC30 and TMC31 registers as shown in Figure 9-100, timer 3 can measure the cycle of signals input to the INTP30 pin or INTP31 pin. The valid edge of the INTP30 pin is selected according to the IES301 and IES300 bits of the SESC register, and the valid edge of the INTP31 pin is selected according to the IES311 and IES310 bits of the SESC register. Either the rising edge, the falling edge, or both edges can be selected as the valid edges of both pins. If the CC30 register is set to a capture register and TM3 is started, the valid edge input of the INTP30 pin is set as the trigger for capturing the TM3 register value in the CC30 register. When this value is captured, an INTCC30 interrupt is generated. Similarly, if the CC31 register is set to a capture register and TM3 is started, the valid edge input of the INTP31 pin is set as the trigger for capturing the TM3 register value in the CC31 register. When this value is captured, an INTCC31 interrupt is generated. The cycle of signals input to the INTP30 pin is calculated by obtaining the difference between the TM3 register's count value (Dx) that was captured in the CC30 register according to the x-th valid edge input of the INTP30 pin and the TM3 register's count value (D(x+1)) that was captured in the CC30 register according to the (x+1)-th valid edge input of the INTP30 pin and multiplying the value of this difference by the cycle of the clock control signal. The cycle of signals input to the INTP31 pin is calculated by obtaining the difference between the TM3 register's count value (Dx) that was captured in the CC31 register according to the x-th valid edge input of the INTP31 pin and the TM3 register's count value (D(x+1)) that was captured in the CC31 register according to the (x+1)-th valid edge input of the INTP31 pin and multiplying the value of this difference by the cycle of the clock control signal. Figure 9-100. Contents of Register Settings When Timer 3 Is Used for Cycle Measurement TM3OVF CS2 TMC30 0/1 0/1 CS1 0/1 CS0 0/1 0 0 TM3CETM3CAE 1 1 Supply input clocks to internal units Enable count operation OST ENT1 TMC31 0 0/1 ALV 0/1 ETI 0/1 CCLR ECLR CMS1 CMS0 0/1 0/1 0 0 Use CC30 register as capture register (when measuring the cycle of INTP30 input) Use CC31 register as capture register (when measuring the cycle of INTP31 input) Continue counting after TM3 register overflows Remark 0/1: Set to 0 or 1 as necessary 396 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-101. Cycle Measurement Operation Timing Example t Count clock TM3 register 0000H 0001H Count start INTP30 (input) CC30 register INTCC30 interrupt INTTM3 interrupt (D1 - D0) x t No overflow {(10000H - D1) + D2} x tNote Overflow occurs (D3 - D2) x t No overflow D0 D1 D2 D3 D0 D1 FFFFH 0000H 0001H Clear D2 D3 Note When an overflow occurs once Remarks 1. D0 to D3: TM3 register count values t: Count clock cycle 2. In this example, the valid edge of INTP30 input has been set to both edges (rising and falling). User's Manual U14492EJ5V0UD 397 CHAPTER 9 TIMER/COUNTER FUNCTION 9.4.7 Precautions Various precautions concerning timer 3 are shown below. (1) If a conflict occurs between the reading of the CC30 register and a capture operation when the CC30 register is used in capture mode, an external trigger (INTP30) valid edge is detected and an external interrupt request signal (INTCC30) is generated however, the timer value is not stored in the CC30 register. (2) If a conflict occurs between the reading of the CC31 register and a capture operation when the CC31 register is used in capture mode, an external trigger (INTP31) valid edge is detected and an external interrupt request signal (INTCC31) is generated however, the timer value is not stored in the CC31 register. (3) The following bits and registers must not be rewritten during operation (TMC30 register TM3CE = 1). * CS2 to CS0 bits of TMC30 register * TMC31 register * SESC register (4) The TM3CAE bit of the TMC30 register is a TM3 reset signal. To use TM3, first set (1) the TM3CAE bit. (5) The analog noise elimination time + two count clocks are required to detect a valid edge of the external interrupt input (INTP30 or INTP31) and external clock input (TI3). Therefore, edge detection will not be performed normally for changes that are less than the analog noise elimination time + two count clocks. For the analog noise elimination, refer to 14.5 Noise Eliminator. (6) The operation of an external interrupt output (INTCC30 or INTCC31) is automatically determined according to the operating state of the capture/compare registers 30, 31 (CC30, CC31). When the capture/compare register is used for a capture mode, the external trigger (INTP30, INTP31) is used for valid edge detection. When the capture/compare register is used for a compare mode, the external interrupt output is used for a match interrupt indicating a match with the TM3 register. (7) If the ENT1 and ALV bits of the TMC31 register are changed at the same time, a glitch (spike shaped noise) may be generated in the TO3 pin output. Either create a circuit configuration that will not malfunction even if a glitch is generated or make sure that the ENT1 and ALV bits do not change at the same time. 398 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.5 Timer 4 9.5.1 Features (timer 4) Timer 4 (TM4) functions as a 16-bit interval timer. 9.5.2 Function overview (timer 4) * 16-bit interval timer: 1 channel * Compare register: 1 * Count clock selected from divisions of internal system clock (set the frequency of the count clock to 16 MHz or less) * Base clock (fCLK): 1 type (set fCLK to 32 MHz or less) fXX/2 * Prescaler division ratio The following division ratios can be selected according to the base clock (fCLK). Division Ratio 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 Base Clock (fCLK) fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 * Interrupt request source: 1 * Compare match interrupt INTCM4 generated with CM4 match signal * Timer clear TM4 register can be cleared by CM4 register match. Remark fXX: Internal system clock User's Manual U14492EJ5V0UD 399 CHAPTER 9 TIMER/COUNTER FUNCTION 9.5.3 Basic configuration Table 9-14. Timer 4 Configuration List Timer Count Clock Register Read/Write Generated Interrupt Signal Timer 4 fXX/4, fXX/8, fXX/16, fXX/32, fXX/64, fXX/128, fXX/256, fXX/512 TM4 CM4 Read Read/write - INTCM4 Capture Trigger Timer Output S/R Other Functions - - - - - - Remark fXX: Internal system clock S/R: Set/Reset Figure 9-102 shows the block diagram of timer 4. Figure 9-102. Block Diagram of Timer 4 fCLK fXX/2 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256 TM4 (16-bit) Clear & start CM4 INTCM4 Remark fCLK: Base clock (32 MHz (MAX.)) fXX: Internal system clock 400 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION (1) Timer 4 (TM4) TM4 is a 16-bit timer. It is mainly used as an interval timer for software. Starting and stopping TM4 is controlled by the TM4CE0 bit of the timer control register 4 (TMC4). A division by the prescaler can be selected for the count clock from among fXX/4, fXX/8, fXX/16, fXX/32, fXX/64, fXX/128, fXX/256, and fXX/512 by the CS2 to CS0 bits of the TMC4 register (fXX: Internal system clock). TM4 is read-only, in 16-bit units. 15 TM4 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF540H Initial value 0000H The conditions for which the TM4 register becomes 0000H are shown below. * * * * * Reset input TM4CAE0 bit = 0 TM4CE0 bit = 0 Match of TM4 register and CM4 register Overflow Cautions 1. If the TM4CAE0 bit of the TMC4 register is cleared (0), a reset is performed asynchronously. 2. If the TM4CE0 bit of the TMC4 register is cleared (0), a reset is performed, synchronized with the internal clock. Similarly, a synchronized reset is performed after a match with the CM4 register and after an overflow. 3. The count clock must not be changed during a timer operation. If it is to be overwritten, it should be overwritten after the TM4CE0 bit is cleared (0). 4. Up to 4 internal system clocks are required after a value is set in the TM4CE0 bit until the set value is transferred to internal units. When a count operation begins, the count cycle from 0000H to 0001H differs from subsequent count cycles. 5. After a compare match is generated, the timer is cleared at the next count clock. Therefore, if the division ratio is large, the timer value may not be zero even if the timer value is read immediately after a match interrupt is generated. User's Manual U14492EJ5V0UD 401 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Compare register 4 (CM4) CM4 and the TM4 register count value are compared, and an interrupt request signal (INTCM4) is generated when a match occurs. TM4 is cleared, synchronized with this match. If the TM4CAE0 bit of the TMC4 register is set to 0, a reset is performed asynchronously, and the registers are initialized. The CM4 register is configured with a master/slave configuration. When a write operation to a CM4 register is performed, data is first written to the master register and then the master register data is transferred to the slave register. In a compare operation, the slave register value is compared with the count value of the TM4 register. When a read operation to a CM4 register is performed, data in the master side is read out. CM4 can be read/written in 16-bit units. Cautions 1. A write operation to a CM4 register requires 4 internal system clocks until the value that was set in the CM4 register is transferred to internal units. When writing continuously to the CM4 register, be sure to reserve a time interval of at least 4 internal system clocks. 2. The CM4 register can be overwritten only once in a single TM4 register cycle (from 0000H until an INTCM4 interrupt is generated due to a match of the TM4 register and CM4 register). If this cannot be secured by the application, make sure that the CM4 register is not overwritten during timer operation. 3. Note that an INTCM4 interrupt will be generated after an overflow if a value less than the counter value is written in the CM4 register during TM4 register operation (Figure 9-103). 15 CM4 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF542H Initial value 0000H 402 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-103. Example of Timing During TM4 Operation (a) When TM4 < CM4 TM4 M TM4CAE0 TM4CE0 CM4 INTCM4 N N N Remark M = TM4 value when overwritten N = CM4 value when overwritten M TM4 M TM4CAE0 TM4CE0 CM4 INTCM4 N FFFFH N N Remark M = TM4 value when overwritten N = CM4 value when overwritten M>N User's Manual U14492EJ5V0UD 403 CHAPTER 9 TIMER/COUNTER FUNCTION 9.5.4 Control register (1) Timer control register 4 (TMC4) The TMC4 register controls the operation of timer 4. This register can be read/written in 8-bit or 1-bit units. Caution The TM4CAE0 bit and other bits cannot be set at the same time. TM4CAE0 bit and then set the other bits and the other registers of TM4. Be sure to set the 7 TMC4 0 6 CS2 5 CS1 4 CS0 3 0 2 0 <1> <0> Address Initial value 00H TM4CE0 TM4CAE0 FFFFF544H Bit position 6 to 4 Bit name CS2 to CS0 Selects the TM4 count clock. CS2 0 0 0 0 1 1 1 1 CS1 0 0 1 1 0 0 1 1 CS0 0 1 0 1 0 1 0 1 Function Count clock fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 Caution Do not change the CS2 to CS0 bits during timer operation. If they are to be changed, they must be changed after setting the TM4CE0 bit to 0. If the CS2 to CS0 bits are overwritten during timer operation, the operation is not guaranteed. 1 TM4CE0 Controls the operation of TM4. 0: Disable count (timer stopped at 0000H and does not operate) 1: Perform count operation Caution TM4CE0 bit is not cleared even if a match is detected by the compare operation. To stop the count operation, clear the TM4CE0 bit. 0 TM4CAE0 Controls the internal count clock. 0: Asynchronously reset entire TM4 unit. Stop base clock (fCLK) supply to TM4 unit. 1: Supply base clock (fCLK) to TM4 unit. Cautions 1. When TM4CAE0 = 0 is set, the TM4 unit can be reset asynchronously. 2. When TM4CAE0 = 0, the TM4 unit is in a reset state. To operate TM4, first set TM4CAE0 = 1. 3. When the TM4CAE0 bit is changed from 1 to 0, all the registers of the TM4 unit are initialized. When again setting TM4CAE0 = 1, be sure to then again set all the registers of the TM4 unit. 404 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.5.5 Operation (1) Compare operation TM4 can be used for a compare operation in which the value that was set in a compare register (CM4) is compared with the TM4 count value. If a match is detected by the compare operation, an interrupt (INTCM4) is generated. The generation of the interrupt causes TM4 to be cleared (0) at the next count timing. This function enables timer 4 to be used as an interval timer. CM4 can also be set to 0. In this case, when an overflow occurs and TM4 becomes 0, a match is detected and INTCM4 is generated. Although the TM4 value is cleared (0) at the next count timing, INTCM4 is not generated according to this match. Figure 9-104. TM4 Compare Operation Example (1/2) (a) When CM4 is set to n (non-zero) Count clock Count up TM4 clear Clear TM4 n 0 1 CM4 n Match detection (INTCM4) Remark Interval time = (n + 1) x Count clock cycle n = 1 to 65536 (FFFFH) User's Manual U14492EJ5V0UD 405 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-104. TM4 Compare Operation Example (2/2) (b) When CM4 is set to 0 Count clock Count up TM4 clear Clear TM4 FFFFH 0 0 1 CM4 0 Match detection (INTCM4) Overflow Remark Interval time = (FFFFH + 2) x Count clock cycle 406 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.5.6 Application example (1) Interval timer This section explains an example in which timer 4 is used as an interval timer with 16-bit precision. Interrupt requests (INTCM4) are output at equal intervals (refer to Figure 9-104 TM4 Compare Operation Example). The setup procedure is shown below. <1> Set (1) the TM4CAE0 bit. <2> Set each register. * Select the count clock using the CS2 to CS0 bits of the TMC4 register. * Set the compare value in the CM4 register. <3> Start counting by setting (1) the TM4CE0 bit. <4> If the TM4 register and CM4 register values match, an INTCM4 interrupt is generated. <5> INTCM4 interrupts are generated thereafter at equal intervals. 9.5.7 Precautions Various precautions concerning timer 4 are shown below. (1) To operate TM4, first set (1) the TM4CAE0 bit of the TMC4 register. (2) Up to 4 internal system clocks are required after a value is set in the TM4CE0 bit of the TMC4 register until the set value is transferred to internal units. When a count operation begins, the count cycle from 0000H to 0001H differs from subsequent count cycles. (3) To initialize the TM4 register status and start counting again, clear (0) the TM4CE0 bit and then set (1) the TM4CE0 bit after an interval of 4 internal system clocks has elapsed. (4) Up to 4 internal system clocks are required until the value that was set in the CM4 register is transferred to internal units. When writing continuously to the CM4 register, be sure to secure a time interval of at least 4 internal system clocks. (5) The CM4 register can be overwritten only once during a timer/counter operation (from 0000H until an INTCM4 interrupt is generated due to a match of the TM4 register and CM4 register). If this cannot be secured by the application, make sure that the CM4 register is not overwritten during a timer/counter operation. (6) The count clock must not be changed during a timer operation. If it is to be overwritten, it should be overwritten after the TM4CE0 bit is cleared (0). If the count clock is overwritten during a timer operation, operation cannot be guaranteed. (7) An INTCM4 interrupt will be generated after an overflow if a value less than the counter value is written in the CM4 register during TM4 register operation. User's Manual U14492EJ5V0UD 407 CHAPTER 9 TIMER/COUNTER FUNCTION 9.6 Timer Connection Function 9.6.1 Overview The V850E/IA1 provides a function to connect timer 1 and timer 2. Figure 9-105. Block Diagram of Timer Connection Function Timer connection selector Capture 0 Capture 1 Timer 1 INTCM100 INTCM0 Timer 2 CVSE10/ CVPE10 CVSE20/ CVPE20 INTCM101 INTCM1 TMIC0 TMIC1 TMIC2 TMIC3 TMIC0 register 408 User's Manual U14492EJ5V0UD CHAPTER 9 TIMER/COUNTER FUNCTION 9.6.2 Control register (1) Timer connection selection register 0 (TMIC0) The TMIC0 register enables/disables input of the INTCM100, INTCM101 signals to the CVSEn0/CVPEn0 registers (n = 1, 2). This register can be read/written in 8-bit or 1-bit units. 7 TMIC0 0 6 0 5 0 4 0 3 TMIC3 2 TMIC2 1 TMIC1 0 TMIC0 Address FFFFF620H Initial value 00H Bit position 3 Bit name TMIC3 Function Enables/disables input of INTCM101 signal to CVSE20/CVPE20 registers. 0: Don't input INTCM101 signal to CVSE20/CVPE20 registers. 1: Input INTCM101 signal to CVSE20/CVPE20 registers. 2 TMIC2 Enables/disables input of INTCM100 signal to CVSE20/CVPE20 registers. 0: Don't input INTCM100 signal to CVSE20/CVPE20 registers. 1: Input INTCM100 signal to CVSE20/CVPE20 registers. 1 TMIC1 Enables/disables input of INTCM101 signal to CVSE10/CVPE10 registers. 0: Don't input INTCM101 signal to CVSE10/CVPE10 registers. 1: Input INTCM101 signal to CVSE10/CVPE10 registers. 0 TMIC0 Enables/disables input of INTCM100 signal to CVSE10/CVPE10 registers. 0: Don't input INTCM100 signal to CVSE10/CVPE10 registers. 1: Input INTCM100 signal to CVSE10/CVPE10 registers. User's Manual U14492EJ5V0UD 409 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.1 Features The serial interface function provides three types of serial interfaces combining a total of six transmit/receive channels. All six channels can be used simultaneously. The three interface formats are as follows. (1) Asynchronous serial interfaces (UART0 to UART2): 3 channels (2) Clocked serial interfaces (CSI0, CSI1): 2 channels (3) FCAN controller: 1 channel Remark For details about the FCAN controller, refer to CHAPTER 11 FCAN CONTROLLER. UART0 to UART2, whereby one byte of serial data is transmitted/received following a start bit, support full-duplex communication. In the UART1 and UART2 interfaces, one higher bit is added to 8 bits of transmit/receive data, enabling communication using 9-bit data. CSI0 and CSI1 perform data transfer according to three types of signals, namely serial clocks (SCK0, SCK1), serial inputs (SI0, SI1), and serial outputs (SO0, SO1) (3-wire serial I/O). FCAN conforms to CAN specification Ver. 2.0 PartB active, and provides a 32-message buffer. 410 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2 Asynchronous Serial Interface 0 (UART0) 10.2.1 Features * Transfer rate: 300 bps to 1562.5 Kbps (using a dedicated baud rate generator and an internal system clock of 50 MHz) * Full-duplex communications On-chip receive buffer register 0 (RXB0) On-chip transmit buffer register 0 (TXB0) * Two-pin configurationNote TXD0: Transmit data output pin RXD0: Receive data input pin * Reception error detection functions * Parity error * Framing error * Overrun error * Interrupt sources: 3 types * Reception error interrupt (INTSER0): * Reception completion interrupt (INTSR0): Interrupt is generated according to the logical OR of the three types of reception errors Interrupt is generated when receive data is transferred from the receive shift register to receive buffer register 0 after serial transfer is completed during a reception enabled state * Transmission completion interrupt (INTST0): Interrupt is generated when the serial transmission of transmit data (8 or 7 bits) from the transmit shift register is completed * The character length of transmit/receive data is specified according to the ASIM0 register * Character length: 7 or 8 bits * Parity functions: Odd, even, 0, or none * Transmission stop bits: 1 or 2 bits * On-chip dedicated baud rate generator Note The SCK and CTS pins are not available for UART0. User's Manual U14492EJ5V0UD 411 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.2 Configuration UART0 is controlled by asynchronous serial interface mode register 0 (ASIM0), asynchronous serial interface status register 0 (ASIS0), and asynchronous serial interface transmit status register 0 (ASIF0). Receive data is maintained in receive buffer register 0 (RXB0), and transmit data is written to transmit buffer register 0 (TXB0). Figure 10-1 shows the configuration of asynchronous serial interface 0 (UART0). (1) Asynchronous serial interface mode register 0 (ASIM0) The ASIM0 register is an 8-bit register for specifying the operation of the asynchronous serial interface. (2) Asynchronous serial interface status register 0 (ASIS0) The ASIS0 register consists of a set of flags that indicate the error contents when a reception error occurs. The various reception error flags are set (1) when a reception error occurs and are reset (0) when the ASIS0 register is read. (3) Asynchronous serial interface transmit status register 0 (ASIF0) The ASIF0 register is an 8-bit register that indicates the status when a transmit operation is performed. This register consists of a transmit buffer data flag, which indicates the hold status of TXB0 data, and the transmit shift register data flag, which indicates whether transmission is in progress. (4) Reception control parity check The receive operation is controlled according to the contents set in the ASIM0 register. A check for parity errors is also performed during a receive operation, and if an error is detected, a value corresponding to the error contents is set in the ASIS0 register. (5) Receive shift register This is a shift register that converts the serial data that was input to the RXD0 pin to parallel data. One byte of data is received, and if a stop bit is detected, the receive data is transferred to receive buffer register 0 (RXB0). This register cannot be directly manipulated. (6) Receive buffer register 0 (RXB0) This is an 8-bit buffer register for holding receive data. When 7 characters are received, 0 is stored in the MSB. During a reception enabled state, receive data is transferred from the receive shift register to the RXB0 register, synchronized with the end of the shift-in processing of one frame. Also, the reception completion interrupt request (INTSR0) is generated by the transfer of data to the RXB0 register. (7) Transmit shift register This is a shift register that converts the parallel data that was transferred from transmit buffer register 0 (TXB0) to serial data. When one byte of data is transferred from the TXB0 register, the shift register data is output from the TXD0 pin. The transmission completion interrupt request (INTST0) is generated synchronized with the completion of transmission of one frame. This register cannot be directly manipulated. 412 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (8) Transmit buffer register 0 (TXB0) This is an 8-bit buffer for transmit data. A transmit operation is started by writing transmit data to TXB0. (9) Addition of transmission control parity A transmit operation is controlled by adding a start bit, parity bit, or stop bit to the data that is written to the TXB0 register, according to the contents that were set in the ASIM0 register. Figure 10-1. Asynchronous Serial Interface 0 Block Diagram Internal bus Asynchronous serial interface mode register 0 (ASIM0) Receive buffer register 0 (RXB0) Transmit buffer register 0 (TXB0) RXD0 TXD0 Receive shift register Transmit shift register Reception control parity check Parity Framing Overrun Addition of transmission control parity INTST0 INTSR0 INTSER0 BRG0 Remark For the configuration of baud rate generator 0, see Figure 10-12. User's Manual U14492EJ5V0UD 413 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.3 Control registers (1) Asynchronous serial interface mode register 0 (ASIM0) The ASIM0 register is an 8-bit register that controls the UART0 transfer operation. This register can be read/written in 8-bit or 1-bit units. Cautions 1. When using UART0, be sure to set the external pins related to the UART0 function to the control mode before setting clock selection register 0 (CKSR0) and baud rate generator control register 0 (BRGC0), and then set the UARTCAE0 bit to 1. Then set the other bits. 2. Set the UARTCAE0 and RXE0 bits to 1 while a high level is input to the RXD0 pin. If these bits are set to 1 while a low high level is input to the RXD0 pin, reception will be started. (1/3) <7> ASIM0 UARTCAE0 <6> TXE0 <5> RXE0 4 PS1 3 PS0 2 CL 1 SL 0 ISRM Address FFFFFA00H Initial value 01H Bit position 7 Bit name UARTCAE0 Controls the operating clock. 0: Stops clock supply to UART0. 1: Supplies clock to UART0. Function Cautions 1. When UARTCAE0 = 0 is set, UART0 is asynchronously reset 2. When UARTCAE0 = 0, UART0 is in a reset state. To operate UART0, first set UARTCAE0 = 1. Note . 3. When the UARTCAE0 bit is cleared from 1 to 0, all the registers of UART0 are initialized. When setting UARTCAE0 = 1 again, be sure to re-set the registers of UART0. The output of the TXD0 pin goes high when transmission is disabled, regardless of the setting of the UARTCAE0 bit. 6 TXE0 Enables/disables transmission. 0: Disable transmission 1: Enable transmission Cautions 1. Set the TXE0 bit to 1 after setting the UARTCAE0 bit to 1 at startup. Set the UARTCAE0 bit to 0 after setting the TXE0 bit to 0 to stop. 2. To initialize the transmission unit, clear (0) the TXE0 bit, and after letting 2 cycles of the base clock elapse, set (1) the TXE0 bit again. If the TXE0 bit is not set again, initialization may not be successful (for details about the base clock, refer to 10.2.6 (1) (a) Base clock). Note Only the ASIS0, ASIF0, and RXB0 registers are reset. 414 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (2/3) Bit position 5 Bit name RXE0 Enables/disables reception. 0: Disable reception 1: Enable reception Cautions 1. Set the RXE0 bit to 1 after setting the UARTCAE0 bit to 1 at startup. Set the UARTCAE0 bit to 0 after setting the RXE0 bit to 0 to stop. 2. To initialize the reception unit status, clear (0) the RXE0 bit, and after letting 2 cycles of the base clock elapse, set (1) the RXE0 bit again. If the RXE0 bit is not set again, initialization may not be successful (for details about the base clock, refer to 10.2.6 (1) (a) Base clock). 4, 3 PS1, PS0 Controls parity bit. Note Function PS1 0 0 1 1 PS0 0 1 0 1 Transmit operation Don't output parity bit Output 0 parity Output odd parity Output even parity Receive operation Receive with no parity Receive as 0 parity Judge as odd parity Judge as even parity Cautions 1. To overwrite the PS1 and PS0 bits, first clear (0) the TXE0 and RXE0 bits. 2. If "0 parity" is selected for reception, no parity judgment is performed. Therefore, no error interrupt is generated because the PE bit of the ASIS0 register is not set. * Even parity If the transmit data contains an odd number of bits with the value "1", the parity bit is set (1). If it contains an even number of bits with the value "1", the parity bit is cleared (0). This controls the number of bits with the value "1" contained in the transmit data and the parity bit so that it is an even number. During reception, the number of bits with the value "1" contained in the receive data and the parity bit is counted, and if the number is odd, a parity error is generated. * Odd parity In contrast to even parity, odd parity controls the number of bits with the value "1" contained in the transmit data and the parity bit so that it is an odd number. During reception, the number of bits with the value "1" contained in the receive data and the parity bit is counted, and if the number is even, a parity error is generated. Note When reception is disabled, the receive shift register does not detect a start bit. No shift-in processing or transfer processing to receive buffer register 0 (RXB0) is performed, and the contents of the RXB0 register are retained. When reception is enabled, the reception shift operation starts, synchronized with the detection of the start bit, and when the reception of one frame is completed, the contents of the receive shift register are transferred to the RXB0 register. A reception completion interrupt (INTSR0) is also generated in synchronization with the transfer to the RXB0 register. User's Manual U14492EJ5V0UD 415 CHAPTER 10 SERIAL INTERFACE FUNCTION (3/3) Bit position 4, 3 Bit name PS1, PS0 * 0 parity During transmission, the parity bit is cleared (0) regardless of the transmit data. During reception, no parity error is generated because no parity bit is checked. * No parity No parity bit is added to transmit data. During reception, the receive data is considered to have no parity bit. No parity error is generated because there is no parity bit. 2 CL Specifies character length of 1 frame of transmit/receive data. 0: 7 bits 1: 8 bits Function Caution To overwrite the CL bit, first clear (0) the TXE0 and RXE0 bits. 1 SL Specifies stop bit length of transmit data. 0: 1 bit 1: 2 bits Cautions 1. To overwrite the SL bit, first clear (0) the TXE0 bit. 2. Since reception is always done with a stop bit length of 1, the SL bit setting does not affect receive operations. 0 ISRM Enables/disables generation of reception completion interrupt requests when an error occurs. 0: Generate a reception error interrupt request (INTSER0) as an interrupt when an error occurs. In this case, no reception completion interrupt request (INTSR0) is generated. 1: Generate a reception completion interrupt request (INTSR0) as an interrupt when an error occurs. In this case, no reception error interrupt request (INTSER0) is generated. Caution To overwrite the ISRM bit, first clear (0) the RXE0 bit. 416 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface status register 0 (ASIS0) The ASIS0 register, which consists of 3-bit error flags (PE, FE, and OVE), indicates the error status when UART0 reception is completed. The ASIS0 register is cleared to 00H by a read operation. When a reception error occurs, receive buffer register 0 (RXB0) should be read and the error flag should be cleared after the ASIS0 register is read. This register is read-only, in 8-bit units. Cautions 1. When the UARTCAE0 bit or RXE0 bit of the ASIM0 register is set to 0, or when the ASIS0 register is read, the PE, FE, and OVE bits of the ASIS0 register are cleared (0). 2. Manipulation using a bit manipulation instruction is prohibited. 7 ASIS0 0 6 0 5 0 4 0 3 0 2 PE 1 FE 0 OVE Address FFFFFA03H Initial value 00H Bit position 2 Bit name PE Function This is a status flag that indicates a parity error. 0: When the ASIM0 register's UARTCAE0 and RXE0 bits are both set to 0, or after the ASIS0 register is read 1: When reception was completed, the receive data parity did not match the parity bit Caution The operation of the PE bit differs according to the settings of the PS1 and PS0 bits of the ASIM0 register. 1 FE This is a status flag that indicates a framing error. 0: When the ASIM0 register's UARTCAE0 and RXE0 bits are both set to 0, or after the ASIS0 register is read 1: When reception was completed, no stop bit was detected Caution For receive data stop bits, only the first bit is checked regardless of the stop bit length. 0 OVE This is a status flag that indicates an overrun error. 0: When the ASIM0 register's UARTCAE0 and RXE0 bits are both set to 0, or after the ASIS0 register is read. 1: UART0 completed the next receive operation before reading the RXB0 register receive data. Caution When an overrun error occurs, the next receive data value is not written to the RXB0 register and the data is discarded. User's Manual U14492EJ5V0UD 417 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Asynchronous serial interface transmit status register 0 (ASIF0) The ASIF0 register, which consists of 2-bit status flags, indicates the status during transmission. By writing the next data to the TXB0 register after data is transferred from the TXB0 register to the transmit shift register, transmit operations can be performed continuously without suspension even during an interrupt interval. When transmission is performed continuously, data should be written after referencing the TXBF0 bit of the ASIF0 register to prevent writing to the TXB0 register by mistake. This register is read-only, in 8-bit or 1-bit units. 7 ASIF0 0 6 0 5 0 4 0 3 0 2 0 <1> TXBF0 <0> TXSF0 Address FFFFFA05H Initial value 00H Bit position 1 Bit name TXBF0 This is a transmit buffer data flag. Function 0: Data to be transferred next to TXB0 register does not exist (When the ASIM0 register's UARTCAE0 or TXE0 bit is 0, or when data has been transferred to the transmit shift register) 1: Data to be transferred next exists in TXB0 register (Data exists in TXB0 register when the TXB0 register has been written to) Caution When transmission is performed continuously, data should be written to the TXB0 register after confirming that this flag is 0. If writing to TXB0 register is performed when this flag is 1, transmit data cannot be guaranteed. 0 TXSF0 This is a transmit shift register data flag. It indicates the transmission status of UART0. 0: Initial status or a waiting transmission (When the ASIM0 register's UARTCAE0 or TXE0 bit is set to 0, or when following transmission completion, the next data transfer from the TXB0 register is not performed) 1: Transmission in progress (When data has been transferred from the TXB0 register) Caution When the transmission unit is initialized, initialization should be executed after confirming that this flag is 0 following the occurrence of a transmission completion interrupt (INTST0). If initialization is performed when this flag is 1, transmit data cannot be guaranteed. 418 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Receive buffer register 0 (RXB0) The RXB0 register is an 8-bit buffer register for storing parallel data that had been converted by the receive shift register. When reception is enabled (RXE0 bit = 1 in the ASIM0 register), receive data is transferred from the receive shift register to the RXB0 register, synchronized with the completion of the shift-in processing of one frame. Also, a reception completion interrupt request (INTSR0) is generated by the transfer to the RXB0 register. For information about the timing for generating this interrupt request, refer to 10.2.5 (4) operation. If reception is disabled (RXE0 bit = 0 in the ASIM0 register), the contents of the RXB0 register are retained, and no processing is performed for transferring data to the RXB0 register even when the shift-in processing of one frame is completed. Also, no INTSR0 signal is generated. When 7 bits is specified for the data length, bits 6 to 0 of the RXB0 register are transferred for the receive data and the MSB (bit 7) is always 0. However, if an overrun error (OVE bit of ASIS0 register = 1) occurs, the receive data at that time is not transferred to the RXB0 register. Except when a reset is input, the RXB0 register becomes FFH even when UARTCAE0 bit = 0 in the ASIM0 register. This register is read-only, in 8-bit units. Reception 7 RXB0 RXB7 6 RXB6 5 RXB5 4 RXB4 3 RXB3 2 RXB2 1 RXB1 0 RXB0 Address FFFFFA02H Initial value FFH Bit position 7 to 0 Bit name RXB7 to RXB0 Stores receive data. Function 0 can be read for RXB7 when 7-bit or character data is received. User's Manual U14492EJ5V0UD 419 CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Transmit buffer register 0 (TXB0) The TXB0 register is an 8-bit buffer register for setting transmit data. When transmission is enabled (TXE0 bit = 1 in the ASIM0 register), the transmit operation is started by writing data to TXB0 register. When transmission is disabled (TXE0 bit = 0 in the ASIM0 register), even if data is written to TXB0 register, the value is ignored. The TXB0 register data is transferred to the transmit shift register, and a transmission completion interrupt request (INTST0) is generated, synchronized with the completion of the transmission of one frame from the transmit shift register. For information about the timing for generating this interrupt request, refer to 10.2.5 (2) Transmission operation. When TXBF0 bit = 1 in the ASIF0 register, writing must not be performed to TXB0 register. This register can be read/written in 8-bit units. 7 TXB0 TXB7 6 TXB6 5 TXB5 4 TXB4 3 TXB3 2 TXB2 1 TXB1 0 TXB0 Address FFFFFA04H Initial value FFH Bit position 7 to 0 Bit name TXB7 to TXB0 Writes transmit data. Function 420 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.4 Interrupt requests The following three types of interrupt requests are generated from UART0. * Reception completion interrupt (INTSR0) * Transmission completion interrupt (INTST0) * Reception error interrupt (INTSER0) The default priorities among these three types of interrupt requests is, from high to low, reception completion interrupt, transmission completion interrupt, and reception error interrupt. Table 10-1. Generated Interrupts and Default Priorities Interrupt Reception completion Transmission completion Reception error Priority 1 2 3 (1) Reception completion interrupt (INTSR0) When reception is enabled, an INTSR0 signal is generated when data is shifted in to the receive shift register and transferred to receive buffer register 0 (RXB0). An INTSR0 signal can be generated in place of a reception error interrupt (INTSER0) according to the ISRM bit of the ASIM0 register even when a reception error has occurred. When reception is disabled, no INTSR0 signal is generated. (2) Transmission completion interrupt (INTST0) An INTST0 signal is generated when one frame of transmit data containing 7-bit or 8-bit characters is shifted out from the transmit shift register. (3) Reception error interrupt (INTSER0) When reception is enabled, an INTSER0 signal is generated according to the logical OR of the three types of reception errors explained for the ASIS0 register. Whether an INTSER0 signal or INTSR0 signal is generated when an error occurs can be specified using the ISRM bit of the ASIM0 register. When reception is disabled, no INTSER0 signal is generated. User's Manual U14492EJ5V0UD 421 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.5 Operation (1) Data format Full-duplex serial data transmission and reception can be performed. The transmit/receive data format consists of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in Figure 10-2. The character bit length within one data frame, the type of parity, and the stop bit length are specified according to the asynchronous serial interface mode register 0 (ASIM0). Also, data is transferred with LSB first. Figure 10-2. Asynchronous Serial Interface Transmit/Receive Data Format 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bits Character bits * Start bit *** 1 bit * Character bits *** 7 bits or 8 bits * Parity bit *** Even parity, odd parity, 0 parity, or no parity * Stop bits *** 1 bit or 2 bits 422 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Transmission operation When UARTCAE0 bit is set to 1 in the ASIM0 register, a high level is output from the TXD0 pin. Then, when TXE0 bit is set to 1 in the ASIM0 register, transmission is enabled, and the transmit operation is started by writing transmit data to transmit buffer register 0 (TXB0). (a) Transmission enabled state This state is set by the TXE0 bit in the ASIM0 register. * TXE0 = 1: Transmission enabled state * TXE0 = 0: Transmission disabled state Since UART0 does not have a CTS (transmission enabled signal) input pin, a port should be used to confirm whether the destination is in a reception enabled state. (b) Transmission operation start In transmission enabled state, a transmission operation is started by writing transmit data to transmit buffer register 0 (TXB0). When a transmit operation is started, the data in the TXB0 register is transferred to the transmit shift register. Then, the transmit shift register outputs data to the TXD0 pin (the transmit data is transferred sequentially starting with the start bit). The start bit, parity bit, and stop bits are added automatically. (c) Transmission interrupt request When the transmit shift register becomes empty, a transmission completion interrupt request (INTST0) is generated. The timing for generating the INTST0 signal differs according to the specification of the stop bit length. The INTST0 signal is generated at the same time that the last stop bit is output. If the data to be transmitted next has not been written to the TXB0 register, the transmit operation is suspended. Caution Normally, when the transmit shift register becomes empty, a transmission completion interrupt (INTST0) is generated. However, no INTST0 signal is generated if the transmit shift register becomes empty due to the input of a RESET. User's Manual U14492EJ5V0UD 423 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-3. Asynchronous Serial Interface Transmission Completion Interrupt Timing (a) Stop bit length: 1 TXD0 (output) Start D0 D1 D2 D6 D7 Parity Stop INTST0 (output) (b) Stop bit length: 2 TXD0 (output) Start D0 D1 D2 D6 D7 Parity Stop INTST0 (output) 424 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Continuous transmission operation UART0 can write the next transmit data to the TXB0 register at the timing that the transmit shift register starts the shift operation. This enables an efficient transmission rate to be realized by continuously transmitting data even during the servicing of the transmission completion interrupt (INTST0) after the transmission of one data frame. In addition, reading the TXSF0 bit of the ASIF0 register after the generation of an INTST0 signal enables the TXB0 register to be efficiently written twice (2 bytes) without waiting for the transmission of 1 data frame. When continuous transmission is performed, data should be written after referencing the ASIF0 register to confirm the transmission status and whether or not data can be written to the TXB0 register. Caution The values of the TXBF0 and TXSF0 bits of the ASIF0 register change from 10 11 01 in continuous transmission. Therefore, do not confirm the status based on the combination of the TXBF0 and TXSF0 bits. Read only the TXBF0 bit during continuous transmission. TXBF0 0 1 Whether or Not Writing to TXB0 Register Is Enabled Writing is enabled Writing is not enabled Caution When transmission is performed continuously, write the first transmit data (first byte) to the TXB0 register and confirm that the TXBF0 bit is 0, and then write the next transmit data (second byte) to TXB0 register. If writing to the TXB0 register is performed when the TXBF0 bit is 1, transmit data cannot be guaranteed. The communication status can be confirmed with the TXSF0 bit. TXSF0 0 1 Transmission is completed Under transmission Transmission Status Cautions 1. When initializing the transmission unit when continuous transmission is completed, confirm that the TXSF0 bit is 0 after the occurrence of the transmission completion interrupt, and then execute initialization. If initialization is performed when the TXSF0 bit is 1, transmit data cannot be guaranteed. 2. While transmission is being performed continuously, an overrun error may occur if the next transmission is completed before the INTST0 interrupt servicing following the transmission of 1 data frame is executed. TXSF0 bit. An overrun error can be detected by embedding a program that can count the number of transmit data and referencing User's Manual U14492EJ5V0UD 425 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-4. Continuous Transmission Processing Flow Set registers Write transmit data to TXB0 register No When reading ASIF0 register, TXBF0 = 0? Yes Write 2nd byte of the transmit data to TXB0 register Interrupt occurrence Required number of transfers performed? No Yes No When reading ASIF0 register, TXSF0 = 1? Yes When reading ASIF0 register, TXSF0 = 0? Yes No Write transmit data to TXB0 register Wait for interrupt End of transmission processing 426 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (a) Starting procedure The procedure to start continuous transmission is shown below. Figure 10-5. Continuous Transmission Starting Procedure TXD0 (output) <1> INTST0 (output) Start bit <2> Data (1) Stop bit <3> Start bit <4> Data (2) Stop bit <5> TXB0 register FFH Data (1) Data (2) Data (3) TXS0 register ASIF0 register (TXBF0, TXSF0 bits) FFH 10 11Note Data (1) Data (2) Data (3) 00 01 11 01 11 01 11 Note Refer to 10.2.7 Precautions (2). Transmission Starting Procedure Internal Operation ASIF0 Register TXBF0 TXSF0 0 0 1 1 Note * Set transmission mode * Write data (1) <1> Start transmission unit 0 1 <2> Generate start bit 1 0 Note Start data (1) transmission * Read ASIF0 register (confirm that TXBF0 bit = 0) * Write data (2) < 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 Note Refer to 10.2.7 Precautions (2). User's Manual U14492EJ5V0UD 427 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Ending procedure The procedure for ending continuous transmission is shown below. Figure 10-6. Continuous Transmission End Procedure TXD0 (output) <6> INTST0 (output) <7> Start bit <8> Data (m - 1) Stop bit <9> Start bit <10> Data (m) <11> Stop bit TXB0 register Transmit shift register ASIF0 register (TXBF0, TXSF0 bits) Data (m - 1) Data (m - 1) Data (m) Data (m) FFH 11 01 11 01 00 UARTCAE0 bit or TXE0 bit Transmission End Procedure Internal Operation ASIF0 Register TXBF0 TXSF0 1 <6> Transmission of data (m - 2) is in progress <7> INTST0 interrupt occurs * Read ASIF0 register (confirm that TXBF0 bit = 0) * Write data (m) <8> Generate start bit Start data (m - 1) transmission < 1 0 0 1 1 1 1 0 0 1 1 0 0 0 0 428 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Reception operation An awaiting reception state is set by setting UARTCAE0 bit to 1 in the ASIM0 register and then setting RXE0 bit to 1 in the ASIM0 register. To start the receive operation, start sampling at the falling edge when the falling of the RXD0 pin is detected. If the RXD0 pin is low level at a start bit sampling point, the start bit is recognized. When the receive operation begins, serial data is stored sequentially in the receive shift register according to the baud rate that was set. A reception completion interrupt (INTSR0) is generated each time the reception of one frame of data is completed. Normally, the receive data is transferred from receive buffer register 0 (RXB0) to memory by this interrupt servicing. (a) Reception enabled state The receive operation is set to reception enabled state by setting the RXE0 bit in the ASIM0 register to 1. * RXE0 bit = 1: Reception enabled state * RXE0 bit = 0: Reception disabled state In reception disabled state, the reception hardware stands by in the initial state. At this time, the contents of receive buffer register 0 (RXB0) are retained, and no reception completion interrupt or reception error interrupt is generated. (b) Start of reception operation A reception operation is started by the detection of a start bit. The RXD0 pin is sampled according to the serial clock from the baud rate generator 0 (BRG0). (c) Reception completion interrupt When RXE0 = 1 in the ASIM0 register and the reception of one frame of data is completed (the stop bit is detected), a reception completion interrupt (INTSR0) is generated and the receive data in the receive shift register is transferred to the RXB0 register at the same time. Also, if an overrun error (OVE bit of ASIS0 register = 1) occurs, the receive data at that time is not transferred to receive buffer register 0 (RXB0), and either an INTSR0 signal or a reception error interrupt (INTSER0) is generated according to the ISRM bit setting in the ASIM0 register. Even if a parity error (PE bit of ASIS0 register = 1) or framing error (FE bit of ASIS0 register = 1) occurs during a receive operation, the receive operation continues until stop bit is received, and after reception is completed, either an INTSR0 signal or an INTSER0 signal is generated according to the ISRM bit setting in the ASIM0 register (the receive data in the receive shift register is transferred to the RXB0 register). If the RXE0 bit is cleared (0) during a receive operation, the receive operation is immediately stopped. The contents of receive buffer register 0 (RXB0) and of the asynchronous serial interface status register (ASIS0) at this time do not change, and no INTSR0 or INTSER0 signal is generated. No INTSR0 or INTSER0 signal is generated when RXE0 = 0 (reception is disabled). User's Manual U14492EJ5V0UD 429 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-7. Asynchronous Serial Interface Reception Completion Interrupt Timing RXD0 (input) Start D0 D1 D2 D6 D7 Parity Stop INTSR0 (output) RXB0 register Cautions 1. Even if a reception error occurs, be sure to read receive buffer register 0 (RXB0). If the RXB0 register is not read, an overrun error will occur at the next data reception, and the reception error state will continue indefinitely. 2. Reception is always performed with the stop bit length set to 1. A second stop bit is ignored. (5) Reception error The three types of error that can occur during a receive operation are a parity error, framing error, or overrun error. The data reception result is that the various flags of the ASIS0 register are set (1), and a reception error interrupt (INTSER0) or a reception completion interrupt (INTSR0) is generated at the same time. The ISRM bit of the ASIM0 register specifies whether an INTSER0 or INTSR0 signal is generated. The type of error that occurred during reception can be detected by reading the contents of the ASIS0 register during the INTSER0 or INTSR0 interrupt servicing. The contents of the ASIS0 register are cleared (0) by reading the ASIS0 register. Table 10-2. Reception Error Causes Error Flag PE Reception Error Parity error Cause The parity specification during transmission did not match the parity of the reception data FE OVE Framing error Overrun error No stop bit was detected The reception of the next data was completed before data was read from receive buffer register 0 (RXB0) 430 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (a) Separation of reception error interrupt A reception error interrupt can be separated from the INTSR0 signal and generated as an INTSER0 signal by clearing the ISRM bit of the ASIM0 register to 0. Figure 10-8. When Reception Error Interrupt Is Separated from INTSR0 Interrupt (ISRM Bit = 0) (a) No error occurs during reception (b) An error occurs during reception INTSR0 signal (output) (Reception completion interrupt) INTSER0 signal (output) (Reception error interrupt) INTSR0 signal (output) (Reception completion interrupt) INTSER0 signal (output) (Reception error interrupt) INTSR0 signal does not occur Figure 10-9. When Reception Error Interrupt Is Included in INTSR0 Interrupt (ISRM Bit = 1) (a) No error occurs during reception (b) An error occurs during reception INTSR0 signal (output) (Reception completion interrupt) INTSER0 signal (output) (Reception error interrupt) INTSR0 signal (output) (Reception completion interrupt) INTSER0 signal (output) (Reception error interrupt) INTSER0 signal does not occur User's Manual U14492EJ5V0UD 431 CHAPTER 10 SERIAL INTERFACE FUNCTION (6) Parity types and corresponding operation A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used at the transmission and reception sides. (a) Even parity (i) During transmission The parity bit is controlled so that the number of bits with the value "1" within the transmit data including the parity bit is even. The parity bit value is as follows. * If the number of bits with the value "1" within the transmit data is odd: 1 * If the number of bits with the value "1" within the transmit data is even: 0 (ii) During reception The number of bits with the value "1" within the receive data including the parity bit is counted, and a parity error is generated if this number is odd. (b) Odd parity (i) During transmission In contrast to even parity, the parity bit is controlled so that the number of bits with the value "1" within the transmit data including the parity bit is odd. The parity bit value is as follows. * If the number of bits with the value "1" within the transmit data is odd: 0 * If the number of bits with the value "1" within the transmit data is even: 1 (ii) During reception The number of bits with the value "1" within the receive data including the parity bit is counted, and a parity error is generated if this number is even. (c) 0 parity During transmission the parity bit is set to "0" regardless of the transmit data. During reception, no parity bit check is performed. Therefore, no parity error is generated regardless of whether the parity bit is "0" or "1". (d) No parity No parity bit is added to the transmit data. During reception, the receive operation is performed as if there were no parity bit. Since there is no parity bit, no parity error is generated. 432 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (7) Receive data noise filter The RXD0 signal is sampled at the rising edge of the prescaler output base clock (fCLK). If the same sampling value is obtained twice, the match detector output changes, and this output is sampled as input data. Therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see Figure 10-11). Refer to 10.2.6 (1) (a) Base clock regarding the base clock. Also, since the circuit is configured as shown in Figure 10-10, internal processing during a receive operation is delayed by up to 2 clocks according to the external signal status. Figure 10-10. Noise Filter Circuit Base clock fCLK RXD0 In Q Internal signal A In LD_EN Q Internal signal B Match detector Figure 10-11. Timing of RXD0 Signal Judged as Noise Base clock RXD0 (input) Internal signal A Match Mismatch (judged as noise) Match Mismatch (judged as noise) Internal signal B User's Manual U14492EJ5V0UD 433 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.6 Dedicated baud rate generator 0 (BRG0) A dedicated baud rate generator, which consists of a source clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception at UART0. The dedicated baud rate generator output can be selected as the serial clock for each channel. Separate 8-bit counters exist for transmission and for reception. (1) Baud rate generator 0 (BRG0) configuration Figure 10-12. Baud Rate Generator 0 (BRG0) Configuration UARTCAE0 fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1024 fXX/2048 Match detector 1/2 Baud rate Selector Base clock (fCLK) 8-bit counter UARTCAE0 and TXE0 (or RXE0) CKSR0: TPS3 to TPS0 BRGC0: MDL7 to MDL0 Remark fXX: Internal system clock (a) Base clock When UARTCAE0 bit = 1 in the ASIM0 register, the clock selected according to the TPS3 to TPS0 bits of the CKSR0 register is supplied to the transmission/reception unit. This clock is called the base clock (fCLK). When UARTCAE0 bit = 0, fCLK is fixed at low level. 434 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Serial clock generation A serial clock can be generated according to the settings of the CKSR0 and BRGC0 registers. The base clock to the 8-bit counter is selected according to the TPS3 to TPS0 bits of the CKSR0 register. The 8-bit counter divisor value can be set according to the MDL7 to MDL0 bits of the BRGC0 register. (a) Clock selection register 0 (CKSR0) The CKSR0 register is an 8-bit register for selecting the base clock (fCLK) according to the TPS3 to TPS0 bits. The clock selected by the TPS3 to TPS0 bits becomes fCLK of the transmission/reception module. This register can be read/written in 8-bit units. Cautions 1. The maximum allowable frequency of the base clock (fCLK) is 25 MHz. Therefore, when the system clock's frequency is 50 MHz, bits TPS3 to TPS0 cannot be set to 0000B. To use 50 MHz, set the TPS3 to TPS0 bits to a value other than 0000B, and set the UARTCAE0 bit of the ASIM0 register to 1. 2. If the TPS3 to TPS0 bits are to be overwritten, the UARTCAE0 bit of the ASIM0 register should be set to 0 first. 7 CKSR0 0 6 0 5 0 4 0 3 TPS3 2 TPS2 1 TPS1 0 TPS0 Address FFFFFA06H Initial value 00H Bit position 3 to 0 Bit name TPS3 to TPS0 TPS3 0 0 0 0 0 0 0 0 1 1 1 1 1 TPS2 0 0 0 0 1 1 1 1 0 0 0 0 1 TPS1 0 0 1 1 0 0 1 1 0 0 1 1 Specifies the base clock (fCLK). Function TPS0 0 1 0 1 0 1 0 1 0 1 0 1 fXX fXX/2 fXX/4 fXX/8 fXX/16 fXX/32 fXX/64 fXX/128 fXX/256 fXX/512 fXX/1024 fXX/2048 Base clock (fCLK) Arbitrary Arbitrary Setting prohibited Remark fXX: Internal system clock User's Manual U14492EJ5V0UD 435 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Baud rate generator control register 0 (BRGC0) The BRGC0 register is an 8-bit register that controls the baud rate (serial transfer speed) of UART0. This register can be read/written in 8-bit units. Caution If the MDL7 to MDL0 bits are to be overwritten, the TXE0 bit and RXE0 bit of the ASIM0 register should be set to 0 first. 7 BRGC0 MDL7 6 MDL6 5 MDL5 4 MDL4 3 MDL3 2 MDL2 1 MDL1 0 MDL0 Address FFFFFA07H Initial value FFH Bit position 7 to 0 Bit name MDL7 to MDL0 Function Specifies the 8-bit counter's division value. MDL7 MDL6 MDL5 MDL4 MDL3 MDL2 MDL1 MDL0 Set value Serial clock (k) 0 0 0 0 0 x x x - Setting prohibited 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 1 0 8 9 10 fCLK/8 fCLK/9 fCLK/10 Remarks 1. fCLK: Frequency [Hz] of base clock selected according to TPS3 to TPS0 bits of CKSR0 register 2. k: Value set according to MDL7 to MDL0 bits (k = 8, 9, 10, ..., 255) 3. The baud rate is the output clock for the 8-bit counter divided by 2 4. x: don't care ... 1 1 1 1 1 1 ... 1 1 1 1 1 1 ... 1 1 1 1 1 1 ... 1 1 1 1 1 1 ... 1 1 1 1 1 1 ... 0 0 1 1 1 1 ... 1 1 0 0 1 1 ... 0 1 0 1 0 1 ... 250 251 252 253 254 255 fCLK/250 fCLK/251 fCLK/252 fCLK/253 fCLK/254 fCLK/255 ... 436 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Baud rate The baud rate is the value obtained according to the following formula. Baud rate = fCLK 2xk [bps] fCLK = Frequency [Hz] of base clock selected according to TPS3 to TPS0 bits of CKSR0 register k = Value set according to MDL7 to MDL0 bits of BRGC0 register (k = 8, 9, 10, ..., 255) (d) Baud rate error The baud rate error is obtained according to the following formula. Error (%) = Actual baud rate (baud rate with error) Target baud rate (normal baud rate) -1 x 100 [%] Cautions 1. Make sure that the baud rate error during transmission does not exceed the allowable error of the reception destination. 2. Make sure that the baud rate error during reception is within the allowable baud rate range during reception, which is described in (4) Allowable baud rate range during reception. Example: Base clock frequency (fCLK) = 20 MHz = 20,000,000 Hz Settings of MDL7 to MDL0 bits in BRGC0 register = 01000001B (k = 65) Target baud rate = 153,600 bps Baud rate = 20M/(2 x 65) = 20000000/(2 x 65) = 153,846 [bps] Error = (153846/153600 - 1) x 100 = 0.160 [%] User's Manual U14492EJ5V0UD 437 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Baud rate setting example Table 10-3. Baud Rate Generator Setting Data fXX = 50 MHz fCLK fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 9 Baud Rate (bps) 300 600 1200 2400 4800 9600 19200 31250 38400 76800 153600 312500 625000 1250000 1562500 fXX = 40 MHz ERR 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0 0.15 0.15 0.47 0 0 0 0 fCLK fXX/2 10 fXX = 33 MHz ERR 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 0.16 0.16 0.16 0 0 0 fCLK fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 - 8 fXX = 10 MHz ERR fCLK fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 - - 7 k 163 163 163 163 163 163 163 100 163 163 81 40 20 10 8 k 65 65 65 65 65 65 65 80 65 65 65 32 16 8 8 k 215 215 215 215 215 215 215 132 215 107 54 26 13 8 - k 130 130 130 130 130 130 130 80 130 65 33 16 8 - - ERR 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 0.16 0.16 -1.36 0 0 - - -0.07 -0.07 -0.07 -0.07 -0.07 -0.07 -0.07 0 -0.07 0.39 -0.54 1.54 1.54 -17.5 - 8 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 9 7 6 7 8 6 5 6 7 5 4 5 6 4 3 4 5 3 2 3 4 2 1 3 3 2 1 2 3 1 0 1 2 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 -18.6 Caution Remark The maximum allowable frequency of the base clock (fCLK) is 25 MHz. fXX: fCLK: k: ERR: Internal system clock frequency Base clock frequency Setting values of MDL7 to MDL0 bits in BRGC0 register Baud rate error [%] 438 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination's baud rate is allowed during reception is shown below. Caution The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range. Figure 10-13. Allowable Baud Rate Range During Reception Latch timing UART0 transfer rate Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FL 1 data frame (11 x FL) Minimum allowable transfer rate Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum allowable transfer rate Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmax As shown in Figure 10-13, after the start bit is detected, the receive data latch timing is determined according to the counter that was set by the BRGC0 register. If all data up to the final data (stop bit) is in time for this latch timing, the data can be received normally. Applying this to 11-bit reception is, theoretically, as follows. FL = (Brate) -1 Brate: UART0 baud rate k: FL: BRGC0 register setting value 1-bit data length When the latch timing margin is made 2 base clocks, the minimum allowable transfer rate (FLmin) is as follows. FL min = 11x FL - k-2 2k x FL = 21k + 2 2k FL User's Manual U14492EJ5V0UD 439 CHAPTER 10 SERIAL INTERFACE FUNCTION Therefore, the transfer destination's maximum baud rate (BRmax) that can be received is as follows. BRmax = (FLmin/11)-1 = 22k 21k + 2 Brate Similarly, the maximum allowable transfer rate (FLmax) can be obtained as follows. 10 k+2 21k - 2 x FL max = 11x FL - x FL = FL 11 2xk 2xk 21k - 2 FL max = FL x 11 20k Therefore, the transfer destination's minimum baud rate (BRmin) that can be received is as follows. BRmin = (FLmax/11)-1 = 20k 21k - 2 Brate The allowable baud rate error of UART0 and the transfer destination can be obtained as follows from the expressions described above for computing the minimum and maximum baud rate values. Table 10-4. Maximum and Minimum Allowable Baud Rate Error Division Ratio (k) Maximum Allowable Baud Rate Error 8 20 50 100 255 +3.53% +4.26% +4.56% +4.66% +4.72% Minimum Allowable Baud Rate Error -3.61% -4.31% -4.58% -4.67% -4.73% Remarks 1. The reception precision depends on the number of bits in one frame, the base clock frequency, and the division ratio (k). The higher the base clock frequency and the larger the division ratio (k), the higher the precision. 2. k: BRGC0 register setting value 440 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Transfer rate during continuous transmission During continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of base clock longer than normal. However, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit. Figure 10-14. Transfer Rate During Continuous Transmission 1 data frame Start bit of second byte Bit 7 Parity bit Stop bit Start bit Bit 0 Bit 1 Start bit FL Bit 0 FL FL FL FL FL FLstp FL Representing the 1-bit data length by FL, the stop bit length by FLstp, and the base clock frequency by fCLK yields the following equation. FLstp = FL + 2/fCLK Therefore, the transfer rate during continuous transmission is as follows (when stop bit length = 1). Transfer rate = 11 x FL + (2/fCLK) 10.2.7 Precautions Precautions to be observed when using UART0 are shown below. (1) When the supply of clocks to UART0 is stopped (for example, IDLE or software STOP mode), operation stops with each register retaining the value it had immediately before the supply of clocks was stopped. The TXD0 pin output also holds and outputs the value it had immediately before the supply of clocks was stopped. However, operation is not guaranteed after the supply of clocks is restarted. Therefore, after the supply of clocks is restarted, the circuits should be initialized by setting UARTCAE0 bit = 0, RXE0 bit = 0, and TXE0 bit = 0 in the ASIM0 register. (2) UART0 has a 2-stage buffer configuration consisting of transmit buffer register 0 (TXB0) and the transmit shift register, and has status flags (TXBF0 and TXSF0 bits of ASIF0 register) that indicate the status of each buffer. If the TXBF0 and TXSF0 bits are read in continuous transmission simultaneously, the values change from 10 11 01. Thus, judge the timing for writing the next data to the TXB0 register by reading only the TXBF0 bit during continuous transmission. User's Manual U14492EJ5V0UD 441 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3 Asynchronous Serial Interfaces 1, 2 (UART1, UART2) 10.3.1 Features * Clocked (synchronous) mode/asynchronous mode can be selected * Operation clock Synchronous mode: Baud rate generator/external clock selectable Asynchronous mode: Baud rate generator * Transfer rate 600 bps to 153,600 bps (in asynchronous mode, fXX = 50 MHz) 4,800 bps to 1,000,000 bps (in synchronous mode) * Full-duplex communications (LSB first) On-chip receive buffer register n (RXBn) * Three-pin configuration TXDn: Transmit data output pin RXDn: Receive data input pin ASCKn: Synchronous serial clock I/O * Reception error detection function * Parity error * Framing error * Overrun error * Interrupt sources: 2 types * Reception completion interrupt (INTSRn): Interrupt is generated when receive data is transferred from the shift register to receive buffer register n (RXBn) after serial transfer is completed during a reception enabled state. * Transmission completion interrupt (INTSTn): Interrupt is generated when the serial transmission of transmit data (8/7 bits) from the shift register is completed. * The character length of transmit/receive data is specified with the ASIMn0 register (extension bits are specified with the ASIMn1 register) * Character length: 7 or 8 bits 9 bits (when extension bit is added) * * * * Parity functions: Odd, even, 0, or no parity Transmission stop bits: 1 or 2 bits Communication mode: 1-frame transfer or 2-frame continuous transfer enabled On-chip dedicated baud rate generator Remarks 1. n = 1, 2 2. fXX: Internal system clock 442 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.2 Configuration UART1 and UART2 are controlled by asynchronous serial interface mode registers 10, 11, 20, and 21 (ASIM10, ASIM11, ASIM20, ASIM21) and asynchronous serial interface status registers 1 and 2 (ASIS1, ASIS2). Receive data is held in the receive buffer registers (RXB1, RXBL1, RXB2, RXBL2), and transmit data is held in the transmit shift registers (TXS1, TXSL1, TXS2, TXSL2). Figure 10-15 shows the configuration of asynchronous serial interfaces 1 and 2 (UART1, UART2). (1) Asynchronous serial interface mode registers 10, 11, 20, 21 (ASIM10, ASIM11, ASIM20, ASIM21) The ASIMn0 and ASIMn1 registers are 8-bit registers that specify the operation of the asynchronous serial interface (n = 1, 2). (2) Asynchronous serial interface status registers 1, 2 (ASIS1, ASIS2) The ASIS1 and ASIS2 registers consist of a transmission status flag (SOTn), reception status flag (SIRn), a bit (RB8) that indicates the 9th bit when extension bit addition is enabled, and 3-bit error flags (PEn, FEn, OVEn) that indicate the error status at reception end (n = 1, 2). (3) Reception control parity check The receive operation is controlled according to the contents set in the ASIMn0 and ASIMn1 registers. A check for parity errors is also performed during receive operation, and if an error is detected, a value corresponding to the error contents is set in the ASIS1 and ASIS2 registers. (4) 2-frame continuous reception buffer registers (RXB1, RXB2)/receive buffer registers (RXBL1, RXBL2) RXBn is a 16-bit (during 2-frame continuous reception, 9-bit extension data reception) buffer register that holds receive data. During 7, 8 bit/character reception, 0 is stored in the MSB. For 16-bit access to this register, specify RXB1, RXB2, and for access to the lower 8 bits, specify RXBL1, RXBL2. In the reception enabled state, receive data is transferred from the receive shift register to the receive buffer in synchronization with the completion of shift-in processing of one frame. A reception completion interrupt request (INTSRn) is generated upon transfer to the receive buffer (when 2frame continuous reception is specified, receive buffer transfer of the second frame). (5) 2-frame continuous transmission shift registers (TXS1, TXS2)/transmit shift registers (TXSL1, TXSL2) TXSn is a 9-bit/2-frame continuous transmission processing shift register. Transmission is started by writing data to this register. A transmission completion interrupt request (INTSTn) is generated in synchronization with the end of transmission of 1 frame or 2 frames including the TXSn data. For 16-bit access to this register, specify TXS1, TXS2, and for access to the lower 8 bits, specify TXSL1, TXSL2. (6) Addition of transmission control parity A transmission operation is controlled by adding a start bit, parity bit, or stop bit to the data that is written to the TXSn or TXSLn register, according to the contents set in the ASIMn0, ASIMn1 registers. (7) Selector The selector selects the serial clock source. User's Manual U14492EJ5V0UD 443 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-15. Block Diagram of Asynchronous Serial Interfaces 1, 2 Internal bus Receive buffers n, Ln (RXBn, RXBLn) PEn FEn OVEn Asynchronous serial interface mode registers n0, n1 (ASIMn0, ASIMn1) Asynchronous serial interface status register n (ASISn) RXDn TXDn Receive shift register Transmit shift registers (TXSn, TXSLn) Reception control parity check Transmission control parity addition INTSTn INTSRn SIRn flag MOD bit Selector 1 16 SOTn flag Selector 1 16 Selector ASCKn BRGn Remark n = 1, 2 444 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.3 Control registers (1) Asynchronous serial interface mode registers 10, 20 (ASIM10, ASIM20) The ASIMn0 register is an 8-bit register that controls the UART1, UART2 transfer operation (n = 1, 2). This register can be read/written in 8-bit or 1-bit units. Cautions 1. If a bit other than the RXEn bit of the ASIMn0 register is changed during UARTn transmission or reception, the UARTn operation cannot be guaranteed (n = 1, 2). 2. Set a bit other than the RXEn bit of the ASIMn0 register when the UARTn operation is stopped (when RXEn bit = 0 and transmission is completed). Change the port 3 mode control register (PMC3) after setting the communication mode for bits other than the RXEn bit of the ASIMn0 register. 3. In the case of serial clock output in the clocked (synchronous) mode, ensure that nodes do not output to one another causing conflicts. User's Manual U14492EJ5V0UD 445 CHAPTER 10 SERIAL INTERFACE FUNCTION 7 ASIM10 1 <6> RXE1 5 PS1 4 PS0 3 CL 2 SL 1 0 0 SCLS Address FFFFFA28H Initial value 81H 7 ASIM20 1 <6> RXE2 5 PS1 4 PS0 3 CL 2 SL 1 0 0 SCLS Address FFFFFA48H Initial value 81H Bit position 6 Bit name RXEn Enables/disables reception. 0: Disable reception 1: Enable reception Function 5, 4 PS1, PS0 Specifies parity bit length. PS1 0 0 PS0 0 1 Operation No parity, extension bit operation 0 parity Transmit side Transmission with parity bit = 0 Receive side No parity error generated during reception Odd parity Even parity 1 1 0 1 3 CL Specifies character length of transmit/receive data (1 frame). 0: 7 bits 1: 8 bits 2 SL Specifies stop bit length of transmit data. 0: 1 bit 1: 2 bits 0 SCLS Specifies serial clock source. SCLS Operation In asynchronous mode In synchronous mode External clock input 0 1 Internal baud rate generator Remark n = 1, 2 446 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface mode registers 11, 21 (ASIM11, ASIM21) The ASIMn1 register is an 8-bit register that controls the UART1 and UART2 transfer modes. This register can be read/written in 8-bit or 1-bit units. 7 ASIM11 0 6 0 5 0 4 0 3 MOD 2 UMST 1 UMSR 0 EBS Address FFFFFA2AH Initial value 00H 7 ASIM21 0 6 0 5 0 4 0 3 MOD 2 UMST 1 UMSR 0 EBS Address FFFFFA4AH Initial value 00H Bit position 3 Bit name MOD Function Specifies operation mode (asynchronous/synchronous mode). 0: Asynchronous mode 1: Synchronous mode 2 UMST Specifies number of continuous frame transmissions. 0: 1-frame data transmission 1: 2-frame continuous data transmission 1 UMSR Specifies number of continuous frame receptions. 0: 1-frame data reception 1: 2-frame continuous data reception 0 EBS Specifies extension bit operation for transmit/receive data when no parity is specified (PS0 = PS1 = 0). 0: Disable extension bit addition 1: Enable extension bit addition When the extension bit is specified, 1 data bit is added on top of the 8 bits of transmit/receive data, enabling 9-bit data communication. Extension bit specification is valid only when no parity (ASIMn0 register's PS0 bit = PS1 bit = 0) and 1-frame data transmission (UMST bit = 0) are specified. When 0 parity, odd parity, or even parity are specified, or when 2-frame continuous data transmission (UMST bit = 1) is specified, the EBS bit setting becomes invalid and extension bit addition is not performed. Extension bit addition (EBS bit = 1) and 2-frame continuous data reception (UMSR bit = 1) cannot be set simultaneously. User's Manual U14492EJ5V0UD 447 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Asynchronous serial interface status registers 1, 2 (ASIS1, ASIS2) The ASISn register is a register that is configured of a UARTn transmission status flag (SOTn), reception status flag (SIRn), a bit (RB8) indicating the 9th bit when extension bit addition is enabled, and 3-bit error flags (PEn, FEn, OVEn) that indicate the error status at reception end (n = 1, 2). The status flag that indicates reception errors always indicates the most recent error status. In other words, if the same error occurs several times before receive data is read, this flag holds only the status of the error that occurred last. Each time the ASISn register is read after a receive completion interrupt (INTSRn), read the receive buffer (RXBn or RXBLn). The error flag is cleared when the receive buffer (RXBn or RXBLn) is read. Also, clear the error flag by reading the receive buffer (RXBn or RXBLn) when a reception error occurs. This register is read-only, in 8-bit or 1-bit units. 448 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION <7> ASIS1 SOT1 <6> SIR1 5 0 4 RB8 3 0 <2> PE1 <1> FE1 <0> OVE1 Address FFFFFA2CH Initial value 00H <7> ASIS2 SOT2 <6> SIR2 5 0 4 RB8 3 0 <2> PE2 <1> FE2 <0> OVE2 Address FFFFFA4CH Initial value 00H Bit position 7 Bit name SOTn Function Status flag indicating transmission status 0: Transmission end timing (when INTSTn is generated) 1: Indicates transmission status Note Note The transmission status is the status until the specified number of stop bits has been transmitted following write operation to the transmit register. During 2-frame continuous transmission, this status is until the stop bit of the 2nd frame has been transmitted. 6 SIRn Status flag indicating reception status 0: Reception end timing (when INTSRn is generated) 1: Indicates reception status Note Note The reception status is the status until stop bit detection from the start bit detection timing. 4 2 RB8 PEn Indicates contents of receive data extension bit (1 bit) when 9-bit extended format is specified (EBS bit of ASIMn1 register = 1). Status flag indicating parity error 0: Processing to read data from receive buffer 1: When transmit parity and receive parity don't match Caution No parity error is generated if no parity is specified or 0 parity is specified with the PS1, PS0 bits of the ASIMn0 register. 1 FEn Status flag indicating framing error 0: Processing to read data from receive buffer 1: When stop bit is not detected 0 OVEn Status flag indicating overrun error 0: Processing to read data from receive buffer 1: When UARTn has completed next reception processing prior to loading receive data from receive buffer Since the contents of the receive shift register are transferred to the receive buffer (RXBn, RXBLn) every time 1 frame is received, the following receive data is overwritten to the receive buffer (RXBn, RXBLn) and the previous receive data is discarded. Remark n = 1, 2 User's Manual U14492EJ5V0UD 449 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) 2-frame continuous reception buffer registers 1, 2 (RXB1, RXB2)/receive buffer registers L1, L2 (RXBL1, RXBL2) The RXBn register is a 16-bit buffer register that holds receive data (during 2-frame continuous reception (UMSR bit of ASIMn1 register = 1), during 9-bit extended data reception (EBS bit of ASIMn1 register = 1)) (n = 1, 2). During 7 or 8 bit/character reception, 0 is stored in the MSB. For 16-bit access to this register, specify RXBn, and for access to the lower 8 bits, specify RXBLn. In the receive enabled status, receive data is transferred from the receive shift register to the receive buffer in synchronization with the end of shift-in processing for 1 frame of data. The reception completion interrupt request (INTSRn) is generated upon transfer of data to the receive buffer (when 2-frame continuous reception is specified, receive buffer transfer of the second frame). In the reception disabled status, transfer processing to the receive buffer is not performed even if shift-in processing for 1 frame of data has been completed, and the contents of the receive buffer are held. Neither is a reception completion interrupt request generated. The RXBn register is read-only, in 16-bit units, and the RXBLn register is read-only, in 8-bit units. 450 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION [2-frame continuous reception buffer register 1] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value RXB1 RXB15 RXB14 RXB13 RXB12 RXB11 RXB10 RXB9 RXB8 RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0 FFFFFA20H Undefined [Receive buffer register L1] 7 6 5 4 3 2 1 0 Address Initial value RXBL1 RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0 FFFFFA22H Undefined [2-frame continuous reception buffer register 2] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value RXB2 RXB15 RXB14 RXB13 RXB12 RXB11 RXB10 RXB9 RXB8 RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0 FFFFFA40H Undefined [Receive buffer register L2] 7 6 5 4 3 2 1 0 Address Initial value RXBL2 RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0 FFFFFA42H Undefined Bit position 15 to 0 Bit name RXB15 to RXB0 Stores receive data. Function 0 can be read for the RXBn register when 7, 8 bit/character data is received. When an extension bit is set during 9 bit/character data reception, the extension bit (RXB8) is stored in RB8 of the ASISn register simultaneously with saving to the receive buffer. 0 can be read for the RXB7 bit of the RXBLn register during 7 bit/character data reception. (a) When 2-frame continuous reception is set 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXBn RXB15 RXB14 RXB13 RXB12 RXB11 RXB10 RXB9 RXB8 RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0 7-/8-bit data of 1st frame 7-/8-bit data of 2nd frame (b) When 9-bit extension reception is set 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXBn RXB15 RXB14 RXB13 RXB12 RXB11 RXB10 RXB9 RXB8 RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0 9-bit extended data When 9-bit extension is set, the extension bit (RXB8) is stored in the RB8 bit of the ASISn register simultaneously with saving to the receive buffer. User's Manual U14492EJ5V0UD 451 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Cautions <1> Operation upon occurrence of overrun error during 2-frame continuous reception * During normal reception Reception completion interrupt (INTSRn) generated upon end of reception of 2nd frame, no error RXDn Frame 1 Frame 2 * Reception of 3rd frame started before performing reception processing Reception completion interrupt (INTSRn) generated upon end of reception of 2nd frame, no error RXDn Frame 1 Frame 2 Reception completion interrupt not generated upon end of reception of 3rd frame, occurrence of error RXDn Frame 3 Frame 3 Value of OVEn bit of ASISn register becomes 1. * Start of reception of 3rd frame and 4th frame before performing reception processing Reception completion interrupt (INTSRn) generated upon end of reception of 2nd frame, no error RXDn Frame 1 Frame 2 Reception completion interrupt not generated upon end of reception of 3rd frame, occurrence of error RXDn Frame 3 Frame 3 Value of OVEn bit of ASISn register becomes 1. Reception completion interrupt (INTSRn) generated upon end of reception of 4th frame, no error RXDn Frame 3 Frame 4 Value of OVEn bit of ASISn register remains 1. * Start of reception of 3rd frame before performing reception processing, start of reception of 4th frame after performing reception processing Reception completion interrupt (INTSRn) generated upon end of reception of 2nd frame, no error RXDn Frame 1 Frame 2 Reception completion interrupt not generated upon end of reception of 3rd frame, occurrence of error RXDn Frame 3 Frame 3 Value of OVEn bit of ASISn register becomes 1. Value of OVEn flag becomes 0 during reception processing. Reception completion interrupt (INTSRn) generated upon end of reception of 4th frame, no error RXDn Frame 3 Frame 4 No occurrence of error 452 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (5) 2-frame continuous transmission shift registers 1, 2 (TXS1, TXS2)/transmit shift registers L1, L2 (TXSL1, TXSL2) The TXSn register is a 9-bit/2-frame continuous transmission processing shift register (n = 1, 2). Transmission is started by writing data to this register. A transmission completion interrupt request (INTSTn) is generated in synchronization with the end of transmission of 1 frame or 2 frames including the TXSn data. For 16-bit access to this register, specify TXSn, and for access to the lower 8 bits, specify TXSLn. The TXSn register is write-only, in 16-bit units, and the TXSLn register is write-only, in 8-bit units. Caution TXSn, TXSLn can be read, but since shifting is done in synchronization with the shift clock, the data that is read cannot be guaranteed. [2-frame continuous transmission shift register 1] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value TXS1 TXS15 TXS14 TXS13 TXS12 TXS11 TXS10 TXS9 TXS8 TXS7 TXS6 TXS5 TXS4 TXS3 TXS2 TXS1 TXS0 FFFFFA24H Undefined [Transmit shift register L1] 7 6 5 4 3 2 1 0 Address Initial value TXSL1 TXS7 TXS6 TXS5 TXS4 TXS3 TXS2 TXS1 TXS0 FFFFFA26H Undefined [2-frame continuous transmission shift register 2] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value TXS2 TXS15 TXS14 TXS13 TXS12 TXS11 TXS10 TXS9 TXS8 TXS7 TXS6 TXS5 TXS4 TXS3 TXS2 TXS1 TXS0 FFFFFA44H Undefined [Transmit shift register L2] 7 6 5 4 3 2 1 0 Address Initial value TXSL2 TXS7 TXS6 TXS5 TXS4 TXS3 TXS2 TXS1 TXS0 FFFFFA46H Undefined Bit position 15 to 0 Bit name TXB15 to TXB0 Writes transmit data. Function User's Manual U14492EJ5V0UD 453 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.4 Interrupt requests The following two types of interrupt request are generated from UARTn (n = 1, 2). * * Reception completion interrupt (INTSRn) Transmission completion interrupt (INTSTn) The reception completion interrupt has higher default priority than the transmission completion interrupt. Table 10-5. Default Priority of Generated Interrupts Interrupt Reception completion Transmission completion Priority 1 2 (1) Reception completion interrupt (INTSRn) In the reception enabled state, the reception completion interrupt (INTSRn) is generated when data in the receive shift register undergoes shift-in processing and is transferred to the receive buffer. The reception completion interrupt request (INTSRn) is generated following stop bit sampling. The reception completion interrupt (INTSRn) is generated upon occurrence of an error. In the reception disabled state, no reception completion interrupt is generated. Caution A reception completion interrupt (INTSRn) is generated when the last bit of receive data (stop bit) is sampled. (2) Transmission completion interrupt (INTSTn) Since UARTn does not have a transmit buffer, a transmission completion interrupt request (INTSTn) is generated when one frame of data containing 7-bit or 8-bit characters or two frames of data containing 9-bit characters are shifted out from the transmit shift register (TXSn, TXSLn). 454 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.5 Operation (1) Data format Full-duplex serial data is transmitted and received. Figure 10-16 shows the format of transmit/receive data. One data frame consists of a start bit, character bits, a parity bit, and a stop bit(s). When 2 data frame transfer is set, both frames have the above-described format. Specification of the character bit length in one data frame, parity selection, and specification of the stop bit length is done using asynchronous serial interface mode registers 10, 20 (ASIM10, ASIM20). Specification of the number of frames and specification of the extension bit is done with asynchronous serial interface mode registers 11, 21 (ASIM11, ASIM21). Data is transmitted LSB first. Figure 10-16. Asynchronous Serial Interface Transmit/Receive Data Format (a) 1-frame format 1 frame Data Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity/ extension bit Stop bit (b) 2-frame format Higher frame Data Lower frame Start D8 D9 D10 D11 D12 D13 D14 D15 Parity Stop Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop bit bit bit bit bit bit Start bit: 1 bit Character bits: 7 or 8 bits Parity bit: Even parity, odd parity, 0 parity, or no parity Stop bit: 1 or 2 bits Caution The extension bit is invalid in the 2-frame continuous mode or when a parity bit is added. User's Manual U14492EJ5V0UD 455 CHAPTER 10 SERIAL INTERFACE FUNCTION Table 10-6. ASIMn0, ASIMn1 Register Settings and Data Format ASIMn0, ASIMn1 Register Settings CL Bit 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PS1 Bit 0 PS0 Bit 0 SL Bit 0 EBS Bit 0 D0 to D6 DATA DATA DATA DATA 1 0 DATA DATA DATA DATA 0 1 DATA DATA DATA DATA 1 1 DATA DATA DATA DATA D7 Stop bit Parity bit DATA DATA Stop bit Parity bit DATA DATA Stop bit Parity bit DATA DATA Stop bit Parity bit DATA DATA Data Format D8 Stop bit Stop bit Parity bit Stop bit Stop bit Stop bit Parity bit Stop bit DATA Parity bit Stop bit Stop bit DATA Parity bit D9 Stop bit Stop bit Stop bit Stop bit Stop bit Stop bit Stop bit Stop bit Stop bit D10 Stop bit Stop bit Stop bit Other than PS1 = PS0 = 0 0 0 Other than PS1 = PS0 = 0 0 0 Other than PS1 = PS0 = 0 0 0 Other than PS1 = PS0 = 0 0 0 Other than PS1 = PS0 = 0 0 0 Other than PS1 = PS0 = 0 0 0 Other than PS1 = PS0 = 0 0 0 Other than PS1 = PS0 = 0 456 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Transmission operation The transmission operation is started by writing data to 2-frame continuous transmission shift registers 1, 2 (TXS1, TXS2)/transmit shift registers L1, L2 (TXSL1, TXSL2). Following data write, the start bit is transmitted from the next shift timing. Since the UARTn does not have a CTS (transmission enable signal) input pin, use a port when the other party confirms the reception enabled status (n = 1, 2). (a) Transmission operation start The transmission operation is started by writing transmit data to 2-frame continuous transmission shift registers 1, 2 (TXS1, TXS2)/transmit shift registers L1, L2 (TXSL1, TXSL2). Then data is output in sequence from LSB to the TXDn pin (transmission in sequence from the start bit). A start bit, parity bit, and stop bit(s) are automatically added. (b) Transmission interrupt request When the transmit shift register becomes empty upon completion of the transmission of 1 or 2 frames of data, a transmission completion interrupt request (INTSTn) is generated. the same time that the last stop bit is output. The transmission operation remains stopped until the data to be transmitted next has been written to the TXSn/TXSLn registers. Figure 10-17 shows the INTSTn interrupt generation timing. Cautions 1. Normally, the transmission completion interrupt (INTSTn) is generated when the transmit shift register becomes empty. generated. 2. No data can be written to the TXSn or TXSLn registers during transmission operation until INTSTn is generated. Even if data is written, this does not affect the transmission operation. However, if the transmit shift register has become empty due to input of RESET, no transmission completion interrupt (INTSTn) is The INTSTn interrupt generation timing differs depending on the specified stop bit length. The INTSTn interrupt is generated at User's Manual U14492EJ5V0UD 457 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-17. Asynchronous Serial Interface Transmission Completion Interrupt Timing (a) When stop bit length = 1 bit TXDn (output) Start D0 D1 D2 D6 D7 Parity Stop INTSTn interrupt Flag in transmission (SOTn) (b) When stop bit length = 2 bits TXDn (output) Start D0 D1 D2 D6 D7 Parity Stop INTSTn interrupt Flag in transmission (SOTn) (c) In 2-frame continuous transmission mode TXDn (output) Start D0 D1 Parity Stop Start D1 D5 D6 D7 Parity Stop 1st frame INTSTn interrupt 2nd frame Flag in transmission (SOTn) 458 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Continuous transmission of 3 or more frames In addition to the 1-frame/2-frame transmission function, UARTn also enables continuous transmission of 3 or more frames, using the method shown below (n = 1, 2). (a) How to continuously transmit 3 or more frames (when the stop bit is 1 bit (SL bit = 0)) Three frames can be continuously transmitted by writing transmit data to the TXSn/TXSLn register in the period between the generation of the transmission completion interrupt request (INTSTn) and 4 x 2/fXX before the output of the last stop bit. The INTSTn interrupt becomes high level 2/fXX after being output and returns to low level 2/fXX later. TXSn/TXSLn can only be written after the INTSTn interrupt level has fallen. The time from INTSTn interrupt generation to the completion of transmit data writing (t) is therefore indicated by the following expression. t = (Time of one stop bit) - (2 x 2/fXX + 4 x 2/fXX) fXX = Internal system clock Caution 4 x 2/fXX has a margin of double the clock that can actually be used for operation. Example Count clock frequency = 32 MHz = 32,000,000 Hz Target baud rate in synchronous mode = 9,600 bps t = (1/9615.385) - ((4 + 8)/32,000,000) = 104.000 - 0.375 = 103.625 [s] Therefore, be sure to write transmit data to TXSn/TXSLn within 103 s of the generation of the INTSTn interrupt. Note, however, that because writing to TXSn/TXSLn may be delayed depending on the priority order of the INTSTn interrupt or the interrupt servicing time, be sure to allow sufficient time for writing transmit data after the INTSTn interrupt has been generated. If there is not enough time for continuous transmission due to a delay in writing to TXSn/TXSLn, a 1-bit high level is transmitted. Note also that if the stop bit length is 2 bits (SL bit = 1), the INTSTn interrupt will be generated when the second stop bit is output. Figure 10-18. Continuous Transmission of 3 or More Frames (When SL Bit = 0) 2/fXX Stop bit INTSTn interrupt 4 x 2/fXX 2/fXX 2/fXX TXSn/TXSLn write period for 3-frame continuous transmission User's Manual U14492EJ5V0UD 459 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Reception operation The reception wait status is entered by setting the RXEn bit of the ASIMn0 register to 1 (n = 1, 2). To start the reception operation, first perform start bit detection. Start bit detection is done by performing sampling of the RXDn pin. When the reception operation is started, serial data is stored to the receive shift register in sequence at the set baud rate. Each time reception of 2 frames or 1 frame of RXBn or RXBLn data has been completed, a reception completion interrupt (INTSRn) is generated. Receive data is transmitted from the receive buffer (RXBn/RXBLn) to memory when this interrupt is serviced. (a) Reception enabled status The reception operation is enabled by setting (1) the RXEn bit of the ASIMn0 register. * RXEn = 1: Reception enabled status * RXEn = 0: Reception disabled status In the reception disabled status, the reception hardware is in standby in an initialized state. At this time, no reception completion interrupt is generated, and the contents of the receive buffer are held. (b) Start of reception operation The reception operation is started through detection of the start bit. * In asynchronous mode (MOD bit of ASIMn1 register = 0) The RXDn pin is sampled using the serial clock from the baud rate generator. After 8 serial clocks have been output following detection of the falling edge of the RXDn pin, the RXDn pin is again sampled. If a low level is detected at this time, the falling edge of the RXDn pin is interpreted as a start bit, the operation shifts to reception processing, and the RXDn pin input is sampled from this point on in units of 16 serial clock output. If the high level is detected during sampling after 8 serial clocks from detection of the falling edge of the RXDn pin, this falling edge is not recognized as a start bit. The serial clock counter that generates the sample timing is initialized and stops, and input of the next falling edge is waited for. * In synchronous mode (MOD bit of ASIMn1 register = 1) The RXDn pin is sampled using the serial clock from the baud rate generator or at the rising edge of serial clock I/O. If the RXDn pin is low level at this time, this is interpreted as a start bit and reception processing starts. If reception data is interrupted at the fixed low level during reception, reception of this receive data (including error detection) is completed and reception completion interrupt is generated. However, even if the RXD line is fixed at low level, the next reception operation is not started (start bit detection is not performed). Be sure to set the high level when restarting the reception operation. If the high level is not set, the start bit detection position becomes undefined, and correct reception operation cannot be performed. 460 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Reception completion interrupt request When reception of one frame of data has been completed (stop bit detection) when the RXEn bit of the ASIMn0 register = 1, the receive data in the shift register is transferred to RXBn/RXBLn and a reception completion interrupt request (INTSRn) is generated after 1 frame or 2 frames of data have been transferred to RXBn/RXBLn. A reception completion interrupt is also generated upon detection of an error. When the RXEn bit = 0 (reception disabled), no reception completion interrupt is generated. Figure 10-19. Asynchronous Serial Interface Reception Completion Interrupt Timing (a) When stop bit length = 1 bit 8 serial clocks 8 serial clocks RXDn (input) Start D0 D1 D2 D6 D7 Parity Stop INTSRn interrupt Flag in reception (SIRn) (b) When stop bit length = 2 bits 8 serial clocks 8 serial clocks RXDn (input) Start D0 D1 D2 D6 D7 Parity Stop INTSRn interrupt Flag in reception (SIRn) (c) In 2-frame continuous transmission mode 8 serial clocks 8 serial clocks RXDn (input) Start D0 D1 Parity Stop Start D1 D5 D6 D7 Parity Stop INTSRn interrupt 1st frame 2nd frame Flag in reception (SIRn) User's Manual U14492EJ5V0UD 461 CHAPTER 10 SERIAL INTERFACE FUNCTION Cautions 1. Even if a reception error occurs, be sure to read 2-frame continuous reception buffer register n (RXBn)/receive buffer register n (RXBLn). If the RXBn or RXBLn register is not read, an overrun error will occur at the next data reception, and the reception error state will continue indefinitely. 2. Reception is always performed with the stop bit length set to 1 bit. A second stop bit is ignored. (5) Reception errors The three types of error flags of parity errors, framing errors, and overrun errors are affected in synchronization with reception operation. As a result of data reception, the PEn, FEn, and OVEn flags of the ASISn register are set (1) and a reception completion interrupt request (INTSRn) is generated at the same time. The contents of error that occurred during reception can be detected by reading the contents of the PEn, FEn, and OVEn flags of the ASISn register during the INTSRn interrupt servicing. The contents of the ASISn register are reset (0) by reading the ASISn register (if the next receive data contains an error, the corresponding error flag is set (1)). Table 10-7. Reception Error Causes Error Flag PEn Reception Error Parity error Causes The parity specification during transmission did not match the parity of the reception data FEn OVEn Framing error Overrun error No stop bit was detected The reception of the next data was completed before data was read from the receive buffer (6) Parity types and corresponding operation A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used at the transmission and reception sides. (a) Even parity <1> During transmission The parity bit is controlled so that number of bits with the value "1" within the transmit data including the parity bit is even. The parity bit value is as follows. * If the number of bits with the value "1" within the transmit data is odd: 1 * If the number of bits with the value "1" within the transmit data is even: 0 <2> During reception The number of bits with the value "1" within the receive data including the parity bit is counted, and a parity error is generated if this number is odd. 462 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Odd parity <1> During transmission In contrast to even parity, the parity bit is controlled so that the number of bits with the value "1" within the transmit data including the parity bit is odd. The parity bit value is as follows. * If the number of bits with the value "1" within the transmit data is odd: 0 * If the number of bits with the value "1" within the transmit data is even: 1 <2> During reception The number of bits with the value "1" within the receive data including the parity bit is counted, and a parity error is generated if this number is even. (c) 0 parity During transmission, the parity bit is set to "0" regardless of the transmit data. During reception, no parity bit check is performed. Therefore, no parity error is generated regardless of whether the parity bit is "0" or "1". (d) No parity No parity bit is added to the transmit data. During reception, the receive operation is performed as if there were no parity bit. Since there is no parity bit, no parity error is generated. User's Manual U14492EJ5V0UD 463 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.6 Synchronous mode The synchronous mode can be set with the ASCKn pin, which is the serial clock I/O pin (n = 1, 2). The synchronous mode is set with the MOD bit of the ASIMn1 register, and the serial clock to be used for synchronization is selected with the SCLS bit of the ASIMn0 register. In the synchronous mode, external clock input is selected when the value of the SCLS bit is 0 (default), and the serial clock output is selected in the case of all other settings. Therefore, when performing settings, make sure that outputs between connection nodes do not conflict. In the synchronous mode, the falling edge of the serial clock is used as the transmission timing, and the rising edge as the reception timing, but transmit data is output with a delay of 1 system clock (serial clock) (in the external clock synchronous mode, the maximum delay is 2.5 system clocks). Figure 10-20. Transmission/Reception Timing in Synchronous Mode ASCKn Output data (TXDn) Input data (RXDn) Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop On the data output side, the data changes at the falling edge of the serial clock output. On the data input side, the data is latched at the rising edge of the serial clock output. Serial clock output continues as long as the setting is not canceled. Remark n = 1, 2 464 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-21. Transmission/Reception Timing Chart for Synchronous Mode (1/3) (a) In 1-frame transmission/reception mode Serial clock Transmit data Stop bit Transmission register write signal Flag in transmission (SOTn) Transmission completion interrupt (INTSTn) Flag in reception (SIRn) Reception completion interrupt (INTSRn) Reception buffer (RXBn) Reception buffer (RXBLn) Undefined (hold previous value) 005AH Undefined (hold previous value) 5AH Remark n = 1, 2 User's Manual U14492EJ5V0UD 465 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-21. Transmission/Reception Timing Chart for Synchronous Mode (2/3) (b) In 2-frame continuous transmission/reception mode Serial clock Transmit data Transmission register write signal Stop bit Stop bit Flag in transmission (SOTn) Transmission completion interrupt (INTSTn) Flag in reception (SIRn) Reception completion interrupt (INTSRn) Reception buffer (RXBn) Undefined (hold previous value) 5A5AH 5A15H Reception buffer (RXBLn) Undefined (hold previous value) 5AH 15H Remark n = 1, 2 466 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-21. Transmission/Reception Timing Chart for Synchronous Mode (3/3) (c) Transmission/reception timing and transmit data timing during serial clock output Serial clock (output) System clock Transmit data Transmission timing Reception timing Note Note The transmit data is delayed by 1 system clock in relation to the serial clock. (d) Transmission/reception timing and transmit data timing using external serial clock External serial clock System clock Transmit data Transmission timing Reception timing Note Note Since, during external serial clock synchronization, synchronization is done with the internal system clock when feeding the external serial clock to the internal circuit, a delay ranging from 1 system clock to a maximum of 2.5 system clocks results. User's Manual U14492EJ5V0UD 467 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-22. Reception Completion Interrupt and Error Interrupt Generation Timing During Synchronous Mode Reception (a) During normal operation (in 1-frame reception mode) Receive data Flag in reception (SIRn) Reception completion interrupt (INTSRn) Error interrupt START STOP (b) In 2-frame continuous reception mode Receive data Flag in reception (SIRn) Reception completion interrupt (INTSRn) Error interrupt (2) (3) START STOP START STOP (1) (1) If the start bit of the second frame is not detected, no reception completion interrupt is generated. (2) If an error occurs in the first frame, an error interrupt is generated following detection of the stop bit of the first frame (at the calculated position). (3) If an error occurs in the second frame, an error interrupt is generated simultaneously with a reception completion interrupt. If an error occurs in the first frame, no error interrupt is generated even if an error occurs in the second frame. Remark n = 1, 2 468 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.7 Dedicated baud rate generators 1, 2 (BRG1, BRG2) (1) Configuration of baud rate generators 1, 2 (BRG1, BRG2) For UART1 and UART2, the serial clock can be selected from the dedicated baud rate generator output or internal system clock (fXX) for each channel. The serial clock source is specified with registers ASIM10 and ASIM20. If dedicated baud rate generator output is specified, BRG1 and BRG2 are selected as the clock sources. Since the same serial clock can be shared for transmission and reception for one channel, baud rate is the same for the transmission/reception. Figure 10-23. Block Diagram of Baud Rate Generators 1, 2 (BRG1, BRG2) fXX/2 Selector fXX/4 8-bit timer counter fXX/8 fXX/16 Match detector 1/2 UARTn BGCS1, BGCS0 PRSCMn Remark fXX: Internal system clock n = 1, 2 User's Manual U14492EJ5V0UD 469 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Dedicated baud rate generators 1, 2 (BRG1, BRG2) BRGn is configured of an 8-bit timer counter for baud rate signal generation, a prescaler mode register that controls the generation of the baud rate signal (PRSMn), a prescaler compare register that sets the value of the 8-bit timer counter (PRSCMn), and a prescaler (n = 1, 2). (a) Input clock The internal system clock (fXX) is input to BRGn. (b) Prescaler mode registers 1, 2 (PRSM1, PRSM2) The PRSMn register controls generation of the UARTn baud rate signal (n = 1, 2). These registers can be read/written in 8-bit or 1-bit units. Cautions 1. Do not change the values of the BGCS1 and BGCS0 bits during transmission/ reception operations. 2. Set PRSMn register other than the UARTCEn bit prior to setting the UARTCEn bit to 1 (n = 1, 2). <7> PRSM1 UARTCE1 6 0 5 0 4 0 3 0 2 0 1 BGCS1 0 BGCS0 Address FFFFFA2EH Initial value 00H <7> PRSM2 UARTCE2 6 0 5 0 4 0 3 0 2 0 1 BGCS1 0 BGCS0 Address FFFFFA4EH Initial value 00H Bit position 7 Bit name UARTCEn Function Enables baud rate counter operation. 0: Stop baud rate counter operation and fix baud rate output signal to "0". 1: Enable baud rate counter operation and start baud rate output operation. 1, 0 BGCS1, BGCS0 Selects count clock to baud rate counter. BGCS1 0 0 1 1 BGCS0 0 1 0 1 fXX/2 fXX/4 fXX/8 fXX/16 Count clock selection Remark fXX: Internal system clock Remark n = 1, 2 470 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Prescaler compare registers 1, 2 (PRSCM1, PRSCM2) PRSCMn is an 8-bit compare register that sets the value of the 8-bit timer counter (n = 1, 2). These registers can be read/written in 8-bit units. Cautions 1. The internal timer counter is cleared by writing to the PRSCMn register. Therefore, do not overwrite the PRSCMn register during transmission operation. 2. Perform PRSCMn register settings prior to setting the UARTCEn bit to 1. If the contents of the PRSCMn register are overwritten when the value of the UARTCEn bit is 1, the cycle of the baud rate signal is not guaranteed. 3. Set the baud rate to 153,600 bps or lower in asynchronous mode, and 1,000,000 bps or lower in synchronous mode. 7 6 5 4 3 2 1 0 Address Initial value 00H PRSCM1 PRSCM7 PRSCM6 PRSCM5 PRSCM4 PRSCM3 PRSCM2 PRSCM1 PRSCM0 FFFFFA30H 7 6 5 4 3 2 1 0 Address Initial value 00H PRSCM2 PRSCM7 PRSCM6 PRSCM5 PRSCM4 PRSCM3 PRSCM2 PRSCM1 PRSCM0 FFFFFA50H (d) Baud rate generation First, when the UARTCEn bit of the PRSMn register is overwritten with 1, the 8-bit timer counter for baud rate signal generation starts counting up with the clock selected with bits BGCS1 and BGCS0 of the PRSMn register. The count value of the 8-bit timer counter is compared with the value of the PRSCMn register, and if these values match, a timer count clock pulse of 1 cycle is output to the output controller for the baud rate. The output controller for the baud rate reverses the baud rate signal in synchronization with the rising edge of the timer count clock when this pulse is "1". (e) Cycle of baud rate signal The cycle of the baud rate signal is calculated as follows. * * When setting value of PRSCMn register is 00H (Cycle of signal selected with bits BGCS1, BGCS0 of PRSMn register) x 256 x 2 In cases other than above (Cycle of signal selected with bits BGCS1, BGCS0 of PRSMn register) x (setting value of PRSCMn register) x 2 User's Manual U14492EJ5V0UD 471 CHAPTER 10 SERIAL INTERFACE FUNCTION (f) Baud rate setting value The formulas for calculating the baud rate in the asynchronous mode and the synchronous mode and the formula for calculating the error are as follows. <1> Formula for calculating baud rate in asynchronous mode Baud rate = fXX 2 x m x 2k x 16 [bps] fXX = Internal system clock frequency [Hz] = CPU clock/2 [Hz] m: Setting value of PRSCMn register (1 m 256 Note ) k: Value set with bits BGCS1, BGCS0 of PRSMn register (k = 0, 1, 2, 3) Note The setting of m = 256 is performed by writing 00H to the PRSCMn register. <2> Formula for calculating the baud rate in synchronous mode Baud rate = fXX 2xmx2 k [bps] fXX = Internal system clock frequency [Hz] = CPU clock/2 [Hz] m: Setting value of PRSCMn register (1 m 256 Note ) k: Value set with bits BGCS1, BGCS0 of PRSMn register (k = 0, 1, 2, 3) Note The setting of m = 256 is performed by writing 00H to the PRSCMn register. <3> Formula for calculating error Error [%] = Actual baud rate - Target baud rate Target baud rate x 100 Example (9520 - 9600)/9600 x 100 = -0.833 [%] Remark Actual baud rate: Baud rate with error Target baud rate: Normal baud rate 472 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION <4> Baud rate setting example In an actual system, the output of a prescaler module, etc. is connected to input clock. Table 10-8 shows the baud rate generator setting data at this time. Table 10-8. Baud Rate Generator Setting Data (BRG = fXX/2) (1/2) (a) When fXX = 32 MHz Target Baud Rate Synchronous Mode 4800 9600 19200 38400 76800 153600 166400 307200 614400 Setting prohibited Setting prohibited Asynchronous Mode 300 600 1200 2400 4800 9600 10400 19200 38400 76800 153600 Actual Baud Rate Synchronous Mode 4807.692 9615.385 19230.77 38461.54 76923.08 153846.2 166666.7 307692.3 615384.6 - - Asynchronous Mode 300.4808 600.9615 1201.923 2403.846 4807.692 9615.385 10416.67 19230.77 38461.54 71428.57 166666.7 3 3 3 3 3 2 1 1 0 0 0 BGCSm Bit (m = 0, 1) PRSCMn Register Setting Value (n = 1, 2) 208 104 52 26 13 13 24 13 13 7 3 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 8.51 Error (b) When fXX = 40 MHz Target Baud Rate Synchronous Mode 4800 9600 19200 38400 76800 153600 166400 307200 614400 Setting prohibited Setting prohibited Asynchronous Mode 300 600 1200 2400 4800 9600 10400 19200 38400 76800 153600 Actual Baud Rate Synchronous Mode 4882.813 9615.385 19230.77 38461.54 76923.08 153846.2 166666.7 303030.3 625000 - - Asynchronous Mode 305.1758 600.9615 1201.923 2403.846 4807.692 9615.385 10416.67 18939.39 39062.5 78125 156250 BGCSm Bit (m = 0, 1) PRSCMn Register Setting Value (n = 1, 2) 256 130 65 65 65 65 60 33 16 8 4 1.73 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 1.73 Error 3 3 3 2 1 0 0 0 0 0 0 User's Manual U14492EJ5V0UD 473 CHAPTER 10 SERIAL INTERFACE FUNCTION Table 10-8. Baud Rate Generator Setting Data (BRG = fXX/2) (2/2) (c) When fXX = 50 MHz Target Baud Rate Synchronous Mode 9600 19200 38400 76800 153600 166400 307200 614400 Setting prohibited Setting prohibited Asynchronous Mode 600 1200 2400 4800 9600 10400 19200 38400 76800 153600 Actual Baud Rate Synchronous Mode 9585.89 19171.78 38343.56 76687.12 154321 166666.7 312500 625000 - - Asynchronous Mode 599.1181 1198.236 2396.472 4792.945 9645.062 10416.67 19531.25 39062.5 78125 156250 3 2 1 0 0 0 0 0 0 0 BGCSm Bit (m = 0, 1) PRSCMn Register Setting Value (n = 1, 2) 163 163 163 163 81 75 40 20 10 5 -0.15 -0.15 -0.15 -0.15 0.47 0.16 1.73 1.73 1.73 1.73 Error 474 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination's baud rate is allowed during reception is shown below. Caution The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range. Figure 10-24. Allowable Baud Rate Range During Reception Latch timing UARTn transfer rate Start bit Bit 0 FL Bit 1 Bit 7 Parity bit Stop bit 1 data frame (11 x FL) Minimum allowable transfer rate Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmin Maximum allowable transfer rate Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FLmax As shown in Figure 10-24, after the start bit is detected, the receive data latch timing is determined according to the counter that was set by the PRSCMn register. If all data up to the final data (stop bit) is in time for this latch timing, the data can be received normally. If this is applied to 11-bit reception, the following is theoretically true. FL = (Brate) -1 Brate: UARTn baud rate k: FL: PRSCMn register setting value 1-bit data length When the latch timing margin is 2 clocks of fXX/2, the minimum allowable transfer rate (FLmin) is as follows (fXX: Internal system clock). FL min = 11x FL - k-2 2k x FL = 21k + 2 2k FL User's Manual U14492EJ5V0UD 475 CHAPTER 10 SERIAL INTERFACE FUNCTION Therefore, the transfer destination's maximum receivable baud rate (BRmax) is as follows. BRmax = (FLmin/11)-1 = 22k 21k + 2 Brate Similarly, the maximum allowable transfer rate (FLmax) can be obtained as follows. 10 k+2 21k - 2 x FL max = 11x FL - x FL = FL 11 2xk 2xk 21k - 2 FL max = FL x 11 20k Therefore, the transfer destination's minimum receivable baud rate (BRmin) is as follows. BRmin = (FLmax/11)-1 = 20k 21k - 2 Brate (4) Transfer rate in 2-frame continuous reception In 2-frame continuous reception, the timing is initialized by detecting the start bit of the second frame, so the transfer results are not affected. 476 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4 Clocked Serial Interfaces 0, 1 (CSI0, CSI1) 10.4.1 Features * * * * * * * High-speed transfer: Maximum 5 Mbps Half-duplex communications Master mode or slave mode can be selected Transmission data length: 8 bits or 16 bits can be set Transfer data direction can be switched between MSB first and LSB first Eight clock signals can be selected (7 master clocks and 1 slave clock) 3-wire type SOn: SIn: SCKn: Serial transmit data output Serial receive data input Serial clock I/O * Interrupt sources: 1 type * Transmission/reception completion interrupt (INTCSIn) * Transmission/reception mode and reception-only mode can be specified * Two transmission buffers (SOTBFn/SOTBFLn, SOTBn/SOTBLn) and two reception buffers (SIRBn/SIRBLn, SIRBEn/SIRBELn) are provided on chip * Single transfer mode and repeat transfer mode can be specified Remark n = 0, 1 10.4.2 Configuration CSIn is controlled via the clocked serial interface mode register (CSIMn) (n = 0, 1). Transmission/reception of data is performed by writing/reading the SIOn register (n = 0, 1). (1) Clocked serial interface mode registers 0, 1 (CSIM0, CSIM1) The CSIMn register is an 8-bit register that specifies the operation of CSIn. (2) Clocked serial interface clock selection registers 0, 1 (CSIC0, CSIC1) The CSICn register is an 8-bit register that controls the CSIn serial transfer operation. (3) Serial I/O shift registers 0, 1 (SIO0, SIO1) The SIOn register is a 16-bit shift register that converts parallel data into serial data. The SIOn register is used for both transmission and reception. Data is shifted in (reception) and shifted out (transmission) from the MSB or LSB side. The actual transmission/reception operations are started up by accessing the buffer register. (4) Serial I/O shift registers L0, L1 (SIOL0, SIOL1) The SIOLn register is an 8-bit shift register that converts parallel data into serial data. The SIOLn register is used for both transmission and reception. Data is shifted in (reception) and shifted out (transmission) from the MSB or LSB side. The actual transmission/reception operations are started up by accessing the buffer register. User's Manual U14492EJ5V0UD 477 CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Clocked serial interface receive buffer registers 0, 1 (SIRB0, SIRB1) The SIRBn register is a 16-bit buffer register that stores receive data. (6) Clocked serial interface receive buffer registers L0, L1 (SIRBL0, SIRBL1) The SIRBLn register is an 8-bit buffer register that stores receive data. (7) Clocked serial interface read-only receive buffer registers 0, 1 (SIRBE0, SIRBE1) The SIRBEn register is a 16-bit buffer register that stores receive data. The SIRBEn register is the same as the SIRBn register. It is used to read the contents of the SIRBn register. (8) Clocked serial interface read-only receive buffer registers L0, L1 (SIRBEL0, SIRBEL1) The SIRBELn register is an 8-bit buffer register that stores receive data. The SIRBELn register is the same as the SIRBLn register. It is used to read the contents of the SIRBLn register. (9) Clocked serial interface transmit buffer registers 0, 1 (SOTB0, SOTB1) The SOTBn register is a 16-bit buffer register that stores transmit data. (10) Clocked serial interface transmit buffer registers L0, L1 (SOTBL0, SOTBL1) The SOTBLn register is an 8-bit buffer register that stores transmit data. (11) Clocked serial interface initial transmit buffer registers (SOTBF0, SOTBF1) The SOTBFn register is a 16-bit buffer register that stores the initial transmit data in the repeat transfer mode. (12) Clocked serial interface initial transmit buffer register L (SOTBFL0, SOTBFL1) The SOTBFLn register is an 8-bit buffer register that stores initial transmit data in the repeat transfer mode. (13) Selector The selector selects the serial clock to be used. (14) Serial clock controller Controls the serial clock supply to the shift register. Also controls the clock output to the SCKn pin when the internal clock is used. (15) Serial clock counter Counts the serial clock output or input during transmission/reception operation, and checks whether 8-bit or 16-bit data transmission/reception has been performed. (16) Interrupt controller Controls the interrupt request timing. 478 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-25. Block Diagram of Clocked Serial Interface fXX/27 fXX/26 fXX/25 fXX/24 fXX/23 fXX/22 BRG3 SCKn Selector Serial clock controller Clock start/stop control & clock phase control SCKn Interrupt controller INTCSIn Transmission control Transmission data control Initial transmit buffer register (SOTBFn/SOTBFLn) Control signal SO selection SOn Transmit buffer register (SOTBn/SOTBLn) SIn Shift register (SIOn/SIOLn) SO latch Receive buffer register (SIRBn/SIRBLn) Remarks 1. n = 0, 1 2. fXX: Internal system clock 10.4.3 Control registers (1) Clocked serial interface mode registers 0, 1 (CSIM0, CSIM1) The CSIMn register controls the CSIn operation (n = 0, 1). These registers can be read/written in 8-bit or 1-bit units (however, bit 0 is read-only). Caution Overwriting the TRMDn, CCL, DIRn, CSIT, and AUTO bits of the CSIMn register can be done only when the CSOTn bit = 0. If these bits are overwritten at any other time, the operation cannot be guaranteed. User's Manual U14492EJ5V0UD 479 CHAPTER 10 SERIAL INTERFACE FUNCTION <7> <6> 5 CCL 5 CCL <4> DIR0 <4> DIR1 3 CSIT 3 CSIT 2 AUTO 2 AUTO 1 0 1 0 <0> CSOT0 <0> CSOT1 Address FFFFF900H Address FFFFF910H Initial value 00H Initial value 00H CSIM0 CSICAE0 TRMD0 <7> <6> CSIM1 CSICAE1 TRMD1 Bit position 7 Bit name CSICAEn Enables/disables CSIn operation. 0: Disable CSIn operation. 1: Enable CSIn operation. Function The internal CSIn circuit can be reset asynchronously by setting the CSICAEn bit to 0. For the SCKn and SOn pin output status when the CSICAEn bit = 0, refer to 10.4.5 Output pins. 6 TRMDn Specifies transmission/reception mode. 0: Receive-only mode 1: Transmission/reception mode When the TRMDn bit = 0, receive-only transfer is performed and the SOn pin output is fixed to low level. Data reception is started by reading the SIRBn register. When the TRMDn bit = 1, transmission/reception is started by writing data to the SOTBn register. 5 CCL Specifies data length. 0: 8 bits 1: 16 bits 4 DIRn Specifies transfer direction mode (MSB/LSB). 0: First bit of transfer data is MSB 1: First bit of transfer data is LSB 3 CSIT Controls delay of interrupt request signal. 0: No delay 1: Delay mode (interrupt request signal is delayed 1/2 cycle). Caution The delay mode (CSIT bit = 1) is valid only in the master mode (CKS2 to CSK0 bits of the CSICn register are not 111B). In the slave mode (CKS2 to CKS0 bits are 111B), do not set the delay mode. 2 AUTO Specifies single transfer mode or repeat transfer mode. 0: Single transfer mode 1: Repeat transfer mode 0 CSOTn Flag indicating transfer status. 0: Idle status 1: Transfer execution status Caution The CSOTn bit is cleared (0) by writing 0 to the CSICAEn bit. Remark n = 0, 1 480 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Clocked serial interface clock selection registers 0, 1 (CSIC0, CSIC1) The CSICn register is an 8-bit register that controls the CSIn transfer operation (n = 0, 1). These registers can be read/written in 8-bit or 1-bit units. Caution The CSICn register can be overwritten only when the CSICAEn bit of the CSIMn register = 0. User's Manual U14492EJ5V0UD 481 CHAPTER 10 SERIAL INTERFACE FUNCTION 7 CSIC0 0 7 CSIC1 0 6 0 6 0 5 0 5 0 4 CKP 4 CKP 3 DAP 3 DAP 2 CKS2 2 CKS2 1 CKS1 1 CKS1 0 CKS0 0 CKS0 Address FFFFF901H Address FFFFF911H Initial value 00H Initial value 00H Bit position 4, 3 Bit name CKP, DAP Specifies operation mode. Function CKP 0 DAP 0 SCKn (I/O) SOn (output) SIn (input) Operation mode DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 0 1 SCKn (I/O) SOn (output) SIn (input) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 1 0 SCKn (I/O) SOn (output) SIn (input) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 1 1 SCKn (I/O) SOn (output) SIn (input) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 Remark 2 to 0 CKS2 to CKS0 CKS2 0 0 0 0 1 1 1 1 n = 0, 1 Specifies serial clock. CKS1 0 0 1 1 0 0 1 1 CKS0 0 1 0 1 0 1 0 1 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 fXX/2 7 6 5 4 3 2 Serial clock Mode Master mode Master mode Master mode Master mode Master mode Master mode Master mode Slave mode Clock generated by BRG3 External clock (SCKn) Remark fXX: Internal system clock frequency n = 0, 1 482 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Clocked serial interface receive buffer registers 0, 1 (SIRB0, SIRB1) The SIRBn register is a 16-bit buffer register that stores receive data (n = 0, 1). When the receive-only mode is set (TRMDn bit of CSIMn register = 0), the reception operation is started by reading data from the SIRBn register. These registers are read-only, in 16-bit units. In addition to reset input, these registers can also be initialized by clearing (0) the CSICAEn bit of the CSIMn register. Cautions 1. Read the SIRBn register only when the 16-bit data length has been set (CCL bit of CSIMn register = 1). 2. When the single transfer mode has been set (AUTO bit of CSIMn register = 0), perform read operation only in the idle state (CSOTn bit of CSIMn register = 0). If the SIRBn register is read during data transfer, the data cannot be guaranteed. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value 0000H SIRB0 SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB FFFFF902H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value 0000H SIRB1 SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB SIRB FFFFF912H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit position 15 to 0 Bit name SIRB15 to SIRB0 Stores receive data. Function User's Manual U14492EJ5V0UD 483 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Clocked serial interface receive buffer registers L0, L1 (SIRBL0, SIRBL1) The SIRBLn register is an 8-bit buffer register that stores receive data (n = 0, 1). When the receive-only mode is set (TRMDn bit of CSIMn register = 0), the reception operation is started by reading data from the SIRBLn register. These registers are read-only, in 8-bit or 1-bit units. In addition to reset input, these registers can also be initialized by clearing (0) the CSICAEn bit of the CSIMn register. The SIRBLn register is the same as the lower bytes of the SIRBn register. Cautions 1. Read the SIRBLn register only when the 8-bit data length has been set (CCL bit of CSIMn register = 0). 2. When the single transfer mode is set (AUTO bit of CSIMn register = 0), perform read operation only in the idle state (CSOTn bit of CSIMn register = 0). If the SIRBLn register is read during data transfer, the data cannot be guaranteed. 7 SIRBL0 SIRB7 6 SIRB6 5 SIRB5 4 SIRB4 3 SIRB3 2 SIRB2 1 SIRB1 0 SIRB0 Address FFFFF902H Initial value 00H 7 SIRBL1 SIRB7 6 SIRB6 5 SIRB5 4 SIRB4 3 SIRB3 2 SIRB2 1 SIRB1 0 SIRB0 Address FFFFF912H Initial value 00H Bit position 7 to 0 Bit name SIRB7 to SIRB0 Stores receive data. Function 484 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Clocked serial interface read-only receive buffer registers 0, 1 (SIRBE0, SIRBE1) The SIRBEn register is a 16-bit buffer register that stores receive data (n = 0, 1). These registers are read-only, in 16-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSICAEn bit of the CSIMn register. The SIRBEn register is the same as the SIRBn register. It is used to read the contents of the SIRBn register. Cautions 1. The receive operation is not started even if data is read from the SIRBEn register. 2. The SIRBEn register can be read only if the 16-bit data length is set (CCL bit of CSIMn register = 1). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value 0000H SIRBE0 SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE FFFFF906H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value 0000H SIRBE1 SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE SIRBE FFFFF916H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit position 15 to 0 Bit name SIRBE15 to SIRBE0 Stores receive data. Function User's Manual U14492EJ5V0UD 485 CHAPTER 10 SERIAL INTERFACE FUNCTION (6) Clocked serial interface read-only receive buffer registers L0, L1 (SIRBEL0, SIRBEL1) The SIRBELn register is an 8-bit buffer register that stores receive data (n = 0, 1). These registers are read-only, in 8-bit or 1-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSICAEn bit of the CSIMn register. The SIRBELn register is the same as the SIRBLn register. It is used to read the contents of the SIRBLn register. Cautions 1. The receive operation is not started even if data is read from the SIRBELn register. 2. The SIRBELn register can be read only if the 8-bit data length has been set (CCL bit of CSIMn register = 0). 7 SIRBEL0 SIRBE7 6 SIRBE6 5 SIRBE5 4 SIRBE4 3 SIRBE3 2 SIRBE2 1 SIRBE1 0 SIRBE0 Address FFFFF906H Initial value 00H 7 SIRBEL1 SIRBE7 6 SIRBE6 5 SIRBE5 4 SIRBE4 3 SIRBE3 2 SIRBE2 1 SIRBE1 0 SIRBE0 Address FFFFF916H Initial value 00H Bit position 7 to 0 Bit name SIRBE7 to SIRBE0 Stores receive data. Function 486 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (7) Clocked serial interface transmit buffer registers 0, 1 (SOTB0, SOTB1) The SOTBn register is a 16-bit buffer register that stores transmit data (n = 0, 1). When the transmission/reception mode is set (TRMDn bit of CSIMn register = 1), the transmission operation is started by writing data to the SOTBn register. These registers can be read/written in 16-bit units. Cautions 1. Access the SOTBn register only when the 16-bit data length is set (CCL bit of CSIMn register = 1). 2. When the single transfer mode is set (AUTO bit of CSIMn register = 0), perform access only in the idle state (CSOTn bit of CSIMn register = 0). accessed during data transfer, the data cannot be guaranteed. If the SOTBn register is 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value 0000H SOTB0 SOTB SOTB SOTB SOTB SOTB SOTB SOTB SOTB SOTB SOTB SOTB SOTB SOTB SOTB SOTB SOTB FFFFF904H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value 0000H SOTB1 SOTB SOTB SOTB SOTB SOTB SOTB SOTB SOTB SOTB SOTB SOTB SOTB SOTB SOTB SOTB SOTB FFFFF914H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit position 15 to 0 Bit name SOTB15 to SOTB0 Stores transmit data. Function User's Manual U14492EJ5V0UD 487 CHAPTER 10 SERIAL INTERFACE FUNCTION (8) Clocked serial interface transmit buffer registers L0, L1 (SOTBL0, SOTBL1) The SOTBLn register is an 8-bit buffer register that stores transmit data (n = 0, 1). When the transmission/reception mode is set (TRMDn bit of CSIMn register = 1), the transmission operation is started by writing data to the SOTBLn register. These registers can be read/written in 8-bit or 1-bit units. The SOTBLn register is the same as the lower bytes of the SOTBn register. Cautions 1. Access the SOTBLn register only when the 8-bit data length has been set (CCL bit of CSIMn register = 0). 2. When the single transfer mode is set (AUTO bit of CSIMn register = 0), perform access only in the idle state (CSOTn bit of CSIMn register = 0). If the SOTBLn register is accessed during data transfer, the data cannot be guaranteed. 7 SOTBL0 SOTB7 6 SOTB6 5 SOTB5 4 SOTB4 3 SOTB3 2 SOTB2 1 SOTB1 0 SOTB0 Address FFFFF904H Initial value 00H 7 SOTBL1 SOTB7 6 SOTB6 5 SOTB5 4 SOTB4 3 SOTB3 2 SOTB2 1 SOTB1 0 SOTB0 Address FFFFF914H Initial value 00H Bit position 7 to 0 Bit name SOTB7 to SOTB0 Stores transmit data. Function 488 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (9) Clocked serial interface initial transmit buffer registers 0, 1 (SOTBF0, SOTBF1) The SOTBFn register is a 16-bit buffer register that stores initial transmission data in the repeat transfer mode (n = 0, 1). The transmission operation is not started even if data is written to the SOTBFn register. These registers can be read/written in 16-bit units. Caution Access the SOTBFn register only when the 16-bit data length has been set (CCL bit of CSIMn register = 1), and only in the idle state (CSOTn bit of CSIMn register = 0). If the SOTBFn register is accessed during data transfer, the data cannot be guaranteed. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value 0000H SOTBF0 SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF FFFFF908H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value 0000H SOTBF1 SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF SOTBF FFFFF918H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit position 15 to 0 Bit name SOTBF15 to SOTBF0 Function Stores initial transmission data in repeat transfer mode. User's Manual U14492EJ5V0UD 489 CHAPTER 10 SERIAL INTERFACE FUNCTION (10) Clocked serial interface initial transmit buffer registers L0, L1 (SOTBFL0, SOTBFL1) The SOTBFLn register is an 8-bit buffer register that stores initial transmission data in the repeat transfer mode (n = 0, 1). The transmission operation is not started even if data is written to the SOTBFLn register. These registers can be read/written in 8-bit or 1-bit units. The SOTBFLn register is the same as the lower bytes of the SOTBFn register. Caution Access the SOTBFLn register only when the 8-bit data length has been set (CCL bit of CSIMn register = 0), and only in the idle state (CSOTn bit of CSIMn register = 0). If the SOTBFLn register is accessed during data transfer, the data cannot be guaranteed. 7 6 5 4 3 2 1 0 Address Initial value 00H SOTBFL0 SOTBF7 SOTBF6 SOTBF5 SOTBF4 SOTBF3 SOTBF2 SOTBF1 SOTBF0 FFFFF908H 7 6 5 4 3 2 1 0 Address Initial value 00H SOTBFL1 SOTBF7 SOTBF6 SOTBF5 SOTBF4 SOTBF3 SOTBF2 SOTBF1 SOTBF0 FFFFF918H Bit position 7 to 0 Bit name SOTBF7 to SOTBF0 Function Stores initial transmission data in repeat transfer mode. 490 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (11) Serial I/O shift registers 0, 1 (SIO0, SIO1) The SIOn register is a 16-bit shift register that converts parallel data into serial data (n = 0, 1). The transfer operation is not started even if the SIOn register is read. These registers are read-only, in 16-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSICAEn bit of the CSIMn register. Caution Read the SIOn register only when the 16-bit data length has been set (CCL bit of CSIMn register = 1), and only in the idle state (CSOTn bit of CSIMn register = 0). If the SIOn register is read during data transfer, the data cannot be guaranteed. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF90AH Initial value 0000H SIO0 SIO15 SIO14 SIO13 SIO12 SIO11 SIO10 SIO9 SIO8 SIO7 SIO6 SIO5 SIO4 SIO3 SIO2 SIO1 SIO0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF91AH Initial value 0000H SIO1 SIO15 SIO14 SIO13 SIO12 SIO11 SIO10 SIO9 SIO8 SIO7 SIO6 SIO5 SIO4 SIO3 SIO2 SIO1 SIO0 Bit position 15 to 0 Bit name SIO15 to SIO0 Function Data is shifted in (reception) or shifted out (transmission) from the MSB or LSB side. User's Manual U14492EJ5V0UD 491 CHAPTER 10 SERIAL INTERFACE FUNCTION (12) Serial I/O shift registers L0, L1 (SIOL0, SIOL1) The SIOLn register is an 8-bit shift register that converts parallel data into serial data (n = 0, 1). The transfer operation is not started even if the SIOLn register is read. These registers are read-only, in 8-bit or 1-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSICAEn bit of the CSIMn register. The SIOLn register is the same as the lower bytes of the SIOn register. Caution Read the SIOLn register only when the 8-bit data length has been set (CCL bit of CSIMn register = 0), and only in the idle state (CSOTn bit of CSIMn register = 0). If the SIOLn register is read during data transfer, the data cannot be guaranteed. 7 SIOL0 SIO7 6 SIO6 5 SIO5 4 SIO4 3 SIO3 2 SIO2 1 SIO1 0 SIO0 Address FFFFF90AH Initial value 00H 7 SIOL1 SIO7 6 SIO6 5 SIO5 4 SIO4 3 SIO3 2 SIO2 1 SIO1 0 SIO0 Address FFFFF91AH Initial value 00H Bit position 7 to 0 Bit name SIO7 to SIO0 Function Data is shifted in (reception) or shifted out (transmission) from the MSB or LSB side. 492 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.4 Operation (1) Single transfer mode (a) Usage In the receive-only mode (TRMDn bit of CSIMn register = 0), transfer is started by readingNote 1 the receive data buffer register (SIRBn/SIRBLn) (n = 0, 1). In the transmission/reception mode (TRMDn bit of CSIMn register = 1), transfer is started by writingNote to the transmit data buffer register (SOTBn/SOTBLn). In the slave mode, the operation must be enabled beforehand (CSICAEn bit of CSIMn register = 1). When transfer is started, the value of the CSOTn bit of the CSIMn register becomes 1 (transmission execution status). Upon transfer completion, the transmission/reception completion interrupt (INTCSIn) is set (1), and the CSOTn bit is cleared (0). The next data transfer request is then waited for. Notes 1. When the 16-bit data length (CCL bit of CSIMn register = 1) has been set, read the SIRBn register. When the 8-bit data length (CCL bit of CSIMn register = 0) has been set, read the SIRBLn register. 2. When the 16-bit data length (CCL bit of CSIMn register = 1) has been set, write to the SOTBn register. When the 8-bit data length (CCL bit of CSIMn register = 0) has been set, write to the SOTBLn register. Caution When the CSOTn bit of the CSIMn register = 1, do not manipulate the CSIn register. 2 User's Manual U14492EJ5V0UD 493 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-26. Timing Chart in Single Transfer Mode (1/2) (a) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, operation mode: CKP bit = 0, DAP bit = 0 SCKn (I/O) SOn (output) SIn (input) 0 1 0 1 0 1 0 1 (55H) 1 0 1 0 1 0 1 0 (AAH) Reg_R/W SOTBLn register SIOLn register SIRBLn register CSOTn bit INTCSIn interrupt Write 55H to SOTBLn register 55H (transmit data) ABH 56H ADH 5AH B5H 6AH D5H AAH AAH Remarks 1. n = 0, 1 2. Reg_R/W: Internal signal. performed. This signal indicates that receive data buffer register (SIRBn/ SIRBLn) read or transmit data buffer register (SOTBn/SOTBLn) write was 494 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-26. Timing Chart in Single Transfer Mode (2/2) (b) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, operation mode: CKP bit = 0, DAP bit = 1 SCKn (I/O) SOn (output) SIn (input) Reg_R/W SOTBLn register SIOLn register SIRBLn register CSOTn bit INTCSIn interrupt ABH 56H 0 1 0 1 0 1 0 1 (55H) 1 0 1 0 1 0 1 0 (AAH) Write 55H to SOTBLn register 55H (transmit data) ADH 5AH B5H 6AH D5H AAH AAH Remarks 1. n = 0, 1 2. Reg_R/W: Internal signal. performed. This signal indicates that receive data buffer register (SIRBn/ SIRBLn) read or transmit data buffer register (SOTBn/SOTBLn) write was User's Manual U14492EJ5V0UD 495 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Clock phase selection The following shows the timing when changing the conditions for clock phase selection (CKP bit of CSICn register) and data phase selection (DAP bit of CSICn register) under the following conditions. * Data length = 8 bits (CCL bit of CSIMn register = 0) * First bit of transfer data = MSB (DIRn bit of CSIMn register = 0) * No interrupt request signal delay control (CSIT bit of CSIMn register = 0) Figure 10-27. Timing Chart According to Clock Phase Selection (1/2) (a) When CKP bit = 0, DAP bit = 0 SCKn (I/O) SIn (input) SOn (output) Reg_R/W INTCSIn interrupt CSOTn bit DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 (b) When CKP bit = 1, DAP bit = 0 SCKn (I/O) SIn (input) SOn (output) Reg_R/W INTCSIn interrupt CSOTn bit DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Remarks 1. n = 0, 1 2. Reg_R/W: Internal signal. performed. This signal indicates that receive data buffer register (SIRBn/ SIRBLn) read or transmit data buffer register (SOTBn/SOTBLn) write was 496 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-27. Timing Chart According to Clock Phase Selection (2/2) (c) When CKP bit = 0, DAP bit = 1 SCKn (I/O) SIn (input) SOn (output) Reg_R/W INTCSIn interrupt CSOTn bit DI7 DO7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO6 DO5 DO4 DO3 DO2 DO1 DO0 (d) When CKP bit = 1, DAP bit = 1 SCKn (I/O) SIn (input) SOn (output) Reg_R/W INTCSIn interrupt CSOTn bit DI7 DO7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Remarks 1. n = 0, 1 2. Reg_R/W: Internal signal. performed. This signal indicates that receive data buffer register (SIRBn/ SIRBLn) read or transmit data buffer register (SOTBn/SOTBLn) write was User's Manual U14492EJ5V0UD 497 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Transmission/reception completion interrupt request signals (INTCSI0, INTCSI1) INTCSIn is set (1) upon completion of data transmission/reception. Caution The delay mode (CSIT bit = 1) is valid only in the master mode (bits CKS2 to CKS0 of the CSICn register are not 111B). The delay mode cannot be set when the slave mode is set (bits CKS2 to CKS0 = 111B). Figure 10-28. Timing Chart of Interrupt Request Signal Output in Delay Mode (1/2) (a) When CKP bit = 0, DAP bit = 0 Input clock SCKn (I/O) SIn (input) DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SOn (output) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Reg_R/W INTCSIn interrupt CSOTn bit Delay Remarks 1. n = 0, 1 2. Reg_R/W: Internal signal. performed. This signal indicates that receive data buffer register (SIRBn/ SIRBLn) read or transmit data buffer register (SOTBn/SOTBLn) write was 498 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-28. Timing Chart of Interrupt Request Signal Output in Delay Mode (2/2) (b) When CKP bit = 1, DAP bit = 1 Input clock SCKn (I/O) SIn (input) DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SOn (output) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Reg_R/W INTCSIn interrupt CSOTn bit Delay Remarks 1. n = 0, 1 2. Reg_R/W: Internal signal. performed. This signal indicates that receive data buffer register (SIRBn/ SIRBLn) read or transmit data buffer register (SOTBn/SOTBLn) write was User's Manual U14492EJ5V0UD 499 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Repeat transfer mode (a) Usage (receive-only) <1> Set the repeat transfer mode (AUTO bit of CSIMn register = 1) and the receive-only mode (TRMDn bit of CSIMn register = 0). <2> Read SIRBn register (start transfer with dummy read). <3> Wait for transmission/reception completion interrupt request (INTCSIn). <4> When the transmission/reception completion interrupt request (INTCSIn) has been set (1), read the SIRBn registerNote (reserve next transfer). <5> Repeat steps <3> and <4> (N - 2) times (N: Number of transfer data). <6> Following output of the last transmission/reception completion interrupt request (INTCSIn), read the SIRBEn register and the SIOn registerNote. Note When transferring N number of data, receive data is loaded by reading the SIRBn register from the first data to the (N - 2)th data. The (N - 1)th data is loaded by reading the SIRBEn register, and the Nth (last) data is loaded by reading the SIOn register. 500 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-29. Repeat Transfer (Receive-Only) Timing Chart SCKn (I/O) SIn (input) SIOLn register SIRBLn register Reg_RD CSOTn bit INTCSIn interrupt SOn (output) rq_clr trans_rq <1> <2> <3> <4> <3> <5> Period during which next transfer can be reserved <4> <3> <4> <6> L SIRBn (dummy) din-1 din-2 din-3 din-4 din-5 din-5 din-1 SIRBn (d1) din-2 din-3 SIRBn (d2) din-4 SIRBn (d3) SIRBEn (d4) SIOn (d5) Remarks 1. n = 0, 1 2. Reg_RD: Internal signal. This signal indicates that the receive data buffer register (SIRBn/ SIRBLn) has been read. rq_clr: Internal signal. Transfer request clear signal. trans_rq: Internal signal. Transfer request signal. In the case of the repeat transfer mode, two transfer requests are set at the start of the first transfer. Following the transmission/reception completion interrupt request (INTCSIn), transfer is continued if the SIRBn register can be read within the next transfer reservation period. If the SIRBn register cannot be read, transfer ends and the SIRBn register does not receive the new value of the SIOn register. The last data can be obtained by reading the SIOn register following completion of the transfer. User's Manual U14492EJ5V0UD 501 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Usage (transmission/reception) <1> Set the repeat transfer mode (AUTO bit of CSIMn register = 1) and the transmission/reception mode (TRMDn bit of CSIMn register = 1). <2> Write the first data to the SOTBFn register. <3> Write the 2nd data to the SOTBn register (start transfer). <4> Wait for a transmission/reception completion interrupt request (INTCSIn). <5> When the transmission/reception completion interrupt request (INTCSIn) has been set (1), write the next data to the SOTBn register (reserve next transfer), and read the SIRBn register to load the receive data. <6> Repeat steps <4> and <5> as long as data to be sent remains. <7> Wait for the INTCSIn interrupt. When the interrupt request signal is set (1), read the SIRBn register to load the (N - 1)th receive data (N: Number of transfer data). <8> Following the last transmission/reception completion interrupt request (INTCSIn), read the SIOn register to load the Nth (last) receive data. 502 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-30. Repeat Transfer (Transmission/Reception) Timing Chart SCKn (I/O) SOn (output) SIn (input) SOTBFLn register SOTBLn register SIOLn register SIRBLn register dout-1 dout-2 dout-3 dout-4 dout-5 din-5 din-1 SOTBn (d3) SIRBn (d1) din-2 din-3 SOTBn (d4) SIRBn (d2) din-4 SOTBn (d5) SIRBn (d3) SIRBn (d4) SIOn (d5) dout-1 din-1 dout-2 din-2 dout-3 din-3 dout-4 din-4 dout-5 din-5 SOTBFn (d1) Reg_WR SOTBn (d2) Reg_RD CSOTn bit INTCSIn interrupt rq_clr trans_rq <1> <2> <3> <4> <5> <4> <6> Period during which next transfer can be reserved <5> <4> <5> <7> <8> Remarks 1. n = 0, 1 2. Reg_WR: Internal signal. This signal indicates that the transmit data buffer register (SOTBn/ SOTBLn) has been written. Reg_RD: Internal signal. This signal indicates that the receive data buffer register (SIRBn/ SIRBLn) has been read. rq_clr: Internal signal. Transfer request clear signal. trans_rq: Internal signal. Transfer request signal. In the case of the repeat transfer mode, two transfer requests are set at the start of the first transfer. Following the transmission/reception completion interrupt request (INTCSIn), transfer is continued if the SOTBn register can be written within the next transfer reservation period. If the SOTBn register cannot be written, transfer ends and the SIRBn register does not receive the new value of the SIOn register. The last receive data can be obtained by reading the SIOn register following completion of the transfer. User's Manual U14492EJ5V0UD 503 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Next transfer reservation period In the repeat transfer mode, the next transfer must be prepared with the period shown in Figure 10-31. Figure 10-31. Timing Chart of Next Transfer Reservation Period (1/2) (a) When data length: 8 bits, operation mode: CKP bit = 0, DAP bit = 0 SCKn (I/O) INTCSIn interrupt Reservation period: 7 SCKn cycles (b) When data length: 16 bits, operation mode: CKP bit = 0, DAP bit = 0 SCKn (I/O) INTCSIn interrupt Reservation period: 15 SCKn cycles Remark n = 0, 1 504 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-31. Timing Chart of Next Transfer Reservation Period (2/2) (c) When data length: 8 bits, operation mode: CKP bit = 0, DAP bit = 1 SCKn (I/O) INTCSIn interrupt Reservation period: 6.5 SCKn cycles (d) When data length: 16 bits, operation mode: CKP bit = 0, DAP bit = 1 SCKn (I/O) INTCSIn interrupt Reservation period: 14.5 SCKn cycles Remark n = 0, 1 User's Manual U14492EJ5V0UD 505 CHAPTER 10 SERIAL INTERFACE FUNCTION (d) Cautions To continue repeat transfers, it is necessary to either read the SIRBn register or write to the SOTBn register during the transfer reservation period. If access is performed to the SIRBn register or the SOTBn register when the transfer reservation period is over, the following occurs. (i) In case of contention between transfer request clear and register access Since request cancellation has higher priority, the next transfer request is ignored. transfer is interrupted, and normal data transfer cannot be performed. Figure 10-32. Transfer Request Clear and Register Access Contention Therefore, Transfer reservation period SCKn (I/O) INTCSIn interrupt rq_clr Reg_R/W Remarks 1. n = 0, 1 2. rq_clr: Internal signal. Transfer request clear signal. Reg_R/W: Internal signal. This signal indicates that the receive data buffer register (SIRBn/ SIRBLn) read or transmit data buffer register (SOTBn/SOTBLn) write was performed. 506 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (ii) In case of contention between interrupt request and register access Since continuous transfer has stopped once, executed as a new repeat transfer. In the slave mode, a bit phase error transfer error results (refer to Figure 10-33). In the transmission/reception mode, the value of the SOTBFn register is retransmitted, and illegal data is sent. Figure 10-33. Interrupt Request and Register Access Contention Transfer reservation period SCKn (I/O) INTCSIn interrupt 0 1 2 3 4 rq_clr Reg_R/W Remarks 1. n = 0, 1 2. rq_clr: Internal signal. Transfer request clear signal. Reg_R/W: Internal signal. performed. This signal indicates that receive data buffer register (SIRBn/ SIRBLn) read or transmit data buffer register (SOTBn/SOTBLn) write was User's Manual U14492EJ5V0UD 507 CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.5 Output pins (1) SCKn pin When the CSIn operation is disabled (CSICAEn bit of CSIMn register = 0), the SCKn pin output status is as follows (n = 0, 1). Table 10-9. SCKn Pin Output Status CKP 0 1 CKS2 Don't care 1 CKS1 Don't care 1 CKS0 Don't care 1 SCKn Pin Output Fixed to high level Fixed to high level Fixed to low level Other than above Remarks 1. n = 0, 1 2. When any of bits CKP and CKS2 to CKS0 of the CSICn register is overwritten, the SCKn pin output changes. (2) SOn pin When the CSIn operation is disabled (CSICAEn bit of CSIMn register = 0), the SOn pin output status is as follows (n = 0, 1). Table 10-10. SOn Pin Output Status TRMDn 0 1 DAP Don't care 0 1 AUTO Don't care Don't care 0 CCL Don't care Don't care 0 DIRn Don't care Don't care 0 1 1 0 1 1 0 0 1 1 0 1 SOn Pin Output Fixed to low level SO latch value (low level) SOTB7 value SOTB0 value SOTB15 value SOTB0 value SOTBF7 value SOTBF0 value SOTBF15 value SOTBF0 value Remarks 1. n = 0, 1 2. When any of bits TRMDn, CCL, DIRn, and AUTO of the CSIMn register or DAP bit of the CSICn register is overwritten, the SOn pin output changes. 3. SOTBm: Bit m of SOTBn register (m = 0, 7, 15) 4. SOTBFm: Bit m of SOTBFn register (m = 0, 7, 15) 508 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.6 Dedicated baud rate generator 3 (BRG3) (1) Configuration of baud rate generator 3 (BRG3) The CSI0 and CSI1 serial clocks can be selected from the dedicated baud rate generator output or internal system clock (fXX). The serial clock source is specified with registers CSIC0 and CSIC1. If dedicated baud rate generator output is specified, BRG3 is selected as the clock source. Since the same serial clock can be shared for transmission and reception, baud rate is the same for the transmission/reception. Figure 10-34. Block Diagram of Baud Rate Generator 3 (BRG3) fXX/4 Selector fXX/8 8-bit timer counter fXX/16 fXX/32 Match detector 1/2 CSIn BGCS1, BGCS0 PRSCM3 Remark fXX: Internal system clock n = 0, 1 User's Manual U14492EJ5V0UD 509 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Dedicated baud rate generator 3 (BRG3) BRG3 is configured of an 8-bit timer counter that generates the baud rate signal, a prescaler mode register 3 (PRSM3) that controls baud rate signal generation, a prescaler compare register 3 (PRSCM3) that sets the value of the 8-bit timer counter, and a prescaler. (a) Input clock The internal system clock (fXX) is input to BRG3. (b) Prescaler mode register 3 (PRSM3) The PRSM3 register controls generation of the CSI0 and CSI1 baud rate signals. This register can be read/written in 8-bit or 1-bit units. Cautions 1. Do not change the values of the BGCS1 and BGCS0 bits during transmission/ reception operation. 2. Set the PRSM3 register prior to setting the CSICAEn bit of the CSIMn register to 1 (n = 0, 1). 7 PRSM3 0 6 0 5 0 4 CE 3 0 2 0 1 BGCS1 0 BGCS0 Address FFFFF920H Initial value 00H Bit position 4 Bit name CE Function Enables baud rate counter operation. 0: Stop baud rate counter operation and fix baud rate output signal to 0. 1: Enable baud rate counter operation and start baud rate output operation. 1, 0 BGCS1, BGCS0 Selects count clock for baud rate counter. BGCS1 0 0 1 1 BGCS0 0 1 0 1 fXX/4 fXX/8 fXX/16 fXX/32 Count clock selection Remark fXX: Internal system clock 510 User's Manual U14492EJ5V0UD CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Prescaler compare register 3 (PRSCM3) PRSCM3 is an 8-bit compare register that sets the value of the 8-bit timer counter. This register can be read/written in 8-bit units. Cautions 1. The internal timer counter is cleared by writing to the PRSM3 register. Therefore, do not write to the PRSCM3 register during transmission. 2. Set the PRSCM3 register prior to setting the CSICAEn bit of the CSIMn register to 1. If the contents of the PRSCM3 register are overwritten when the value of the CSICAEn bit is 1, the cycle of the baud rate signal is not guaranteed. 7 6 5 4 3 2 1 0 Address Initial value 00H PRSCM3 PRSCM7 PRSCM6 PRSCM5 PRSCM4 PRSCM3 PRSCM2 PRSCM1 PRSCM0 FFFFF922H (d) Baud rate signal cycle The baud rate signal cycle is calculated as follows. * * When setting value of PRSCM3 register is 00H (Cycle of signal selected with bits BGCS1, BGCS0 of PRSM3 register) x 256 x 2 In cases other than above (Cycle of signal selected with bits BGCS1, BGCS0 of PRSM3 register) x (setting value of PRSCM3 register) x 2 User's Manual U14492EJ5V0UD 511 CHAPTER 10 SERIAL INTERFACE FUNCTION (e) Baud rate setting value Table 10-11. Baud Rate Generator Setting Data (a) When fXX = 32 MHz BGCS1 0 0 0 0 0 0 0 0 0 1 BGCS0 0 0 0 0 0 0 0 0 1 0 PRSCM Register Value 1 2 4 8 16 40 80 160 200 200 Clock (Hz) 4000000 2000000 1000000 500000 250000 100000 50000 25000 10000 5000 (b) When fXX = 40 MHz BGCS1 0 0 0 0 0 0 0 0 1 BGCS0 0 0 0 0 0 0 0 1 0 PRSCM Register Value 2 5 10 20 50 100 200 250 250 Clock (Hz) 2500000 1000000 500000 250000 100000 50000 25000 10000 5000 (c) When fXX = 50 MHz BGCS1 0 0 0 0 0 0 0 0 0 1 BGCS0 0 0 0 0 0 0 0 0 1 0 PRSCM Register Value 2 4 5 10 25 50 125 250 250 250 Clock (Hz) 3125000 1562500 1250000 625000 250000 125000 50000 25000 12500 6250 Caution Set the transfer clock so that it does not fall below the minimum value of 200 ns of the SCKn cycle (tCYSK1) prescribed in the electrical specifications. 512 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER The V850E/IA1 features a 1 channel on-chip FCAN (Full Controller Area Network) controller that complies with the CAN specification Ver. 2.0, PartB active. 11.1 Function Overview Table 11-1 presents an overview of V850E/IA1 functions. Table 11-1. Overview of Functions Function Protocol Baud rate Data storage Description CAN Protocol Ver. 2.0, PartB active (standard and extended frame transmission/reception) Maximum 1 Mbps (during 16 MHz clock input) * Allocated to common access-enabled RAM area * RAM that is mapped to an unused message byte can be used for CPU processing or other processing Mask functions * Four * Global masks and local masks can be used without distinction Message configuration No. of messages Message storage method Remote reception Can be declared as transmit or receive messages 32 * Storage to receive buffer corresponding to ID * Storage to buffer specified by receive mask function * Remote frames can be received in either the receive message buffer or the transmit message buffer * If a remote frame is received by a transmit message buffer, there is a choice between having the remote request processed by the CPU or starting the auto transmit function. Remote transmission The remote frame can be sent either by setting the transmit message's RTR bit (M_CTRLn register) or by setting the receive message's send request. Time stamp function Diagnostic functions A time stamp function can be set for receive messages and transmit messages. * Read-enabled error counter is provided. * "Valid protocol operation flag" is provided for verification of bus connections. * Receive-only mode (with auto baud rate detection) is provided. * Diagnostic processing mode is provided. Low-power mode * CAN sleep mode (wake up function using CAN bus is enabled) * CAN stop mode (wake up function using CAN bus is disabled) Remark n = 00 to 31 User's Manual U14492EJ5V0UD 513 CHAPTER 11 FCAN CONTROLLER 11.2 Configuration FCAN is composed of the following four blocks. (1) NPB interface This functional block provides an NPB (NEC peripheral I/O bus) interface as a means of transmitting and receiving signals. (2) MAC (Memory Access Controller) This functional block controls access to the CAN module and to the CAN RAM within the FCAN. (3) CAN module This functional block is involved in the operation of the CAN protocol layer and its related settings. (4) CAN RAM This is the CAN memory functional block, which is used to store message IDs, message data, etc. 514 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER Figure 11-1. Block Diagram of FCAN CPU Interrupt request INTCREC INTCTRX INTCERR INTCMAC NPB (NEC peripheral I/O bus) CAN bus FCAN controller MAC (Memory Access Controller) CTXD CAN module CRXD CAN transceiver CAN_L CAN_H NPB interface CAN RAM Message buffer 0 Message buffer 1 Message buffer 2 Message buffer 3 Message buffer 31 CMASK0 CMASK1 CMASK2 CMASK3 ... User's Manual U14492EJ5V0UD 515 CHAPTER 11 FCAN CONTROLLER 11.3 Configuration of Messages and Buffers Table 11-2. Configuration of Messages and Buffers Address Note (m = 2, 6, A, E) Register Name Message buffer 0 field Message buffer 1 field Message buffer 2 field Message buffer 3 field Message buffer 4 field Message buffer 5 field Message buffer 6 field Message buffer 7 field Message buffer 8 field Message buffer 9 field Message buffer 10 field Message buffer 11 field Message buffer 12 field Message buffer 13 field Message buffer 14 field Message buffer 15 field Address Note (m = 2, 6, A, E) Register Name Message buffer 16 field Message buffer 17 field Message buffer 18 field Message buffer 19 field Message buffer 20 field Message buffer 21 field Message buffer 22 field Message buffer 23 field Message buffer 24 field Message buffer 25 field Message buffer 26 field Message buffer 27 field Message buffer 28 field Message buffer 29 field Message buffer 30 field Message buffer 31 field xxxxm800H to xxxxm81FH xxxxm820H to xxxxm83FH xxxxm840H to xxxxm85FH xxxxm860H to xxxxm87FH xxxxm880H to xxxxm89FH xxxxm8A0H to xxxxm8BFH xxxxm8C0H to xxxxm8DFH xxxxm8E0H to xxxxm8FFH xxxxm900H to xxxxm91FH xxxxm920H to xxxxm93FH xxxxm940H to xxxxm95FH xxxxm960H to xxxxm97FH xxxxm980H to xxxxm99FH xxxxm9A0H to xxxxm9BFH xxxxm9C0H to xxxxm9DFH xxxxm9E0H to xxxxm9FFH xxxxmA00H to xxxxmA1FH xxxxmA20H to xxxxmA3FH xxxxmA40H to xxxxmA5FH xxxxmA60H to xxxxmA7FH xxxxmA80H to xxxxmA9FH xxxxmAA0H to xxxxmABFH xxxxmAC0H to xxxxmADFH xxxxmAE0H to xxxxmAFFH xxxxmB00H to xxxxmB1FH xxxxmB20H to xxxxmB3FH xxxxmB40H to xxxxmB5FH xxxxmB60H to xxxxmB7FH xxxxmB80H to xxxxmB9FH xxxxmBA0H to xxxxmBBFH xxxxmBC0H to xxxxmBDFH xxxxmBE0H to xxxxmBFFH Note CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. Caution When emulating the FCAN controller using the in-circuit emulator (IE-V850E-MC or IE-703116-MCEM1), perform the following settings in the Configuration screen that appears when the debugger is started. * Set the start address of the programmable peripheral I/O area that is set using the BPC register to the Programmable I/O Area field. * Map the programmable peripheral I/O area as "Target" or "Emulation RAM" in the Memory Mapping field. Remark For details of message buffers, see 3.4.9 Programmable peripheral I/O registers. 516 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER 11.4 Time Stamp Function The FCAN controller supports a time stamp function. This function is needed to build a global time system. The time stamp function is implemented using a 16-bit free-running time stamp counter. Two types of time stamp function can be selected for message reception in the FCAN controller. Use bit 3 (TMR) of the CAN1 control register (C1CTRL) to set the desired time stamp function. When the TMR bit is 0, the time stamp counter value is captured after the SOF is detected on the CAN bus (see Figure 11-2) and when the TMR bit is 1, the time stamp counter value is captured after the EOF is detected on the CAN bus (a valid message is confirmed) (see Figure 11-3). Figure 11-2. Time Stamp Function Setting for Message Reception (When C1CTRL Register's TMR Bit = 0) SOF ACK field EOF Message CAN message buffer n Time stamp counter <1> Temporary buffer <2> M_TIMEn User's Manual U14492EJ5V0UD 517 CHAPTER 11 FCAN CONTROLLER Figure 11-3. Time Stamp Function Setting for Message Reception (When C1CTRL Register's TMR Bit = 1) SOF ACK field EOF Message CAN message buffer n Time stamp counter <1> M_TIMEn In a global time system, the timer value must be captured using the SOF. In addition, the ability to capture the time stamp counter value when message is stored in CAN message buffer n is useful for evaluating the FCAN controller's performance. The captured time stamp counter value is stored in CAN message buffer n, so CAN message buffer n has its own time stamp function (n = 00 to 31). When the SOF is detected on the CAN bus while transmitting a message, there is an option to replace the last two bytes of the message with the captured time stamp counter value by setting bit 5 (ATS) of CAN message control register n (M_CTRLn). This function can be selected for CAN message buffer n on a buffer by buffer basis. Figure 11-4 shows the time stamp setting when the ATS bit = 1. 518 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER Figure 11-4. Time Stamp Function Setting for Message Transmission (When M_CTRL Register's ATS Bit = 1) SOF ACK field EOF Message <2> Time stamp counter <1> Temporary buffer Table 11-3. Example When Adding Captured Time Stamp Counter Value to Last 2 Bytes of Transmit Message Data Field DLC Note1 Bit Value 1 2 3 4 5 6 7 8 9 to 15 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 M_DATAn0 register value Note 2 M_DATAn0 register value M_DATAn0 register value M_DATAn0 register value M_DATAn0 register value M_DATAn0 register value M_DATAn0 register value M_DATAn0 register value - Note 3 Note 2 M_DATAn1 register value M_DATAn1 register value M_DATAn1 register value M_DATAn1 register value M_DATAn1 register value M_DATAn1 register value - - Note 3 Note 2 M_DATAn2 register value M_DATAn2 register value M_DATAn2 register value M_DATAn2 register value M_DATAn2 register value - - - Note 3 Note 2 M_DATAn3 register value M_DATAn3 register value M_DATAn3 register value M_DATAn3 register value - - - - Note 3 Note 2 M_DATAn4 register value M_DATAn4 register value M_DATAn4 register value - - - - - Note 3 Note 2 M_DATAn5 register value M_DATAn5 register value - - - - - - Note 3 Note 2 Note 2 - - - - - - - Note 3 Note 3 Notes 1. 2. 3. Remark See 11.10 (2) CAN message data length registers 00 to 31 (M_DLC00 to M_DLC31). The lower 8 bits of the time stamp counter value when the SOF is detected on the CAN bus The higher 8 bits of the time stamp counter value when the SOF is detected on the CAN bus n = 00 to 31 User's Manual U14492EJ5V0UD 519 CHAPTER 11 FCAN CONTROLLER 11.5 Message Processing A modular system is used for the FCAN controller. Consequently, messages can be placed at any location within the message area. The messages can be linked to mask functions that are in turn linked to CAN modules. 11.5.1 Message transmission The FCAN system is a multiplexed communication system. The priority of message transmission within this system is determined based on message identifiers (IDs). To facilitate communication processing by application software when there are several messages awaiting transmission, the CAN module uses hardware to check the message IDs and automatically determine whether or not linked messages are prioritized. This eliminates the need for software-based priority control. In addition, the priority at transmission can be controlled by setting the PBB bit of the C1DEF register. * When the PBB bit is set to 0 (see Figure 11-5) Transmission priority is controlled by the identifier (ID). The numberNote of messages waiting to be transmitted in the message buffer that can be set simultaneously by application software is up to five messages per CAN module. Note The number of message buffers when the TRQ bit of the M_STAT00 to M_STAT31 registers = 1. * When the PBB bit is set to 1 (see Figure 11-6) Transmission priority is controlled by the message numbers. The number of messages waiting to be transmitted in the message buffer is not limited by the application software. 520 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER Figure 11-5. Message Processing Example (When PBB Bit = 0) Message No. Message waiting to be transmitted 0 1 2 3 4 5 6 7 8 9 ID = 123H ID = 223H ID = 023H ID = 120H ID = 229H CAN module transmits messages in the following sequence. 1. Message 6 2. Message 1 3. Message 8 4. Message 5 5. Message 2 Figure 11-6. Message Processing Example (When PBB Bit = 1) Message No. Message waiting to be transmitted 0 1 2 3 4 5 6 7 8 9 ID = 123H ID = 223H ID = 023H ID = 120H ID = 229H CAN module transmits messages in the following sequence. 1. Message 1 2. Message 2 3. Message 5 4. Message 6 5. Message 8 User's Manual U14492EJ5V0UD 521 CHAPTER 11 FCAN CONTROLLER 11.5.2 Message reception When two or more message buffers of the CAN module receive a message, the storage priority of the received messages is as follows (the storage priority differs between data frames and remote frames). Table 11-4. Storage Priority for Data Frame Reception Priority 2 (High) 3 4 5 6 (Low) Unmasked message buffer Message buffer linked to mask 0 Message buffer linked to mask 1 Message buffer linked to mask 2 Message buffer linked to mask 3 Conditions Table 11-5. Storage Priority for Remote Frame Reception Priority 1 (High) 2 3 4 5 6 (Low) Transmit message buffer Unmasked message buffer Message buffer linked to mask 0 Message buffer linked to mask 1 Message buffer linked to mask 2 Message buffer linked to mask 3 Conditions A message (data frame or remote frame) is always stored in a receive message buffer with a higher priority, not in a receive buffer with a lower priority. For example, when the unmasked receive message buffer and the message buffer linked to mask 0 have the same ID, a message is always stored in the unmasked receive message buffer even if the unmasked receive message buffer has already received a message. When two or more message buffers with the same priority exist in the same CAN module, the priority is as follows. Table 11-6. Priority of Same Priority Level Priority 1 (High) 2 (Low) DN bit of M_STAT register is not set (1) DN bit of M_STAT register is set (1) Condition When two or more message buffers with the same priority exist, the message buffer with the smaller message number takes precedence. Also, when two or more message buffers with the same ID exist, the message buffer with the smaller message number takes precedence. 522 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER 11.6 Mask Function A mask linkage function can be defined for each received message. This means that there is no need to distinguish between local masks and global masks. When the mask function is used, the received message's identifier is compared with the message buffer's identifier and the message can be stored in the defined message buffer regardless of whether the mask sets "0" or "1" as a result of the comparison. When the mask function is operating, a bit whose value is defined as "1" by masking is not subject to the abovementioned comparison between the received message's identifier and the message buffer's identifier. However, this comparison is performed for any bit whose value is defined as "0" by masking. For example, let us assume that all messages that have a standard-format ID in which bits ID27 to ID25 = 0 and bits ID24 and ID22 = 1 are to be stored in message buffer 14 (which is linked by mask 1 as explained in 11.10 (7)). The procedure for this example is shown below. <1> Identifier bits to be stored in message buffer ID28 x ID27 0 ID26 0 ID25 0 ID24 1 ID23 x ID22 1 ID21 x ID20 x ID19 x ID18 x Remark x = don't care Messages with an ID in which bits ID27 to ID25 = 0 and bits ID24 and ID22 = 1 are registered (initialized) in message buffer 14 (see 11.10 (6)). <2> Identifier bits set to message buffer 14 (example) (Using CAN message ID registers L14 and H14 (M_IDL14 and M_IDH14)) ID28 0 ID17 0 ID6 0 ID27 0 ID16 0 ID5 0 ID26 0 ID15 0 ID4 0 ID25 0 ID14 0 ID3 0 ID24 1 ID13 0 ID2 0 ID23 0 ID12 0 ID1 0 ID22 1 ID11 0 ID0 0 ID21 0 ID10 0 ID20 0 ID9 0 ID19 0 ID8 0 ID18 0 ID7 0 Message buffer 14 is set as a standard-format identifier linked to mask 1 (see 11.10 (7)). User's Manual U14492EJ5V0UD 523 CHAPTER 11 FCAN CONTROLLER <3> Mask setting for mask 1 (example) (Using CAN1 address mask 1 registers L and H (C1MASKL1 and C1MASKH1)) CMID28 1 CMID17 1 CMID6 1 CMID27 0 CMID16 1 CMID5 1 CMID26 0 CMID15 1 CMID4 1 CMID25 0 CMID14 1 CMID3 1 CMID24 0 CMID13 1 CMID2 1 CMID23 1 CMID12 1 CMID1 1 CMID22 0 CMID11 1 CMID0 1 CMID21 1 CMID10 1 CMID20 1 CMID9 1 CMID19 1 CMID8 1 CMID18 1 CMID7 1 Remark 1: Do not compare (mask) 0: Compare Values are written to mask 1 (see 11.10 (19)), bits CMID27 to CMID24 and CMID22 are set to 0 and bits CMID28, CMID23, and CMID21 to CMID0 are set to 1. 524 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER 11.7 Protocol FCAN is a high-speed multiplex communication protocol designed to enable real-time communications in automotive applications. The CAN specification is generally divided into two layers (physical layer and data link layer). The data link layer is further divided into logical link control and medium access control. The composition of these layers is illustrated below. Figure 11-7. Composition of Layers Higher Application layer Data link layer Not applicable Message and status handling rules * Logical link control (LLC) * Medium access control (MAC) Protocol rules Signal level and bit expression rules Lower Physical layer 11.7.1 Protocol mode function (1) Standard format mode 2048 different identifiers can be set in this mode. The standard format mode uses 11-bit identifiers, which means that it can handle up to 2032 messages. (2) Extended format mode This mode is used to extend the number of identifiers that can be set. * While the standard format mode uses 11-bit identifiers, the extended format mode uses 29-bit (11 bits + 18 bits) identifiers which expands the amount of messages that can be handled to 2048 x 218 messages. * Extended format mode is set when "recessive (R): recessive in wired OR" is set for both the SRR and IDE bits in the arbitration field. * When an extended format mode message and a standard format mode remote frame are transmitted at the same time, the node that transmitted the extended format mode message is set to receive mode. User's Manual U14492EJ5V0UD 525 CHAPTER 11 FCAN CONTROLLER 11.7.2 Message formats Four types of frames are used in CAN protocol messages. The output conditions for each type of frame are as follows. * Data frame: * Remote frame: * Error frame: Frame used for transmit data Frame used for transmit requests from receiving side Frame that is output when an error has been detected * Overload frame: Frame that is output when receiving side is not ready Remark Dominant (D): Recessive (R): Dominant in wired OR Recessive in wired OR In the figure shown below, (D) = 0 and (R) = 1. (1) Data frame and remote frame <1> Data frame A data frame is the frame used for transmit data. This frame is composed of seven fields. Figure 11-8. Data Frame Data frame R D <1> <2> <3> <4> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Data field Control field Arbitration field Start of frame (SOF) 526 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER <2> Remote frame A remote frame is transmitted when the receiving node issues a transmit request. A remote frame is similar to a data frame, except that the "data field" is deleted and the RTR bit of the "arbitration field" is recessive. Figure 11-9. Remote Frame Remote frame R D <1> <2> <3> <5> <6> <7> <8> Interframe space End of frame (EOF) ACK field CRC field Control field Arbitration field Start of frame (SOF) Remark The data field is not transferred even if the control field's data length code is not "0000B". (2) Description of fields <1> Start of frame (SOF) The start of frame field is a 1-bit dominant (D) field that is located at the start of a data frame or remote frame. Figure 11-10. Start of Frame (SOF) (Interframe space or bus idle) R D Start of frame (Arbitration field) 1 bit * The start of frame field starts when the bus line level changes. * When "dominant (D)" is detected at the sample point, reception continues. * When "recessive (R)" is detected at the sample point, bus idle mode is set. User's Manual U14492EJ5V0UD 527 CHAPTER 11 FCAN CONTROLLER <2> Arbitration field The arbitration field is used to set the priority, data frame or remote frame, and protocol mode. This field includes an identifier, frame setting (RTR bit), and protocol mode setting bit. Figure 11-11. Arbitration Field (In Standard Format Mode) Arbitration field R D Identifier RTR (Control field) IDE (r1) (1 bit) r0 ID28 * * * * * * * * * * * * * * * * * * * * ID18 (11 bits) (1 bit) Figure 11-12. Arbitration Field (In Extended Format Mode) Arbitration field R D IdentifierNote SRR IDE Identifier RTR (Control field) r1 r0 ID28 * * * * * * * * * * * * * * ID18 ID17 * * * * * * * * * * * * * * * * * ID0 (11 bits) (1 bit) (1 bit) (18 bits) (1 bit) Note Setting the higher 7 bits of the identifier as 1111111B is prohibited. Cautions 1. ID28 to ID0 are identifier bits. 2. Identifier bits are transferred in MSB-first order. Table 11-7. RTR Bit Settings Frame Type Data frame Remote frame RTR Bit Dominant Recessive Table 11-8. Protocol Mode Setting and Number of Identifier (ID) Bits Protocol Mode Standard format mode Extended format mode SRR Bit None Recessive (R) IDE Bit Dominant (D) Recessive (R) No. of Bits 11 bits 29 bits 528 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER <3> Control field The control field sets "N" as the number of data bytes in the data field (N = 0 to 8). r1 and r0 are fixed as dominant (D). The data length code bits (DLC3 to DLC0) set the byte count. Remark DLC3 to DLC0: Bits 3 to 0 in CAN message data length registers 00 to 31 (M_DLC00 to M_DLC31) (see 11.10 (2)) Figure 11-13. Control Field (Arbitration field) R D RTR r1 (IDE) r0 Control field (Data field) DLC3 DLC2 DLC1 DLC0 In standard format mode, the arbitration field's IDE bit is the same bit as the r1 bit. Table 11-9. Data Length Code Settings Data Length Code DLC3 0 0 0 0 0 0 0 0 1 DLC2 0 0 0 0 1 1 1 1 0 DLC1 0 0 1 1 0 0 1 1 0 DLC0 0 1 0 1 0 1 0 1 0 0 bytes 1 byte 2 bytes 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes 8 bytes regardless of the values of DLC3 to DLC0 Data Byte Count Other than above Caution In the remote frame, there is no data field even if the data length code is not 0000B. User's Manual U14492EJ5V0UD 529 CHAPTER 11 FCAN CONTROLLER <4> Data field The data field contains the amount of data set by the control field. Up to 8 units of data can be set. Remark Data units in the data field are each 8 bits long and are ordered MSB first. Figure 11-14. Data Field (Control field) R D Data (8 bits) Data field (CRC field) Data (8 bits) <5> CRC field The CRC field is a 16-bit field that is used to check for errors in transmit data. It includes a 15-bit CRC sequence and a 1-bit CRC delimiter. Figure 11-15. CRC Field (Data field, control field) R D CRC field (ACK field) CRC sequence CRC delimiter (1 bit) (15 bits) * The polynomial P(X) used to generate the 15-bit CRC sequence is expressed as: X15 + X14 + X10 + X8 + X7 + X4 + X3 + 1 * Transmitting node: No bit stuffing in start of frame, arbitration field, control field, or data field: The transferred CRC sequence is calculated entirely from basic data bits. * Receiving node: The CRC sequence calculated using data bits that exclude the stuffing bits in the receive data is compared with the CRC sequence in the CRC field. If the two CRC sequences do not match, the node is passed to an error frame. 530 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER <6> ACK field The ACK field is used to confirm normal reception. It includes a 1-bit ACK slot and a 1-bit ACK delimiter. Figure 11-16. ACK Field (CRC field) R D ACK field (End of frame) ACK slot (1 bit) ACK delimiter (1 bit) * The receiving node outputs the following depending on whether or not an error is detected between the start of frame field and the CRC field. If an error is detected: ACK slot = Recessive (R) If no error is detected: ACK slot = Dominant (D) * The transmitting node outputs two "recessive (R)" bits and confirms the receiving node's receive status. <7> End of frame (EOF) The end of frame field indicates the end of transmission or reception. It includes 7 "recessive (R)" bits. Figure 11-17. End of Frame (EOF) (ACK field) R D End of frame (Interframe space or overload frame) (7 bits) User's Manual U14492EJ5V0UD 531 CHAPTER 11 FCAN CONTROLLER <8> Interframe space The interframe space is inserted after the data frame, remote frame, error frame, and overload frame to separate one frame from the next one. * Error active node When the bus is idle, transmit enable mode is set for each node. Transmission then starts from a node that has received a transmit request. If the node is an error active node, the interframe space is composed of a 3- or 2-bit intermission field and bus idle field. * Error passive node After an 8-bit bus idle field, transmit enable mode is set. Receive mode is set if a transmission starts from a different node in bus idle mode. The error passive node is composed of an intermission field, suspend transmission field, and bus idle field. Figure 11-18. Interframe Space (a) Error active (Frame) R D Intermission (3 or 2 bits) Bus idle (0 or more bits) Interframe space (Frame) (b) Error passive (Frame) R D Interframe space (Frame) Intermission (3 or 2 bits) Suspend transmission (8 bits) Bus idle (0 or more bits) * Bit length of intermission When transmission is pending, transmission is resumed after a 3-bit intermission. When receiving, the receive operation starts after only two bits. * Bus idle This mode is set when no nodes are using any buses. * Suspend transmission This is an 8-bit recessive (R) field that is transmitted from a node that is in error passive mode. 532 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER Table 11-10. Operation When Third Bit of Intermission Is "Dominant (D)" Transmit Status No pending transmissions Operation Receive operation is performed when start of frame output by other node is detected. Pending transmission exists Identifier is transmitted when start of frame output by local node is detected. <9> Error frame An error frame is used to output from a node in which an error has been detected. When a passive error flag is being output, if there is "dominant (D)" output from another node, the passive error flag does not end until 6 consecutive bits are detected on the same level. If the bit following the 6 consecutive "recessive (R)" bits is "dominant (D)", the error frame ends when the next "recessive (R)" bit is detected. Figure 11-19. Error Frame Error frame R D (<4>) <1> 6 bits <2> 0 to 6 bits <3> 8 bits Interframe space or overload frame Error delimiter Error flag Error flag Error bit (<5>) No <1> Error flag Name Bit count 6 Error active node Definition Consecutive output of 6 "dominant (D)" bits Error passive node Consecutive output of 6 "recessive (R)" bits <2> Error flag 0 to 6 A node that receives an error flag is a node in which bit stuffing errors are detected, after which an error flag is output. <3> Error delimiter 8 8 consecutive "recessive (R)" bits are output. If a "dominant (D)" bit is detected as the eighth bit, an overload frame is sent starting at the next bit. <4> Error bit - This bit is output following the bit where an error occurred. If the error is a CRC error, it is output following an ACK delimiter. <5> Interframe space or overload frame 3/10 20 MAX. An interframe space or overload frame starts from here. User's Manual U14492EJ5V0UD 533 CHAPTER 11 FCAN CONTROLLER <10> Overload frame An overload frame is output starting from the first bit in an intermission in cases where the receiving node is not yet ready to receive. If a bit error is detected in intermission mode, it is output starting from the bit following the bit where the bit error was detected. Figure 11-20. Overload Frame Overload frame R D (<4>) <1> 6 bits <2> 0 to 6 bits <3> 8 bits Interframe space or overload frame Overload delimiter Overload flag (node n) Overload flag (node m) Frame (<5>) No <1> Name Overload flag starting from node m Overload flag starting from node n Bit count 6 Definition Consecutive output of 6 "dominant (D)" bits. Output when node m is not ready to receive. Node n, which has received an overload flag in the interframe space, outputs an overload flag. <2> 0 to 6 <3> Overload delimiter 8 8 consecutive "recessive (R)" bits are output. If a "dominant (D)" bit is detected as the eighth bit, an overload frame is sent starting at the next bit. <4> Frame - Output following an end of frame, error delimiter, or overload delimiter. An interframe space or overload frame starts from here. <5> Interframe space or overload frame 3/10 20 MAX. Remark nm 534 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER 11.8 Functions 11.8.1 Determination of bus priority (1) When one node has started transmitting * In bus idle mode, the node that outputs data first starts transmission. (2) When several nodes have started transmitting * The node that has the longest string of consecutive "dominant (D)" bits starting from the first bit in the arbitration field has top priority for bus access ("dominant (D)" bits take precedence due to wired OR bus arbitration). * The transmitting node compares the arbitration field which it has output and the bus data level. Table 11-11. Determination of Bus Priority Matched levels Mismatched levels Transmission continues When a mismatch is detected, data output stops at the next bit, and the operation switches to receiving. (3) Priority between data frame and remote frame * If a bus conflict occurs between a data frame and a remote frame, the data frame takes priority because its last bit (RTR) is "dominant (D)". 11.8.2 Bit stuffing Bit stuffing is when one bit of inverted data is added for resynchronization to prevent burst errors when the same level is maintained for five consecutive bits. Table 11-12. Bit Stuffing Transmit When transmitting data frames and remote frames, if the same level is maintained for five bits between the start of frame and CRC fields, one bit of data whose level is inverted from the previous level is inserted before the next bit. Receive When receiving data frames and remote frames, if the same level is maintained for five bits between the start of frame and CRC fields, the next bit of data is deleted before receiving is resumed. 11.8.3 Multi-master Since bus priority is determined based on the identifier, any node can be used as the bus master. 11.8.4 Multi-cast Even when there is only one transmitting node, the same identifier can be set for several nodes, so that the same data can be received by several nodes at the same time. User's Manual U14492EJ5V0UD 535 CHAPTER 11 FCAN CONTROLLER 11.8.5 CAN sleep mode/CAN stop mode function The CAN sleep mode/CAN stop mode function is able to set the FCAN controller to sleep (standby) mode to reduce power consumption. The CAN sleep mode is set via the procedure stipulated in the CAN specification. The CAN sleep mode can be set to wake up by the bus operation, however the CAN stop mode cannot be set to wake up by the bus operation (this is controlled via CPU access). 11.8.6 Error control function (1) Types of errors Table 11-13. Types of Errors Error Type Description of Error Detection Method Detection Condition Transmit/ Receive Bit error Comparison of output level and bus level (excludes stuff bits) Stuff error Use stuff bits to check receive data Mismatch between levels Transmitting/ receiving nodes Transmitting/ receiving nodes Receiving node Bits outputting data on bus in start of frame to end of frame, error frame, or overload frame Start of frame to CRC sequence Detected Status Field/Frame Six consecutive bits of same-level data CRC error Comparison of CRC generated from receive data and received CRC sequence CRC mismatch Start of frame to data field Form error Check fixed-format field/frame Detection of inverted fixed format Receiving node * CRC delimiter * ACK field * End of frame * Error frame * Overload frame ACK error Use transmitting node to check ACK slot Use ACK slot to detect recessive Transmitting node ACK slot (2) Error frame output timing Table 11-14. Error Frame Output Timing Error Type Bit error, stuff error, form error, ACK error CRC error Error frame is output at the next bit following the ACK delimiter Output Timing Error frame is output at the next bit following the bit where error was detected (3) Handling of errors The transmitting node retransmits the data frame or remote frame after the error frame has been transmitted. 536 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (4) Error statuses (a) Types of error statuses The three types of error statuses are listed below. Error active Error passive Bus off * Error status is controlled by the transmit error counter and receive error counter (see 11.10 (23) CAN1 error count register (C1ERC)). * The various error statuses are categorized according to their error counter values. * The error flags used to output error statuses differ between transmit and receive operations. * When the error counter value reaches 96 or more, the bus status must be tested since the bus may become seriously damaged. * During startup, if only one node is active, the error frame and data are repeatedly resent because no ACK is returned even data has been transmitted. In such cases, bus off mode cannot be set. Even if the node that is sending the transmit message repeatedly experiences an error status, bus off mode cannot be set. Table 11-15. Types of Error Statuses Error Status Type Error active Operation Transmit/ receive Error passive Transmit Receive Bus off Transmit 128 to 255 128 or more 256 or more Error Counter Value 0 to 127 Type of Output Error Flag Active error flag (6 consecutive "dominant (D)" bits) Passive error flag (6 consecutive "recessive (R)" bits) Transfer is not possible. When a string of at least 11 consecutive "recessive (R)" bits occurs 128 times, the error counter is zero-cleared and the error active status can be resumed. User's Manual U14492EJ5V0UD 537 CHAPTER 11 FCAN CONTROLLER (b) Error counter The error counter value is incremented each time an error occurs and is decremented when a transmit or receive operation ends normally. The count-up/count-down timing occurs at the first bit of the error delimiter. Table 11-16. Error Counter Status Transmit Error Counter (TEC7 to TEC0) Receiving node has detected an error (except for bit errors that occur in an active error flag or overload flag) "Dominant (D)" is detected following error frame's error flag output by the receiving node Transmitting node has sent an error flag [When error counter = 0] <1> When an ACK error was detected during error passive status and a "dominant (D)" was not detected during passive error flag output <2> When a stuff error occurs in the arbitration field Detection of bit error during output of active error flag or overload flag (transmitting node with error active status) Detection of bit error during output of active error flag or overload flag (receiving node with error active status) 14 consecutive "dominant (D)" bits were detected from the start of each node's active error flag or overload flag, followed by detection of eight consecutive dominant bits. Each node has detected eight consecutive dominant bits after a passive error flag. The transmitting node has completed a transmit operation without any errors (0 if error counter value is 0). The receiving node has completed a receive operation without any errors. No change * -1 (1 REC7 to REC0 127) * 0 (REC7 to REC0 = 0) * 127 is set (REC7 to REC0 > 127) -1 No change +8 +8 No change +8 +8 No change No change +8 No change +1 Receive Error Counter (REC7 to REC0) +8 No change (c) Occurrence of bit error during intermission In this case, an overload frame occurs. Caution When an error occurs, error control is performed according to the contents of the transmitting and receiving error counters as they existed prior to the error's occurrence. The error counter value is incremented only after an error flag has been output. 538 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER 11.8.7 Baud rate control function (1) Prescaler The FCAN controller of the V850E/IA1 includes a prescaler for dividing the clock supplied to the CAN (fMEM1). This prescaler generates a clock (fBTL) that is based on a division ratio ranging from 2 to 128 applied to the CAN base clock (fMEM) when the C1BRP register's TLM bit = 0 and based on a division ratio ranging from 2 to 256 applied to the CAN base clock (fMEM) when the TLM bit = 1 (refer to 11.10 (26) CAN1 bit rate prescaler register (C1BRP)). (2) Nominal bit time (8 to 25 time quantum) A definition of 1 data bit time is shown below. Remark 1 time quantum = 1/fBTL Figure 11-21. Nominal Bit Time Nominal bit time Sync segment Prop segment Phase segment 1 Phase segment 2 SJW Sample point SJW Segment name Sync segment (Synchronization Segment) Prop segment (Propagation Segment) 1 Segment length Description This segment begins when resynchronization occurs. 1 to 8 (programmable) This segment is used to absorb the delays caused by the output buffer, CAN bus, and input buffer. It is set to return an ACK signal until phase segment 1 begins. Prop segment time (output buffer delay) + (CAN bus delay) + (input buffer delay) Phase segment 1 (Phase Buffer Segment 1) Phase segment 2 (Phase Buffer Segment 2) 1 to 8 (programmable) This segment is used to compensate for errors in the data bit time. It accommodates a wide margin or error but slows down communication speed. Maximum value from phase segment 1 or Note IPT (IPT = 0 to 2) 1 to 4 (programmable) SJW (reSynchronization Jump Width) This sets the range for bit synchronization. Note IPT: Information Processing Time IPT is a period in which the current bit level is referenced and judgment for the next processing is performed. IPT is indicated by the expression below using the clock supplied to CAN (fMEM1). IPT = 1/fMEM1 x 3 User's Manual U14492EJ5V0UD 539 CHAPTER 11 FCAN CONTROLLER (3) Data bit synchronization * Since the receiving node has no synchronization signal, synchronization is performed using level changes that occur on the bus. * As for the transmitting node, data is transmitted in sync with the transmitting node's bit timing. (a) Hardware synchronization This is bit synchronization that is performed when the receiving node has detected a start of frame in bus idle mode. * When a falling edge is detected on the bus, the current bit is assigned to the sync segment and the next bit is assigned to the prop segment. In such cases, synchronization is performed regardless of the SJW. * Since bit synchronization must be established after a reset or after a wake-up, hardware synchronization is performed only at the first level change that occurs on the bus (for the second and subsequent level changes, bit synchronization is performed as shown below). Figure 11-22. Coordination of Data Bit Synchronization Bus idle CAN bus Start of frame Bit timing Sync segment Prop segment Phase segment 1 Phase segment 2 540 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (b) Resynchronization Resynchronization is performed when a level change is detected on the bus (only when the previous sampling is at the recessive level) during a receive operation. * The edge's phase error is produced by the relative positions of the detected edge and sync segment. Previous bit CAN bus SOF Bit timing Sync segment SJW Prop segment Next bit Phase segment 1 Phase segment 2 User's Manual U14492EJ5V0UD 541 CHAPTER 11 FCAN CONTROLLER 11.9 Cautions on Bit Set/Clear Function The FCAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if the following registers are written to directly, so do not directly write (via bit manipulation, read/modify/write, or direct writing of target values) values to them. * CAN global status register (CGST) * CAN global interrupt enable register (CGIE) * CAN1 control register (C1CTRL) * CAN1 definition register (C1DEF) * CAN1 interrupt enable register (C1IE) All 16 bits in the above registers can be read via the usual method. Use the procedure described in Figure 11-24 below to set or clear the lower 8 bits in these registers. Setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits (see Figure 11-25). Figure 11-24 shows how the values of set bits or clear bits relate to set/clear/no change operations in the corresponding register. Figure 11-24. Example of Bit Setting/Clearing Operations 15 Register's current values 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 1 6 1 5 0 4 1 3 0 2 0 1 0 0 1 15 Write values 0 14 0 13 0 12 0 11 1 10 0 9 1 8 1 7 1 6 1 5 0 4 1 3 1 2 0 1 0 0 0 set 0 0 1 0 0 0 1 1 1 0 0 1 0 1 0 clear 1 No change No change Bit status No change Clear Clear Clear Set 1 1 15 Register's value after write operations 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 542 User's Manual U14492EJ5V0UD Set 0 1 CHAPTER 11 FCAN CONTROLLER Figure 11-25. 16-Bit Data During Write Operation 15 set 7 14 set 6 13 set 5 12 set 4 11 set 3 10 set 2 9 set 1 8 7 6 5 4 3 2 1 0 set 0 clear 7 clear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 set n 0 0 1 1 clear n 0 1 0 1 Bit n status after bit set/clear operation No change 0 1 No change Remark n = 0 to 7 User's Manual U14492EJ5V0UD 543 CHAPTER 11 FCAN CONTROLLER 11.10 Control Registers (1) FCAN clock selection register (PRM04) The PRM04 register is used to select the clock (fMEM1) supplied to CAN1. The clock is selected according to the clock frequency. This register can be read/written in 8-bit or 1-bit units. Caution Set this register before using FCAN. 7 PRM04 0 6 0 5 0 4 0 3 0 2 0 1 PRM5 0 PRM4 Address FFFFF930H Initial value 00H Bit position 1, 0 Bit name PRM5, PRM4 PRM5 0 0 1 1 PRM4 0 1 0 1 Function Specifies FCAN clock (fMEM1) supplied to CAN1. Input clock specification fXX/4 (when fXX > 48 MHz) fXX/2 (when 16 MHz < fXX 32 MHz) fXX/3 (when 32 MHz < fXX 48 MHz) fXX (when fXX 16 MHz) Remark fXX: Internal system clock 544 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (2) CAN message data length registers 00 to 31 (M_DLC00 to M_DLC31) The M_DLCn register sets the byte count in the data field of CAN message buffer n (n = 00 to 31). When receiving, the receive data field's byte count is set (to 1). These registers can be read/written in 8-bit units. Caution When receiving a remote frame with an extended ID and storing it in the receive message buffer, the values of DLC3 to DLC0 in the message buffer are cleared to 0 regardless of the values of DLC3 to DLC0 on the CAN bus. 7 M_DLCn (n = 00 to 31) RFUNote 6 RFUNote 5 RFUNote 4 RFUNote 3 DLC3 2 DLC2 1 DLC1 0 DLC0 Address Initial value See Table 11-17 Undefined Bit position 3 to 0 Bit name DLC3 to DLC0 DLC3 0 0 0 0 0 0 0 0 1 DLC2 0 0 0 0 1 1 1 1 0 DLC1 0 0 1 1 0 0 1 1 0 Function Control field data for setting the number of bytes in the data field DLC0 0 1 0 1 0 1 0 1 0 Data Length Code of Transmit/Receive Message 0 bytes 1 byte 2 bytes 3 bytes 4 bytes 5 bytes 6 bytes 7 bytes 8 bytes 8 bytes regardless of the values of DLC3 to DLC0 Other than above Note RFU (Reserved for Future Use) indicates a reserved bit. Be sure to clear this bit to 0 when writing the M_DLCn register. User's Manual U14492EJ5V0UD 545 CHAPTER 11 FCAN CONTROLLER Table 11-17. Addresses of M_DLCn (n = 00 to 31) Register Name M_DLC00 M_DLC01 M_DLC02 M_DLC03 M_DLC04 M_DLC05 M_DLC06 M_DLC07 M_DLC08 M_DLC09 M_DLC10 M_DLC11 M_DLC12 M_DLC13 M_DLC14 M_DLC15 Address Note (m = 2, 6, A, E) Register Name M_DLC16 M_DLC17 M_DLC18 M_DLC19 M_DLC20 M_DLC21 M_DLC22 M_DLC23 M_DLC24 M_DLC25 M_DLC26 M_DLC27 M_DLC28 M_DLC29 M_DLC30 M_DLC31 Address Note (m = 2, 6, A, E) xxxxm804H xxxxm824H xxxxm844H xxxxm864H xxxxm884H xxxxm8A4H xxxxm8C4H xxxxm8E4H xxxxm904H xxxxm924H xxxxm944H xxxxm964H xxxxm984H xxxxm9A4H xxxxm9C4H xxxxm9E4H xxxxmA04H xxxxmA24H xxxxmA44H xxxxmA64H xxxxmA84H xxxxmAA4H xxxxmAC4H xxxxmAE4H xxxxmB04H xxxxmB24H xxxxmB44H xxxxmB64H xxxxmB84H xxxxmBA4H xxxxmBC4H xxxxmBE4H Note CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. 546 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (3) CAN message control registers 00 to 31 (M_CTRL00 to M_CTRL31) The M_CTRLn register is used to set the frame format of the data field in messages stored in CAN message buffer n (n = 00 to 31). These registers can be read/written in 8-bit units. (1/2) 7 M_CTRLn (n = 00 to 31) RMDE1 6 RMDE0 5 ATS 4 IE 3 MOVR RFU 2 Notes 1, 2 1 RFU Notes 1, 3 0 RTR Address Initial value See Table 11-18 Undefined Bit position 7 Bit name RMDE1 Function Specifies operation of the DN flag when a remote frame is received on a transmit message buffer. 0: DN flag not set when remote frame is received 1: DN flag set when remote frame is received Cautions 1. When the RMDE1 bit is set, the setting of the RMDE0 bit is irrelevant. 2. If a remote frame arrives at the transmit message buffer when the RMDE1 bit has not been set, the CPU is not notified, nor are other operations performed. 6 RMDE0 Specifies setting/clearing status of remote frame auto acknowledge function. 0: Remote frame auto acknowledge function cleared 1: Remote frame auto acknowledge function set Cautions 1. The RMDE0 bit's setting is used only for transmit messages. 2. When the RTR bit has been set (to 1) (when the receive message or transmit message has a remote frame), the RMDE0 bit is processed as RMDE0 = 0. This prevents a worst-case scenario (in which transmission of a remote frame draws a 100% bus load due to reception of the same remote frame). Notes 1. 2. 3. Remark RFU (Reserved for Future Use) indicates a reserved bit. Be sure to clear this bit to 0 when writing the M_DLCn register. The value of the r1 bit on the CAN bus is set during reception. The value of the r0 bit on the CAN bus is set during reception. DN: Bit 2 of M_STATn register (see 11.10 (8) CAN message status registers 00 to 31 (M_STAT00 to M_STAT31)) User's Manual U14492EJ5V0UD 547 CHAPTER 11 FCAN CONTROLLER (2/2) Bit position 5 Bit name ATS Function Specifies whether or not to add a time stamp when transmitting. 0: Time stamp not added when transmitting 1: Time stamp added when transmitting Cautions 1. The ATS bit is used only for transmit messages. 2. When the ATS bit has been set (to 1) and the data length code specifies at least two bytes, the last two bytes are replaced by a time stamp (see Table 11-3). The added time stamp counter value is sent over the bus via the SOF of the message. When this occurs, the last two bytes (which are defined as a data field) are ignored. 4 IE Specifies the enable/disable setting for interrupt requests. 0: Interrupt requests disabled 1: Interrupt requests enabled Cautions 1. An interrupt request is generated when interrupts are enabled under the following conditions. * * * * When a message is transmitted from the transmit message buffer When a message is received by the receive message buffer When a remote frame is transmitted from the receive message buffer When a remote frame is received by the transmit message buffer when the auto acknowledge function has not been set (RMDE0 bit = 0) 2. An interrupt request is not generated when interrupts are enabled under the following conditions. * When a remote frame is received by the transmit message buffer when the auto acknowledge function has been set (RMDE0 bit = 1) 3. An interrupt request is generated under the following conditions even if interrupts are disabled. * When a remote frame is received by the receive message buffer when the auto acknowledge function has not been set (RMDE0 bit = 0) 3 MOVR This is the flag that indicates a message buffer overwrite. 0: Overwrite does not occur after DN bit is cleared 1: Overwrite occurs at least once after DN bit is cleared Caution An overwrite of the message buffer occurs when the CAN module writes new data to the message buffer or when the DN bit has already been set (to 1). The MOVR bit is updated each time new data is stored in the message buffer. 0 RTR Specifies frame type. 0: Data frame transmit/receive 1: Remote frame transmit/receive Caution When the RTR bit has been set (to 1) for a transmit message, a remote frame is transmitted instead of a data frame. Remark DN: Bit 2 of M_STATn register (see 11.10 (8) CAN message status registers 00 to 31 (M_STAT00 to M_STAT31)) 548 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER Table 11-18. Addresses of M_CTRLn (n = 00 to 31) Register Name M_CTRL00 M_CTRL01 M_CTRL02 M_CTRL03 M_CTRL04 M_CTRL05 M_CTRL06 M_CTRL07 M_CTRL08 M_CTRL09 M_CTRL10 M_CTRL11 M_CTRL12 M_CTRL13 M_CTRL14 M_CTRL15 Address Note (m = 2, 6, A, E) Register Name M_CTRL16 M_CTRL17 M_CTRL18 M_CTRL19 M_CTRL20 M_CTRL21 M_CTRL22 M_CTRL23 M_CTRL24 M_CTRL25 M_CTRL26 M_CTRL27 M_CTRL28 M_CTRL29 M_CTRL30 M_CTRL31 Address Note (m = 2, 6, A, E) xxxxm805H xxxxm825H xxxxm845H xxxxm865H xxxxm885H xxxxm8A5H xxxxm8C5H xxxxm8E5H xxxxm905H xxxxm925H xxxxm945H xxxxm965H xxxxm985H xxxxm9A5H xxxxm9C5H xxxxm9E5H xxxxmA05H xxxxmA25H xxxxmA45H xxxxmA65H xxxxmA85H xxxxmAA5H xxxxmAC5H xxxxmAE5H xxxxmB05H xxxxmB25H xxxxmB45H xxxxmB65H xxxxmB85H xxxxmBA5H xxxxmBC5H xxxxmBE5H Note CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. User's Manual U14492EJ5V0UD 549 CHAPTER 11 FCAN CONTROLLER (4) CAN message time stamp registers 00 to 31 (M_TIME00 to M_TIME31) The M_TIMEn register is the register where the time stamp counter value is written upon completion of data reception (n = 00 to 31). These registers can be read/written in 16-bit units. 15 M_TIMEn (n = 00 to 31) TS 15 14 TS 14 13 TS 13 12 TS 12 11 TS 11 10 TS 10 9 TS 9 8 TS 8 7 TS 7 6 TS 6 5 TS 5 4 TS 4 3 TS 3 2 TS 2 1 TS 1 0 Address Initial value TS See Table 11-19 Undefined 0 Bit position 15 to 0 Bit name TS15 to TS0 Indicates the time stamp counter value. Function Caution When a data frame or remote frame is received in the receive message buffer, if the new data is stored in the message buffer, a 16-bit time tag (time stamp counter value) is stored in the M_TIMEn register only when the MT2 to MT0 bits of the M_CONFn register are set to value other than "000" or "110" (receive message). This time tag is set according to the FCAN's time stamp setting, which is either the time stamp counter value that was captured when the SOF was sent via the bus or the value captured when the CAN module writes data to the message buffer. Table 11-19. Addresses of M_TIMEn (n = 00 to 31) Register Name M_TIME00 M_TIME01 M_TIME02 M_TIME03 M_TIME04 M_TIME05 M_TIME06 M_TIME07 M_TIME08 M_TIME09 M_TIME10 M_TIME11 M_TIME12 M_TIME13 M_TIME14 M_TIME15 Address Note (m = 2, 6, A, E) Register Name M_TIME16 M_TIME17 M_TIME18 M_TIME19 M_TIME20 M_TIME21 M_TIME22 M_TIME23 M_TIME24 M_TIME25 M_TIME26 M_TIME27 M_TIME28 M_TIME29 M_TIME30 M_TIME31 Address Note (m = 2, 6, A, E) xxxxm806H xxxxm826H xxxxm846H xxxxm866H xxxxm886H xxxxm8A6H xxxxm8C6H xxxxm8E6H xxxxm906H xxxxm926H xxxxm946H xxxxm966H xxxxm986H xxxxm9A6H xxxxm9C6H xxxxm9E6H xxxxmA06H xxxxmA26H xxxxmA46H xxxxmA66H xxxxmA86H xxxxmAA6H xxxxmAC6H xxxxmAE6H xxxxmB06H xxxxmB26H xxxxmB46H xxxxmB66H xxxxmB86H xxxxmBA6H xxxxmBC6H xxxxmBE6H Note CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. 550 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (5) CAN message data registers n0 to n7 (M_DATAn0 to M_DATAn7) (n = 00 to 31) The M_DATAnx registers are areas where up to 8 bytes of transmit or receive data is stored (n = 00 to 31, x = 0 to 7). These registers can be read/written in 8-bit units. 7 M_DATAn0 (n = 00 to 31) M_DATAn1 (n = 00 to 31) M_DATAn2 (n = 00 to 31) M_DATAn3 (n = 00 to 31) M_DATAn4 (n = 00 to 31) M_DATAn5 (n = 00 to 31) M_DATAn6 (n = 00 to 31) M_DATAn7 (n = 00 to 31) D0_7 7 D1_7 7 D2_7 7 D3_7 7 D4_7 7 D5_7 7 D6_7 7 D7_7 6 D0_6 6 D1_6 6 D2_6 6 D3_6 6 D4_6 6 D5_6 6 D6_6 6 D7_6 5 D0_5 5 D1_5 5 D2_5 5 D3_5 5 D4_5 5 D5_5 5 D6_5 5 D7_5 4 D0_4 4 D1_4 4 D2_4 4 D3_4 4 D4_4 4 D5_4 4 D6_4 4 D7_4 3 D0_3 3 D1_3 3 D2_3 3 D3_3 3 D4_3 3 D5_3 3 D6_3 3 D7_3 2 D0_2 2 D1_2 2 D2_2 2 D3_2 2 D4_2 2 D5_2 2 D6_2 2 D7_2 1 D0_1 1 D1_1 1 D2_1 1 D3_1 1 D4_1 1 D5_1 1 D6_1 1 D7_1 0 D0_0 0 D1_0 0 D2_0 0 D3_0 0 D4_0 0 D5_0 0 D6_0 0 D7_0 Address Initial value See Table 11-20 Undefined Address Initial value See Table 11-20 Undefined Address Initial value See Table 11-20 Undefined Address Initial value See Table 11-20 Undefined Address Initial value See Table 11-20 Undefined Address Initial value See Table 11-20 Undefined Address Initial value See Table 11-20 Undefined Address Initial value See Table 11-20 Undefined Bit position 7 to 0 Bit name D7_7 to D0_0 Function Indicates the contents of the message data. Cautions 1. The M_DATAn0 to M_DATAn7 registers are fields used to hold receive data and transmit data. When data is transmitted, the number of messages defined by the DLC3 to DLC0 bits in the M_DLCn register are transmitted via the CAN bus. 2. When the M_CTRLn register's ATS bit has been set (to 1) and the value of the DLC3 to DLC0 bits in the M_DLCn register is at least two bytes, the last two bytes that are sent normally via the CAN bus are ignored and the time stamp value is sent. 3. When a new message is received, all data fields are updated, even when the value of the DLC3 to DLC0 bits in the M_DLCn register is less than 8 bytes. The values of data bytes that have not been received may be updated, but they are ignored. Remark n = 00 to 31 User's Manual U14492EJ5V0UD 551 CHAPTER 11 FCAN CONTROLLER Table 11-20. Addresses of M_DATAnx (n = 00 to 31, x = 0 to 7) Register M_DATAn0Note M_DATAn1Note M_DATAn2Note M_DATAn3Note M_DATAn4Note M_DATAn5Note M_DATAn6Note M_DATAn7Note Name (m = 2, 6, A, E) (m = 2, 6, A, E) (m = 2, 6, A, E) (m = 2, 6, A, E) (m = 2, 6, A, E) (m = 2, 6, A, E) (m = 2, 6, A, E) (m = 2, 6, A, E) 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 xxxxm808H xxxxm828H xxxxm848H xxxxm868H xxxxm888H xxxxm8A8H xxxxm8C8H xxxxm8E8H xxxxm908H xxxxm928H xxxxm948H xxxxm968H xxxxm988H xxxxm9A8H xxxxm9C8H xxxxm9E8H xxxxmA08H xxxxmA28H xxxxmA48H xxxxmA68H xxxxmA88H xxxxmAA8H xxxxmAC8H xxxxmAE8H xxxxmB08H xxxxmB28H xxxxmB48H xxxxmB68H xxxxmB88H xxxxmBA8H xxxxmBC8H xxxxmBE8H xxxxm809H xxxxm829H xxxxm849H xxxxm869H xxxxm889H xxxxm8A9H xxxxm8C9H xxxxm8E9H xxxxm909H xxxxm929H xxxxm949H xxxxm969H xxxxm989H xxxxm9A9H xxxxm9C9H xxxxm9E9H xxxxmA09H xxxxmA29H xxxxmA49H xxxxmA69H xxxxmA89H xxxxmAA9H xxxxmAC9H xxxxmAE9H xxxxmB09H xxxxmB29H xxxxmB49H xxxxmB69H xxxxmB89H xxxxmBA9H xxxxmBC9H xxxxmBE9H xxxxm80AH xxxxm82AH xxxxm84AH xxxxm86AH xxxxm88AH xxxxm8AAH xxxxm8CAH xxxxm8EAH xxxxm90AH xxxxm92AH xxxxm94AH xxxxm96AH xxxxm98AH xxxxm9AAH xxxxm9CAH xxxxm9EAH xxxxmA0AH xxxxmA2AH xxxxmA4AH xxxxmA6AH xxxxmA8AH xxxxmAAAH xxxxmACAH xxxxmAEAH xxxxmB0AH xxxxmB2AH xxxxmB4AH xxxxmB6AH xxxxmB8AH xxxxmBAAH xxxxmBCAH xxxxmBEAH xxxxm80BH xxxxm82BH xxxxm84BH xxxxm86BH xxxxm88BH xxxxm8ABH xxxxm8CBH xxxxm8EBH xxxxm90BH xxxxm92BH xxxxm94BH xxxxm96BH xxxxm98BH xxxxm9ABH xxxxm9CBH xxxxm9EBH xxxxmA0BH xxxxmA2BH xxxxmA4BH xxxxmA6BH xxxxmA8BH xxxxmAABH xxxxmACBH xxxxmAEBH xxxxmB0BH xxxxmB2BH xxxxmB4BH xxxxmB6BH xxxxmB8BH xxxxmBABH xxxxmBCBH xxxxmBEBH xxxxm80CH xxxxm82CH xxxxm84CH xxxxm86CH xxxxm88CH xxxxm8ACH xxxxm8CCH xxxxm8ECH xxxxm90CH xxxxm92CH xxxxm94CH xxxxm96CH xxxxm98CH xxxxm9ACH xxxxm9CCH xxxxm9ECH xxxxmA0CH xxxxmA2CH xxxxmA4CH xxxxmA6CH xxxxmA8CH xxxxmAACH xxxxmACCH xxxxmAECH xxxxmB0CH xxxxmB2CH xxxxmB4CH xxxxmB6CH xxxxmB8CH xxxxmBACH xxxxmBCCH xxxxmBECH xxxxm80DH xxxxm82DH xxxxm84DH xxxxm86DH xxxxm88DH xxxxm8ADH xxxxm8CDH xxxxm8EDH xxxxm90DH xxxxm92DH xxxxm94DH xxxxm96DH xxxxm98DH xxxxm9ADH xxxxm9CDH xxxxm9EDH xxxxmA0DH xxxxmA2DH xxxxmA4DH xxxxmA6DH xxxxmA8DH xxxxmAADH xxxxmACDH xxxxmAEDH xxxxmB0DH xxxxmB2DH xxxxmB4DH xxxxmB6DH xxxxmB8DH xxxxmBADH xxxxmBCDH xxxxmBEDH xxxxm80EH xxxxm82EH xxxxm84EH xxxxm86EH xxxxm88EH xxxxm8AEH xxxxm8CEH xxxxm8EEH xxxxm90EH xxxxm92EH xxxxm94EH xxxxm96EH xxxxm98EH xxxxm9AEH xxxxm9CEH xxxxm9EEH xxxxmA0EH xxxxmA2EH xxxxmA4EH xxxxmA6EH xxxxmA8EH xxxxmAAEH xxxxmACEH xxxxmAEEH xxxxmB0EH xxxxmB2EH xxxxmB4EH xxxxmB6EH xxxxmB8EH xxxxmBAEH xxxxmBCEH xxxxmBEEH xxxxm80FH xxxxm82FH xxxxm84FH xxxxm86FH xxxxm88FH xxxxm8AFH xxxxm8CFH xxxxm8EFH xxxxm90FH xxxxm92FH xxxxm94FH xxxxm96FH xxxxm98FH xxxxm9AFH xxxxm9CFH xxxxm9EFH xxxxmA0FH xxxxmA2FH xxxxmA4FH xxxxmA6FH xxxxmA8FH xxxxmAAFH xxxxmACFH xxxxmAEFH xxxxmB0FH xxxxmB2FH xxxxmB4FH xxxxmB6FH xxxxmB8FH xxxxmBAFH xxxxmBCFH xxxxmBEFH n Note CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. 552 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (6) CAN message ID registers L00 to L31 and H00 to H31 (M_IDL00 to M_IDL31 and M_IDH00 to M_IDH31) The M_IDLn and M_IDHn registers are areas used to set identifiers (n = 00 to 31). These registers can be read/written in 16-bit units. When in standard format mode, any data can be stored in the following areas. Bits ID17 to ID10: First byte of receive dataNote is stored. Bits ID9 to ID2: Bits ID1, ID0: Second byte of receive dataNote is stored. Third byte (higher two bits) of receive dataNote is stored. Note See 11.10 (5) CAN message data registers n0 to n7 (M_DATAn0 to M_DATAn7) (n = 00 to 31). 15 M_IDHn IDE (n = 00 to 31) 14 0 13 0 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID19 ID18 ID17 ID16 See Table 11-22 Undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value M_IDLn ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 See Table 11-21 Undefined (n = 00 to 31) Bit position 15 (M_IDHn) Bit name IDE (M_IDHn) Specifies format setting mode. Function 0: Standard format mode (ID28 to ID18: 11 bits) 1: Extended format mode (ID28 to ID0: 29 bits) Remark n = 00 to 31 User's Manual U14492EJ5V0UD 553 CHAPTER 11 FCAN CONTROLLER Table 11-21. Addresses of M_IDLn (n = 00 to 31) Register Name M_IDL00 M_IDL01 M_IDL02 M_IDL03 M_IDL04 M_IDL05 M_IDL06 M_IDL07 M_IDL08 M_IDL09 M_IDL10 M_IDL11 M_IDL12 M_IDL13 M_IDL14 M_IDL15 Address Note (m = 2, 6, A, E) Register Name M_IDL16 M_IDL17 M_IDL18 M_IDL19 M_IDL20 M_IDL21 M_IDL22 M_IDL23 M_IDL24 M_IDL25 M_IDL26 M_IDL27 M_IDL28 M_IDL29 M_IDL30 M_IDL31 Address Note (m = 2, 6, A, E) xxxxm810H xxxxm830H xxxxm850H xxxxm870H xxxxm890H xxxxm8B0H xxxxm8D0H xxxxm8F0H xxxxm910H xxxxm930H xxxxm950H xxxxm970H xxxxm990H xxxxm9B0H xxxxm9D0H xxxxm9F0H xxxxmA10H xxxxmA30H xxxxmA50H xxxxmA70H xxxxmA90H xxxxmAB0H xxxxmAD0H xxxxmAF0H xxxxmB10H xxxxmB30H xxxxmB50H xxxxmB70H xxxxmB90H xxxxmBB0H xxxxmBD0H xxxxmBF0H Note CAN message buffer registers can be allocated to the addresses xxxx as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. Table 11-22. Addresses of M_IDHn (n = 00 to 31) Register Name M_IDH00 M_IDH01 M_IDH02 M_IDH03 M_IDH04 M_IDH05 M_IDH06 M_IDH07 M_IDH08 M_IDH09 M_IDH10 M_IDH11 M_IDH12 M_IDH13 M_IDH14 M_IDH15 Address Note (m = 2, 6, A, E) Register Name M_IDH16 M_IDH17 M_IDH18 M_IDH19 M_IDH20 M_IDH21 M_IDH22 M_IDH23 M_IDH24 M_IDH25 M_IDH26 M_IDH27 M_IDH28 M_IDH29 M_IDH30 M_IDH31 Address Note (m = 2, 6, A, E) xxxxm812H xxxxm832H xxxxm852H xxxxm872H xxxxm892H xxxxm8B2H xxxxm8D2H xxxxm8F2H xxxxm912H xxxxm932H xxxxm952H xxxxm972H xxxxm992H xxxxm9B2H xxxxm9D2H xxxxm9F2H xxxxmA12H xxxxmA32H xxxxmA52H xxxxmA72H xxxxmA92H xxxxmAB2H xxxxmAD2H xxxxmAF2H xxxxmB12H xxxxmB32H xxxxmB52H xxxxmB72H xxxxmB92H xxxxmBB2H xxxxmBD2H xxxxmBF2H Note CAN message buffer registers can be allocated to the addresses xxxx as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. 554 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (7) CAN message configuration registers 00 to 31 (M_CONF00 to M_CONF31) The M_CONFn register is used to set the message buffer type and mask (n = 00 to 31). These registers can be read/written in 8-bit units. 7 M_CONFn (n = 00 to 31) 0 6 0 5 MT2 4 MT1 3 MT0 2 0 1 0 0 MA Address Initial value See Table 11-23 Undefined Bit position 5 to 3 Bit name MT2 to MT0 Function Specifies message type and mask setting. MT2 0 0 0 0 1 1 1 1 MT1 0 0 1 1 0 0 1 1 MT0 0 1 0 1 0 1 0 1 Transmit message Operation Receive message (no mask setting) Receive message (mask 0 is set) Receive message (mask 1 is set) Receive message (mask 2 is set) Receive message (mask 3 is set) Setting prohibited Receive message (used in diagnostic processing mode) When bits MT2 to MT0 have been set as "111", processing can be performed only when the FCAN has been set to diagnostic processing mode. In such cases, all messages received are stored regardless of the following conditions. * Storage to other message buffer * Identifier type (standard frame or extended frame) * Data frame or remote frame 0 MA Specifies message buffer's address. MA 0 1 Message buffer is not used Used as message buffer Operation Caution When the MA bit has been set to 0, message buffer area is used for application RAM or for event processing as a temporary buffer. User's Manual U14492EJ5V0UD 555 CHAPTER 11 FCAN CONTROLLER Table 11-23. Addresses of M_CONFn (n = 00 to 31) Register Name M_CONF00 M_CONF01 M_CONF02 M_CONF03 M_CONF04 M_CONF05 M_CONF06 M_CONF07 M_CONF08 M_CONF09 M_CONF10 M_CONF11 M_CONF12 M_CONF13 M_CONF14 M_CONF15 Address Note (m = 2, 6, A, E) Register Name M_CONF16 M_CONF17 M_CONF18 M_CONF19 M_CONF20 M_CONF21 M_CONF22 M_CONF23 M_CONF24 M_CONF25 M_CONF26 M_CONF27 M_CONF28 M_CONF29 M_CONF30 M_CONF31 Address Note (m = 2, 6, A, E) xxxxm814H xxxxm834H xxxxm854H xxxxm874H xxxxm894H xxxxm8B4H xxxxm8D4H xxxxm8F4H xxxxm914H xxxxm934H xxxxm954H xxxxm974H xxxxm994H xxxxm9B4H xxxxm9D4H xxxxm9F4H xxxxmA14H xxxxmA34H xxxxmA54H xxxxmA74H xxxxmA94H xxxxmAB4H xxxxmAD4H xxxxmAF4H xxxxmB14H xxxxmB34H xxxxmB54H xxxxmB74H xxxxmB94H xxxxmBB4H xxxxmBD4H xxxxmBF4H Note CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. 556 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (8) CAN message status registers 00 to 31 (M_STAT00 to M_STAT31) The M_STATn register indicates the transmit/receive status information of each message buffer (n = 00 to 31). These registers are read-only, in 8-bit units. Cautions 1. Writing directly to M_STATn register cannot be performed. Writing must be performed using CAN status set/clear register n (SC_STATn). 2. Messages are transmitted only when the M_STATn register's TRQ and RDY bits have been set (to 1). 7 M_STATn (n = 00 to 31) 0 6 0 5 0 4 0 3 RFU Note 1 2 DN 1 TRQ 0 RDY Note 2 Address Initial value See Table 11-24 Undefined Bit position 2 Bit name DN This is the message update flag. Function 0: No message was received after DN bit was cleared. 1: At least one message was received after DN bit was cleared. * When the DN bit has been set (to 1) by the transmit message buffer, it indicates that the message buffer has received a remote frame. When this message is sent, the DN bit is automatically cleared (to 0). * When a frame is again received in the receive message buffer for which the DN bit has been set (to 1), an overwrite condition occurs and the M_CTRLn register's MOVR bit is set (to 1) (n = 00 to 31). 1 TRQ This is the transmit request flag. 0: Message transmission disabled 1: Message transmission enabled * A transmit request is processed as a CAN module only when the RDY bit is set to 1. * A remote frame is transmitted for the receive message buffer in which the TRQ bit is set to 1. 0 RDY This is the transmit message ready flag. 0: Message is not ready. 1: Message is ready. * A receive operation is performed only for a message buffer in which the RDY bit is set to 1 during reception. * A transmit operation is performed only for a message buffer in which the RDY bit is set to 1 and the TRQ bit is set to 1 during transmission. Notes 1. 2. RFU (Reserved for Future Use) indicates a reserved bit. 0 or 1 is read from this bit regardless of the message buffer setting. The FCAN controller incorporated in the V850E/IA1 can perform reception even if the RDY bit is not set. However, in products other than the V850E/IA1, the RDY bit must be set for reception. In order to maintain software compatibility, be sure to set the RDY bit even for the FCAN controller of the V850E/IA1 prior to reception. User's Manual U14492EJ5V0UD 557 CHAPTER 11 FCAN CONTROLLER Table 11-24. Addresses of M_STATn (n = 00 to 31) Register Name M_STAT00 M_STAT01 M_STAT02 M_STAT03 M_STAT04 M_STAT05 M_STAT06 M_STAT07 M_STAT08 M_STAT09 M_STAT10 M_STAT11 M_STAT12 M_STAT13 M_STAT14 M_STAT15 Address Note (m = 2, 6, A, E) Register Name M_STAT16 M_STAT17 M_STAT18 M_STAT19 M_STAT20 M_STAT21 M_STAT22 M_STAT23 M_STAT24 M_STAT25 M_STAT26 M_STAT27 M_STAT28 M_STAT29 M_STAT30 M_STAT31 Address Note (m = 2, 6, A, E) xxxxm815H xxxxm835H xxxxm855H xxxxm875H xxxxm895H xxxxm8B5H xxxxm8D5H xxxxm8F5H xxxxm915H xxxxm935H xxxxm955H xxxxm975H xxxxm995H xxxxm9B5H xxxxm9D5H xxxxm9F5H xxxxmA15H xxxxmA35H xxxxmA55H xxxxmA75H xxxxmA95H xxxxmAB5H xxxxmAD5H xxxxmAF5H xxxxmB15H xxxxmB35H xxxxmB55H xxxxmB75H xxxxmB95H xxxxmBB5H xxxxmBD5H xxxxmBF5H Note CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. 558 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (9) CAN status set/clear registers 00 to 31 (SC_STAT00 to SC_STAT31) The SC_STATn register is used to set/clear the transmit/receive status information (n = 00 to 31). These registers are write-only, in 16-bit units. 15 SC_STATn (n = 00 to 31) 0 14 0 13 0 12 0 11 0 10 set 9 set 8 set 7 0 6 0 5 0 4 0 3 0 2 1 0 Address Initial value 0000H clear clear clear See Table 11-25 DN TRQ RDY DN TRQ RDY Bit position 10, 2 Bit name set DN, clear DN set DN 0 1 clear DN 1 0 Function Specifies setting/clearing of the message update flag. Operation Cleared (DN bit cleared) Set (DN bit set) No change in DN bit value Other than above 9, 1 set TRQ, clear TRQ Specifies setting/clearing of the transmit request flag. set TRQ 0 1 clear TRQ 1 0 Cleared (TRQ bit cleared) Set (TRQ bit set) Operation Other than above No change in TRQ bit value 8, 0 set RDY, clear RDY Specifies setting of the message ready flag. set RDY 0 1 clear RDY 1 0 Cleared (RDY bit cleared) Set (RDY bit set) Operation Other than above No change in RDY bit value Remark DN: Bit 2 of CAN message status register n (M_STATn) TRQ: Bit 1 of CAN message status register n (M_STATn) RDY: Bit 0 of CAN message status register n (M_STATn) User's Manual U14492EJ5V0UD 559 CHAPTER 11 FCAN CONTROLLER Table 11-25. Addresses of SC_STATn (n = 00 to 31) Register Name SC_STAT00 SC_STAT01 SC_STAT02 SC_STAT03 SC_STAT04 SC_STAT05 SC_STAT06 SC_STAT07 SC_STAT08 SC_STAT09 SC_STAT10 SC_STAT11 SC_STAT12 SC_STAT13 SC_STAT14 SC_STAT15 Address Note (m = 2, 6, A, E) Register Name SC_STAT16 SC_STAT17 SC_STAT18 SC_STAT19 SC_STAT20 SC_STAT21 SC_STAT22 SC_STAT23 SC_STAT24 SC_STAT25 SC_STAT26 SC_STAT27 SC_STAT28 SC_STAT29 SC_STAT30 SC_STAT31 Address Note (m = 2, 6, A, E) xxxxm816H xxxxm836H xxxxm856H xxxxm876H xxxxm896H xxxxm8B6H xxxxm8D6H xxxxm8F6H xxxxm916H xxxxm936H xxxxm956H xxxxm976H xxxxm996H xxxxm9B6H xxxxm9D6H xxxxm9F6H xxxxmA16H xxxxmA36H xxxxmA56H xxxxmA76H xxxxmA96H xxxxmAB6H xxxxmAD6H xxxxmAF6H xxxxmB16H xxxxmB36H xxxxmB56H xxxxmB76H xxxxmB96H xxxxmBB6H xxxxmBD6H xxxxmBF6H Note CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. 560 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (10) CAN interrupt pending register (CCINTP) The CCINTP register is used to confirm the pending status of various interrupts. This register is read-only, in 16-bit units. 15 CCINTP 14 13 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 1 0 Address Initial value 0000H 0 INTMAC 0 CAN1 CAN1 CAN1 xxxxmC00H ERR REC TRX Note 1 Bit position 14 Bit name INTMAC Indicates an MAC error 0: Not pending 1: Pending Note 2 Function interrupt (GINT2, GINT1) is pending. 2 CAN1ERR Indicates a CAN access error interrupt (C1INT6 to C1INT2) is pending. 0: Not pending 1: Pending 1 CAN1REC Indicates a CAN receive completion interrupt (C1INT1) is pending. 0: Not pending 1: Pending 0 CAN1TRX Indicates a CAN transmit completion interrupt (C1INT0) is pending. 0: Not pending 1: Pending Notes 1. xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, A, E 2. MAC (Memory Access Control) errors are errors that are set only when an interrupt source has occurred for the CAN global interrupt pending register (CGINTP). Remark GINT3 to GINT1: Bits 3 to 1 of the CAN global interrupt pending register (CGINTP) C1INT6 to C1INT0: Bits 6 to 0 of the CAN1 interrupt pending register (C1INTP) User's Manual U14492EJ5V0UD 561 CHAPTER 11 FCAN CONTROLLER (11) CAN global interrupt pending register (CGINTP) The CGINTP register is used to confirm the pending status of MAC error interrupts. This register can be read/written in 8-bit units. Cautions 1. When "1" is written to a bit in the CGINTP register, that bit is cleared (to 0). When "0" is written to it, the bit's value does not change. 2. An interrupt is generated when the corresponding interrupt request is enabled and when no interrupt pending bit has been set (to 1) for a new interrupt. The correct or incorrect timing of setting the interrupt pending bit (to 1) is controlled by an interrupt service routine. The earlier that the interrupt service routine clears the interrupt pending bit (to 0), the more quickly the interrupt is generated without losing any new interrupts of the same type. The interrupt pending bit can be set (to 1) only when the interrupt enable bit has been set (to 1). However, the interrupt pending bit is not automatically cleared (to 0) just because the interrupt enable bit has been cleared (to 0). Use software processing to clear the interrupt pending bit (to 0). Remark For details of invalid write access error interrupts and unavailable memory address access error interrupts, see 11.14.2 Interrupts that are generated for global CAN interface. 7 CGINTP 0 6 0 5 0 4 0 3 GINT3 2 GINT2 1 GINT1 0 0 Address xxxxmC02H Note Initial value 00H Bit position 3 Bit name GINT3 Function Indicates that a wake-up interrupt from CAN sleep mode with stopped clock supply to FCAN is pending. 0: Not pending 1: Pending 2 GINT2 Indicates that an invalid write access error interrupt is pending. 0: Not pending 1: Pending 1 GINT1 Indicates that an unavailable memory address access error interrupt is pending. 0: Not pending 1: Pending Note xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, A, E 562 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (12) CAN1 interrupt pending register (C1INTP) The C1INTP register is used to confirm the pending status of interrupts issued to FCAN. This register can be read/written in 8-bit units. Cautions 1. When "1" is written to a bit in the C1INTP register, that bit is cleared (to 0). When "0" is written to it, the bit's value does not change. 2. An interrupt is generated when the corresponding interrupt request is enabled and when no interrupt pending bit has been set (to 1) for a new interrupt. The correct or incorrect timing of setting the interrupt pending bit (to 1) is controlled by an interrupt service routine. The earlier that the interrupt service routine clears the interrupt pending bit (to 0), the more quickly the interrupt is generated without losing any new interrupts of the same type. The interrupt pending bit can be set (to 1) only when the interrupt enable bit has been set (to 1). However, the interrupt pending bit is not automatically cleared (to 0) just because the interrupt enable bit has been cleared (to 0). Use software processing to clear the interrupt pending bit (to 0). 7 C1INTP 0 6 C1INT6 5 C1INT5 4 C1INT4 3 C1INT3 2 C1INT2 1 C1INT1 0 C1INT0 Address xxxxmC04HNote Initial value 00H Bit position 6 Bit name C1INT6 Function Indicates pending status of the CAN error interrupt. 0: Not pending 1: Pending 5 C1INT5 Indicates pending status of the CAN bus error interrupt. 0: Not pending 1: Pending 4 C1INT4 Indicates pending status of the wake-up interrupt from CAN sleep mode. 0: Not pending 1: Pending 3 C1INT3 Indicates pending status of the CAN receive error passive status interrupt. 0: Not pending 1: Pending 2 C1INT2 Indicates pending status of the CAN transmit error passive or bus-off status interrupt. 0: Not pending 1: Pending 1 C1INT1 Indicates pending status of the CAN receive completion interrupt. 0: Not pending 1: Pending 0 C1INT0 Indicates pending status of the CAN transmit completion interrupt. 0: Not pending 1: Pending Note xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, A, E User's Manual U14492EJ5V0UD 563 CHAPTER 11 FCAN CONTROLLER (13) CAN stop register (CSTOP) The CSTOP register controls clock supply to the entire CAN system. This register can be read/written in 16-bit units. Cautions 1. Be sure to set the CSTP bit (to 1) if the FCAN function will not be used. 2. When the CSTP bit has been set (to 1), access to FCAN registers other than the CSTOP register is prohibited. Access to FCAN (other than the CSTOP register) is possible only when the CSTP bit has not been set (to 1). 3. When a change occurs on the CAN bus via a CSTP bit setting while the clock supply to the CPU or peripheral functions is stopped, CPU can be woken up. 4. If the CAN main clock (fMEM1) is stopped in other than CAN sleep mode, first set the CAN module to initial mode (INIT bit of C1CTRL register = 1), clear (0) the GOM bit of the CGST register, and then set (1) the CSTP bit. 15 CSTOP CSTP 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Address xxxxmC0CH Note Initial value 0000H Bit position 15 Bit name CSTP Controls clock supply to FCAN. Function 0: FCAN is operating (supplies clock to FCAN) 1: FCAN is stopped (access to FCAN is disabled) Note xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, A, E 564 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (14) CAN global status register (CGST) The CGST register indicates global status information. This register can be read/written in 16-bit units. Cautions 1. Both bitwise writing and direct writing to the CGST register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 11.9 Cautions on Bit Set/Clear Function. 2. When writing to the CGST register, set or clear bits according to the register configuration shown in part (b) Write. (1/3) 15 CGST (Read) 0 14 0 13 0 12 0 11 0 10 0 9 0 8 1 7 MERR 6 0 5 0 4 0 3 2 1 0 Address xxxxmC10HNote Initial value 0100H EFSD TSM 0 GOM 15 CGST (Write) 0 14 0 13 0 12 0 11 set 10 set 9 0 8 7 6 0 5 0 4 0 3 2 1 0 0 clear GOM set clear GOM MERR clear clear EFSD TSM EFSD TSM (a) Read (1/2) Bit position 7 Bit name MERR Function This is the status flag that indicates an MAC error. 0: Error has not occurred after the MERR bit has been cleared. 1: Error occurred at least once after the MERR bit was cleared. Caution MAC errors occur under the following conditions. * When invalid address is accessed * When access prohibited by MAC is performed * When the GOM bit is cleared (0) before the INIT bit of the C1CTRL register is set (1) 3 EFSD Indicates shutdown request. 0: Shutdown disabled 1: Shutdown enabled Caution Be sure to set the EFSD bit (to 1) before clearing the GOM bit (to 0) (needs to be accessed twice). The EFSD bit will be cleared (to 0) automatically when the CGST register is accessed again. Note xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, A, E User's Manual U14492EJ5V0UD 565 CHAPTER 11 FCAN CONTROLLER (2/3) (a) Read (2/2) Bit position 2 Bit name TSM Function Indicates the operation status of the time stamp counter 0: Time stamp counter is stopped 1: Time stamp counter is operating Note See 11.10 (17) CAN time stamp count register (CGTSC) 0 GOM Indicates the status of the global operation mode. 0: Access to CAN module register 1: Access to CAN module register Note 1 Note 1 Note . is prohibited is enabled Cautions 1. The GOM bit controls the method the memory is accessed by the MAC and CAN module operation state. * When GOM bit = 0 * All the CAN modules are reset. * Access to the CAN module register is prohibited (if accessed, a MAC error interrupt occurs) Note 2 . * Read/write access to the temporary buffer is enabled. * Access to the message buffer area is enabled. * When GOM bit = 1 * Access to the CAN module register is enabled a MAC error interrupt occurs). * Access to the message buffer area is enabled. 2. The GOM bit is cleared to 0 only when all the CAN modules are in the initial status (when the ISTAT bit of the C1CTRL register = 1). If one of the CAN modules is not in the initial status, the GOM bit remains set (1) even if it is cleared to 0. 3. To clear (0) the GOM bit, first set (1) the INIT bit of the C1CTRL register, and then set (1) the EFSD bit. Do not manipulate the GOM bit and EFSD bit simultaneously. Note 3 . * Access to the temporary buffer is prohibited (if access is attempted, Notes 1. 2. Register with a name starting with "C1" The CGCS register can be accessed. Write accessing the CGMSS register is prohibited. If the CGMSS register is write accessed, the wrong search result is reflected in the CGMSR register. 3. Write-accessing the CGCS register is prohibited. Write-accessing the CGMSS register is possible. 566 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (3/3) (b) Write Bit position 11, 3 Bit name set EFSD, clear EFSD Sets/clears the EFSD bit. set EFSD clear EFSD 0 1 1 0 EFSD bit cleared (to 0) EFSD bit set (to 1) No change in EFSD bit value Operation Function Other than above Sets/clears the TSM bit. set TSM 0 1 clear TSM 1 0 10, 2 set TSM, clear TSM Operation TSM bit cleared (to 0) TSM bit set (to 1) No change in TSM bit value Other than above Sets/clears the GOM bit. set GOM clear GOM 0 1 1 0 8, 0 set GOM, clear GOM Operation GOM bit cleared (to 0) GOM bit set (to 1) No change in GOM bit value Other than above 7 clear MERR Clears the MERR bit. 0: No change in the MERR bit 1: MERR bit cleared (to 0) User's Manual U14492EJ5V0UD 567 CHAPTER 11 FCAN CONTROLLER (15) CAN global interrupt enable register (CGIE) The CGIE register is used to issue interrupt requests for global interrupts. This register can be read/written in 16-bit units. Cautions 1. Both bitwise writing and direct writing to the CGIE register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 11.9 Cautions on Bit Set/Clear Function. 2. When writing to the CGIE register, set or clear bits according to the register configuration during a write operation. 15 CGIE (Read) 0 14 0 13 0 12 0 11 1 10 0 9 1 8 0 7 0 6 0 5 0 4 0 3 0 2 1 0 0 Address xxxxmC12H Note Initial value 0A00H G_IE2 G_IE1 15 CGIE (Write) 0 14 0 13 0 12 0 11 0 10 set 9 set 8 0 7 0 6 0 5 0 4 0 3 0 2 1 0 0 clear clear G_IE2 G_IE1 G_IE2 G_IE1 (a) Read Bit position 2 Bit name G_IE2 Function This is the invalid write access (to temporary buffer, etc.) interrupt enable flag. 0: Interrupt disabled 1: Interrupt enabled 1 G_IE1 This is the unavailable memory address access interrupt enable flag. 0: Interrupt disabled 1: Interrupt enabled (b) Write Bit position 10, 9, 2, 1 Bit name set G_IEn, clear G_IEn Sets/clears the G_IEn bit. Function set G_IEn 0 1 clear G_IEn 1 0 G_IEn bit cleared G_IEn bit set Setting of G_IEn Bit Other than above No change in G_IEn bit value Note xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, A, E Remark n = 1, 2 568 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (16) CAN main clock selection register (CGCS) The CGCS register is used to select the main clock. This register can be read/written in 16-bit units. Caution When the GOM bit of the CGST register is 1, write accessing the CGCS register is prohibited. (1/2) 15 CGCS 14 13 12 11 10 9 8 7 6 5 0 4 3 2 1 0 Address xxxxmC14H Note 3 Initial value 7F05H CGTS CGTS CGTS CGTS CGTS CGTS CGTS CGTS GTCS GTCS 7 6 5 4 3 2 1 0 1 0 0Note 1 MCP3 MCP2 MCP1 MCP0 Bit position 15 to 8 Bit name CGTS7 to CGTS0 Function Indicates global timer system clock (fGTS) (see Figure 11-26). n CGTS CGTS CGTS CGTS CGTS CGTS CGTS CGTS 7 6 5 4 3 2 1 0 System timer prescaler selection fGTS = fGTS1 /(n + 1) fGTS = fGTS1/1 fGTS = fGTS1/2 fGTS = fGTS1/(n + 1) 0 1 0 0 0 0 0 0 0 0 : 0 0 0 0 0 0 0 1 127 0 1 1 1 : 1 1 1 1 fGTS = fGTS1/128 (after reset) fGTS = fGTS1/(n + 1) 254 255 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 fGTS = fGTS1/255 fGTS = fGTS1/256 Note 3 The global timer system clock (fGTS) is the source clock for the time stamp counter is used for the time stamp function. that 7, 6 GTCS1, GTCS0 Specifies the global timer clock (fGTS1) (see Figure 11-26). GTCS1 0 0 1 1 GTCS0 0 1 0 1 fMEM/2 fMEM/4 fMEM/8 fMEM/16 Global timer clock selection (fGTS1) Notes 1. 2. When writing to this bit, always set it to 0. xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, A, E 3. Refer to 11.10 (17) CAN time stamp count register (CGTSC). User's Manual U14492EJ5V0UD 569 CHAPTER 11 FCAN CONTROLLER (2/2) Bit position 3 to 0 Bit name MCP3 to MCP0 n 0 1 2 MCP3 MCP2 MCP1 MCP0 0 0 0 0 0 0 0 0 1 0 1 0 Selection of clock to memory access controller (fMEM) fMEM1 fMEM1/2 fMEM1/3 : 14 15 1 1 1 1 1 1 0 1 fMEM1/15 fMEM1/16 Function Specifies the clock to memory access controller (fMEM) (see Figure 11-26). Once the values of the MCP3 to MCP0 bits are set after reset is released, do not change these values. 570 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER Figure 11-26. FCAN Clocks FCAN CAN main clock selection register (CGCS) CGTS7 CGTS6 CGTS5 CGTS4 CGTS3 CGTS2 CGTS1 CGTS0 GTCS1 GTCS0 MCP3 MCP2 MCP1 MCP0 fXX fXX/2 fXX/3 fXX/4 Selector fMEM1 Prescaler fMEM Global timer clock prescaler fGTS1 Global timer system clock fGTS Time stamp counter PRM04 fBTL Baud rate generator CAN1 synchronization control register (C1SYNC) Data bit time BTYPE BRP7Note BRP6Note BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 CAN1 bit rate prescaler register (C1BRP) Note Only when the TLM bit of the CAN1 bit rate prescaler register (C1BRP) is 1 Caution When using a 1 Mbps transfer rate for the CPU, input fMEM1 as a 16 MHz clock signal. If input at another frequency, subsequent operation is not guaranteed. (17) CAN time stamp count register (CGTSC) The CGTSC register indicates the contents of the time stamp counter. This register can be read at any time. This register can be written to only when clearing bits. The clear function writes 0 to all bits in the CGTSC register. This register is read-only, in 16-bit units. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address xxxxmC18HNote Initial value 0000H CGTSC TSC15 TSC14 TSC13 TSC12 TSC11 TSC10 TSC9 TSC8 TSC7 TSC6 TSC5 TSC4 TSC3 TSC2 TSC1 TSC0 Note xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, A, E User's Manual U14492EJ5V0UD 571 CHAPTER 11 FCAN CONTROLLER (18) CAN message search start/result register (CGMSS (during write)/CGMSR (during read)) The CGMSS/CGMSR register indicates the message search start/result status. Messages in the message buffer that match the specified search criteria can be searched quickly. These registers can be read/written in 16-bit units. Caution Execute a search by writing the CGMSS register only once. (1/2) 15 CGMSR (Read) 0 14 0 13 0 12 0 11 0 10 0 9 8 7 0 6 0 5 0 4 3 2 1 0 Address xxxxmC1AHNote Initial value 0000H MM AM MFND4 MFND3 MFND2 MFND1 MFND0 15 14 13 12 11 10 CGMSS (Write) CIDE 0 CTRQ CMSK CDN 0 9 0 8 SMNO 7 0 6 0 5 0 4 3 2 1 0 STRT4 STRT3 STRT2 STRT1 STRT0 (a) Read Bit position 9 Bit name MM Function Confirms multiple hits from message search. 0: No messages or only one message meets the search criteria 1: Several messages meet the search criteria If several message buffers that meet search criteria are detected, the MM bit is set (to 1). 8 AM Confirms hits from message search. 0: No messages meet the search criteria 1: At least one message meets the search criteria 4 to 0 MFND4 to MFND0 Indicates searched message number (0 to 31). When multiple message buffer numbers match as a result of a search (MM = 1), the return value of the MFND4 to MFND0 bits is the lowest message buffer number. When no message buffer numbers match as a result of a search (AM = 0), the return value of the MFND4 to MFND0 bits is the number of message buffers - 1. Note xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, A, E 572 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (2/2) (b) Write Bit position 15 Bit name CIDE Function Checks message identifier (ID) format flag. 0: Message identifier format flag not checked 1: Only message with standard format identifier checked 13 CTRQ Checks transmit request and message ready flag. 0: Transmit request and message ready flag not checked 1: Transmit request and message ready flag checked 12 CMSK Checks masked messages. 0: Masked messages not checked 1: Only masked messages checked 11 CDN Checks status of the DN flag of M_STATn register (n = 00 to 31). 0: Status of the DN flag of M_STATn register not checked 1: Status of the DN flag of M_STATn register checked 8 SMNO Sets search module. 0: No search module setting 1: CAN module set as search target 4 to 0 STRT4 to STRT0 Indicates message search start position. 0 to 31: Message search start position (message number) Search starts from the message number defined by bits STRT4 to STRT0. Search continues until it reaches the message buffer having the highest number among the usable message buffers. If the search results include several message buffer numbers among the matching messages, the message buffer with the lowest message buffer number is selected. To fetch the next message buffer number without changing the search criteria, "(MFND4 to MFND0) + 1" must be set as the values of bits STRT4 to STRT0. User's Manual U14492EJ5V0UD 573 CHAPTER 11 FCAN CONTROLLER (19) CAN1 address mask a registers L and H (C1MASKLa and C1MASKHa) The C1MASKLa and C1MASKHa registers are used to extend the number of receivable messages by masking part of the message's identifier (ID) and then ignoring the masked parts (a = 0 to 3). These registers can be read/written in 16-bit units. Cautions 1. When the receive message buffer is linked to the C1MASKLa and C1MASKHa registers, regardless of whether the ID in the receive message buffer is a standard ID (11 bits) or extended ID (29 bits), set all the 32-bit values of the C1MASKLa and C1MASKHa registers (a = 0 to 3). 2. When the C1MASKLa and C1MASKHa registers are linked to a message buffer for standard ID, the lower 18 bits of the data field in the data frame are also automatically compared. Therefore, if it is not necessary to compare the lower 18 bits (i.e., to mask the lower 18 bits), set the CMID17 to CMID0 bits to 1 (a = 0 to 3). The standard ID and extended ID can use the same mask. 15 C1MASKHa (a = 0 to 3) CMIDE 14 0 13 0 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value CMID CMID CMID CMID CMID CMID CMID CMID CMID CMID CMID CMID CMID See Table 11-26 Undefined 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value C1MASKLa CMID CMID CMID CMID CMID CMID CMID CMID CMID CMID CMID CMID CMID CMID CMID CMID See Table 11-26 Undefined (a = 0 to 3) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit position 15 (C1MASKHa) Bit name CMIDE Sets mask for identifier (ID) format. Function 0: ID format (standard or extended) checked 1: ID format (standard or extended) not checked When the CMIDE bit is set (1), the higher 11 bits of the ID are compared. The receive message and the ID format stored in a message buffer are not compared. 12 to 0 CMID28 to Sets mask for identifier (ID) bit. 0: ID bit in message buffer linked to bits CMID28 to CMID0 compared with received ID bit 1: ID bit in message buffer linked to bits CMID28 to CMID0 not compared (ID bit masked) with received ID bit (C1MASKHa) CMID16 15 to 0 (C1MASKHa) (C1MASKLa) CMID15 to CMID0 (C1MASKLa) Remark n = 0 to 3 574 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER Table 11-26. Addresses of C1MASKLa and C1MASKHa (a = 0 to 3) Register Name C1MASKL0 C1MASKH0 C1MASKL1 C1MASKH1 C1MASKL2 C1MASKH2 C1MASKL3 C1MASKH3 Address Note (m = 2, 6, A, E) xxxxmC40H xxxxmC42H xxxxmC44H xxxxmC46H xxxxmC48H xxxxmC4AH xxxxmC4CH xxxxmC4EH Note CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. User's Manual U14492EJ5V0UD 575 CHAPTER 11 FCAN CONTROLLER (20) CAN1 control register (C1CTRL) The C1CTRL register is used to control the operation of the CAN module. This register can be read/written in 16-bit units. Cautions 1. Both bitwise writing and direct writing to the C1CTRL register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 11.9 Cautions on Bit Set/Clear Function. 2. When writing to the C1CTRL register, set or clear bits according to the register configuration during a write operation. 3. When canceling CAN stop mode, CAN sleep mode must be canceled at the same time. (1/4) 15 C1CTRL (Read) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address xxxxmC50H Note Initial value 0101H TECS1 TECS0 RECS1 RECS0 BOFF TSTAT RSTAT ISTAT 0 DLEVR DLEVT OVM TMR STOP SLEEP INIT 15 C1CTRL (Write) 0 14 set 13 12 11 set 10 set 9 set 8 set 7 0 6 5 4 3 2 1 0 set set clear clear clear clear clear clear clear DLEVR DLEVT OVM TMR STOP SLEEP INIT DLEVR DLEVT OVM TMR STOP SLEEP INIT (a) Read (1/3) Bit position 15, 14 Bit name TECS1, TECS0 TECS1 0 0 1 1 TECS0 0 1 0 1 Status of transmit error counter Transmit error counter value < 96 Transmit error counter value = 96 to 127 (warning level) Not used Transmit error counter value 128 (error passive) Function This is the transmit error counter status flag. 13, 12 RECS1, RECS0 This is the receive error counter status flag. RECS1 0 0 1 1 RECS0 0 1 0 1 Status of receive error counter Receive error counter value < 96 Receive error counter value = 96 to 127 (warning level) Not used Receive error counter value 128 (error passive) Note xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, A, E 576 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (2/4) (a) Read (2/3) Bit position 11 Bit name BOFF This is the bus off status flag. 0: Transmit error counter < 256 (not bus off status) 1: Transmit error counter 256 (bus off status) 10 TSTAT This is the transmit status flag. 0: Transmission stopped status 1: Transmitting status 9 RSTAT This is the receive status flag. 0: Reception stopped status 1: Receiving status 8 ISTAT This is the initialization status flag. 0: Normal operating status 1: FCAN is stopped and initialized Cautions 1. The ISTAT bit is set (to 1) when the CAN protocol layer acknowledges the settings of the INIT and STOP bits. Also, this bit is automatically cleared (to 0) when the INIT and STOP bits are cleared (to 0). 2. In the initialization status, "recessive" is output to the CTXD pin. 3. The C1SYNC and C1BRP registers can be written only in initialization mode. 4. In the initialization status, the error counter (see 11.10 (23) CAN1 error count register (C1ERC)) is cleared (to 0) and the error status (bits TECS1, TECS0, RECS0, and RECS1) is reset. 6 DLEVR This is the dominant level control bit for receive pins. 0: A low level to a receive pin is acknowledged as dominant 1: A high level to a receive pin is acknowledged as dominant 5 DLEVT This is the dominant level control bit for transmit pins. 0: A low level is transmitted from a transmit pin as dominant 1: A high level is transmitted from a transmit pin as dominant 4 OVM This is the overwrite mode control bit. 0: New messages stored in message buffer in which DN bit of M_STATn register (n = 00 to 31) is set 1: New messages in message buffer in which DN bit is set are discarded. When the OVM bit = 1, the receive completion interrupt (INTCREC) is not generated even if new messages are received in the message buffer in which the DN bit is set. 3 TMR This is the time stamp control bit for reception. 0: Captures time stamp counter value when SOF is detected on CAN bus 1: Captures time stamp counter value when EOF is detected on CAN bus (a valid message is confirmed) 2 STOP This is the CAN stop mode control bit. 0: No CAN stop mode setting 1: CAN stop mode Function The CAN stop mode can be selected only when the CAN module is set to CAN sleep mode (the SLEEP bit is set (to 1)). CAN stop mode can be canceled only by the CPU (STOP bit cleared (to 0)). User's Manual U14492EJ5V0UD 577 CHAPTER 11 FCAN CONTROLLER (3/4) (a) Read (3/3) Bit position 1 Bit name SLEEP This is the CAN sleep mode control bit. 0: Normal operation mode 1: Switch to CAN sleep mode. Change in CAN bus performs wake-up. Cautions 1. CAN sleep mode can be set only when the CAN bus is in the idle state. 2. CAN sleep mode is canceled under the following conditions. * When the CPU has cleared the SLEEP bit (to 0) * When the CAN bus changes (only when CAN stop mode has not been set) 3. The WAKE bit (see 11.10 (21) CAN1 definition register (C1DEF)) can be set (to 1) only when CAN sleep mode is canceled by the change of the CAN bus, and an error interrupt occurs. 0 INIT This is the initialization request bit used to initialize the CAN module. 0: Normal operation mode 1: Initialization mode Cautions 1. Be sure to confirm that the CAN module has entered the initialization mode using the ISTAT bit (ISTAT bit = 1) after setting the INIT bit (to 1). When the ISTAT bit = 0, set the INIT bit (to 1) again. 2. If the INIT bit is set (to 1) when the CAN module is in the bus off status (BOFF bit = 1), the CAN module enters initialization mode (ISTAT bit = 1) after returning from the bus off status (BOFF bit = 0). Function (b) Write (1/2) Bit position 14, 6 Bit name Set DLEVR, clear DLEVR Sets/clears the DLEVR bit. set DLEVR 0 1 clear DLEVR 1 0 DLEVR bit cleared (to 0) DLEVR bit set (to 1) DLEVR bit not changed Operation Function Other than above 13, 5 Set DLEVT, clear DLEVT Sets/clears the DLEVT bit. set DLEVT 0 1 clear DLEVT 1 0 DLEVT bit cleared (to 0) DLEVT bit set (to 1) DLEVT bit not changed Operation Other than above 578 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (4/4) (b) Write (2/2) Bit position 12, 4 Bit name set OVM, clear OVM Sets/clears the OVM bit. set OVM 0 1 clear OVM 1 0 OVM bit cleared (to 0) OVM bit set (to 1) OVM bit not changed Operation Function Other than above 11, 3 set TMR, clear TMR Sets/clears the TMR bit. set TMR 0 1 clear TMR 1 0 TMR bit cleared (to 0) TMR bit set (to 1) TMR bit not changed Operation Other than above 10, 2 set STOP, clear STOP Sets/clears the STOP bit. set STOP 0 1 clear STOP 1 0 STOP bit cleared (to 0) STOP bit set (to 1) STOP bit not changed Operation Other than above 9, 1 set SLEEP, clear SLEEP Sets/clears the SLEEP bit. set SLEEP 0 1 clear SLEEP 1 0 SLEEP bit cleared (to 0) SLEEP bit set (to 1) SLEEP bit not changed Operation Other than above 8, 0 set INIT, clear INIT Sets/clears the INIT bit. set INIT 0 1 clear INIT 1 0 INIT bit cleared (to 0) INIT bit set (to 1) INIT bit not changed Operation Other than above User's Manual U14492EJ5V0UD 579 CHAPTER 11 FCAN CONTROLLER (21) CAN1 definition register (C1DEF) The C1DEF register is used to define the operation of the CAN module. This register can be read/written in 16-bit units. Cautions 1. Both bitwise writing and direct writing to the C1DEF register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 11.9 Cautions on Bit Set/Clear Function. 2. When writing to the C1DEF register, set or clear bits according to the register configuration during a write operation. (1/4) 15 C1DEF (Read) 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 6 5 4 3 2 1 0 Address xxxxmC52HNote Initial value 0000H DGM MOM SSHT PBB BERR VALID WAKE OVR 15 C1DEF (Write) set 14 set 13 12 11 0 10 0 9 0 8 0 7 6 5 4 3 2 1 0 set set clear clear clear clear clear clear clear clear DGM MOM SSHT PBB BERR VALID WAKE OVR DGM MOM SSHT PBB (a) Read (1/3) Bit position 7 Bit name DGM Specifies diagnostic processing mode. 0: Only when receiving, valid messages received using message buffer used for diagnostic processing mode (Bits MT2 to MT0 of M_CONF register = 111) 1: Only when receiving, valid messages received using normal operation mode. The diagnostic processing mode (MOM bit = 1) is used for CAN baud rate detection and for diagnostic purposes. When this mode has been set, the following operations are performed. * When the VALID bit = 1, it indicates that the current receive operation is valid. * Setting the DGM bit confirms whether or not valid data has been stored in the message buffer used for diagnostic processing mode, the same as for normal operation mode. Function Note xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, A, E 580 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (2/4) (a) Read (2/3) Bit position 6 Bit name MOM Function Specifies the CAN module operation mode. 0: Normal operating mode 1: Diagnostic processing mode Cautions 1. When in diagnostic processing mode (MOM bit = 1), the C1BRP register can be accessed only when the CAN module has been set to initialization mode (i.e., when the C1CTRL register's ISTAT bit = INIT bit = 1). When the CAN module is operating (i.e., when the C1CTRL register's ISTAT bit = 0), the C1BRP register cannot be used, and the CAN1 bus diagnostic information register (refer to 11. 10 (27) CAN1 bus diagnostic information register (C1DINF)) can be used instead. 2. The CAN protocol layer does not send ACK, error frame, or transmit messages, nor does it operate an error counter. The internal transmit output is fed back to the internal input due to auto baud rate detection. 5 SSHT Specifies single shot mode. 0: Normal operating mode 1: Single shot mode In single shot mode, the CAN module can transmit a message only one time. The M_STATn register's TRQ bit is then cleared (to 0) regardless of whether or not there are any pending normal transmit operations (n = 00 to 31). Also, if a bus error has occurred due to a transmission, it is handled as an incomplete transmission. Cautions 1. In single shot mode, even if the CAN lost in arbitration, it is handled as a completed message transmission. When in this mode, the BERR bit is set (to 1) but the error counter value (refer to 11.10 (23) CAN1 error count register (C1ERC)) does not change since there are no CAN bus errors. 2. In single shot mode, even when transmission is stopped due to error detection or a loss in the arbitration phase, the transmission completion interrupt occurs. 3. During the time when the CAN module is active, the CPU switches between normal operation mode and single shot mode without causing any errors to occur on the CAN bus. 4 PBB Specifies priority control for transmission. 0: Identifier (ID) based priority control 1: Message number based priority control Ordinarily, priority for transmission is defined based on message IDs, but when the PBB bit has been set (to 1) priority becomes based instead on the position of messages, so that messages with lower message numbers have higher priority. 3 BERR Indicates CAN bus error status. 0: CAN bus error was not detected 1: CAN bus error was detected at least once after bit was cleared 2 VALID Indicates valid message detection status. 0: Valid message was not detected 1: Valid message was detected at least once after bit was cleared User's Manual U14492EJ5V0UD 581 CHAPTER 11 FCAN CONTROLLER (3/4) (a) Read (3/3) Bit position 1 Bit name WAKE Function Indicates CAN sleep mode cancellation status. 0: Normal operation 1: CAN sleep mode canceled Cautions 1. The WAKE bit is set (1) only when the CAN sleep mode is released due to a change in the CAN bus and an error interrupt occurs. 2. While the WAKE bit is set (1), the error interrupt signal holds the active status. Therefore, always clear (0) the WAKE bit after recognition that the WAKE bit is set. 0 OVR Indicates overrun error status. 0: Normal operation 1: Overrun occurred during RAM access Caution When an overrun error has occurred, the OVR bit is set (to 1) and an error interrupt occurs at the same time. The source of the overrun error may be that the RAM access clock is slower than the selected CAN baud rate. 582 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (4/4) (b) Write Bit position 15, 7 Bit name set DGM, clear DGM Sets/clears the DGM bit. set DGM 0 1 clear DGM 1 0 DGM bit cleared (to 0) DGM bit set (to 1) DGM bit not changed Operation Function Other than above 14, 6 set MOM, clear MOM Sets/clears the MOM bit. set MOM clear MOM 0 1 1 0 MOM bit cleared (to 0) MOM bit set (to 1) MOM bit not changed Operation Other than above 13, 5 set SSHT, clear SSHT Sets/clears the SSHT bit. set SSHT clear SSHT 0 1 1 0 SSHT bit cleared (to 0) SSHT bit set (to 1) SSHT bit not changed Operation Other than above 12, 4 set PBB, clear PBB Sets/clears the PBB bit. set PBB 0 1 clear PBB 1 0 PBB bit cleared (to 0) PBB bit set (to 1) PBB bit not changed Operation Other than above 3 clear BERR Clears the BERR bit. 0: No change in BERR bit 1: BERR bit cleared (to 0) Clears the VALID bit. 0: No change in VALID bit 1: VALID bit cleared (to 0) Clears the WAKE bit. 0: No change in WAKE bit 1: WAKE bit cleared (to 0) Clears the OVR bit. 0: No change in OVR bit 1: OVR bit cleared (to 0) 2 clear VALID 1 clear WAKE 0 clear OVR User's Manual U14492EJ5V0UD 583 CHAPTER 11 FCAN CONTROLLER (22) CAN1 information register (C1LAST) The C1LAST register indicates the CAN module's error information and the number of the message buffer received last. This register is read-only, in 16-bit units. 15 C1LAST 0 14 0 13 0 12 0 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value 00FFH LERR3 LERR2 LERR1 LERR0 LREC7 LREC6 LREC5 LREC4 LREC3 LREC2 LREC1 LREC0 xxxxmC54HNote Bit position 11 to 8 Bit name LERR3 to LERR0 Indicates the last error information. LERR3 0 0 0 0 0 0 0 LERR2 0 0 0 0 1 1 1 LERR1 0 0 1 1 0 0 1 Function LERR0 0 1 0 1 0 1 0 Last error information Error not detected Bit error Stuff error CRC error Form error ACK error Arbitration lost (only in single shot mode (C1DEF register's SSHT bit = 1)) 0 1 1 0 1 0 1 0 CAN overrun error Wake-up from CAN bus Undefined Other than above Caution Since the LERR3 to LERR0 bits cannot be cleared, the current status is retained until the next error occurs. 7 to 0 LREC7 to LREC0 Indicates the last received message number. 0 to 31: The number of the message buffer last received 32 to 255: Not used Note xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, A, E 584 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (23) CAN1 error count register (C1ERC) The C1ERC register indicates the count values of the transmission/reception error counters. This register is read-only, in 16-bit units. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Note Initial value 0000H C1ERC REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 xxxxmC56H Bit position 15 to 8 Bit name REC7 to REC0 Indicates the reception error count. Function 0 to 255: The number of reception errors This reflects the current status of the reception error counter. The number of counts is defined by the CAN protocol. 7 to 0 TEC7 to TEC0 Indicates the transmission error count. 0 to 255: The number of transmission errors This reflects the current status of the transmission error counter. The number of counts is defined by the CAN protocol. Note xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, A, E User's Manual U14492EJ5V0UD 585 CHAPTER 11 FCAN CONTROLLER (24) CAN1 interrupt enable register (C1IE) The C1IE register is used to enable/disable the CAN module's interrupts. This register can be read/written in 16-bit units. Cautions 1. Both bitwise writing and direct writing to the C1IE register are prohibited. Attempts to write directly to this register may result in operation faults, so be sure to follow the sequence described in 11.9 Cautions on Bit Set/Clear Function. 2. When writing to the C1IE register, set or clear bits according to the register configuration during a write operation. (1/3) 15 C1IE (Read) 0 14 0 13 0 12 0 11 1 10 0 9 0 8 1 7 0 6 5 4 3 2 1 0 Address xxxxmC58HNote Initial value 0900H E_INT6 E_INT5 E_INT4 E_INT3 E_INT2 E_INT1 E_INT0 15 C1IE (Write) 0 14 set 13 12 11 set 10 set 9 set 8 set 7 0 6 5 4 3 2 1 0 set set clear clear clear clear clear clear clear E_INT6 E_INT5 E_INT4 E_INT3 E_INT2 E_INT1 E_INT0 E_INT6 E_INT5 E_INT4 E_INT3 E_INT2 E_INT1 E_INT0 (a) Read (1/2) Bit position 6 Bit name E_INT6 Function This is the CAN module error interrupt enable flag. 0: Interrupt disabled 1: Interrupt enabled 5 E_INT5 This is the CAN bus error interrupt enable flag. 0: Interrupt disabled 1: Interrupt enabled 4 E_INT4 This is the wake up from CAN sleep mode interrupt enable flag. 0: Interrupt disabled 1: Interrupt enabled 3 E_INT3 This is the receive error passive interrupt enable flag. 0: Interrupt disabled 1: Interrupt enabled 2 E_INT2 This is the transmit error passive or bus off interrupt enable flag. 0: Interrupt disabled 1: Interrupt enabled Note xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, A, E 586 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (2/3) (a) Read (2/2) Bit position 1 Bit name E_INT1 Function This is the receive completion interrupt enable flag. 0: Interrupt disabled 1: Interrupt enabled * When IE bit of the M_CTRLn register is 1, a reception completion interrupt occurs regardless of the setting of the E_INT1 bit if the transmit message buffer receives a remote frame while the auto response function is not set (RMDE0 bit of the M_CTRLn register = 0) (n = 00 to 31). 0 E_INT0 This is the transmit completion interrupt enable flag. 0: Interrupt disabled 1: Interrupt enabled (b) Write (1/2) Bit position 14, 6 Bit name set E_INT6, clear E_INT6 Sets/clears the E_INT6 bit. set E_INT6 clear E_INT6 0 1 1 0 Operation E_INT6 interrupt cleared (to 0) E_INT6 interrupt set (to 1) E_INT6 interrupt not changed Function Other than above 13, 5 set E_INT5, clear E_INT5 Sets/clears the E_INT5 bit. set E_INT5 clear E_INT5 0 1 1 0 Operation E_INT5 interrupt cleared (to 0) E_INT5 interrupt set (to 1) E_INT5 interrupt not changed Other than above 12, 4 set E_INT4, clear E_INT4 Sets/clears the E_INT4 bit. set E_INT4 clear E_INT4 0 1 1 0 Operation E_INT4 interrupt cleared (to 0) E_INT4 interrupt set (to 1) E_INT4 interrupt not changed Other than above 11, 3 set E_INT3, clear E_INT3 Sets/clears the E_INT3 bit. set E_INT3 clear E_INT3 0 1 1 0 Operation E_INT3 interrupt cleared (to 0) E_INT3 interrupt set (to 1) E_INT3 interrupt not changed Other than above User's Manual U14492EJ5V0UD 587 CHAPTER 11 FCAN CONTROLLER (3/3) (b) Write (2/2) Bit position 10, 2 Bit name set E_INT2, clear E_INT2 Sets/clears the E_INT2 bit. set E_INT2 clear E_INT2 0 1 1 0 Operation E_INT2 interrupt cleared (to 0) E_INT2 interrupt set (to 1) E_INT2 interrupt not changed Function Other than above 9, 1 set E_INT1, clear E_INT1 Sets/clears the E_INT1 bit. set E_INT1 clear E_INT1 0 1 1 0 Operation E_INT1 interrupt cleared (to 0) E_INT1 interrupt set (to 1) E_INT1 interrupt not changed Other than above 8, 0 set E_INT0, clear E_INT0 Sets/clears the E_INT0 bit. set E_INT0 clear E_INT0 0 1 1 0 Operation E_INT0 interrupt cleared (to 0) E_INT0 interrupt set (to 1) E_INT0 interrupt not changed Other than above 588 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (25) CAN1 bus active register (C1BA) The C1BA register indicates frame information output via the CAN bus. This register is read-only, in 16-bit units. 15 C1BA 0 14 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value 00FFH 0 CACT4 CACT3 CACT2 CACT1 CACT0 TMNO7 TMNO6 TMNO5 TMNO4 TMNO3 TMNO2 TMNO1 TMNO0 xxxxmC5AHNote Bit position 12 to 8 Bit name CACT4 to CACT0 Indicates CAN module status. Function CACT4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 CACT3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 CACT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 CACT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 CACT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 CAN module status Reset state Bus idle wait Bus idle state Start of frame Standard identifier area Data length code area Data field area CRC field area CRC delimiter ACK slot ACK delimiter End of frame area Intermission state Suspend transmission Error frame Error delimiter wait Error delimiter Extended identifier area 7 to 0 TMNO7 to TMNO0 Specifies transmit message counter. 0 to 31: Message number of message awaiting transmission or being transmitted 32 to 254: Not used 255: No messages awaiting transmission or being transmitted Note xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, A, E User's Manual U14492EJ5V0UD 589 CHAPTER 11 FCAN CONTROLLER (26) CAN1 bit rate prescaler register (C1BRP) The C1BRP register is used to set the transmission baud rate for the CAN module. Use the C1BRP register to select the CAN protocol layer base system clock (fBTL). determined by the value set to the C1SYNC register. While in normal operation mode (C1DEF register's MOM bit = 0), the C1BRP register can only be accessed when the initialization mode has been set (C1CTRL register's INIT bit = 1). This register can be read/written in 16-bit units. Caution While in diagnostic processing mode (C1DEF register's MOM bit = 1), the C1BRP register can only be accessed when the initialization mode has been set (C1CTRL register's INIT bit = 1) (refer to 11.10 (21) CAN1 definition register (C1DEF)). The baud rate is 590 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (1/2) 15 C1BRP (TLM = 0) TLM 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 5 4 3 2 1 0 Address Initial value 0000H BTYPE BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 xxxxmC5CHNote 15 C1BRP (TLM = 1) TLM 14 0 13 0 12 0 11 0 10 0 9 0 8 7 6 5 4 3 2 1 0 BTYPE BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 (a) When TLM = 0 Bit position 15 Bit name TLM Specifies transfer layer mode. 0: 6-bit prescaler mode Specifies CAN bus type. 0: Low speed ( 125 kbps) 1: High speed (> 125 kbps) Specifies CAN protocol layer base system clock (fBTL) for CAN module. Function 6 BTYPE 5 to 0 BRP5 to BRP0 n BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 CAN protocol layer base system clock (fBTL) 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 * * * 0 0 0 0 0 0 1 1 0 1 0 1 fMEM/2 fMEM/4 fMEM/6 fMEM/8 fMEM/(n + 1) x 2 60 61 62 63 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 fMEM/122 fMEM/124 fMEM/126 fMEM/128 Remark fBTL = fMEM/{(n + 1) x 2}: CAN protocol layer base system clock n = 0 to 63 (set by bits BRP5 to BRP0) fMEM = CAN base clock Note xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, A, E User's Manual U14492EJ5V0UD 591 CHAPTER 11 FCAN CONTROLLER (2/2) (b) When TLM = 1 Bit position 15 Bit name TLM Specifies transfer layer mode. 1: 8-bit prescaler mode Specifies CAN bus type. 0: Low speed ( 125 kbps) 1: High speed (> 125 kbps) Specifies CAN protocol layer base system clock (fBTL) for CAN module. Function 8 BTYPE 7 to 0 BRP7 to BRP0 n BRP7 BRP6 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 CAN protocol layer base system clock (fBTL) 0 1 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 Setting prohibited fMEM/2 fMEM/3 fMEM/4 fMEM/(n + 1) 252 253 254 255 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 fMEM/253 fMEM/254 fMEM/255 fMEM/256 Remark fBTL = fMEM/(n + 1): CAN protocol layer base system clock n = 0 to 255 (set by bits BRP7 to BRP0) fMEM = CAN base clock 592 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (27) CAN1 bus diagnostic information register (C1DINF) The C1DINF register indicates all CAN bus bits, including stuff bits, delimiters, etc. This information is used only for diagnostic purposes. Because the number of bits starting from SOF is added at each frame, the actual number of bits is the value obtained by subtracting the previous data. This register is read-only, in 16-bit units. Cautions 1. While in diagnostic processing mode (C1DEF register's MOM bit = 1) and in normal operation mode (C1CTRL register's INIT bit = 0), the C1DINF register can only be accessed. In normal operation mode (C1DEF register's MOM bit = 0), this register cannot be accessed. 2. Storage of the last 8 bits is automatically stopped if an error or a valid message (ACK delimiter) is detected on the CAN bus. Reset is automatically performed each time when the SOF is detected on the CAN bus. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value 0000H C1DINF DINF15 DINF14 DINF13 DINF12 DINF11 DINF10 DINF9 DINF8 DINF7 DINF6 DINF5 DINF4 DINF3 DINF2 DINF1 DINF0 xxxxmC5CHNote Bit position 15 to 0 Bit name DINF15 to DINF0 Function Indicates CAN bus diagnostic information. Bit name DINF15 to DINF8 DINF7 to DINF0 CAN Bus Diagnostic Information Number of bits starting from SOF Information from last 8 bits Note xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, A, E User's Manual U14492EJ5V0UD 593 CHAPTER 11 FCAN CONTROLLER (28) CAN1 synchronization control register (C1SYNC) The C1SYNC register controls the data bit time for transmission speed. This register can be read/written in 16-bit units. Cautions 1. The CPU is able to read the C1SYNC register at any time. 2. Writing to the C1SYNC register is enabled when in initialization mode (when C1CTRL register's INIT bit = 1). 3. The limit values of the CAN protocol when setting the SPTn bit and DBTn bit are as follows. 5 x BTL SPT (sampling point) 17 x BTL [4 SPT4 to SPT0 set values 16] 8 x BTL DBT (data bit time) 25 x BTL [7 DBT4 to DBT0 set values 24] SJW (synchronization jump width) DBT - SPT 2 (DBT - SPT) 8 Remark BTL = 1/fBTL (fBTL: CAN protocol layer base system clock) (1/3) 15 C1SYNC 0 14 0 13 0 12 11 10 9 8 7 6 5 4 3 2 1 0 Address Initial value 0218H SAMP SJW1 SJW0 SPT4 SPT3 SPT2 SPT1 SPT0 DBT4 DBT3 DBT2 DBT1 DBT0 xxxxmC5EHNote Bit position 12 Bit name SAMP Specifies bit sampling. Function 0: Receive data sampled once at the sampling point. 1: Receive data sampled three times and the majority value used as the sampled value. 11, 10 SJW1, SJW0 Specifies synchronization jump width stipulated in the CAN protocol specification, Ver. 2.0, PartB active. Note SJW1 0 0 1 1 SJW0 0 1 0 1 BTL BTL x 2 BTL x 3 BTL x 4 Synchronization jump width Note Stipulated in CAN protocol specification Ver. 2.0, PartB active Remark BTL = 1/fBTL (fBTL: CAN protocol layer base system clock) Note xxxx: CAN message buffer registers can be allocated to the xxxx addresses as programmable peripheral I/O registers. Note, however, that the xxxx addresses cannot be changed after being set. m = 2, 6, A, E 594 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (2/3) Bit position 9 to 5 Bit name SPT4 to SPT0 Specifies position of sampling points. SPT4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SPT3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 SPT2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 SPT1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 SPT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Position of sampling point BTL x 3 BTL x 4 BTL x 5 BTL x 6 BTL x 7 BTL x 8 BTL x 9 BTL x 10 BTL x 11 BTL x 12 BTL x 13 BTL x 14 BTL x 15 BTL x 16 BTL x 17 Setting prohibited Note Note Function Other than above Note This setting is reserved for setting sample point extension and is not compliant with the CAN protocol specifications. Remark Sampling point within bit timing is selected. User's Manual U14492EJ5V0UD 595 CHAPTER 11 FCAN CONTROLLER (3/3) Bit position 4 to 0 Bit name DBT4 to DBT0 Sets data bit time. DBT4 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 DBT3 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 DBT2 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 DBT1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 DBT0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Data bit time BTL x 8 BTL x 9 BTL x 10 BTL x 11 BTL x 12 BTL x 13 BTL x 14 BTL x 15 BTL x 16 BTL x 17 BTL x 18 BTL x 19 BTL x 20 BTL x 21 BTL x 22 BTL x 23 BTL x 24 BTL x 25 Setting prohibited Function Other than above Remark 1-bit data length is set for CAN bus. Remark BTL = 1/fBTL (fBTL: CAN protocol layer base system clock) 11.11 Operations 11.11.1 Initialization processing Figure 11-27 shows a flowchart of initialization processing. The register setting flow is shown in Figures 11-28 to 11-40. 596 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER Figure 11-27. Initialization Processing START CSTP = 1? (CSTOP) No Set CAN main clock selection register (CGCS) Yes CSTP = 0 (CSTOP) : See Figure 11-28 CAN Main Clock Selection Register (CGCS) Settings Set CAN global interrupt enable register (CGIE) : See Figure 11-29 CAN Global Interrupt Enable Register (CGIE) Settings Set CAN global status register (CGST) set INIT = 1 (C1CTRL) : See Figure 11-30 CAN Global Status Register (CGST) Settings ISTAT = 1? (C1CTRL) Yes Set CAN1 bit rate prescaler (C1BRP) No : See Figure 11-31 CAN1 Bit Rate Prescaler Register (C1BRP) Settings Set CAN1 synchronization control register (C1SYNC) : See Figure 11-32 CAN1 Synchronization Control Register (C1SYNC) Settings Set CAN1 interrupt enable register (C1IE) Set CAN1 definition register (C1DEF) Set CAN1 control register (C1CTRL) : See Figure 11-33 CAN1 Interrupt Enable Register (C1IE) Settings : See Figure 11-34 CAN1 Definition Register (C1DEF) Settings : See Figure 11-35 CAN1 Control Register (C1CTRL) Settings Mask required for message ID? Yes Set message buffer (repeat as many times as number of messages) clear INIT = 1 (C1CTRL) No Set mask (C1MASKa) : See Figure 11-36 CAN1 Address Mask a Registers L and H (C1MASKLa and C1MASKHa) (a = 0 to 3) Settings : See Figure 11-37 Message Buffer Settings ISTAT = 0? (C1CTRL) Yes END No User's Manual U14492EJ5V0UD 597 CHAPTER 11 FCAN CONTROLLER Figure 11-28. CAN Main Clock Selection Register (CGCS) Settings START Select clock for memory access controller (MCP0 to MCP3) fMEM Select global timer clock (GTCS0, GTCS1) fGTS1 Select system timer prescaler (CGTS0 to CGTS7) fGTS fMEM = fMEM1/(n + 1) n = 0 to 15 (set using bits MCP0 to MCP3) GTCS1, GTCS0 = 00: fGTS1 = fMEM/2 GTCS1, GTCS0 = 01: fGTS1 = fMEM/4 GTCS1, GTCS0 = 10: fGTS1 = fMEM/8 GTCS1, GTCS0 = 11: fGTS1 = fMEM/16 fGTS = fGTS1/(n + 1) n = 0 to 255 (set using bits CGTS0 to CGTS7) Remark fMEM = CAN base clock fMEM1 = Clock supplied to CAN fGTS1 = Global timer clock fGTS = System timer prescaler Figure 11-29. CAN Global Interrupt Enable Register (CGIE) Settings START * An interrupt occurs if a memory address in the undefined area is accessed. * An interrupt occurs if the GOM bit is not cleared (0) under the following conditions. * When shutdown is disabled (EFSD bit = 0) * When a CAN module not in the initialization status (ISTAT bit = 0) exists * An interrupt occurs if an illegal write access is made to the TEMP buffer when the GOM bit = 1. * An interrupt occurs if the CAN module register (register starting with "C1") is accessed when the GOM bit = 0. Enable interrupt for G_IE1 bit No Yes set G_IE1 = 1 clear G_IE1 = 0 Enable interrupt for G_IE2 bit No Yes set G_IE2 = 1 clear G_IE2 = 0 Remark GOM: Bit of CAN global status register (CGST) EFSD: Bit of CAN global status register (CGST) ISTAT: Bit of CAN1 control register (C1CTRL) 598 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER Figure 11-30. CAN Global Status Register (CGST) Settings START Start FCAN operation set GOM = 1 clear GOM = 0 Use time stamp function? No Yes set TSM = 1 clear TSM = 0 Figure 11-31. CAN1 Bit Rate Prescaler Register (C1BRP) Settings START Transfer speed is 125 kbps or less Yes BTYPE = 0 (low speed) No BTYPE = 1 (high speed) fBTL setting When TLM = 0 BRP5 to BRP0 When TLM = 1 BRP7 to BRP0 fBTL When TLM = 0 fBTL = fMEM/{(n + 1) x 2} n = 0 to 63 (set using bits BRP5 to BRP0) When TLM = 1 fBTL = fMEM/(n + 1) n = 0 to 255 (set using bits BRP7 to BRP0) Remark fBTL = CAN protocol layer base system clock fMEM = CAN base clock User's Manual U14492EJ5V0UD 599 CHAPTER 11 FCAN CONTROLLER Figure 11-32. CAN1 Synchronization Control Register (C1SYNC) Settings START Set data bit time (DBT4 to DBT0) 1 bit time = BTL x (m + 1) m = 7 to 24 (set using bits DBT4 to DBT0) Set sampling point (SPT4 to SPT0) Sampling point = BTL x (m + 1) m = 2 to 16 (set using bits SPT4 to SPT0)Note Set SJW (SJW1, SJW0) SJW = BTL x (m + 1) m = 0 to 3 (set using bits SJW1 and SJW0) Set once-only (single shot) sampling Yes SAMP = 0 Set sampling for one location only No SAMP = 1 Set sampling for three locations Note The setting of m = 2, 3 is reserved for setting sample point extension, and is not compliant with the CAN protocol specifications. Remark BTL = 1/fBTL (fBTL: CAN protocol layer base system clock) 600 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER Figure 11-33. CAN1 Interrupt Enable Register (C1IE) Settings START Interrupt enable flag for end of transmission Enable interrupt for E_INT0? No clear E_INT0 = 1 set E_INT0 = 0 Yes set E_INT0 = 1 clear E_INT0 = 0 Interrupt enable flag for end of reception Enable interrupt for E_INT1? No clear E_INT1 = 1 set E_INT1 = 0 Yes set E_INT1 = 1 clear E_INT1 = 0 Interrupt enable flag for error passive or bus off by TEC Enable interrupt for E_INT2? No clear E_INT2 = 1 set E_INT2 = 0 Yes set E_INT2 = 1 clear E_INT2 = 0 Interrupt enable flag for error passive by REC Enable interrupt for E_INT3? No clear E_INT3 = 1 set E_INT3 = 0 Yes set E_INT3 = 1 clear E_INT3 = 0 Interrupt enable flag for wake-up from CAN sleep mode Enable interrupt for E_INT4? No clear E_INT4 = 1 set E_INT4 = 0 Yes set E_INT4 = 1 clear E_INT4 = 0 Interrupt enable flag for CAN bus error Enable interrupt for E_INT5? No clear E_INT5 = 1 set E_INT5 = 0 Yes set E_INT5 = 1 clear E_INT5 = 0 Interrupt enable flag for CAN error Enable interrupt for E_INT6? No clear E_INT6 = 1 set E_INT6 = 0 Yes set E_INT6 = 1 clear E_INT6 = 0 User's Manual U14492EJ5V0UD 601 CHAPTER 11 FCAN CONTROLLER Figure 11-34. CAN1 Definition Register (C1DEF) Settings START Set to diagnostic processing mode? No clear MOM = 1 set MOM = 0 Yes Normal operation mode set MOM = 1 clear MOM = 0 Diagnostic processing mode Store to bufferNote used for diagnostic processing mode? No set DGM = 1 clear DGM = 0 Yes clear DGM = 1 set DGM = 0 Determine transmit priority based on identifiers? Transmit priority is determined based on message numbers No set PBB = 1 clear PBB = 0 Yes clear PBB = 1 set PBB = 0 Transmit priority is determined based on identifiers Set single shot mode? No clear SSHT = 1 set SSHT = 0 Yes Normal operation mode set SSHT = 1 clear SSHT = 0 Single shot mode: Transmit only once. Do not retransmit. Note Bits 5 to 3 (MT2 to MT0) in CAN message configuration register n (M_CONFn) (n = 00 to 31) are set as "111" 602 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER Figure 11-35. CAN1 Control Register (C1CTRL) Settings START Set time stamp for receiving Store timer value when SOF occurs? Yes clear TMR = 1 set TMR = 0 No set TMR = 1 clear TMR = 0 Store timer value when EOF occurs Set overwrite for receive message buffer Store message of DN flag? Yes clear OVM = 1 set OVM = 0 No set OVM = 1 clear OVM = 0 Do not overwrite message in DN flag (delete new message) Set dominant level for transmit pins Set dominant level to low level? Yes clear DLEVT = 1 set DLEVT = 0 No set DLEVT = 1 clear DLEVT = 0 Set dominant level to high level Set dominant level for receive pins Set dominant level to low level? Yes clear DLEVR = 1 set DLEVR = 0 No set DLEVR = 1 clear DLEVR = 0 Set dominant level to high level User's Manual U14492EJ5V0UD 603 CHAPTER 11 FCAN CONTROLLER Figure 11-36. CAN1 Address Mask a Registers L and H (C1MASKLa and C1MASKHa) (a = 0 to 3) Settings START Standard frame Yes (y = 0 to 17) Mask setting for standard frame (x = 18 to 28) CMIDy = 1 No Mask setting for extended frame (x = 0 to 28) Yes Mask ID bit? No Mask setting for message ID format CMIDx = 0 CMIDx = 1 Mask ID bit? No CMIDx = 0 Yes CMIDx = 1 Check ID type? Yes CMIDE = 0 No CMIDE = 1 604 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER Figure 11-37. Message Buffer Settings START Set message ID type No Standard frame? Yes IIDE = 0 (standard) (M_IDHn) IDE = 1 (extended) (M_IDHn) Set identifier (standard, extended) Set message configuration See Figure 11-38 CAN Message Configuration Registers 00 to 31 (M_CONF00 to M_CONF31) Settings Set message length Set message control byte See Figure 11-39 CAN Message Control Registers 00 to 31 (M_CTRL00 to M_CTRL31) Settings See Figure 11-40 CAN Message Status Registers 00 to 31 (M_STAT00 to M_STAT31) Settings Set message status Remark n = 00 to 31 User's Manual U14492EJ5V0UD 605 CHAPTER 11 FCAN CONTROLLER Figure 11-38. CAN Message Configuration Registers 00 to 31 (M_CONF00 to M_CONF31) Settings START Release CAN message buffer Use message buffer? Yes No MA = 0 MA = 1 Yes Transmit message No Receive message (no mask setting) No Yes MT2 to MT0 = 010 Yes MT2 to MT0 = 001 MT2 to MT0 = 000 Receive message (set mask 0) No Receive message (set mask 1) No Yes MT2 to MT0 = 011 Receive message (set mask 2) No Receive message (set mask 3) No MT2 to MT0 = 111 (used in diagnostic processing mode) Yes MT2 to MT0 = 100 Yes MT2 to MT0 = 101 Remark n = 00 to 31 606 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER Figure 11-39. CAN Message Control Registers 00 to 31 (M_CTRL00 to M_CTRL31) Settings START Transmit/receive data frame? Yes RTR = 0 No RTR = 1 Transmit/receive remote frame No Disable interrupt? Yes IE = 0 IE = 1 Enable interrupt Set remote frame auto acknowledge function Remote frame auto acknowledge? Yes RMDE0 = 1 No RMDE0 = 0 Set DN flag when remote frame is received No Set DN flag? Yes RMDE1 = 1 RMDE1 = 0 Apply time stamp? Yes ATS = 1 No ATS = 0 User's Manual U14492EJ5V0UD 607 CHAPTER 11 FCAN CONTROLLER Figure 11-40. CAN Message Status Registers 00 to 31 (M_STAT00 to M_STAT31) Settings START Clear DN flag clear DN = 1, set DN = 0 (SC_STATm) Clear TRQ flag clear TRQ = 1, set TRQ = 0 (SC_STATm) Clear RDY flag clear RDY = 1, set RDY = 0 (SC_STATm) Remark m = 00 to 31 608 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER 11.11.2 Transmit setting Transmit messages are output from the target message buffer. Figure 11-41. Transmit Setting START Select transmit message buffer Set data (M_DATAnm) Set RDY flag set RDY = 1, clear RDY = 0 (SC_STATn) Set transmit request flag set TRQ = 1, clear TRQ = 0 (SC_STATn) TRQ = 0? (M_STATn) Yes End of transmit operationNote No Note The RDY flag is not automatically cleared, so clear it by clearing the set RDY bit to 0 and set the clear RDY bit to 1. Remark n = 00 to 31, m = 0 to 7 User's Manual U14492EJ5V0UD 609 CHAPTER 11 FCAN CONTROLLER 11.11.3 Receive setting Receive messages are retrieved from the target message buffer. Figure 11-42. Setting of Receive Completion Interrupt and Reception Operation Using Reception Polling START Set RDY flag set RDY = 1, clear RDY = 0 (SC_STATn) Receive completion interrupt occurs Detect target message buffer Clear DN flag clear DN = 1, set DN = 0 (SC_STATn) : Detection methods <1> Detect using CAN1 information register (C1LAST) <2> Detect using CAN message search start/result register (CGMSS/CGMSR) (see Figure 11-43 CAN Message Search Start/Result Register (CGMSS/CGMSR) Settings) Receive remote frame No Receive data frame? Receive data frame Yes Transmit operation Get data length Get data Get time stamp No DN = 0 (M_STATn) Yes End of receive operation Remark n = 00 to 31 610 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER Figure 11-43. CAN Message Search Start/Result Register (CGMSS/CGMSR) Settings START Check DN flag (CDN = 1) Check masked messages? Yes Search non masklinked messages only CMSK = 1 (CGMSS) No CMSK = 0 (CGMSS) Search all messages (regardless of mask setting) No Check message ID? Yes Search standard ID only CIDE = 1 (CGMSS) CIDE = 0 (CGMSS) Do not check message ID format Set start position and start search Get search results User's Manual U14492EJ5V0UD 611 CHAPTER 11 FCAN CONTROLLER 11.11.4 CAN sleep mode In CAN sleep mode, the FCAN controller can be set to standby mode. A wake-up occurs when there is a bus operation. Figure 11-44. CAN Sleep Mode Settings START set SLEEP = 1 clear SLEEP = 0 (C1CTRL) No SLEEP = 1 (C1CTRL) Yes End of CAN sleep mode settings Figure 11-45. Clearing of CAN Sleep Mode by CAN Bus Active Status START CAN bus active SLEEP = 0 (C1CTRL) WAKE = 1 (C1DEF) Wake-up interrupt occurs End of CAN sleep mode clearing operation 612 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER Figure 11-46. Clearing of CAN Sleep Mode by CPU START clear SLEEP = 1 set SLEEP = 0 (C1CTRL) SLEEP = 0 (C1CTRL) End of CAN sleep mode clearing operation 11.11.5 CAN stop mode In CAN stop mode, the FCAN controller can be set to standby mode. No wake-up occurs when there is a bus operation (stop mode is controlled by CPU access only). Figure 11-47. CAN Stop Mode Settings START SLEEP = 1 (C1CTRL) Yes set STOP = 1 clear STOP = 0 (C1CTRL) No Set CAN sleep mode (see Figure 11-44) STOP = 1 (C1CTRL) Yes End of CAN stop mode settings No User's Manual U14492EJ5V0UD 613 CHAPTER 11 FCAN CONTROLLER Figure 11-48. Clearing of CAN Stop Mode START clear STOP = 1 set STOP = 0 clear SLEEP = 1 set SLEEP = 0 (C1CTRL) STOP = 0 SLEEP = 0 (C1CTRL) End of CAN stop mode clearing operation 614 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER 11.12 Rules for Correct Setting of Baud Rate The CAN protocol limit values for ensuring correct operation of FCAN are described below. If these limit values are exceeded, a CAN protocol violation may occur, which can result in operation faults. Always make sure that settings are within the range of limit values. (a) 5 x BTL SPT (sampling point) 17 x BTL [4 SPT4 to SPT0 set values 16] (b) 8 x BTL DBT (data bit time) 25 x BTL [7 DBT4 to DBT0 set values 24] (c) SJW (synchronization jump width) DBT - SPT (d) 2 x (DBT - SPT) 8 Remark BTL = 1/fBTL (fBTL: CAN protocol layer base system clock) SPT4 to SPT0 (Bits 9 to 5 of CAN1 synchronization control register (C1SYNC)) DBT4 to DBT0 (Bits 4 to 0 of CAN1 synchronization control register (C1SYNC)) (1) Example of FCAN baud rate setting (when C1BRP register's TLM bit = 0) The following is an example of how correct settings for the C1BRP register and C1SYNC register can be calculated. Conditions from CAN bus: <1> CAN base clock frequency (fMEM): 16 MHz <2> CAN bus baud rate: 83 kbps <3> Sampling point: 80% or more <4> Synchronization jump width: 3 BTL First, calculate the ratio between the CAN base clock frequency and the CAN bus baud rate frequency as shown below. fMEM/CAN bus baud rate = 16 MHz/83 kHz 192.77 26 x 3 Set an even number between 2 and 128 to the C1BRP register's bits BRP5 to BRP0 as the setting for the prescaler (CAN protocol layer base system clock: fBTL), then set a value between 8 and 25 to the C1SYNC register's bits DBT4 to DBT0 as the data bit time. Since it is assumed that the SJW (synchronization jump width) value is 3, the maximum setting for SPT (sampling point) is 3 less than the data bit time setting and is 17. (SPT DBT - 3 and SPT = 17) User's Manual U14492EJ5V0UD 615 CHAPTER 11 FCAN CONTROLLER Given the above limit values, the following four settings are possible. Prescaler 24 16 12 8 DBT 8 12 16 24 SPT (MAX.) 5 9 13 17 Calculated SPT 5/8 = 62.5% 9/12 = 75% 13/16 = 81% 17/24 = 71% 16 MHz/83 kbps 192 = 64 x 3 = 48 x 4 = 32 x 6 = 24 x 8 = 16 x 12 = 12 x 16 = 8 x 24 = 6 x 32 = 4 x 48 = 3 x 64 <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> The settings that can actually be made for the V850E/IA1 are in the range from <4> to <7> above (the section enclosed in broken lines). Among these options in the range from <4> to <7> above, option <6> is the ideal setting for the specifications when actually setting the register. (i) Prescaler (CAN protocol layer base system clock: fBTL) setting fBTL is calculated as below. * fBTL = fMEM/{(a + 1) x 2} : [0 a 63] Value a is set using bits 5 to 0 (BRP5 to BRP0) of the C1BRP register. fBTL = 16 MHz/12 = 16 MHz/{(5 + 1) x 2} thus a = 5 Therefore, C1BRP register = 0005H 616 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER (ii) DBT (data bit time) setting DBT is calculated as below. * DBT = BTL x (a + 1) : [7 a 24] Value a is set using bits 4 to 0 (DBT4 to DBT0) of the C1SYNC register. DBT = BTL x 16 = BTL x (a + 1) thus a = 15 Therefore, C1SYNC register's bits DBT4 to DBT0 = 01111B Note that 1/DBT = fBTL/16 1333 kHz/16 83 kbps (nearly equal to the CAN bus baud rate) (iii) SPT (sampling point) setting Given SJW = 3: SJW DBT - SPT 3 16 - SPT SPT 13 Therefore, SPT is set as 13 (max.) SPT is calculated as below. * SPT = BTL x (a + 1) : [4 a 16] Value a is set using bits 9 to 5 (SPT4 to SPT0) of the C1SYNC register. SPT = BTL x 13 = BTL x (12 + 1) thus a = 12 Therefore, the SPT4 to SPT0 bits of the C1SYNC register = 01100B (iv) SJW (synchronization jump width) setting SJW is calculated as below. * SJW = BTL x (a + 1) : [0 a 3] Value a is set using bits11 and 10 (SJW1, SJW0) of the C1SYNC register. C1SYNC register's bits SJW1 and SJW0 = BTL x 3 = BTL x (2 + 1) thus a = 2 Therefore, the SJW1 and SJW0 bits of the C1SYNC register = 10B. The C1SYNC register settings based on these results are shown in Figure 11-49 below. User's Manual U14492EJ5V0UD 617 CHAPTER 11 FCAN CONTROLLER Figure 11-49. C1SYNC Register Settings 15 C1SYNC Setting 0 0 14 0 0 13 0 0 12 SAMP 0 11 SJW1 1 10 SJW0 0 9 SPT4 0 8 SPT3 1 7 SPT2 Setting 1 6 SPT1 0 5 SPT0 0 4 DBT4 0 3 DBT3 1 2 DBT2 1 1 DBT1 1 0 DBT0 1 618 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER 11.13 Ensuring Data Consistency When the CPU reads data from CAN message buffers, it is essential for the read data to be consistent. Two methods are used to ensure data consistency: sequential data read and burst read mode. 11.13.1 Sequential data read When the CPU performs sequential access of a CAN message buffer, data is read from the buffer in the order shown in Figure 11-50 below. Only the FCAN internal operation can set the M_STATn register's DN bit (to 1) and only the CPU can clear it (to 0), so during the read operation the CPU must be able to check whether or not any new data has been stored in the message buffer. Figure 11-50. Sequential Data Read Read CPU Clear DN flag clear DN = 1, set DN = 0 (SC_STATn) Read data from message buffer DN = 0 (M_STATn) No Yes End of CPU's read operation Remark n = 00 to 31 User's Manual U14492EJ5V0UD 619 CHAPTER 11 FCAN CONTROLLER 11.13.2 Burst read mode Burst read mode is implemented in the FCAN to enable faster access to complete messages and secure the synchrony of data. Burst read mode starts up automatically each time the CPU reads the M_DLCn register and data is then copied from the message buffer area to a temporary read buffer. Data continues to be read from the temporary buffer as long as the CPU keeps directly incrementing (+1) the read address (when data is read in the following order: M_DLCn register M_CTRLn register M_TIMEn register M_DATAn0 to M_DATAn7 registers M_IDLn, M_IDHn register). If these linear address rules are not followed or if access is attempted to an address that is lower than the M_IDHn register's address (such as the M_CONFn register or M_STATn register), burst read mode becomes invalid. Cautions 1. 16-bit read access is required for the memory buffer area when using the burst read mode. If 8-bit access (byte read operation) is attempted, burst read mode does not start up even if the address is linearly incremented (+1) as described above. 2. Be sure to read out the value of FCAN control registers other than the M_DLCn register before starting the burst read mode. Remark n = 00 to 31 620 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER 11.14 Interrupt Conditions 11.14.1 Interrupts that are generated for FCAN controller When interrupts are enabled (condition <1>: M_CTRLn register's IE bit = 1, conditions other than <1>: C1IE register's interrupt enable flag = 1), interrupts will be generated under the following conditions (n = 00 to 31). <1> Message-related operation has succeeded * When a message has been received in the receive message buffer * When a remote frame has been received in the transmit message buffer (when auto acknowledge mode has not been set, i.e., when the M_CTRLn register's RMDE0 bit = 0) * When a message has been transmitted from the transmit message buffer <2> When a CAN bus error has been detected * Bit error * Bit stuff error * Form error * CRC error * ACK error <3> When the CAN bus mode has been changed * Error passive status elapsed while FCAN was transmitting * Bus off status was set while FCAN was transmitting * Error passive status elapsed while FCAN was receiving <4> Internal error * Overrun error 11.14.2 Interrupts that are generated for global CAN interface Interrupts are generated for the global CAN interface under the following conditions. * An undefined area is accessed * If the GOM bit is cleared to 0 when one of the CAN modules is not in the initialization status (ISTAT bit of C1CTRL register = 0) with the EFSD bit of the CGST register = 0 * A CAN module register (register starting with "C1") is accessed when the GOM bit of the CGST register = 0 * A temporary buffer (in the area following the address of the C1SYNC register) is accessed when the GOM bit of the CGST register = 1 User's Manual U14492EJ5V0UD 621 CHAPTER 11 FCAN CONTROLLER 11.15 How to Shut Down FCAN Controller The following procedure should be used to stop CAN bus operations in order to stop the clock supply to the CAN interface (to set low power mode). <1> FCAN controller's initialization mode setting * Set initialization mode (INIT bit = 1 in C1CTRL register (set INIT bit = 1, clear INIT bit = 0)) <2> Stop time stamp counter * Set TSM bit = 0 in CGST register (set TSM bit = 0, clear TSM bit = 1) <3> Stop CAN interface * Set GOM bit = 0 in CGST register (set GOM bit = 0, clear GOM bit = 1) * Stop CAN clock Caution If the above procedure is not performed correctly, the CAN interface (in active status) can cause operation faults. 622 User's Manual U14492EJ5V0UD CHAPTER 11 FCAN CONTROLLER 11.16 Cautions on Use <1> Bit manipulation is prohibited for all FCAN controller registers. <2> Be sure to properly clear (0) all interrupt request flagsNote in the interrupt routine. If these flags are not cleared (0), subsequent interrupt requests may not be generated. Note also that if an interrupt is generated at the same time as a CPU clear operation, that interrupt request flag will not be cleared (0). It is therefore important to confirm that interrupt request flags have been properly cleared (0). Note See 11.10 (10) CAN interrupt pending register (CCINTP), 11.10 (11) CAN global interrupt pending register (CGINTP), and 11.10 (12) CAN1 interrupt pending register (C1INTP). <3> When a change occurs on the CAN bus via a setting of the CSTP bit in the CSTOP register while the clock supply to the CPU or peripheral functions is stopped, the CPU can be woken up. <4> Do not read the same register of the FCAN controller twice or more in a row. If the same register is read twice or more in a row, and even if the value of the register is changed while it is being read the second or subsequent time, the new value is not reflected, and the same value as the one read the first time is always read. Example Reading the C1CTRL and C1BA registers (i) Correct usage: New value is reflected when C1CTRL is read the second time. C1CTRL read C1BA read C1CTRL read (ii) Incorrect usage: The second read value of C1CTRL is the same as the first read value of C1CTRL. C1CTRL read C1CTRL read C1BA read <5> When receiving a remote frame with an extended ID and storing it in the receive message buffer, the values of DLC3 to DLC0 in the message buffer are cleared to 0 regardless of the values of DLC3 to DLC0 on the CAN bus. User's Manual U14492EJ5V0UD 623 CHAPTER 11 FCAN CONTROLLER <6> If the OS (OSEK/COM) is not used, be sure to execute the following processing. [When CAN communication is performed using an interrupt routine] * Clear (0) the following interrupt pending bits at the start of the corresponding interrupt routine. * C1INTm bit of C1INTP register (m = 0 to 6) * GINT1 bit of CGINTP register (m = 1 to 3) * Clear (0) the following enable bits during the corresponding interrupt routine. * E_INTm bit of C1IE register (m = 0 to 6) * G_IEn bit of CGIE register (n = 1, 2) [When CAN communication is performed by polling of bits, not using interrupt routines] * The following interrupt mask flags and interrupt enable bits are used when set (1) (do not clear (0) them). * CANMKn bit of CANICn register (n = 0 to 3) * E_INTm bit of C1IE register (m = 0 to 6) * G_IEn bit of CGIE register (n = 1, 2) * IE bit of M_CTRLn register (n = 00 to 31) * Clear (0) the following interrupt pending bits in accordance with procedures (i) to (iii) below. * C1INTm bit of C1INTP register (m = 0 to 6) * GINTn bit of CGINTP register (n = 1 to 3) (i) Poll the corresponding interrupt request flag. (ii) If the value of the bit in procedure (i) is 1, clear (0) the corresponding interrupt pending bit. (iii) After executing procedure (ii), clear (0) the interrupt request flag. Example CAN reception (i) Poll until the CANIF0 bit of the CANIC0 register becomes 1. (ii) Clear (0) the C1INT1 bit of the C1INTP register. (iii) Clear (0) the CANIF0 bit of the CANIC0 register. <7> When emulating the FCAN controller using the in-circuit emulator (IE-V850E-MC or IE-703116-MC-EM1), perform the following settings in the Configuration screen that appears when the debugger is started. * Set the start address of the programmable peripheral I/O area that is set using the BPC register to the Programmable I/O Area field. * Maps the programmable peripheral I/O area as "Target" or "Emulation RAM" in the Memory Mapping field. 624 User's Manual U14492EJ5V0UD CHAPTER 12 NBD FUNCTION (PD70F3116) The V850E/IA1 provides the Non Break Debug (NBD) function for on-chip data tuning. 12.1 Overview The NBD function encompasses the following functions. (1) RAM monitoring function This function makes an arbitrary RAM area readable or writable using an NBD tool via DMA. [Corresponding RAM area] XFFFC000H to XFFFE7FFH If executed using an address outside the above, the function instantly returns "ready". Output is undefined on a read, and the write operation is not performed on a write. (2) Event detection function By having a comparator (24-bit address setting) for match detection on-chip, this function outputs a match trigger (falling edge) to the NBD tool when the address match detection shown below is performed. The lower 2 bits are masked. * Execution PC address match detection * Internal RAM area address write timing match detection [Detection range] ROM: X0000000H to X003FFFFH RAM: XFFFC000H to XFFFE7FFH Table 12-1. NBD Block Dedicated Pin Summary Pin Name CLK_DBG SYNC AD0_DBG to AD3_DBG TRIG_DBG I/O Input Input I/O Output Function Summary Serial clock input for debugging interface Synchronization signal for debugging Command data and RAM data I/O (4 bits) Outputs trigger (falling edge) synchronized to timing of write to arbitrary specified RAM address or to timing of execution of instruction at specified address. User's Manual U14492EJ5V0UD 625 CHAPTER 12 NBD FUNCTION (PD70F3116) Figure 12-1. Image of NBD Space V850E/IA1 CPU Not possible NBD dedicated interface (7 ways) NBD unit NBD tool NBD : Non Break Debug Caution The debug function does not operate under the following conditions. * During reset period * Until DMA initialization termination after reset * Software STOP mode/IDLE mode * Oscillation stabilization time (during TBC count) 12.2 NBD Function Register Map Table 12-2 shows a map of the control registers of the NBD function. The NBD space does not exist in the internal space of the CPU but exists independently as NBD space. Because of this, the NBD space is space that cannot be read or written from the CPU but can only be read or written via the NBD dedicated interface (refer to Figure 12-1). Table 12-2. NBD Space Map Address 000H 001H 002H 800H 801H 802H 803H 820H User event condition setting register Register Name Chip ID register 0 Chip ID register 1 Chip ID register 2 User event address setting register TID0 TID1 TID2 EVTU_A0 to EVTU_A7 EVTU_A8 to EVTU_A15 EVTU_A16 to EVTU_A23 EVTU_A24 to EVTU_A27 EVTU_C0 R/W Symbol R/W R After Reset 4EH 01H 01H Undefined Undefined Undefined Undefined Undefined Caution Since the V850E/IA1 NBD uses the DMA controller that is incorporated in the V850E1 CPU core, settings for the DMA controller are initialized after reset. 626 User's Manual U14492EJ5V0UD CHAPTER 12 NBD FUNCTION (PD70F3116) 12.3 NBD Function Protocol The basic protocol of the NBD function is shown below. (1) Basic protocol Figure 12-2. Basic Protocol (1) On a read CLK_DBG SYNC AD0_DBG to AD3_DBG Control section Address section N N R Command packet Flag sense Data packet (2) On a write CLK_DBG SYNC AD0_DBG to AD3_DBG Control section Address section Data section N N R Command packet Flag sense Remark N: Not ready R: Ready User's Manual U14492EJ5V0UD 627 CHAPTER 12 NBD FUNCTION (PD70F3116) (2) Command packet NBD Bus Line 1st 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th 13th 14th 15th 16th AD3_DBG aux3 SIZ1 A3 A7 A11 A15 A19 A23 D3 D7 D11 D15 D19 D23 D27 D31 AD2_DBG aux2 SIZ0 A2 A6 A10 A14 A18 A22 D2 D6 D10 D14 D18 D22 D26 D30 AD1_DBG aux1 R/W A1 A5 A9 A13 A17 A21 D1 D5 D9 D13 D17 D21 D25 D29 AD0_DBG aux0 I/T A0 A4 A8 A12 A16 A20 D0 D4 D8 D12 D16 D20 D24 D28 Caution Values are for command packet maximum setup. Address: 12 bits (A0 to A11) [Fixed] Data: 8 bits (D0 to D7) Address: 24 bits (A0 to A23) [Fixed] Data: 32 bits (D0 to D31) * Access to NBD space * Access to target space (a) aux0 to aux3: Expansion bits aux0 0 aux1 0 aux2 0 aux3 0 Fixed For future expansion Remarks Other than 0000 (b) I/T: Access address space mode specification I/T 0 1 Remarks Specifies access to NBD space Specifies access to target space (c) R/W: Access mode specification from NBD tool R/W 0 1 Remarks Read mode from NBD tool Write mode from NBD tool 628 User's Manual U14492EJ5V0UD CHAPTER 12 NBD FUNCTION (PD70F3116) (d) SIZ0, SIZ1: Access data size specification SIZ1 0 0 1 1 SIZ0 0 1 0 1 Target Space Access 8-bit length Note 1 NBD Space Access 8-bit length Setting prohibited Note 2 16-bit length 32-bit length Note 1 Setting prohibited Note 2 Notes 1. 2. Can be set only on a read. If set on a write, RAM data will be lost. A write is invalid and read data is undefined in cases where "Setting prohibited" is specified. (3) Flag sense packet NBD Bus Line 1st AD3_DBG 0 AD2_DBG 0 AD1_DBG 0 AD0_DBG RFLG RFLG 0: Not Ready 1: Ready (4) Data packet The data packet data size is the data size specified by SIZ1 and SIZ0 in a command packet (8, 16, or 32 bits). NBD Bus Line 1st 2nd 3rd 4th 5th 6th 7th 8th AD3_DBG D3 D7 D11 D15 D19 D23 D27 D31 AD2_DBG D2 D6 D10 D14 D18 D22 D26 D30 AD1_DBG D1 D5 D9 D13 D17 D21 D25 D29 AD0_DBG D0 D4 D8 D12 D16 D20 D24 D28 User's Manual U14492EJ5V0UD 629 CHAPTER 12 NBD FUNCTION (PD70F3116) 12.4 NBD Function 12.4.1 RAM monitoring, accessing NBD space The NBD function performs reading and writing of internal RAM data for addresses in internal RAM via the DMA (direct memory access) controller. It also performs reading or writing to the NBD space. (1) RAM monitoring The following are the commands for reading and writing to internal RAM areas from the NBD tool. (a) Write command The target address (real address of target: lower 24 bits) at which a write to internal RAM is to be performed and the data sent from the NBD tool are received as a command packet. After receiving the command packet shown below from the NBD tool, a Ready command is output following write completion. Command packets can be received once more from the NBD tool (after Ready command SYNC inactive confirmation). Table 12-3. Command Packet (Write Access) ADn_DBG 1st 2nd 3rd to 8th 9th to 16th AD3_DBG 0 SIZ1 AD2_DBG 0 SIZ0 AD1_DBG 0 1 AD0_DBG 0 1 Target space write address specification (24 bits) Write data (data specified by SIZ0 and SIZ1) (b) Read command The target address (real address of target: lower 24 bits), at which read of internal RAM is to be performed, which is sent from the NBD tool, is received as a command packet. After receiving the command packet from the NBD tool, a Ready command is output, SYNC is made inactive, and the data at the address specified by the command packet is transmitted to the NBD tool. The address (A27 to A24) during read is "1111". Table 12-4. Command Packet (Read Access) ADn_DBG 1st 2nd 3rd to 8th AD3_DBG 0 SIZ1 AD2_DBG 0 SIZ0 AD1_DBG 0 0 AD0_DBG 0 1 Target space read address specification (24 bits) Caution In read mode, the output data section from the NBD tool is deleted. Table 12-5. Data Packet (Read Access) ADn_DBG 1st to 8th AD3_DBG AD2_DBG AD1_DBG AD0_DBG Target space read data 630 User's Manual U14492EJ5V0UD CHAPTER 12 NBD FUNCTION (PD70F3116) (2) Access to NBD space The following are the commands for reading or writing to the NBD space from the NBD tool. For the NBD space, the access address length is fixed to 12 bits and the access data length is fixed to 8 bits. (a) Write command The address (NBD space address: 12 bits) at which write to the NBD space is to be performed and the data sent from the NBD tool are received as a command packet. After receiving the command packet shown in Table 12-6 from the NBD tool, a Ready command is output following write completion. Command packets can be received once more from the NBD tool (after Ready command SYNC inactive confirmation). Table 12-6. Command Packet (Write Access to NBD Space) ADn_DBG 1st 2nd 3rd 4th 5th 6th 7th AD3_DBG 0 0 A3 A7 A11 D3 D7 AD2_DBG 0 0 A2 A6 A10 D2 D6 AD1_DBG 0 1 A1 A5 A9 D1 D5 AD0_DBG 0 0 A0 A4 A8 D0 D4 Caution The length of an NBD space write address is fixed to 12 bits. The length of the write data is fixed to 8 bits. (b) Read command The target address (real address of target: 12 bits), at which read of internal RAM is to be performed, which is sent from the NBD tool, is received as a command packet. After receiving the command packet from the NBD tool, a Ready command is output, SYNC is made inactive, and the data at the address specified by the command packet is transmitted to the NBD tool. Table 12-7. Command Packet (Read Access to NBD Space) ADn_DBG 1st 2nd 3rd 4th 5th AD3_DBG 0 0 A3 A7 A11 AD2_DBG 0 0 A2 A6 A10 AD1_DBG 0 0 A1 A5 A9 AD0_DBG 0 0 A0 A4 A8 Caution The length of an NBD space read address is fixed to 12 bits. In read mode, the output data section from the NBD tool is deleted. User's Manual U14492EJ5V0UD 631 CHAPTER 12 NBD FUNCTION (PD70F3116) Table 12-8. Data Packet ADn_DBG 1st 2nd AD3_DBG D3 D7 AD2_DBG D2 D6 AD1_DBG D1 D5 AD0_DBG D0 D4 Caution The length of the read data is fixed to 8 bits. 12.4.2 Event detection function By having a comparator (24-bit address setting) for match detection on-chip, this function detects match of the address setting registers shown below and outputs a match trigger (falling edge) to the NBD tool. Event trigger output is low active and during the active period it is output synchronous with the system clock of the target CPU. The active width is one cycle of the internal system clock of the CPU. (1) Event detection conditions * Execution PC address match Match detection range for timing of a write to a set address in the internal RAM area XFFFC000H to XFFFE7FFH (2) Event detection function control register (a) NBD event condition setting register (EVTU_C) 7 EVTU_C7 to EVTU_C0 0 6 0 5 0 4 0 3 0 2 0 1 0 0 PCU/DTU NBD space address Initial value 820H Undefined Bit position 0 Bit name PCU/DTU Function Selects an execution PC event or RAM access event. 0: Internal RAM access event is invalid 1: Execution PC event is invalid Note Note If the EVTU_C register is set to a location other than the internal RAM area, an event also is output when writing to other than the RAM. 632 User's Manual U14492EJ5V0UD CHAPTER 12 NBD FUNCTION (PD70F3116) (b) NBD event address register (EVTU_A) The EVTU_A register sets the value of the address that is the subject of the event. 7 EVTU_A7 to EVTU_A0 EVAU7 6 EVAU6 5 EVAU5 4 EVAU4 3 EVAU3 2 EVAU2 1 EVAU1 0 EVAU0 NBD space address Initial value 800H Undefined 15 EVTU_A15 to EVTU_A8 EVAU15 14 EVAU14 13 EVAU13 12 EVAU12 11 EVAU11 10 EVAU10 9 EVAU9 8 EVAU8 NBD space address Initial value 801H Undefined 23 EVTU_A23 to EVTU_A16 EVAU23 22 EVAU22 21 EVAU21 20 EVAU20 19 EVAU19 18 EVAU18 17 EVAU17 16 EVAU16 NBD space address Initial value 802H Undefined 30 31 29 28 27 26 25 24 NBD space address Initial value EVTU_A27 to Undefined Undefined Undefined Undefined EVAU27Note EVAU26Note EVAU25Note EVAU24Note 803H Undefined EVTU_A24 Note Set bit 27 to bit 24 to 0. Cautions 1. ROM address match functions are valid only for internal ROM. 2. This cannot be used in single-chip mode 1. 3. The lower 2 bits (EVAU1, EVAU0) are masked. 12.4.3 Chip ID registers (TID0 to TID2) The chip ID registers are stored in NBD space 000H to 002H. By reading the ID codes in the chip ID registers from the NBD tool in NBD mode, the semiconductor manufacturer, CPU code, and specific product type can be identified. The chip ID registers have fixed values for each product. The chip ID registers (TID0 to TID2) are read-only registers. 7 TID0 MC7 6 MC6 5 MC5 4 MC4 3 MC3 2 MC2 1 MC1 0 MC0 NBD space address 000H * MC7 to MC0: Semiconductor manufacturer classification code NEC Electronics: 4EH 7 TID1 FC7 6 FC6 5 FC5 4 FC4 3 FC3 2 FC2 1 FC1 0 FC0 NBD space address 001H * FC7 to FC0: CPU classification code V850E1 CPU: 01H 7 TID2 SC7 6 SC6 5 SC5 4 SC4 3 SC3 2 SC2 1 SC1 0 SC0 NBD space address 002H * SC7 to SC0: Specific product classification code V850E/IA1: 01H User's Manual U14492EJ5V0UD 633 CHAPTER 12 NBD FUNCTION (PD70F3116) 12.5 Control Registers (1) RAM access data buffer register L (NBDL) The NBDL register operates as the buffer between the DMA controller and the NBD tool when reading or writing RAM from the NBD tool via the DMA controller. This register can be read/written in 16-bit units. When the higher 8 bits of the NBDL register are used as the NBDLU register, and the lower 8 bits are used as the NBDLL register, they can be read/written in 8-bit units. 15 NBDL 14 13 12 11 10 9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 1 D1 0 D0 Address FFFFFA60H Initial value 0000H D15 D14 D13 D12 D11 D10 D9 Cautions 1. Although the NBDL, NBDLU, and NBDLL registers can be used for reading or writing, physically separate registers are used when reading and when writing, so written values cannot be read. 2. Use both the NBDL and NBDH registers (refer to 12.5 (2)) for 32-bit access of RAM. Remark Register values written from the NBD tool can be read by DMA (CPU) and values written by DMA (CPU) can be read by the NBD tool. (2) RAM access data buffer register H (NBDH) The NBDH register operates as the buffer between the DMA controller and the NBD tool when reading or writing RAM from the NBD tool via the DMA controller. This register can be read/written in 16-bit units. When the higher 8 bits of the NBDH register are used as the NBDHU register, and the lower 8 bits are used as the NBDHL register, they can be read/written in 8-bit units. 15 NBDH 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFFA62H Initial value 0000H D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Cautions 1. Although the NBDH, NBDHU, and NBDHL registers can be used for reading or writing, physically separate registers are used when reading and when writing, so written values cannot be read. 2. Use both the NBDL and NBDH registers (refer to 12.5 (1)) for 32-bit access of RAM. Remark Register values written from the NBD tool can be read by DMA (CPU) and values written by DMA (CPU) can be read by the NBD tool. 634 User's Manual U14492EJ5V0UD CHAPTER 12 NBD FUNCTION (PD70F3116) (3) DMA source address setting register SL (NBDMSL) The NBDMSL register specifies a DMA source address. This register can be written from the NBD tool and read by the DMA controller (CPU). This register is read-only, in 16-bit units. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFFA64H Initial value Undefined NBDMSL AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Remarks 1. When reading RAM using the NBD tool, an address signal sent from the NBD tool can be read via the NBDMSL register using the DMA controller (CPU). 2. When writing to RAM using the NBD tool, the NBDL register value can be read via the NBDMSL register using the DMA controller (CPU). (4) DMA source address setting register SH (NBDMSH) The NBDMSH register specifies a DMA source address. This register can be written from the NBD tool and read by the DMA controller (CPU). This register is read-only, in 16-bit units. 15 NBDMSH IR 14 0 13 0 12 0 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFFA66H Initial value Undefined AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 Bit position 15 IR Bit name Function Shows read or write status when NBD accesses internal RAM of the V850E/IA1. 0: NBD is write accessing RAM 1: NBD is read accessing RAM Remarks 1. When reading RAM using the NBD tool, an address signal sent from the NBD tool can be read via the NBDMSH register using the DMA controller (CPU). 2. When writing to RAM using the NBD tool, the NBDL register value can be read via the NBDMSH register using the DMA controller (CPU). User's Manual U14492EJ5V0UD 635 CHAPTER 12 NBD FUNCTION (PD70F3116) (5) DMA destination address setting register DL (NBDMDL) The NBDMDL register specifies a DMA destination address. This register can be written from the NBD tool and read by the DMA controller (CPU). This register is read-only, in 16-bit units. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFFA68H Initial value Undefined NBDMDL AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Remarks 1. When writing to RAM using the NBD tool, an address signal sent from the NBD tool can be read via the NBDMDL register using the DMA controller (CPU). 2. When reading RAM using the NBD tool, the NBDL register value can be read via the NBDMDL register using the DMA controller (CPU). (6) DMA destination address setting register DH (NBDMDH) The NBDMDH register specifies a DMA destination address. This register can be written from the NBD tool and read by the DMA controller (CPU). This register is read-only, in 16-bit units. 15 NBDMDH IR 14 0 13 0 12 0 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFFA6AH Initial value Undefined AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 Bit position 15 IR Bit name Function Shows read or write status when NBD accesses internal RAM of the V850E/IA1. 0: NBD is read accessing RAM 1: NBD is write accessing RAM Remarks 1. When writing to RAM using the NBD tool, an address signal sent from the NBD tool can be read via the NBDMDH register using the DMA controller (CPU). 2. When reading RAM using the NBD tool, the NBDL register value can be read via the NBDMDH register using the DMA controller (CPU). 636 User's Manual U14492EJ5V0UD CHAPTER 12 NBD FUNCTION (PD70F3116) 12.6 Restrictions on NBD 12.6.1 General restrictions (1) CLK_DBG operates at less than half the speed of the internal system clock (fXX) and is 12.5 MHz maximum. (2) If a command packet is sent during a reset period, "ready" is not returned afterwards. Reset again. 12.6.2 Restrictions related to read or write of RAM by NBD (1) Initialize the DMA controller in user software. (2) On a write, RAM can only be accessed in 32-bit units. On a read-only, RAM can be accessed in 32-, 16-, or 8-bit units. On a read/write, RAM can be accessed in 32-bit units. (3) NBD does not function from the start of reset until completion of DMA controller initialization after the reset. If a read or write of RAM is performed in this interval, NBD does not return "ready" afterwards. Reset again. 12.6.3 Restrictions related to NBD event trigger function (1) If a ROM execution address event trigger is set to the address after a branch instruction, an event is generated due to pipeline processing even if it is not executed. The trigger must be set to an address at least 32 bits x 3 words after a branch instruction. (2) Since an event trigger is cleared by a reset, it must be set again after a reset. (3) Unless there is a ROM fetch, a trigger occurs even on a read. (4) ROM address match functions only for internal ROM. The lower 2 bits are masked. RAM address match functions only for internal RAM. The lower 2 bits are masked. Caution ROM and RAM address match cannot be used in the in-circuit emulator. 12.6.4 How to detect termination of DMA initialization via NBD tool Set an event trigger using a RAM write and send a write command from NBD to the relevant address. If an event trigger occurs at this time, DMA initialization has terminated. User's Manual U14492EJ5V0UD 637 CHAPTER 12 NBD FUNCTION (PD70F3116) 12.7 Initialization Required for DMA (2 Channels) (1) The DMA initialization in a setting change request must be performed by user software. (2) Assign DMA two channels in NBD. At this time, assign an NBDAD interrupt to a higher priority channel than an NBDREW interrupt. (3) Initialize registers of the channel to which the NBDAD interrupt is assigned. Set contents so that the contents of NBDMSL/NDBMSH and NBDMDL/NBDMDH (read-only SFR) transfer to DMA source address registers nL and nH (DSAnL, DSAnH)Note and DMA destination address registers nL and nH (DDAnL, DDAnH)Note of the DMA channel assigned to the NBDREW interrupt in 16 bits x 4 blocks (n = 0 to 3). Note DMA registers are 16-bit access only. (4) Set DMA addressing control register n (DADCn) of the DMA channel assigned to the NBDREW interrupt for 32-bit transfer (bit transfer settings of 8 bits x 4, 16 bits x 2, and 32 bits x 1Note) (n = 0 to 3). In addition, set the counter direction of the DMA transfer source address and DMA transfer destination address to increment mode (SADm bit of DADCn register = 0, DADm bit = 0 (m = 0,1)) (since DMA judges data transfer terminated on reading or writing the uppermost 8 bits). Note Bits that can be manipulated on 8 bits x 4, 16 bits x 2, and 32 bits x 1 bit transfer are shown below. 8 bits x 4: 32-, 16-, or 8-bit read is possible. 16 bits x 2: 16- or 8-bit read is possible. 32 bits x 1: 32-bit read is possible. This is the highest read speed. Settings other than the above are prohibited. Moreover, make the setting 32 bits x 1 when reading or writing RAM. Caution In DMA initialization, set the DMA request selection last. 638 User's Manual U14492EJ5V0UD CHAPTER 12 NBD FUNCTION (PD70F3116) Examples of DMA initialization on 32-bit transfer, 16-bit transfer, and 8-bit transfer are shown below. (a) Example of 32-bit transfer DMA initialization -- DMA INITIAL mov st.h mov st.h mov st.h mov st.h mov st.h mov st.h mov st.h mov st.h mov st.b st.b mov st.b mov st.b -- r24 -- DMACH0 Source Address -- 0x0000FA64 , r24 , DSAL0[r0] 0x00000FFF , r24 , DSAH0[r0] 0x0000F088 , r24 , DDAL0[r0] 0x00000FFF , r24 , DDAH0[r0] 0x0000400c , r24 , DADC0[r0] 0x0000800c , r24 , DADC1[r0] 0x00000003 , r24 , DBC0[r0] 0x00000000 , r24 , DBC1[r0] 0x00000009 , r24 , DCHC0[r0] r24 , DCHC1[r0] 0x00000035 , r24 , DTFR0[r0] 0x00000036 , r24 , DTFR1[r0] r24 -- DMACH0 Source Address -- r24 -- DMACH0 Destination Address -- r24 -- DMACH0 Destination Address -- r24 -- DMACH0 Block MODE 16Bit MODE -- r24 -- DMACH1 Block MODE 32Bit MODE -- r24 -- DMACH0 Block MODE 16Bit4 -- r24 -- DMACH1 Block MODE 32Bit1 -- r24 -- DMACH0&1 DMA ready -- r24 -- DMACH0 Trigger -- r24 -- DMACH1 Trigger -- User's Manual U14492EJ5V0UD 639 CHAPTER 12 NBD FUNCTION (PD70F3116) (b) Example of 16-bit transfer DMA initialization -- DMA INITIAL mov st.h mov st.h mov st.h mov st.h mov st.h mov st.h mov st.h mov st.h mov st.b st.b mov st.b mov st.b -- r24 -- DMACH0 Source Address -- 0x0000FA64 , r24 , DSAL0[r0] 0x00000FFF , r24 , DSAH0[r0] 0x0000F088 , r24 , DDAL0[r0] 0x00000FFF , r24 , DDAH0[r0] 0x0000400c , r24 , DADC0[r0] 0x0000400c , r24 , DADC1[r0] 0x00000003 , r24 , DBC0[r0] 0x00000001 , r24 , DBC1[r0] 0x00000009 , r24 , DCHC0[r0] r24 , DCHC1[r0] 0x00000035 , r24 , DTFR0[r0] 0x00000036 , r24 , DTFR1[r0] r24 -- DMACH0 Source Address -- r24 -- DMACH0 Destination Address -- r24 -- DMACH0 Destination Address -- r24 -- DMACH0 Block MODE 16Bit MODE -- r24 -- DMACH1 Block MODE 16Bit MODE - r24 -- DMACH0 Block MODE 16Bit4 -- r24 -- DMACH1 Block MODE 16Bit2 -- r24 -- DMACH0&1 DMA ready -- r24 -- DMACH0 Trigger -- r24 -- DMACH1 Trigger -- 640 User's Manual U14492EJ5V0UD CHAPTER 12 NBD FUNCTION (PD70F3116) (c) Example of 8-bit transfer DMA initialization -- DMA INITIAL mov st.h mov st.h mov st.h mov st.h mov st.h mov st.h mov st.h mov st.h mov st.b st.b mov st.b mov st.b -- r24 -- DMACH0 Source Address -- 0x0000FA64 , r24 , DSAL0[r0] 0x00000FFF , r24 , DSAH0[r0] 0x0000F088 , r24 , DDAL0[r0] 0x00000FFF , r24 , DDAH0[r0] 0x0000400c , r24 , DADC0[r0] 0x0000000c , r24 , DADC1[r0] 0x00000003 , r24 , DBC0[r0] 0x00000003 , r24 , DBC1[r0] 0x00000009 , r24 , DCHC0[r0] r24 , DCHC1[r0] 0x00000035 , r24 , DTFR0[r0] 0x00000036 , r24 , DTFR1[r0] r24 -- DMACH0 Source Address -- r24 -- DMACH0 Destination Address -- r24 -- DMACH0 Destination Address -- r24 -- DMACH0 Block MODE 16Bit MODE -- r24 -- DMACH1 Block MODE 8Bit MODE - r24 -- DMACH0 Block MODE 16Bit4 -- r24 -- DMACH1 Block MODE 8Bit4 -- r24 -- DMACH0&1 DMA ready -- r24 -- DMACH0 Trigger -- r24 -- DMACH1 Trigger -- User's Manual U14492EJ5V0UD 641 CHAPTER 13 A/D CONVERTER 13.1 Features * Two 10-bit resolution on-chip A/D converters (A/D converter 0 and 1) Simultaneous sampling by two circuits is possible. * Analog input: 8 channels per circuit * On-chip A/D conversion result registers 0n, 1n (ADCR0n, ADCR1n) 10 bits x 8 registers x 2 * A/D conversion trigger mode A/D trigger mode A/D trigger polling mode Timer trigger mode External trigger mode * Successive approximation technique * Voltage detection mode Remark n = 0 to 7 13.2 Configuration A/D converters 0 and 1, which employ a successive approximation technique, perform A/D conversion operation using A/D scan mode registers 00, 01, 10, and 11 (ADSCM00, ADSCM01, ADSCM10, and ADSCM11) and registers ADCR0n and ADCR1n (n = 0 to 7). (1) Input circuit The input circuit selects an analog input (ANI0n or ANI1n) according to the mode set in the ADSCM00 or ADSCM10 register and sends it to the sample and hold circuit (n = 0 to 7). (2) Sample and hold circuit The sample and hold circuit individually samples analog inputs sent sequentially from the input circuit and sends them to the comparator. It holds sampled analog inputs during A/D conversion. (3) Voltage comparator The voltage comparator compares the analog input voltage that was input with the output voltage of the D/A converter. (4) D/A converter The D/A converter is used to generate a voltage that matches an analog input. The output voltage of the D/A converter is controlled by the successive approximation register (SAR). (5) Successive approximation register (SAR) The SAR is a 10-bit register that controls the output value of the D/A converter for comparing with an analog input voltage value. When an A/D conversion terminates, the current contents of the SAR (conversion result) are stored in an A/D conversion result register (ADCR0n, ADCR1n) (n = 0 to 7). When all specified A/D conversions terminate, there also is an A/D conversion termination interrupt (INTAD0, INTAD1). 642 User's Manual U14492EJ5V0UD CHAPTER 13 A/D CONVERTER (6) A/D conversion result registers 0n, 1n (ADCR0n, ADCR1n) ADCR0n and ADCR1n are 10-bit registers that hold A/D conversion results (n = 0 to 7). Whenever an A/D conversion terminates, the conversion result from the successive approximation register (SAR) is loaded. RESET input sets these registers to 0000H. (7) Controller The controller selects an analog input, generates sample and hold circuit operation timing, controls conversion triggers, and specifies the conversion operation time according to the mode set in the ADSCMn0 or ADSCMn1 register (n = 0, 1). (8) ANI0n, ANI1n pins (n = 0 to 7) The ANI0n and ANI1n pins are the 8-channel (total of 16 channels for two circuits) analog input pins to A/D converters 0 and 1. They input analog signals to be A/D converted. Caution Use input voltages to ANI0n and ANI1n that are within the range of the ratings. In particular, if a voltage (including noise) higher than AVDD or lower than AVSS (even one within the range of absolute maximum ratings) is input, the conversion value of that channel is invalid, and the conversion values of other channels also may be affected. (9) AVREF0, AVREF1 pins The AVREF0 and AVREF1 pins are used to input reference voltages to A/D converters 0 and 1. A signal input to the ANI0n or ANI1n pin is converted to a digital signal based on the voltage applied between AVREF0 and AVSS or between AVREF1 and AVSS (n = 0 to 7). Caution (10) AVSS pin The AVSS pin is the ground voltage pin of A/D converters 0 and 1. Even if not using A/D converters 0 and 1, always make this pin have the same potential as the VSS5 pin. (11) AVDD pin The AVDD pin is the analog power supply pin of A/D converters 0 and 1. Even if not using A/D converters 0 and 1, always make this pin have the same potential as the VDD5 pin. If not using the AVREF0 or AVREF1 pin, connect it to VSS5. User's Manual U14492EJ5V0UD 643 CHAPTER 13 A/D CONVERTER Figure 13-1. Block Diagram of A/D Converter 0 or 1 ANIn0 ANIn1 ANIn2 ANIn3 ANIn4 ANIn5 ANIn6 ANIn7 Input circuit Sample and hold circuit Comparator and D/A converter AVDD AVREFn AVSS SAR (10) fXX/2 INTADn ITRG0 ADTRGn Trigger source switching circuit in timer trigger mode (Figure 13-2) 15 0 15 0 15 0 15 0 Controller 9 ADCRn0 ADCRn1 ADCRn2 ADCRn3 ADCRn4 ADCRn5 ADCRn6 ADCRn7 10 0 INTDETn ADSCMn0 (16) 16 ADSCMn1 (16) 16 ADETM0 (16) 16 ADETM1 (16) 10 16 Internal bus Remark n = 0, 1 fXX: Internal system clock Cautions 1. Noise at an analog input pin (ANI0n, ANI1n) or reference voltage input pin (AVREF0, AVREF1) may give rise to an invalid conversion result. Software processing is needed in order to prevent this invalid conversion result from adversely affecting the system. The following are examples of software processing. * Use the average value of the results of multiple A/D conversions as the A/D conversion result. * Perform A/D conversion multiple consecutive times and use conversion results with the exception of any abnormal conversion results that are obtained. * If an A/D conversion result from which it is judged that an abnormality occurred in the system is obtained, do not perform abnormality processing at once but perform it upon reconfirming the occurrence of an abnormality. 2. Be sure that voltages outside the range [AVSS to AVREF0, AVSS to AVREF1] are not applied to pins being used as A/D converter 0 and 1 input pins. 644 User's Manual U14492EJ5V0UD CHAPTER 13 A/D CONVERTER Figure 13-2. Block Diagram of Trigger Source Switching Circuit in Timer Trigger Mode ADTRG0 A/D converter 0 ITRG0 INTCM003 INTCM013 ADTRG1 A/D converter 1 Selector Selector Selector INTTM00 INTTM01 ITRG0 Selector ITRG0 0 ITRG22 ITRG21 ITRG20 0 ITRG12 ITRG11 ITRG10 Internal bus Caution For the selection of the trigger source in timer trigger mode, refer to 13.3 (5) A/D internal trigger selection register (ITRG0). User's Manual U14492EJ5V0UD 645 CHAPTER 13 A/D CONVERTER 13.3 Control Registers (1) A/D scan mode registers 00 and 10 (ADSCM00, ADSCM10) The ADSCMn0 registers are 16-bit registers that select analog input pins, specify operation modes, and control conversion operation. The ADSCMn0 register can be read/written in 16-bit units. When the higher 8 bits of the ADSCMn0 register are used as the ADSCMn0H register, and the lower 8 bits are used as the ADSCMn0L register, they can be read/written in 8-bit or 1-bit units. However, writing to an ADSCMn0 register during A/D conversion operation initializes conversion operation and starts the conversion over from the beginning. At this time, overwrite the ADSCMn0 register with the same value. If writing a different value, be sure to clear the ADCEn bit to 0 first before overwriting. Caution Before changing the trigger mode by using the ADPLMn and TRG2 to TRG0 bits, clear the ADCEn bit to 0 (n = 0 or 1). The operation is not guaranteed if the trigger mode is changed and the ADCEn bit is cleared at the same time (by the same instruction). Be sure to access the register twice. 646 User's Manual U14492EJ5V0UD CHAPTER 13 A/D CONVERTER (1/2) <15> <14> 13 <12> <11> 10 ADSCM00 ADCE0 ADCS0 0 9 8 7 6 5 4 3 2 1 0 Address FFFFF200H Initial value 0000H ADMS0 ADPLM0 TRG2 TRG1 TRG0 SANI3 SANI2 SANI1 SANI0 ANIS3 ANIS2 ANIS1 ANIS0 <15> <14> 13 <12> <11> 10 ADSCM10 ADCE1 ADCS1 0 9 8 7 6 5 4 3 2 1 0 Address FFFFF240H Initial value 0000H ADMS1 ADPLM1 TRG2 TRG1 TRG0 SANI3 SANI2 SANI1 SANI0 ANIS3 ANIS2 ANIS1 ANIS0 Bit position 15 Bit name ADCEn Function Specifies enabling or disabling A/D conversion. 0: Disable 1: Enable 14 ADCSn Shows status of A/D converter 0 or 1. This bit is read-only. 0: Stopped 1: Operating The ADCSn bit is "0" for the duration of 6 x fXX/2 immediately after the start of A/D conversion, and is then set to "1". In the scan mode, this operation is performed each time the analog input pin to be A/D converted is switched. 12 ADMSn Specifies operation mode of A/D converter 0 or 1. 0: Scan mode 1: Select mode 11 to 8 ADPLMn, TRG2 to TRG0 ADPLMn: Specifies polling mode. TRG2 to TRG0: Specifies trigger mode. ADPLMn 0 0 0 1 TRG2 0 0 1 0 TRG1 0 0 1 0 TRG0 0 1 1 0 Trigger mode A/D trigger mode Timer trigger mode External trigger mode A/D trigger polling mode Setting prohibited Other than above Remark n = 0, 1 User's Manual U14492EJ5V0UD 647 CHAPTER 13 A/D CONVERTER (2/2) Bit position 7 to 4 Bit name SANI3 to SANI0 Function Specifies conversion start analog input pin in scan mode. These bits are ignored in select mode. SANI3 0 0 0 0 0 0 0 0 SANI2 0 0 0 0 1 1 1 1 SANI1 0 0 1 1 0 0 1 1 SANI0 0 1 0 1 0 1 0 1 ANIn0 ANIn1 ANIn2 ANIn3 ANIn4 ANIn5 ANIn6 ANIn7 Scan start analog input pin Other than above Setting prohibited Caution Always set the conversion start analog input pin number that is set by bits SANI3 to SANI0 to a smaller pin number than the conversion termination analog input pin number that is set by bits ANIS3 to ANIS0. 3 to 0 ANIS3 to ANIS0 Specifies analog input pin in select mode. In scan mode, specifies conversion termination analog input pin. ANIS3 0 0 0 0 0 0 0 0 ANIS2 0 0 0 0 1 1 1 1 ANIS1 0 0 1 1 0 0 1 1 ANIS0 0 1 0 1 0 1 0 1 In select mode ANIn0 ANIn1 ANIn2 ANIn3 ANIn4 ANIn5 ANIn6 ANIn7 Setting prohibited In scan mode ANIn0 SANI ANIn1 SANI ANIn2 SANI ANIn3 SANI ANIn4 SANI ANIn5 SANI ANIn6 SANI ANIn7 Other than above Remark SANI < ANInm m = 1 to 7 Remark n = 0, 1 648 User's Manual U14492EJ5V0UD CHAPTER 13 A/D CONVERTER (2) A/D scan mode registers 01 and 11 (ADSCM01, ADSCM11) The ADSCMn1 registers are 16-bit registers that set the conversion time of the A/D converter. The ADSCMn1 register can be read/written in 16-bit units. When the higher 8 bits of the ADSCMn1 register are used as the ADSCMn1H register, and the lower 8 bits are used as the ADSCMn1L register, the ADSCMn1H register can be read/written in 8-bit or 1-bit units, and the ADSCMn1L register is read-only, in 8-bit units. Caution Do not write to the ADSCMn1 registers during A/D conversion operation. performed, conversion operation is suspended and subsequently terminates. If a write is 15 ADSCM01 0 14 0 13 0 12 0 11 0 10 9 8 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Address FFFFF202H Initial value 0000H FR2 FR1 FR0 15 ADSCM11 0 14 0 13 0 12 0 11 0 10 9 8 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Address FFFFF242H Initial value 0000H FR2 FR1 FR0 Bit position 10 to 8 Bit name FR2 to FR0 FR2 FR1 FR0 Specifies conversion time. Function Conversion Clocks Conversion time (s) fXX = 50 MHz fXX = 40 MHz 8.60 6.20 - - - - - - Note fXX = 33 MHz - 7.51 5.33 - - - - - 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 344 248 176 128 104 80 56 Setting prohibited 6.88 - - - - - - - Note This is the time from sampling until conversion termination. Sampling time = (Conversion clocks - 8)/6 x fXX Caution Be sure to secure the conversion time within a range of 5 to 10 s. Conversion time = fXX x Conversion clocks Remark fXX: Internal system clock User's Manual U14492EJ5V0UD 649 CHAPTER 13 A/D CONVERTER (3) A/D voltage detection mode registers 0 and 1 (ADETM0, ADETM1) The ADETMn registers are 16-bit registers that set voltage detection mode. In voltage detection mode, the analog input pin for which voltage detection is being performed and a reference voltage value are compared and an interrupt is set in response to the comparison result. The ADETMn register can be read/written in 16-bit units. When the higher 8 bits of the ADETMn register are used as the ADETMnH register, and the lower 8 bits are used as the ADETMnL register, they can be read/written in 8-bit or 1-bit units. Caution Do not write to an ADETMn register during A/D conversion operation. performed, conversion is suspended and it subsequently terminates. If a write is <15> <14> 13 ADETM0 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF204H Initial value 0000H ADET ADET DET DET DET DET DET DET DET DET DET DET DET DET DET DET EN0 LH0 ANI3 ANI2 ANI1 ANI0 CMP9 CMP8 CMP7 CMP6 CMP5 CMP4 CMP3 CMP2 CMP1 CMP0 <15> <14> 13 ADETM1 12 11 10 9 8 7 6 5 4 3 2 1 0 Address FFFFF244H Initial value 0000H ADET ADET DET DET DET DET DET DET DET DET DET DET DET DET DET DET EN1 LH1 ANI3 ANI2 ANI1 ANI0 CMP9 CMP8 CMP7 CMP6 CMP5 CMP4 CMP3 CMP2 CMP1 CMP0 Bit position 15 Bit name ADETENn Specifies voltage detection mode. 0: Operate in normal mode 1: Operate in voltage detection mode Function 14 ADETLHn Sets voltage comparison detection. 0: Generate INTDETn interrupt if reference voltage value > analog input pin voltage. 1: Generate INTDETn interrupt if reference voltage value analog input pin voltage. Selects analog input pin to compare to reference voltage value set by DETCMP9 to DETCMP0 when in voltage detection mode. 13 to 10 DETANI3 to DETANI0 DETANI3 0 0 0 0 0 0 0 0 1 DETANI2 0 0 0 0 1 1 1 1 x DETANI1 0 0 1 1 0 0 1 1 x DETANI0 0 1 0 1 0 1 0 1 x Voltage detection analog input pin ANIn0 ANIn1 ANIn2 ANIn3 ANIn4 ANIn5 ANIn6 ANIn7 Setting prohibited Remark 9 to 0 DETCMP9 to DETCMP0 x: Arbitrary Sets reference voltage value to compare with analog input pin selected in DETANI3 to DETANI0. Remark n = 0, 1 650 User's Manual U14492EJ5V0UD CHAPTER 13 A/D CONVERTER (4) A/D conversion result registers 00 to 07 and 10 to 17 (ADCR00 to ADCR07, ADCR10 to ADCR17) The ADCR0n and ADCR1n registers are 10-bit registers that hold the results of A/D conversions (n = 0 to 7). One A/D converter is equipped with eight 10-bit registers for 8 channels, and A/D converters 0 and 1 together have sixteen 10-bit registers. These registers are read-only, in 16-bit units. When reading 10 bits of data of an A/D conversion result from an ADCR0n or ADCR1n register, only the lower 10 bits are valid and the higher 6 bits are always read as 0. 15 ADCR0n 0 14 0 13 0 12 0 11 0 10 0 9 8 7 6 5 4 3 2 1 0 Address Initial value 0000H ADCRn9 ADCRn8 ADCRn7 ADCRn6 ADCRn5 ADCRn4 ADCRn3 ADCRn2 ADCRn1 ADCRn0 See Table 13-1 15 ADCR1n 0 14 0 13 0 12 0 11 0 10 0 9 8 7 6 5 4 3 2 1 0 Address Initial value 0000H ADCRn9 ADCRn8 ADCRn7 ADCRn6 ADCRn5 ADCRn4 ADCRn3 ADCRn2 ADCRn1 ADCRn0 See Table 13-2 Table 13-1. Correspondence Between ADCR0n (n = 0 to 7) Register Names and Addresses Register Name ADCR00 ADCR01 ADCR02 ADCR03 ADCR04 ADCR05 ADCR06 ADCR07 Address FFFFF210H FFFFF212H FFFFF214H FFFFF216H FFFFF218H FFFFF21AH FFFFF21CH FFFFF21EH Table 13-2. Correspondence Between ADCR1n (n = 0 to 7) Register Names and Addresses Register Name ADCR10 ADCR11 ADCR12 ADCR13 ADCR14 ADCR15 ADCR16 ADCR17 Address FFFFF250H FFFFF252H FFFFF254H FFFFF256H FFFFF258H FFFFF25AH FFFFF25CH FFFFF25EH User's Manual U14492EJ5V0UD 651 CHAPTER 13 A/D CONVERTER The correspondence between each analog input pin and the ADCR0n and ADCR1n registers is shown below. Table 13-3. Correspondence Between Each Analog Input Pin and ADCR0n and ADCR1n Registers A/D Converter A/D converter 0 Analog Input Pin ANI00 ANI01 ANI02 ANI03 ANI04 ANI05 ANI06 ANI07 A/D converter 1 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 ANI16 ANI17 A/D Conversion Result Register ADCR00 ADCR01 ADCR02 ADCR03 ADCR04 ADCR05 ADCR06 ADCR07 ADCR10 ADCR11 ADCR12 ADCR13 ADCR14 ADCR15 ADCR16 ADCR17 652 User's Manual U14492EJ5V0UD CHAPTER 13 A/D CONVERTER The relationship between the analog voltage input to an analog input pin (ANI0n or ANI1n) and the value of the A/D conversion result register (ADCR0n or ADCR1n) is as follows (n = 0 to 7): VIN ADCR = INT ( AVREF Or, (ADCR - 0.5) x AVREF 1,024 VIN < (ADCR + 0.5) x AVREF 1,024 x 1,024 + 0.5) INT ( ): Function that returns integer of value in ( ) VIN: Analog input voltage AVREF: AVREF0 or AVREF1 pin voltage ADCR: Value of A/D conversion result register (ADCR0n or ADCR1n) Figure 13-3 illustrates the relationship between the analog input voltages and A/D conversion results. Figure 13-3. Relationship Between Analog Input Voltages and A/D Conversion Results 1023 1022 A/D conversion result 1021 (ADCRn) 3 2 1 0 1 1 3 2 5 3 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048 Input voltage/AVREFm Remark m = 0, 1 n = 00 to 07, 10 to 17 User's Manual U14492EJ5V0UD 653 CHAPTER 13 A/D CONVERTER (5) A/D internal trigger selection register (ITRG0) The ITRG0 register is the register that switches the trigger source in timer trigger mode. The timer trigger source of A/D converters 0 and 1 can be set using the ITRG0 register. This register can be read/written in 8-bit or 1-bit units. 7 ITRG0 0 6 ITRG22 5 ITRG21 4 ITRG20 3 0 2 ITRG12 1 ITRG11 0 ITRG10 Address FFFFF280H Initial value 00H Bit position 6 to 4 Bit name ITRG22 to ITRG20 Function Sets timer trigger source of A/D converter 1. ITRG22 0 0 0 0 1 1 1 1 ITRG21 0 0 1 1 x x x x ITRG20 x x 0 1 0 0 1 1 ITRG10 0 1 x x 0 1 0 1 Trigger Source Select INTCM003 Select INTCM013 Select INTTM00 Select INTTM01 Select INTCM003 and INTTM00 Select INTCM013 and INTTM00 Select INTCM003 and INTTM01 Select INTCM013 and INTTM01 Remark 2 to 0 ITRG12 to ITRG10 x: Arbitrary Specifies timer trigger source of A/D converter 0. ITRG12 0 0 0 0 1 1 1 1 ITRG11 0 0 1 1 x x x x ITRG20 x x 0 1 0 0 1 1 ITRG10 0 1 x x 0 1 0 1 Trigger Source Select INTCM003 Select INTCM013 Select INTTM00 Select INTTM01 Select INTCM003 and INTTM00 Select INTCM013 and INTTM00 Select INTCM003 and INTTM01 Select INTCM013 and INTTM01 Remark x: Arbitrary 654 User's Manual U14492EJ5V0UD CHAPTER 13 A/D CONVERTER 13.4 Interrupt Requests A/D converters 0 and 1 generate two kinds of interrupts. * A/D conversion termination interrupts (INTAD0, INTAD1) * Voltage detection interrupts (INTDET0, INTDET1) (1) A/D conversion termination interrupts (INTAD0, INTAD1) In A/D conversion enabled status, an A/D conversion termination interrupt is generated when a specified number of A/D conversions have terminated. A/D Converter 0 1 A/D Conversion Termination Interrupt Signal Generate INTAD0 Generate INTAD1 (2) Voltage detection interrupts (INTDET0, INTDET1) In voltage detection mode (ADETEN0 or ADETEN1 bit of ADETM0 or ADETM1 = 1), the value of the ADCR0n or ADCR1n register of the relevant analog input pin is compared to the reference voltage set in the DETCMP9 to DETCMP0 bits of the ADETM0 or ADETM1 register and a voltage detection interrupt is generated in response to the value of the ADETLH0 or ADETLH1 bit of the ADETM0 or ADETM1 register (n = 0 to 7). A/D Converter 0 1 Voltage Detection Interrupt Signal Generate INTDET0 Generate INTDET1 User's Manual U14492EJ5V0UD 655 CHAPTER 13 A/D CONVERTER 13.5 A/D Converter Operation 13.5.1 A/D converter basic operation A/D conversion is performed using the following procedure. (1) Set the analog input selection and the operation mode and trigger mode specifications using the ADSCM00 or ADSCM10 registerNote 1. Setting (1) the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register when in A/D trigger mode or A/D trigger polling mode starts A/D conversion. In timer trigger mode or external trigger mode, the status becomes trigger standbyNote 2. (2) When A/D conversion starts, compare the analog input to the voltage generated by the D/A converter. (3) When 10-bit comparison terminates, store the conversion result in the ADCR0n or ADCR1n register. When the specified number of A/D conversions have terminated, generate an A/D conversion termination interrupt (INTAD0, INTAD1) (n = 0 to 7). Notes 1. If the ADSCM00 or ADSCM10 register is overwritten with the same value during A/D conversion, the A/D conversion operation preceding the overwrite stops and the conversion result is not stored in the ADCR0n or ADCR1n register. The conversion operation is initialized and conversion starts from the beginning. 2. In timer trigger mode or external trigger mode, there is a transition to trigger standby status when the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register is set to 1. A/D conversion operation is activated by a trigger signal and there is a return to trigger standby status when A/D conversion operation terminates. The timer trigger is selected by the ITRG0 register. 656 User's Manual U14492EJ5V0UD CHAPTER 13 A/D CONVERTER 13.5.2 Operation modes and trigger modes Diverse conversion operations can be specified for A/D converters 0 and 1 by specifying operation modes and trigger modes. Operation modes and trigger modes are set using the ADSCM00 or ADSCM10 register. The relationship between operation modes and trigger modes is shown below. Trigger Mode Operation Mode ADSCM00 AD trigger Select Scan AD trigger polling Select Scan Timer trigger Select Scan External trigger Select Scan XX010000XXXXXXXXB XX000000XXXXXXXXB XX011000XXXXXXXXB XX001000XXXXXXXXB XX010001XXXXXXXXB XX000001XXXXXXXXB XX010111XXXXXXXXB XX000111XXXXXXXXB Setting ADSCM10 XX010000XXXXXXXXB XX000000XXXXXXXXB XX011000XXXXXXXXB XX001000XXXXXXXXB XX010001XXXXXXXXB XX000001XXXXXXXXB XX010111XXXXXXXXB XX000111XXXXXXXXB (1) Trigger modes The four trigger modes that serve as the start timing of A/D conversion processing are available: A/D trigger mode, A/D trigger polling mode, timer trigger mode, and external trigger mode. These trigger modes are set using the ADSCM00 and ADSCM10 registers. (a) A/D trigger mode A/D trigger mode, which starts the conversion timing of the analog input set for the ANI0n or ANI1n pin (n = 0 to 7), is a mode that starts A/D conversion by setting the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register to 1. In this mode, it is necessary to set the ADCE0 or ADCE1 bit to 1 as an A/D conversion restart operation after an INTAD0 or INTAD1 interrupt (ADCS0 or ADCS1 = 0). (b) A/D trigger polling mode A/D trigger polling mode, which starts the conversion timing of the analog input set for the ANI0n or ANI1n pin (n = 0 to 7), is a mode that starts A/D conversion by setting the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register to 1. In this mode, it is not necessary to set the ADCE0 or ADCE1 bit to 1 as an A/D conversion restart operation after an INTAD0 or INTAD1 interrupt (ADCS0 or ADCS1 = 1). The specified analog input is converted serially until the ADCE0 or ADCE1 bit is set to 0. An INTAD0 or INTAD1 interrupt occurs each time a conversion terminates. (c) Timer trigger mode Timer trigger mode, which starts the conversion timing of the analog input set for the ANI0n or ANI1n pin (n = 0 to 7), is a mode governed by a trigger specified in the A/D internal trigger selection register 0 (ITRG0). (d) External trigger mode External trigger mode, which starts the conversion timing of the analog input set for the ANI0n or ANI1n pin, is a mode specified using the ADTRG0 or ADTRG1 pin. User's Manual U14492EJ5V0UD 657 CHAPTER 13 A/D CONVERTER (2) Operation modes The two operation modes, which are the modes that set the ANI00 to ANI07 and ANI10 to ANI17 pins, are select mode and scan mode. These modes are set using the ADSCM00 and ADSCM10 registers. (a) Select mode Select mode A/D converts one analog input specified in the ADSCM00 or ADSCM10 register. It stores the conversion result in the ADCR0n or ADCR1n register corresponding to the analog input (ANI1n or ANI0n) (n = 0 to 7). Figure 13-4. Example of Select Mode Operation Timing (ANI01): For A/D Converter 0 ANI01 (input) Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 A/D conversion Data 1 (ANI01) Data 2 (ANI01) Data 3 (ANI01) Data 4 (ANI01) Data 5 (ANI01) Data 6 (ANI01) Data 7 (ANI01) ADCR01 register Data 1 (ANI01) Data 2 (ANI01) Data 3 (ANI01) Data 4 (ANI01) Data 6 (ANI01) INTAD0 interrupt Conversion start (ADSCM0 register setting) ADCE0 bit set ADCE0 bit set ADCE0 bit set ADCE0 Conversion start ADCE0 bit set (ADSCM0 bit set register setting) Analog input ANI00 ANI01 ANI02 ANI03 ANI04 ANI05 ANI06 ANI07 AD converter 0 ADCR0n register ADCR00 ADCR01 ADCR02 ADCR03 ADCR04 ADCR05 ADCR06 ADCR07 658 User's Manual U14492EJ5V0UD CHAPTER 13 A/D CONVERTER (b) Scan mode Scan mode sequentially selects and A/D converts pins from the A/D conversion start analog input pin through the A/D conversion termination analog input pin specified in the ADSCM00 or ADSCM10 register. It stores the A/D conversion result in the ADCR0n or ADCR1n register corresponding to the analog input (n = 0 to 7). When the specified analog input conversion terminates, there is an A/D conversion termination interrupt (INTAD0 or INTAD1). Figure 13-5. Example of Scan Mode Operation Timing: For A/D Converter 0 (4-Channel Scan (ANI00 to ANI03)) ANI00 (input) Data 1 ANI01 (input) Data 2 ANI02 (input) ANI03 (input) A/D conversion Data 1 (ANI00) Data 2 (ANI01) Data 3 (ANI02) Data 6 Data 5 Data 3 Data 4 Data 4 (ANI03) Data 5 (ANI00) Data 6 (ANI01) ADCR0n register Data 1 Data 2 Data 3 (ANI00) (ANI01) (ANI02) ADCR00 ADCR01 ADCR02 Data 4 (ANI03) ADCR03 Data 5 (ANI00) ADCR00 INTAD0 interrupt Conversion start (ADSCM00 register setting) Conversion start (ADSCM00 register setting) Analog input ANI00 ANI01 ANI02 ANI03 ANI04 ANI05 ANI06 ANI07 A/D converter 0 ADCR0n register ADCR00 ADCR01 ADCR02 ADCR03 ADCR04 ADCR05 ADCR06 ADCR07 User's Manual U14492EJ5V0UD 659 CHAPTER 13 A/D CONVERTER 13.6 Operation in A/D Trigger Mode Setting the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register to 1 starts A/D conversion. 13.6.1 Operation in select mode One analog input specified in the ADSCM00 or ADSCM10 register is A/D converted at a time and the result is stored in an ADCR0n or ADCR1n register. Analog inputs correspond one-to-one with ADCR0n or ADCR1n registers (n = 0 to 7). An A/D conversion termination interrupt (INTAD0, INTAD1) is generated for each A/D conversion termination, which terminates A/D conversion (ADCS0 or ADCS1 bit = 0). Analog Input ANIx A/D Conversion Result Register ADCRx Remark x = 00 to 07, 10 to 17 To restart A/D conversion, write 1 in the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register. This is optimal for an application that reads a result for each A/D conversion. Figure 13-6. Example of Select Mode (A/D Trigger Select) Operation (ANI02): For A/D Converter 0 ADSCM00 ANI00 ANI01 ANI02 ANI03 ANI04 ANI05 ANI06 ANI07 A/D converter 0 ADCR00 ADCR01 ADCR02 ADCR03 ADCR04 ADCR05 ADCR06 ADCR07 (1) ADCE0 bit of ADSCM00 = 1 (Enabled) (2) A/D conversion of ANI02 (3) Store conversion result in ADCR02 (4) Generate INTAD0 interrupt 660 User's Manual U14492EJ5V0UD CHAPTER 13 A/D CONVERTER 13.6.2 Operation in scan mode Pins from the conversion start analog input pin through the conversion termination analog input pin specified in the ADSCM00 or ADSCM10 register are sequentially selected and A/D converted. An A/D conversion result is stored in the ADCR0n or ADCR1n register corresponding to the analog input (n = 0 to 7). When conversion terminates for all analog inputs through the conversion termination analog input pin, an A/D conversion termination interrupt (INTAD0, INTAD1) is generated, which terminates A/D conversion (ADCS0 or ADCS1 bit of ADSCM0 or ADSCM1 register = 0). Analog Input ANIx | ANIx Note 2 Note 1 A/D Conversion Result Register ADCRx | ADCRx Notes 1. Set using SANI3 to SANI0 bits of ADSCM00 or ADSCM10 register. Be sure to set a pin number that is smaller than the conversion termination analog input pin number set according to Note 2. 2. Remark Set using ANIS3 to ANIS0 bits of ADSCM00 or ADSCM10 register. x = 00 to 07, 10 to 17 To restart A/D conversion, write 1 in the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register. This is optimal for an application that regularly monitors multiple analog inputs. Figure 13-7. Example of Scan Mode (A/D Trigger Scan) Operation (ANI02 to ANI05): For A/D Converter 0 ADSCM00 ANI00 ANI01 ANI02 ANI03 ANI04 ANI05 ANI06 ANI07 A/D converter 0 ADCR00 ADCR01 ADCR02 ADCR03 ADCR04 ADCR05 ADCR06 ADCR07 (6) A/D conversion of ANI04 (7) Store conversion result in ADCR04 (8) A/D conversion of ANI05 (9) Store conversion result in ADCR05 (10) Generate INTAD0 interrupt (1) ADCE0 bit of ADSCM00 = 1 (Enabled) (2) A/D conversion of ANI02 (3) Store conversion result in ADCR02 (4) A/D conversion of ANI03 (5) Store conversion result in ADCR03 User's Manual U14492EJ5V0UD 661 CHAPTER 13 A/D CONVERTER 13.7 Operation in A/D Trigger Polling Mode Setting the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register to 1 starts A/D conversion. Both select mode and scan mode are available in A/D trigger polling mode. Since the ADCS0 or ADCS1 bit of the ADSCM00 or ADSCM10 register remains 1 after an INTAD0 or INTAD1 interrupt in this mode, it is not necessary to write 1 in the ADCE0 or ADCE1 bit as an A/D conversion restart operation. 13.7.1 Operation in select mode The analog input specified in the ADSCM00 or ADSCM10 register is A/D converted. The conversion result is stored in the ADCR0n or ADCR1n register (n = 0 to 7). One analog input is A/D converted at a time and the result is stored in one ADCR0n or ADCR1n register. Analog inputs correspond one-to-one with ADCR0n or ADCR1n register. An A/D conversion termination interrupt (INTAD0 or INTAD1) is generated for each A/D conversion termination. A/D conversion operation is repeated until the ADCE0 or ADCE1 bit = 0 (ADCS0 or ADCS1 bit = 1). Analog Input ANIx A/D Conversion Result Register ADCRx Remark x = 00 to 07, 10 to 17 In A/D trigger polling mode, it is not necessary to write 1 in the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register as an A/D conversion restart operationNote. This is optimal for applications that regularly read A/D conversion values. Note In A/D trigger polling mode, the fact that the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register is 0 means that A/D conversion operation does not stop as long as the ADCS0 or ADCS1 bit is not 0. Therefore, if the ADCR0n or ADCR1n register is not read before the next A/D conversion, it is overwritten. Figure 13-8. Example of Select Mode (A/D Trigger Polling Select) Operation (ANI02): For A/D Converter 0 ADSCM00 ANI00 ANI01 ANI02 ANI03 ANI04 ANI05 ANI06 ANI07 A/D converter 0 ADCR00 ADCR01 ADCR02 ADCR03 ADCR04 ADCR05 ADCR06 ADCR07 (4) Generate INTAD0 interrupt (5) Return to (2) (1) ADCE0 bit of ADSCM00 = 1 (Enabled) (2) A/D conversion of ANI02 (3) Store conversion result in ADCR02 662 User's Manual U14492EJ5V0UD CHAPTER 13 A/D CONVERTER 13.7.2 Operation in scan mode Pins from the conversion start analog input pin through the conversion termination analog input pin specified in the ADSCM00 or ADSCM10 register are sequentially selected and A/D converted. An A/D conversion result is stored in the ADCR0n or ADCR1n register corresponding to the analog input (n = 0 to 7). When conversion terminates for all analog inputs through the conversion termination analog input pin, an A/D conversion termination interrupt (INTAD0, INTAD1) is generated. A/D conversion operation repeats until the ADCE0 or ADCE1 bit = 0 (ADCS0 or ADCS1 bit = 1). Analog Input ANIx | ANIx Note 2 Note 1 A/D Conversion Result Register ADCRx | ADCRx Notes 1. Set using SANI3 to SANI0 bits of ADSCM00 or ADSCM10 register. Be sure to set a pin number that is smaller than the conversion termination analog input pin number set according to Note 2. 2. Remark Set using ANIS3 to ANIS0 bits of ADSCM00 or ADSCM10 register. x = 00 to 07, 10 to 17 It is not necessary to write 1 in the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register as an A/D conversion restart operation in A/D trigger polling modeNote. This is optimal for applications that regularly read A/D conversion values. Note In A/D trigger polling mode, the fact that the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register is 0 means that A/D conversion operation does not stop as long as the ADCS0 or ADCS1 bit is not 0. Therefore, if the ADCR0n or ADCR1n register is not read before the next A/D conversion, it is overwritten. Figure 13-9. Example of Scan Mode (A/D Trigger Polling Scan) Operation (ANI02 to ANI05) : For A/D Converter 0 ADSCM00 ANI00 ANI01 ANI02 ANI03 ANI04 ANI05 ANI06 ANI07 A/D converter 0 ADCR00 ADCR01 ADCR02 ADCR03 ADCR04 ADCR05 ADCR06 ADCR07 (7) Store conversion result in ADCR04 (8) A/D conversion of ANI05 (9) Store conversion result in ADCR05 (10) Generate INTAD0 interrupt (11) Return to (2) (1) ADCE0 bit of ADSCM00 = 1 (Enabled) (2) A/D conversion of ANI02 (3) Store conversion result in ADCR02 (4) A/D conversion of ANI03 (5) Store conversion result in ADCR03 (6) A/D conversion of ANI04 User's Manual U14492EJ5V0UD 663 CHAPTER 13 A/D CONVERTER 13.8 Operation in Timer Trigger Mode The A/D converter can set an interrupt signal specified by the A/D internal trigger selection register 0 (ITRG0) as a conversion trigger for up to 8 channels (a total of 16 channels in 2 circuits) of analog input (ANI00 to ANI07, ANI10 to ANI17). The four interrupt signals that can be selected as triggers are the TM0n timer 0 register underflow interrupt signals (INTTM00 and INTTM01) and the CM003 and CM013 match interrupt signals (INTCM003 and INTCM013) (n = 0, 1). 13.8.1 Operation in select mode Taking the interrupt signal specified by the A/D internal trigger selection register 0 (ITRG0) as a trigger, one analog input (ANI00 to ANI07, ANI10 to ANI17) specified by the ADSCM00 or ADSCM10 register is A/D converted once. The conversion result is stored in the ADCR0n or ADCR1n register corresponding to the analog input (n = 0 to 7). An A/D conversion termination interrupt (INTAD0 or INTAD1) is generated for each A/D conversion, which terminates A/D conversion (ADCS0 or ADCS1 = 0). This is optimal for applications that read A/D conversion values synchronized to a timer trigger. Trigger Interrupt specified by ITRG0 register ANIx Analog Input A/D Conversion Result Register ADCRx Remark x = 00 to 07, 10 to 17 After A/D conversion termination, A/D converter 0 or 1 changes to trigger wait status (ADCE0 or ADCE1 = 1). It performs A/D conversion operation again when the interrupt signal specified in the ITRG0 register occurs. Figure 13-10. Example of Timer Trigger Select Mode Operation (ANI04): For A/D Converter 0 (a) When selecting INTTM00 by ITRG0 register ANI00 ANI01 INTTM00 ANI02 ANI03 ANI04 ANI05 ANI06 ANI07 (1) ADCE0 bit of ADSCM00 = 1 (Enabled) (2) INTTM00 interrupt generation (3) A/D conversion of ANI04 A/D converter 0 ADCR00 ADCR01 ADCR02 ADCR03 ADCR04 ADCR05 ADCR06 ADCR07 (4) Store conversion result in ADCR04 (5) INTAD0 interrupt generation 664 User's Manual U14492EJ5V0UD CHAPTER 13 A/D CONVERTER 13.8.2 Operation in scan mode Using the interrupt signal specified by the A/D internal trigger selection register 0 (ITRG0) as a trigger, the conversion start analog input pin through the conversion termination analog input pin specified by the ADSCM00 or ADSCM10 register are sequentially selected and A/D converted. Conversion results are stored in the ADCR0n or ADCR1n registers corresponding to the analog inputs. When all of the specified A/D conversions terminate, an A/D conversion termination interrupt (INTAD0 or INTAD1) is generated, which terminates A/D conversion (ADCS0 or ADCS1 = 0). This is optimal for applications that regularly monitor multiple analog inputs in synchronization with a timer trigger. Trigger Interrupt specified by ITRG0 register ANIn0 ANIn1 ANIn2 ANIn3 ANIn4 ANIn5 ANIn6 ANIn7 Analog Input A/D Conversion Result Register ADCRn0 ADCRn1 ADCRn2 ADCRn3 ADCRn4 ADCRn5 ADCRn6 ADCRn7 Remark n = 0, 1 After all of the specified A/D conversions terminate, the A/D converter changes to trigger wait status (ADCE0 or ADCE1 = 1). It performs A/D conversion operation again when the interrupt signal specified in the ITRG0 register occurs. Figure 13-11. Example of Timer Trigger Scan Mode Operation (For A/D Converter 0) : INTTM00 Selected by ITRG0 Register (a) Set to scan ANI01 to ANI04 ANI00 ANI01 INTM00 ANI02 ANI03 ANI04 ANI05 ANI06 ANI07 (1) ADCE0 bit of ADSCM00 = 1 (Enabled) (2) INTTM00 interrupt generation (3) A/D conversion of ANI01 (4) Store conversion result in ADCR01 (5) A/D conversion of ANI02 (6) Store conversion result in ADCR02 (7) A/D conversion of ANI03 (8) Store conversion result in ADCR03 (9) A/D conversion of ANI04 (10) Store conversion result in ADCR04 (11) INTAD0 interrupt generation A/D converter 0 ADCR00 ADCR01 ADCR02 ADCR03 ADCR04 ADCR05 ADCR06 ADCR07 User's Manual U14492EJ5V0UD 665 CHAPTER 13 A/D CONVERTER 13.9 Operation in External Trigger Mode In external trigger mode, analog input (ANI00 to ANI07, ANI10 to ANI17) is A/D converted on ADTRG0 or ADTRG1 pin input timing. The valid edge of an external input signal in external trigger mode can be specified as a rising edge, a falling edge, or a rising or falling edge in the ES21 or ES20 bit of the INTM1 register for A/D converter 0 and in the ES31 or ES30 bit of the INTM1 register for A/D converter 1. 13.9.1 Operation in select mode One analog input (ANI00 to ANI07, ANI10 to ANI17) specified by the ADSCM00 or ADSCM10 register is A/D converted. The conversion result is stored in the ADCR0n or ADCR1n register (n = 0 to 7). Using an ADTRG0 or ADTRG1 signal as a trigger, one analog input at a time is A/D converted and the result is stored in one ADCR0n or ADCR1n register. Analog inputs correspond one-to-one with A/D conversion result registers. For each A/D conversion, an A/D conversion termination interrupt (INTAD0 or INTAD1) is generated, which terminates A/D conversion (ADCS0 or ADCS1 bit = 0). Trigger ADTRGm signal ANImn Analog Input A/D Conversion Result Register ADCRmn Remark m = 0, 1 n = 0 to 7 To restart A/D conversion, a trigger must be input again from the ADTRGn pin (n = 0, 1). This is optimal for applications that read results each time there is an A/D conversion in synchronization with an external trigger. Figure 13-12. Example of Select Mode (External Trigger Select) Operation (ANI02): For A/D Converter 0 ANI00 ANI01 ADTRG0 ANI02 ANI03 ANI04 ANI05 ANI06 ANI07 (1) ADCE0 bit of ADSCM00 = 1 (Enabled) (2) External trigger generation (3) A/D conversion of ANI02 (4) Store conversion result in ADCR02 (5) INTAD0 interrupt generation A/D converter 0 ADCR00 ADCR01 ADCR02 ADCR03 ADCR04 ADCR05 ADCR06 ADCR07 666 User's Manual U14492EJ5V0UD CHAPTER 13 A/D CONVERTER 13.9.2 Operation in scan mode Using an ADTRG0 or ADTRG1 signal as a trigger, pins from the conversion start analog input pin through the conversion termination analog input pin specified by the ADSCM00 or ADSCM10 register are sequentially selected and A/D converted. A/D conversion results are stored in the ADCR0n or ADCRN1n registers corresponding to the analog inputs (n = 0 to 7). When conversion terminates for all of the specified analog inputs, an INTAD0 or INTAD1 interrupt is generated, which terminates A/D conversion (ADCS0 or ADCS1 = 0). Trigger ADTRGn signal ANIn0 ANIn1 ANIn2 ANIn3 ANIn4 ANIn5 ANIn6 ANIn7 Analog Input A/D Conversion Result Register ADCRn0 ADCRn1 ADCRn2 ADCRn3 ADCRn4 ADCRn5 ADCRn6 ADCRn7 Remark n = 0, 1 After all specified A/D conversions terminate, A/D conversion is restarted when an external trigger signal occurs. This is optimal for applications that regularly monitor multiple analog inputs in synchronization with an external trigger. Figure 13-13. Example of Scan Mode (External Trigger Scan) Operation: For A/D Converter 0 (a) When setting to scan ANI01 to ANI04 ANI00 ANI01 ANI02 ADTRG0 ANI03 ANI04 ANI05 ANI06 ANI07 (1) ADCE0 bit of ADSCM00 = 1 (Enabled) (2) External trigger generation (3) A/D conversion of ANI01 (4) Store conversion result in ADCR01 (5) A/D conversion of ANI02 (6) Store conversion result in ADCR02 (7) A/D conversion of ANI03 (8) Store conversion result in ADCR03 (9) A/D conversion of ANI04 (10) Store conversion result in ADCR04 (11) INTAD0 interrupt generation A/D converter 0 ADCR00 ADCR01 ADCR02 ADCR03 ADCR04 ADCR05 ADCR06 ADCR07 User's Manual U14492EJ5V0UD 667 CHAPTER 13 A/D CONVERTER 13.10 Precautions on Operation 13.10.1 Stopping A/D conversion operation If 0 is written in the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register during A/D conversion operation, it stops A/D conversion operation and an A/D conversion result is not stored in the ADCR0n or ADCR1n register (n = 0 to 7). 13.10.2 Trigger input during A/D conversion operation If a trigger is input during A/D conversion operation, that trigger input is ignored. 13.10.3 External or timer trigger interval Make the trigger interval (input time interval) in external or timer trigger mode longer than the conversion time specified by the FR2 to FR0 bits of the ADSCM01 or ADSCM11 register. (1) When interval = 0 If multiple triggers are input simultaneously, they are processed as one trigger signal. (2) When 0 < interval < conversion time If an external or timer trigger is input during A/D conversion operation, that trigger input is ignored. (3) When interval = conversion time If an external or timer trigger is input at the same time as A/D conversion termination (comparison termination signal and trigger contention), interrupt generation and ADCR0n or ADCR1n register storage of the value with which conversion terminated are performed correctly (n = 0 to 7). 13.10.4 Operation in standby modes (1) HALT mode A/D conversion operation is suspended. If released by NMI or maskable interrupt input, the ADSCM00, ADSCM10, ADSCM01, or ADSCM11 register and ADCR0n or ADCR1n register maintain their values (n = 0 to 7). If released by RESET input, the ADCR0n or ADCR1n register is initialized. (2) IDLE mode, software STOP mode Since clock supply to A/D converter 0 or 1 stops, A/D conversion operation is not performed. If released by NMI or maskable interrupt input, the ADSCM00, ADSCM10, ADSCM01, or ADSCM11 register and ADCR0n or ADCR1n register maintain their values (n = 0 to 7). However, if IDLE mode or software STOP mode is set during A/D conversion operation, A/D conversion operation stops. If released by RESET input, the ADCR0n or ADCR1n register is initialized. 668 User's Manual U14492EJ5V0UD CHAPTER 13 A/D CONVERTER 13.10.5 Compare match interrupt in timer trigger mode A TM0n timer 0 register underflow interrupt (INTTM00 or INTTM01) and CM003 or CM013 interrupt (INTCM003 or INTCM013) is an A/D conversion start trigger that starts conversion operation (n = 0, 1). At this time, the CM003 or CM013 match interrupt (INTCM003 or INTCM013) also functions as a compare register match interrupt for the CPU. In order not to generate these match interrupts for the CPU, disable interrupts using the mask bits (TM0MK0, TM0MK1, CM03MK0, CM03MK1) of the interrupt control registers (TM0IC0, TM0IC1, CM03IC0, CM03IC1). 13.10.6 Timing that makes the A/D conversion result undefined If the timing of the end of A/D conversion and the timing of the stop of operation of the A/D converter conflict, the A/D conversion value may be undefined. Because of this, be sure to read the A/D conversion result while the A/D converter is in operation. Furthermore, when reading an A/D conversion result after the A/D converter operation has stopped, be sure to have done so by the time the next conversion result is complete. The conversion result read timing is shown in Figures 13-14 and 13-15 below. Figure 13-14. Conversion Result Read Timing (When Conversion Result Is Undefined) A/D conversion end A/D conversion end ADCRnm Normal conversion result Undefined value INTADn ADCEn Normal conversion result read A/D operation stopped Undefined value read Remark n = 0, 1, m = 0 to 7 Figure 13-15. Conversion Result Read Timing (When Conversion Result Is Normal) A/D conversion end ADCRnm Normal conversion result INTADn ADCEn A/D operation stopped Normal conversion result read Remark n = 0, 1, m = 0 to 7 User's Manual U14492EJ5V0UD 669 CHAPTER 13 A/D CONVERTER 13.11 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). %FSR indicates the ratio of analog input voltage that can be converted as a percentage, and is always represented by the following formula regardless of the resolution. 1%FSR = (Max. value of analog input voltage that can be converted - Min. value of analog input voltage that can be converted)/100 = (AVREFn - 0)/100 = AVREFn/100 Remark n = 0, 1 1LSB is as follows when the resolution is 10 bits. 1LSB = 1/210 = 1/1024 = 0.098 %FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. It is a total of zero-scale error, full-scale error, linearity error, and a combination of these errors. Note that the quantization error is not included in the overall error in the characteristics table. Figure 13-16. Overall Error 1......1 Ideal line Digital output Overall error 0......0 0 Analog input AVREFn (n = 0, 1) 670 User's Manual U14492EJ5V0UD CHAPTER 13 A/D CONVERTER (3) Quantization error When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 13-17. Quantization Error 1......1 Digital output 1/2LSB Quantization error 1/2LSB 0......0 0 Analog input AVREFn (n = 0, 1) (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0......000 to 0......001. Figure 13-18. Zero-Scale Error 111 Digital output (Lower 3 bits) Ideal line 100 Zero-scale error 011 010 001 000 -1 0 1 2 3 Analog input (LSB) AVREFn (n = 0, 1) User's Manual U14492EJ5V0UD 671 CHAPTER 13 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (full scale - 3/2LSB) when the digital output changes from 1......110 to 1......111. Figure 13-19. Full-Scale Error Full-scale error Digital output (Lower 3 bits) 111 100 011 010 000 -0 AVREFn-3 AVREFn-2 AVREFn-1 AVREFn (n = 0, 1) Analog input (LSB) (6) Differential linearity error While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and the ideal value. Figure 13-20. Differential Linearity Error 1......1 Ideal 1LSB width Digital output Differential linearity error 0......0 0 Analog input AVREFn (n = 0, 1) 672 User's Manual U14492EJ5V0UD CHAPTER 13 A/D CONVERTER (7) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0. Figure 13-21. Integral Linearity Error 1......1 Ideal line Digital output 0......0 0 Integral linearity error AVREFn (n = 0, 1) Analog input (8) Conversion time This expresses the time from when a trigger was generated to the time when the digital output was obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Figure 13-22. Sampling Time Sampling time Conversion time User's Manual U14492EJ5V0UD 673 CHAPTER 14 PORT FUNCTIONS 14.1 Features * Input dedicated ports : 8 I/O ports: 75 * Ports alternate as I/O pins of other peripheral functions * Input or output can be specified in bit units 14.2 Basic Configuration of Ports The V850E/IA1 has a total of 83 on-chip input/output ports (ports 0 to 4, DH, DL, CS, CT, CM), of which 8 are input-only ports. The port configuration is shown below. P00 Port 0 P07 PDH0 Port DH PDH7 P10 Port 1 P15 PDL0 Port DL PDL15 P20 Port 2 P27 PCS0 Port CS PCS7 P30 Port 3 P37 PCT0 Port CT PCT7 P40 Port 4 P47 PCM0 Port CM PCM4 (1) Functions of each port The V850E/IA1 has the ports shown below. Any port can operate in 8-bit or 1-bit units and can provide a variety of controls. Moreover, besides its function as a port, each has functions as the I/O pins of on-chip peripheral I/O in control mode. Refer to (3) Port block diagrams for a block diagram of the block type of each port. 674 User's Manual U14492EJ5V0UD CHAPTER 14 PORT FUNCTIONS Port Name Port 0 Pin Name P00 to P07 Port Function 8-bit input Function in Control Mode NMI input, timer/counter output stop signal input, external interrupt input, A/D converter (ADC) external trigger input F Block Type Port 1 P10 to P15 6-bit I/O Timer/counter I/O External interrupt input Timer/counter I/O External interrupt input B, N Port 2 P20 to P27 8-bit I/O B, N Port 3 Port 4 Port DH Port DL Port CS Port CT Port CM P30 to P37 P40 to P47 PDH0 to PDH7 PDL0 to PDL15 PCS0 to PCS7 PCT0 to PCT7 PCM0 to PCM4 8-bit I/O 8-bit I/O 8-bit I/O 16-bit I/O 8-bit I/O 8-bit I/O 5-bit I/O Serial interface I/O (UART0 to UART2) Serial interface I/O (CSI0, CSI1, FCAN) External address bus (A16 to A23) External address/data bus (AD0 to AD15) External bus interface control signal output External bus interface control signal output Wait insertion signal input, internal system clock output, external bus interface control signal I/O A, C, G, H, M A, C, M P O J E, J D, E, J Cautions 1. When switching to the control mode, be sure to set ports that operate as output pins or I/O pins in the control mode using the following procedure. <1> Set the inactive level for the signal output in the control mode in the corresponding bits of port n (n = 0 to 4, CM, CS, CT, DH, and DL). <2> Switch to the control mode using the port n mode control register (PMCn). If <1> above is not performed, the contents of port n may be output for a moment when switching from the port mode to the control mode. 2. When port manipulation is performed by a bit manipulation instruction (SET1, CLR1, or NOT1), perform byte data read for the port and process the data of only the bits to be manipulated, and write the byte data after conversion back to the port. For example, in ports in which input and output are mixed, because the contents of the output latch are overwritten to bits other than the bits for manipulation, the output latch of the input pin becomes undefined (in the input mode, however, the pin status does not change because the output buffer is off). Therefore, when switching the port from input to output, set the output expected value to the corresponding bit, and then switch to the output port. This is the same as when the control mode and output port are mixed. 3. The state of the port pin can be read by setting the port n mode register (PMn) to the input mode regardless of the settings of the PMCn register. When the PMn register is set to the output mode, the value of the port n register (Pn) can be read in the port mode while the output state of the alternate function can be read in the control mode. User's Manual U14492EJ5V0UD 675 CHAPTER 14 PORT FUNCTIONS (2) Functions of each port pin after reset and registers that set port or control mode Port Name Pin Name Single-Chip Mode 0 Port 0 P00/NMI P01/ESO0/INTP0 P02/ESO1/INTP1 P03/ADTRG0/INTP2 P04/ADTRG1/INTP3 P05/INTP4 P06/INTP5 P07/INTP6 Port 1 P10/TIUD10/TO10 P11/TCUD10/INTP100 P12/TCLR10/INTP101 P13/TIUD11/TO11 P14/TCUD11/INTP110 P15/TCLR11/INTP111 Port 2 P20/TI2/INTP20 P21/TO21/INTP21 P22/TO22/INTP22 P23/TO23/INTP23 P24/TO24/INTP24 P25/TCLR2/INTP25 P26/TI3/TCLR3/INTP30 P27/TO3/INTP31 Port 3 P30/RXD0 P31/TXD0 P32/RXD1 P33/TXD1 P34/ASCK1 P35/RXD2 P36/TXD2 P37/ASCK2 Pin Function After Reset Single-Chip Mode 1 ROMless Mode 0 ROMless Mode 1 - Mode-Setting Register P00 (Input mode) P01 (Input mode) P02 (Input mode) P03 (Input mode) P04 (Input mode) P05 (Input mode) P06 (Input mode) P07 (Input mode) P10 (Input mode) P11 (Input mode) P12 (Input mode) P13 (Input mode) P14 (Input mode) P15 (Input mode) P20 (Input mode) P21 (Input mode) P22 (Input mode) P23 (Input mode) P24 (Input mode) P25 (Input mode) P26 (Input mode) P27 (Input mode) P30 (Input mode) P31 (Input mode) P32 (Input mode) P33 (Input mode) P34 (Input mode) P35 (Input mode) P36 (Input mode) P37 (Input mode) PMC2 PMC2 PMC1, PFC1 PMC1 PMC1, PFC1 PMC1 PMC2, PFC2 PMC2, PFC2 PMC3 676 User's Manual U14492EJ5V0UD CHAPTER 14 PORT FUNCTIONS Port Name Pin Name Single-Chip Mode 0 Pin Function After Reset Single-Chip Mode 1 ROMless Mode 0 ROMless Mode 1 Mode-Setting Register Port 4 P40/SI0 P41/SO0 P42/SCK0 P43/SI1 P44/SO1 P45/SCK1 P46/CRXD P47/CTXD P40 (Input mode) P41 (Input mode) P42 (Input mode) P43 (Input mode) P44 (Input mode) P45 (Input mode) P46 (Input mode) P47 (Input mode) PCM0 (Input mode) WAIT PMC4 Port CM PCM0/WAIT PMCCM PCM1/CLKOUT PCM1 (Input mode) CLKOUT PCM2/HLDAK PCM2 (Input mode) PCM3 (Input mode) HLDAK PCM3/HLDRQ HLDRQ - PMCCT PCM4 Port CT PCT0/LWR PCM4 (Input mode) PCT0 (Input mode) LWR PCT1/UWR PCT1 (Input mode) UWR - PCT2 PCT3 PCT4/RD PCT2 (Input mode) PCT3 (Input mode) PCT4 (Input mode) RD PMCCT - PMCCT - PMCCS PCT5 PCT6/ASTB PCT5 (Input mode) PCT6 (Input mode) ASTB PCT7 Port CS PCS0/CS0 to PCS7/CS7 PCT7 (Input mode) PCS0 to PCS7 (Input mode) CS0 to CS7 Port DH PDH0/A16 to PDH7/A23 PDH0 to PDH7 (Input mode) A16 to A23 PMCDH Port DL PDL0/AD0 to PDL15/AD15 PDL0 to PDL15 (Input mode) AD0 to AD15 PMCDL User's Manual U14492EJ5V0UD 677 CHAPTER 14 PORT FUNCTIONS (3) Port block diagrams Figure 14-1. Type A Block Diagram WRPMC PMCmn WRPM PMmn Internal bus WRPORT Selector Output signal in control mode Pmn Pmn Selector RDIN Address Remark m: Port number n: Bit number 678 User's Manual U14492EJ5V0UD Selector CHAPTER 14 PORT FUNCTIONS Figure 14-2. Type B Block Diagram WRPMC PMCmn WRPM PMmn Internal bus WRPORT Pmn Pmn Selector Address RDIN Input signal in control mode Noise elimination Edge detection Remark m: Port number n: Bit number Selector User's Manual U14492EJ5V0UD 679 CHAPTER 14 PORT FUNCTIONS Figure 14-3. Type C Block Diagram WRPMC PMCmn WRPM PMmn Internal bus WRPORT Pmn Pmn Selector Address RDIN Input signal in control mode Remark m: Port number n: Bit number 680 User's Manual U14492EJ5V0UD Selector CHAPTER 14 PORT FUNCTIONS Figure 14-4. Type D Block Diagram WRPMC MODE0 to MODE2 PMCmn WRPM PMmn Internal bus WRPORT Pmn Pmn Selector Address RDIN Input signal in control mode Remark m: Port number n: Bit number Figure 14-5. Type E Block Diagram WRPM PMmn Internal bus WRPORT Pmn Pmn Selector Address RDIN Remark m: Port number n: Bit number User's Manual U14492EJ5V0UD Selector Selector 681 CHAPTER 14 PORT FUNCTIONS Figure 14-6. Type F Block Diagram Selector Internal bus 1 Noise elimination Pmn RDIN Input signal in control mode Address Edge detection Figure 14-7. Type G Block Diagram WRPMC PMCmn WRPM Internal bus PMmn WRPORT Selector Output signal in control mode Pmn Pmn Selector RDIN Address Remark m: Port number n: Bit number 682 User's Manual U14492EJ5V0UD Selector CHAPTER 14 PORT FUNCTIONS Figure 14-8. Type H Block Diagram WRPMC PMCmn WRPM Internal bus PMmn WRPORT Pmn Pmn Selector Address RDIN Input signal in control mode Remark m: Port number n: Bit number Selector User's Manual U14492EJ5V0UD 683 CHAPTER 14 PORT FUNCTIONS Figure 14-9. Type J Block Diagram MODE0 to MODE2 WRPMC PMCmn WRPM PMmn Internal bus WRPORT Selector Output signal in control mode Pmn Pmn Selector RDIN Address Remark m: Port number n: Bit number 684 User's Manual U14492EJ5V0UD Selector CHAPTER 14 PORT FUNCTIONS Figure 14-10. Type M Block Diagram WRPMC PMCmn WRPM PMmn SCKx, ASCKy output enable signal Internal bus Selector WRPORT Output signal in control mode Pmn Pmn Selector Address RDIN Input signal in control mode Remark mn: 34, 37, 42, 45 x: y: 0 (When mn = 42) 1 (When mn = 45) 1 (When mn = 34) 2 (When mn = 37) Selector User's Manual U14492EJ5V0UD 685 CHAPTER 14 PORT FUNCTIONS Figure 14-11. Type N Block Diagram WRPFC PFCmn WRPMC PMCmn WRPM PMmn Internal bus Selector WRPORT Output signal in control mode Pmn Pmn Selector Address RDIN Input signal in control mode Noise elimination Edge detection Remark m: Port number n: Bit number 686 User's Manual U14492EJ5V0UD Selector CHAPTER 14 PORT FUNCTIONS Figure 14-12. Type O Block Diagram WRPMC MODE0 to MODE2 I/O control PMCmn WRPM PMmn Internal bus Selector WRPORT Output signal in control mode Pmn Pmn Selector Address RDIN Input signal in control mode I/O control Remark m: Port number n: Bit number Selector User's Manual U14492EJ5V0UD 687 CHAPTER 14 PORT FUNCTIONS Figure 14-13. Type P Block Diagram WRPMC MODE0 to MODE2 I/O control PMCmn WRPM Internal bus PMmn Selector WRPORT Output signal in control mode Pmn Pmn Selector Address RDIN Remark m: Port number n: Bit number 688 User's Manual U14492EJ5V0UD Selector CHAPTER 14 PORT FUNCTIONS 14.3 Pin Functions of Each Port 14.3.1 Port 0 Port 0 is an 8-bit input dedicated port in which all pins are fixed for input. 7 P0 P07 6 P06 5 P05 4 P04 3 P03 2 P02 1 P01 0 P00 Address FFFFF400H Initial value Undefined Besides functioning as an input port, in control mode, it also can operate as the timer/counter output stop signal input, external interrupt request input, and A/D converter (ADC) external trigger input. Although this port also serves as NMI, ESO0/INTP0, ESO1/INTP1, ADTRG0/INTP2, ADTRG1/INTP3, and INTP4 to INTP6, NMI, ESO0/INTP0, ESO1/INTP1, ADTRG0/INTP2, ADTRG1/INTP3, and INTP4 to INTP6 cannot be switched with input port. The status of each pin is read by reading the port. (1) Operation in control mode Port Port 0 P00 P01 P02 P03 P04 P05 to P07 Alternate Pin Name NMI ESO0/INTP0 ESO1/INTP1 ADTRG0/INTP2 ADTRG1/INTP3 INTP4 to INTP6 Remarks Non-maskable interrupt request input Timer/counter output stop signal input or external interrupt request input A/D converter (ADC) external trigger input or external interrupt request input External interrupt request input Block Type F User's Manual U14492EJ5V0UD 689 CHAPTER 14 PORT FUNCTIONS 14.3.2 Port 1 Port 1 is a 6-bit I/O port in which input or output can be specified in 1-bit units. 7 P1 - 6 - 5 P15 4 P14 3 P13 2 P12 1 P11 0 P10 Address FFFFF402H Initial value Undefined Bit position 5 to 0 Bit name P1n (n = 5 to 0) I/O port Function Besides functioning as a port, in control mode, it also can operate as the timer/counter I/O and external interrupt request input. (1) Operation in control mode Port Port 1 P10 P11 P12 P13 P14 P15 Alternate Pin Name TIUD10/TO10 TCUD10/INTP100 TCLR10/INTP101 TIUD11/TO11 TCUD11/INTP110 TCLR11/INTP111 Timer/counter I/O Timer/counter input or external interrupt request input N B Timer/counter I/O Timer/counter input or external interrupt request input Remarks Block Type N B (2) Setting in I/O mode and control mode Port 1 is set in I/O mode using the port 1 mode register (PM1). In control mode, it is set using the port 1 mode control register (PMC1) and port 1 function control register (PFC1). (a) Port 1 mode register (PM1) This register can be read/written in 8-bit or 1-bit units. Write 1 in bits 6 and 7. 7 PM1 1 6 1 5 PM15 4 PM14 3 PM13 2 PM12 1 PM11 0 PM10 Address FFFFF422H Initial value FFH Bit position 5 to 0 Bit name PM1n (n = 5 to 0) Function Specifies input/output mode of P1n pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) 690 User's Manual U14492EJ5V0UD CHAPTER 14 PORT FUNCTIONS (b) Port 1 mode control register (PMC1) This register can be read/written in 8-bit or 1-bit units. Write 0 in bits 6 and 7. Caution The PMC11, PMC12, PMC14, and PMC15 bits also serve as external interrupts (INTP100, INTP101, INTP110, and INTP111). When not using them as external interrupts, mask interrupt requests (refer to 7.3.4 Interrupt control register (xxICn)). 7 PMC1 0 6 0 5 PMC15 4 PMC14 3 PMC13 2 PMC12 1 PMC11 0 PMC10 Address FFFFF442H Initial value 00H Bit position 5 Bit name PMC15 Specifies operation mode of P15 pin. Function 0: I/O port mode 1: TCLR11 input mode or external interrupt request (INTP111) input mode 4 PMC14 Specifies operation mode of P14 pin. 0: I/O port mode 1: TCUD11 input mode or external interrupt request (INTP110) input mode 3 PMC13 Specifies operation mode of P13 pin. 0: I/O port mode 1: TIUD11 input mode or TO11 output mode 2 PMC12 Specifies operation mode of P12 pin. 0: I/O port mode 1: TCLR10 input mode or external interrupt request (INTP101) input mode 1 PMC11 Specifies operation mode of P11 pin. 0: I/O port mode 1: TCUD10 input mode or external interrupt request (INTP100) input mode 0 PMC10 Specifies operation mode of P10 pin. 0: I/O port mode 1: TIUD10 input mode or TO10 output mode User's Manual U14492EJ5V0UD 691 CHAPTER 14 PORT FUNCTIONS (c) Port 1 function control register (PFC1) This register can be read/written in 8-bit or 1-bit units. Write 0 in bits other than 0 and 3. Caution When port mode is specified by the port 1 mode control register (PMC1), the setting of this register is invalid. 7 PFC1 0 6 0 5 0 4 0 3 PFC13 2 0 1 0 0 PFC10 Address FFFFF462H Initial value 00H Bit position 3 Bit name PFC13 Function Specifies operation mode of P13 pin in control mode. 0: TIUD11 input mode 1: TO11 output mode 0 PFC10 Specifies operation mode of P10 pin in control mode. 0: TIUD10 input mode 1: TO10 output mode 692 User's Manual U14492EJ5V0UD CHAPTER 14 PORT FUNCTIONS 14.3.3 Port 2 Port 2 is an 8-bit I/O port in which input or output can be specified in 1-bit units. 7 P2 P27 6 P26 5 P25 4 P24 3 P23 2 P22 1 P21 0 P20 Address FFFFF404H Initial value Undefined Bit position 7 to 0 Bit name P2n (n = 7 to 0) I/O port Function Besides functioning as a port, in control mode, it also can operate as the timer/counter I/O and external interrupt request input. (1) Operation in control mode Port Port 2 P20 P21 to P24 Alternate Pin Name TI2/INTP20 TO21/INTP21 to TO24/INTP24 P25 P26 P27 TCLR2/INTP25 TI3/TCLR3/INTP30 TO3/INTP31 Timer/counter output or external interrupt request input N Remarks Timer/counter input or external interrupt request input Timer/counter output or external interrupt request input Timer/counter input or external interrupt request input B Block Type B N (2) Setting in I/O mode and control mode Port 2 is set in I/O mode using the port 2 mode register (PM2). In control mode, it is set using the port 2 mode control register (PMC2) and port 2 function control register (PFC2). (a) Port 2 mode register (PM2) This register can be read/written in 8-bit or 1-bit units. 7 PM2 PM27 6 PM26 5 PM25 4 PM24 3 PM23 2 PM22 1 PM21 0 PM20 Address FFFFF424H Initial value FFH Bit position 7 to 0 Bit name PM2n (n = 7 to 0) Function Specifies input/output mode of P2n pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) User's Manual U14492EJ5V0UD 693 CHAPTER 14 PORT FUNCTIONS (b) Port 2 mode control register (PMC2) This register can be read/written in 8-bit or 1-bit units. Caution The PMC20, PMC25, and PMC26 bits also serve as external interrupts (INTP20, INTP25, and INTP30). When not using them as external interrupts, mask interrupt requests (refer to 7.3.4 Interrupt control register (xxICn)). 7 PMC2 PMC27 6 PMC26 5 PMC25 4 PMC24 3 PMC23 2 PMC22 1 PMC21 0 PMC20 Address FFFFF444H Initial value 00H Bit position 7 Bit name PMC27 Specifies operation mode of P27 pin. Function 0: I/O port mode 1: TO3 output mode or external interrupt request (INTP31) input mode 6 PMC26 Specifies operation mode of P26 pin. 0: I/O port mode 1: TI3, TCLR3 input mode or external interrupt request (INTP30) input mode 5 PMC25 Specifies operation mode of P25 pin. 0: I/O port mode 1: TCLR2 input mode or external interrupt request (INTP25) input mode 4 to 1 PMC24 to PMC21 Specify operation mode of P24 to P21 pins. 0: I/O port mode 1: TO24 to TO21 output mode or external interrupt request (INTP24 to INTP21) input mode 0 PMC20 Specifies operation mode of P20 pin. 0: I/O port mode 1: TI2 input mode or external interrupt request (INTP20) input mode 694 User's Manual U14492EJ5V0UD CHAPTER 14 PORT FUNCTIONS (c) Port 2 function control register (PFC2) This register can be read/written in 8-bit or 1-bit units. Write 0 in bits 0, 5, and 6. Caution When port mode is specified by the port 2 mode control register (PMC2), the setting of this register is invalid. 7 PFC2 PFC27 6 0 5 0 4 PFC24 3 PFC23 2 PFC22 1 PFC21 0 0 Address FFFFF464H Initial value 00H Bit position 7 Bit name PFC27 Function Specifies operation mode of P27 pin in control mode. 0: External interrupt request (INTP31) input mode 1: TO3 output mode 4 to 1 PFC24 to PFC21 Specify operation mode of P24 to P21 pins in control mode. 0: External interrupt request (INTP24 to INTP21) input mode 1: TO24 to TO21 output mode User's Manual U14492EJ5V0UD 695 CHAPTER 14 PORT FUNCTIONS 14.3.4 Port 3 Port 3 is an 8-bit I/O port in which input or output can be specified in 1-bit units. 7 P3 P37 6 P36 5 P35 4 P34 3 P33 2 P32 1 P31 0 P30 Address FFFFF406H Initial value Undefined Bit position 7 to 0 Bit name P3n (n = 7 to 0) I/O port Function Besides functioning as a port, in control mode, it also can operate as the serial interface (UART0 to UART2) I/O. (1) Operation in control mode Port Port 3 P30 P31 P32 P33 P34 P35 P36 P37 Alternate Pin Name RXD0 TXD0 RXD1 TXD1 ASCK1 RXD2 TXD2 ASCK2 Remarks Serial interface (UART0 to UART2) I/O Block Type H G C A M C A M (2) Setting in I/O mode and control mode Port 3 is set in I/O mode using the port 3 mode register (PM3). In control mode, it is set using the port 3 mode control register (PMC3). (a) Port 3 mode register (PM3) This register can be read/written in 8-bit or 1-bit units. 7 PM3 PM37 6 PM36 5 PM35 4 PM34 3 PM33 2 PM32 1 PM31 0 PM30 Address FFFFF426H Initial value FFH Bit position 7 to 0 Bit name PM3n (n = 7 to 0) Function Specifies input/output mode of P3n pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) 696 User's Manual U14492EJ5V0UD CHAPTER 14 PORT FUNCTIONS (b) Port 3 mode control register (PMC3) This register can be read/written in 8-bit or 1-bit units. 7 PMC3 PMC37 6 PMC36 5 PMC35 4 PMC34 3 PMC33 2 PMC32 1 PMC31 0 PMC30 Address FFFFF446H Initial value 00H Bit position 7 Bit name PMC37 Specifies operation mode of P37 pin. 0: I/O port mode 1: ASCK2 I/O mode Function 6 PMC36 Specifies operation mode of P36 pin. 0: I/O port mode 1: TXD2 output mode 5 PMC35 Specifies operation mode of P35 pin. 0: I/O port mode 1: RXD2 input mode 4 PMC34 Specifies operation mode of P34 pin. 0: I/O port mode 1: ASCK1 I/O mode 3 PMC33 Specifies operation mode of P33 pin. 0: I/O port mode 1: TXD1 output mode 2 PMC32 Specifies operation mode of P32 pin. 0: I/O port mode 1: RXD1 input mode 1 PMC31 Specifies operation mode of P31 pin. 0: I/O port mode 1: TXD0 output mode 0 PMC30 Specifies operation mode of P30 pin. 0: I/O port mode 1: RXD0 input mode User's Manual U14492EJ5V0UD 697 CHAPTER 14 PORT FUNCTIONS 14.3.5 Port 4 Port 4 is an 8-bit I/O port in which input or output can be specified in 1-bit units. 7 P4 P47 6 P46 5 P45 4 P44 3 P43 2 P42 1 P41 0 P40 Address FFFFF408H Initial value Undefined Bit position 7 to 0 Bit name P4n (n = 7 to 0) I/O port Function Besides functioning as a port, in control mode, it also can operate as the serial interface (CSI0, CSI1, FCAN) I/O. (1) Operation in control mode Port Port 4 P40 P41 P42 P43 P44 P45 P46 P47 Alternate Pin Name SI0 SO0 SCK0 SI1 SO1 SCK1 CRXD CTXD Remarks Serial interface (CSI0, CSI1, FCAN) I/O Block Type C A M C A M C A (2) Setting in I/O mode and control mode Port 4 is set in I/O mode using the port 4 mode register (PM4). In control mode, it is set using the port 4 mode control register (PMC4). (a) Port 4 mode register (PM4) This register can be read/written in 8-bit or 1-bit units. 7 PM4 PM47 6 PM46 5 PM45 4 PM44 3 PM43 2 PM42 1 PM41 0 PM40 Address FFFFF428H Initial value FFH Bit position 7 to 0 Bit name PM4n (n = 7 to 0) Function Specifies input/output mode of P4n pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) 698 User's Manual U14492EJ5V0UD CHAPTER 14 PORT FUNCTIONS (b) Port 4 mode control register (PMC4) This register can be read/written in 8-bit or 1-bit units. 7 PMC4 PMC47 6 PMC46 5 PMC45 4 PMC44 3 PMC43 2 PMC42 1 PMC41 0 PMC40 Address FFFFF448H Initial value 00H Bit position 7 Bit name PMC47 Specifies operation mode of P47 pin. 0: I/O port mode 1: CTXD output mode Function 6 PMC46 Specifies operation mode of P46 pin. 0: I/O port mode 1: CRXD input mode 5 PMC45 Specifies operation mode of P45 pin. 0: I/O port mode 1: SCK1 I/O mode 4 PMC44 Specifies operation mode of P44 pin. 0: I/O port mode 1: SO1 output mode 3 PMC43 Specifies operation mode of P43 pin. 0: I/O port mode 1: SI1 input mode 2 PMC42 Specifies operation mode of P42 pin. 0: I/O port mode 1: SCK0 I/O mode 1 PMC41 Specifies operation mode of P41 pin. 0: I/O port mode 1: SO0 output mode 0 PMC40 Specifies operation mode of P40 pin. 0: I/O port mode 1: SI0 input mode User's Manual U14492EJ5V0UD 699 CHAPTER 14 PORT FUNCTIONS 14.3.6 Port DH Port DH is an 8-bit I/O port in which input or output can be specified in 1-bit units. 7 PDH PDH7 6 PDH6 5 PDH5 4 PDH4 3 PDH3 2 PDH2 1 PDH1 0 PDH0 Address FFFFF006H Initial value Undefined Bit position 7 to 0 Bit name PDHn (n = 7 to 0) I/O port Function Besides functioning as a port, in control mode, this can operate as an address bus when memory is expanded externally. (1) Operation in control mode Port Port DH PDH7 to PDH0 Alternate Pin Name A23 to A16 Remarks Memory expansion address bus Block Type P (2) Setting in I/O mode and control mode Port DH is set in I/O mode using the port DH mode register (PMDH). In control mode, it is set using the port DH mode control register (PMCDH). (a) Port DH mode register (PMDH) This register can be read/written in 8-bit or 1-bit units. 7 PMDH PMDH7 6 PMDH6 5 PMDH5 4 PMDH4 3 PMDH3 2 PMDH2 1 PMDH1 0 PMDH0 Address FFFFF026H Initial value FFH Bit position 7 to 0 Bit name PMDHn (n = 7 to 0) Function Specifies input/output mode of PDHn pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) 700 User's Manual U14492EJ5V0UD CHAPTER 14 PORT FUNCTIONS (b) Port DH mode control register (PMCDH) This register can be read/written in 8-bit or 1-bit units. 7 PMCDH 6 5 4 3 2 1 0 Address FFFFF046H Initial valueNote 00H/FFH PMCDH7 PMCDH6 PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 Note 00H: Single-chip mode 0 FFH: Single-chip mode 1, ROMless mode 0 or 1 Bit position 7 to 0 Bit name PMCDHn (n = 7 to 0) Function Specifies operation mode of PDHn pin. 0: I/O port mode 1: A23 to A16 output mode User's Manual U14492EJ5V0UD 701 CHAPTER 14 PORT FUNCTIONS 14.3.7 Port DL Port DL is a 16-bit or 8-bit I/O port in which input or output can be specified in 1-bit units. When using the higher 8 bits of PDL as PDLH and the lower 8 bits as PDLL, it can be used as an 8-bit I/O port that can specify input or output in 1-bit units. 15 PDL PDL15 14 PDL14 13 PDL13 12 PDL12 11 PDL11 10 PDL10 9 PDL9 8 PDL8 Address FFFFF005H Initial value Undefined 7 PDL7 6 PDL6 5 PDL5 4 PDL4 3 PDL3 2 PDL2 1 PDL1 0 PDL0 Address FFFFF004H Bit position 15 to 0 Bit name PDLn (n = 15 to 0) I/O port Function Besides functioning as a port, in control mode, this can operate as an address/data bus when memory is expanded externally. (1) Operation in control mode Port Port DL PDL15 to PDL0 Alternate Pin Name AD15 to AD0 Remarks Memory expansion address/data bus Block Type O (2) Setting in I/O mode and control mode Port DL is set in I/O mode using the port DL mode register (PMDL). In control mode, it is set using the port DL mode control register (PMCDL). 702 User's Manual U14492EJ5V0UD CHAPTER 14 PORT FUNCTIONS (a) Port DL mode register (PMDL) The PMDL register can be read/written in 16-bit units. When using the higher 8 bits of the PMDL register as the PMDLH register and the lower 8 bits as the PMDLL register, it can be read/written in 8-bit or 1-bit units. 15 PMDL 14 13 12 11 10 9 PMDL9 8 PMDL8 Address FFFFF025H Initial value FFFFH PMDL15 PMDL14 PMDL13 PMDL12 PMDL11 PMDL10 7 PMDL7 6 PMDL6 5 PMDL5 4 PMDL4 3 PMDL3 2 PMDL2 1 PMDL1 0 PMDL0 Address FFFFF024H Bit position 15 to 0 Bit name PMDLn (n = 15 to 0) Function Specifies input/output mode of PDLn pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) (b) Port DL mode control register (PMCDL) The PMCDL register can be read/written in 16-bit units. When using the higher 8 bits of the PMCDL register as the PMCDLH register and the lower 8 bits as the PMCDLL register, it can be read/written in 8-bit or 1-bit units. 15 PMCDL 14 13 12 11 10 9 8 Address Initial valueNote PMCDL15 PMCDL14 PMCDL13 PMCDL12 PMCDL11 PMCDL10 PMCDL9 PMCDL8 FFFFF045H 0000H/FFFFH 7 6 5 4 3 2 1 0 Address FFFFF044H PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 Note 0000H : Single-chip mode 0 FFFFH: Single-chip mode 1, ROMless mode 0 or 1 Bit position 15 to 0 Bit name PMCDLn (n = 15 to 0) Function Specifies operation mode of PDLn pin. 0: I/O port mode 1: AD15 to AD0 I/O mode User's Manual U14492EJ5V0UD 703 CHAPTER 14 PORT FUNCTIONS 14.3.8 Port CS Port CS is an 8-bit I/O port in which input or output can be specified in 1-bit units. 7 PCS PCS7 6 PCS6 5 PCS5 4 PCS4 3 PCS3 2 PCS2 1 PCS1 0 PCS0 Address FFFFF008H Initial value Undefined Bit position 7 to 0 Bit name PCSn (n = 7 to 0) I/O port Function Besides functioning as a port, in control mode, this can operate as the chip select signal output when memory is expanded externally. (1) Operation in control mode Port Port CS PCS7 to PCS0 Alternate Pin Name CS0 to CS7 Remarks Chip select signal output Block Type J 704 User's Manual U14492EJ5V0UD CHAPTER 14 PORT FUNCTIONS (2) Setting in I/O mode and control mode Port CS is set in I/O mode using the port CS mode register (PMCS). In control mode, it is set using the port CS mode control register (PMCCS). (a) Port CS mode register (PMCS) This register can be read/written in 8-bit or 1-bit units. 7 PMCS PMCS7 6 PMCS6 5 PMCS5 4 PMCS4 3 PMCS3 2 PMCS2 1 PMCS1 0 PMCS0 Address FFFFF028H Initial value FFH Bit position 7 to 0 Bit name PMCSn (n = 7 to 0) Function Specifies input/output mode of PCSn pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) (b) Port CS mode control register (PMCCS) This register can be read/written in 8-bit or 1-bit units. 7 PMCCS 6 5 4 3 2 1 0 Address FFFFF048H Initial valueNote 00H/FFH PMCCS7 PMCCS6 PMCCS5 PMCCS4 PMCCS3 PMCCS2 PMCCS1 PMCCS0 Note 00H: Single-chip mode 0 FFH: Single-chip mode 1, ROMless mode 0 or 1 Bit position 7 to 0 Bit name PMCCSn (n = 7 to 0) Function Specifies operation mode of PCSn pin. 0: I/O port mode 1: CS7 to CS0 output mode User's Manual U14492EJ5V0UD 705 CHAPTER 14 PORT FUNCTIONS 14.3.9 Port CT Port CT is an 8-bit I/O port in which input or output can be specified in 1-bit units. 7 PCT PCT7 6 PCT6 5 PCT5 4 PCT4 3 PCT3 2 PCT2 1 PCT1 0 PCT0 Address FFFFF00AH Initial value Undefined Bit position 7 to 0 Bit name PCTn (n = 7 to 0) I/O port Function Besides functioning as a port, in control mode, this can operate as control signal outputs when memory is expanded externally. (1) Operation in control mode Port Port CT PCT0 PCT1 PCT2 PCT3 PCT4 PCT5 PCT6 PCT7 ASTB - RD - Read strobe signal output Fixed in port mode Address strobe signal output Fixed in port mode J E J E Alternate Pin Name LWR UWR - Fixed in port mode E Remarks Write strobe signal output Block type J (2) Setting in I/O mode and control mode Port CT is set in I/O mode using the port CT mode register (PMCT). In control mode, it is set using the port CT mode control register (PMCCT). (a) Port CT mode register (PMCT) This register can be read/written in 8-bit or 1-bit units. 7 PMCT PMCT7 6 PMCT6 5 PMCT5 4 PMCT4 3 PMCT3 2 PMCT2 1 PMCT1 0 PMCT0 Address FFFFF02AH Initial value FFH Bit position 7 to 0 Bit name PMCTn (n = 7 to 0) Function Specifies input/output mode of PCTn pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) 706 User's Manual U14492EJ5V0UD CHAPTER 14 PORT FUNCTIONS (b) Port CT mode control register (PMCCT) This register can be read/written in 8-bit or 1-bit units. 7 PMCCT 0 6 PMCCT6 5 0 4 PMCCT4 3 0 2 0 1 0 Address FFFFF04AH Initial valueNote 00H/53H PMCCT1 PMCCT0 Note 00H: Single-chip mode 0 53H: Single-chip mode 1, ROMless mode 0 or 1 Bit position 6 Bit name PMCCT6 Function Specifies operation mode of PCT6 pin. 0: I/O port mode 1: ASTB output mode 4 PMCCT4 Specifies operation mode of PCT4 pin. 0: I/O port mode 1: RD output mode 1 PMCCT1 Specifies operation mode of PCT1 pin. 0: I/O port mode 1: UWR output mode 0 PMCCT0 Specifies operation mode of PCT0 pin. 0: I/O port mode 1: LWR output mode User's Manual U14492EJ5V0UD 707 CHAPTER 14 PORT FUNCTIONS 14.3.10 Port CM Port CM is a 5-bit I/O port in which input or output can be specified in 1-bit units. 7 PCM - 6 - 5 - 4 PCM4 3 PCM3 2 PCM2 1 PCM1 0 PCM0 Address FFFFF00CH Initial value Undefined Bit position 4 to 0 Bit name PCMn (n = 4 to 0) I/O port Function Besides functioning as a port, in control mode, this can operate as the wait insertion signal input, internal system clock output, and bus hold control signal output. (1) Operation in control mode Port Port CM PCM0 PCM1 PCM2 PCM3 PCM4 Alternate Pin Name WAIT Note Remarks Wait insertion signal input Internal system clock output Bus hold acknowledge signal output Block Type D J J D E CLKOUT HLDAK HLDRQ Note Bus hold request signal input Fixed in port mode - Note The WAIT and HLDRQ signals are set to control mode by default in ROMless mode 0, 1 or single-chip mode 1. Be sure to fix these pins to the inactive level when not used. These pins function in control mode until port mode is set using the port CM mode control register (PMCCM), so be sure to set these pins to the inactive level before setting PMCCM. (2) Setting in I/O mode and control mode Port CM is set in I/O mode using the port CM mode register (PMCM). In control mode, it is set using the port CM mode control register (PMCCM). (a) Port CM mode register (PMCM) This register can be read/written in 8-bit or 1-bit units. 7 PMCM 1 6 1 5 1 4 PMCM4 3 PMCM3 2 PMCM2 1 PMCM1 0 PMCM0 Address FFFFF02CH Initial value FFH Bit position 4 to 0 Bit name PMCMn (n = 4 to 0) Function Specifies input/output mode of PCMn pin. 0: Output mode (output buffer on) 1: Input mode (output buffer off) 708 User's Manual U14492EJ5V0UD CHAPTER 14 PORT FUNCTIONS (b) Port CM mode control register (PMCCM) This register can be read/written in 8-bit or 1-bit units. 7 PMCCM 0 6 0 5 0 4 0 3 2 1 0 Address FFFFF04CH Initial valueNote 00H/0FH PMCCM3 PMCCM2 PMCCM1 PMCCM0 Note 00H: Single-chip mode 0 0FH: Single-chip mode 1, ROMless mode 0 or 1 Bit position 3 Bit name PMCCM3 Function Specifies operation mode of PCM3 pin. 0: I/O port mode 1: HLDRQ input mode 2 PMCCM2 Specifies operation mode of PCM2 pin. 0: I/O port mode 1: HLDAK output mode 1 PMCCM1 Specifies operation mode of PCM1 pin. 0: I/O port mode 1: CLKOUT output mode 0 PMCCM0 Specifies operation mode of PCM0 pin. 0: I/O port mode 1: WAIT input mode User's Manual U14492EJ5V0UD 709 CHAPTER 14 PORT FUNCTIONS 14.4 Operation of Port Function The operation of a port differs depending on whether it is set in the input or output mode, as follows. 14.4.1 Writing to I/O port (1) In output mode A value can be written to the output latch (Pn) by writing it to the port n register (Pn). The contents of the output latch are output from the pin. Once data is written to the output latch, it is held until new data is written to the output latch. (2) In input mode A value can be written to the output latch (Pn) by writing it to the port n register (Pn). However, the status of the pin does not change because the output buffer is off. Once data is written to the output latch, it is held until new data is written to the output latch. Caution A bit manipulation instruction (CLR1, SET1, NOT1) manipulates 1 bit but accesses a port in 8-bit units. If this instruction is executed to manipulate a port with a mixture of input and output bits, the contents of the output latch of a pin set in the input mode, in addition to the bit to be manipulated, are overwritten to the current input pin status and become undefined. 14.4.2 Reading from I/O port (1) In output mode The contents of the output latch (Pn) can be read by reading the port n register (Pn). The contents of the output latch do not change. (2) In input mode The status of the pin can be read by reading the port n register (Pn). The contents of the output latch (Pn) do not change. 14.4.3 Output status of alternate function in control mode The status of a port pin is not dependent upon the setting of the PMCn register and can be read by setting the port n mode register (PMn) to the input mode. If the PMn register is set to the output mode, the value of the port n register (Pn) can be read in the port mode, and the output status of the alternate function can be read in the control mode. 710 User's Manual U14492EJ5V0UD CHAPTER 14 PORT FUNCTIONS 14.5 Noise Eliminator 14.5.1 Interrupt pins A timing controller to guarantee the noise elimination times shown below is added to the pins that operate as NMI and valid edge inputs in port control mode. Signal input that changes in less than these elimination times is not accepted internally. Pin P00/NMI P01/ESO0/INTP0, P02/ESO1/INTP1 P03/ADTRG0/INTP2, P04/ADTRG1/INTP3 P05/INTP4 to P07/INTP6 Noise Elimination Time Analog delay (Approx. 10 ns) Cautions 1. The above non-maskable/maskable interrupt pins are used to release standby mode. stopped in standby mode. 2. The noise eliminator is valid only in control mode. A clock control timing circuit is not used since the internal system clock is User's Manual U14492EJ5V0UD 711 CHAPTER 14 PORT FUNCTIONS 14.5.2 Timer 10, timer 11, timer 3 input pins Noise filtering using the clock sampling shown below is added to the pins that operate as valid edge inputs to timer 10, timer 11, and timer 3. A signal input that changes in less than these elimination times is not accepted internally. Pin Timer 10 P10/TIUD10/TO10 P11/TCUD10/INTP100 P12/TCLR10/INTP101 Timer 11 P13/TIUD11/TO11 P14/TCUD11/INTP110 P15/TCLR11/INTP111 Timer 3 P26/TI3/INTP30/TCLR3 Select from fXXTM3/2 fXXTM3/4 fXXTM3/8 fXXTM3/16 P27/TO3/INTP31 Select from fXXTM3/32 fXXTM3/64 fXXTM3/128 fXXTM3/256 Noise Elimination Time 4 to 5 clocks Sampling Clock Select from fXXTM10,11 fXXTM10,11/2 fXXTM10,11/4 fXXTM10,11/8 Cautions 1. Since the above pin noise filtering uses clock sampling, input signals are not received when the CPU clock is stopped. 2. The noise eliminator is valid only in control mode. Remark fXXTM10,11: Clock of TM10 and TM11 selected by PRM02 register fXXTM3: Clock of TM3 selected by PRM03 register 712 User's Manual U14492EJ5V0UD CHAPTER 14 PORT FUNCTIONS Figure 14-14. Example of Noise Elimination Timing Noise elimination clock Input signal 2 clocks 2 clocks 3 clocks 3 clocks 4 clocks 4 clocks 5 clocks 5 clocks Internal signal Timers 1 to 3 rising edge detection Timers 1 to 3 falling edge detection Caution If there are three or less noise elimination clocks while the timers 1 to 3 input signals are high level (or low level), the input pulse is eliminated as noise. If it is sampled at least four times, the edge is detected as valid input. User's Manual U14492EJ5V0UD 713 CHAPTER 14 PORT FUNCTIONS (1) Timer 10 noise elimination time selection register (NRC10) The NRC10 register is used to set the clock source of timer 10 input pin noise elimination times. This register can be read/written in 8-bit or 1-bit units. Caution The noise elimination function starts operating by setting the TM1CE0 bit of the TMC10 register to 1 (enabling count operations). 7 NRC10 0 6 0 5 0 4 0 3 0 2 0 1 0 Address FFFFF5F8H Initial value 00H NRC101 NRC100 Bit position 1, 0 Bit name NRC101, NRC100 Function Selects the TIUD10/TO10, TCUD10/INTP100, and TCLR10/INTP101 pin noise elimination clocks. NRC101 0 0 1 1 NRC100 0 1 0 1 fXXTM10/8 fXXTM10/4 fXXTM10/2 fXXTM10 Noise elimination clock Remark fXXTM10: Clock of TM10 selected by PRM02 register (2) Timer 11 noise elimination time selection register (NRC11) The NRC11 register is used to set the clock source of timer 11 input pin noise elimination times. This register can be read/written in 8-bit or 1-bit units. Caution The noise elimination function starts operating by setting the TM1CE1 bit of the TMC11 register to 1 (enabling count operations). 7 NRC11 0 6 0 5 0 4 0 3 0 2 0 1 0 Address FFFFF618H Initial value 00H NRC111 NRC110 Bit position 1, 0 Bit name NRC111, NRC110 Function Selects the TIUD11/TO11, TCUD11/INTP110, and TCLR11/INTP111 pin noise elimination clocks. NRC111 0 0 1 1 NRC110 0 1 0 1 fXXTM11/8 fXXTM11/4 fXXTM11/2 fXXTM11 Noise elimination clock Remark fXXTM11: Clock of TM11 selected by PRM02 register 714 User's Manual U14492EJ5V0UD CHAPTER 14 PORT FUNCTIONS (3) Timer 3 noise elimination time selection register (NRC3) The NRC3 register is used to set the clock source of timer 3 input pin noise elimination times. This register can be read/written in 8-bit or 1-bit units. Caution The noise elimination function starts operating by setting the TM3CE bit of the TMC30 register to 1 (enabling count operations). 7 NRC3 0 6 0 5 0 4 0 3 NRC33 2 NRC32 1 NRC31 0 NRC30 Address FFFFF698H Initial value 00H Bit position 3, 2 Bit name NRC33, NRC32 Function Selects the TO3/INTP31 pin noise elimination clock. NRC33 0 0 1 1 NRC32 0 1 0 1 fXXTM3/256 fXXTM3/128 fXXTM3/64 fXXTM3/32 Noise elimination clock Remark 1, 0 NRC31, NRC30 NRC31 0 0 1 1 fXXTM3: Clock selected by PRM03 register Selects the TI3/INTP30/TCLR3 pin noise elimination clock. NRC30 0 1 0 1 fXXTM3/16 fXXTM3/8 fXXTM3/4 fXXTM3/2 Noise elimination clock Remark fXXTM3: Clock selected by PRM03 register User's Manual U14492EJ5V0UD 715 CHAPTER 14 PORT FUNCTIONS 14.5.3 Timer 2 input pins A noise eliminator using analog filtering and digital filtering using clock sampling are added to the timer 2 input pins. A signal input that changes in less than these elimination times is not accepted internally. Pin Analog Filter Noise Elimination Time P20/TI2/INTP20 P21/TO21/INTP21 to P24/TO24/INTP24 P25/TCLR2/INTP25 10 to 100 ns Digital Filter Noise Elimination Time 4 to 5 clocks Sampling Clock fXXTM2 Cautions 1. Since digital filtering uses clock sampling, if it is selected, input signals are not received when the CPU clock is stopped. 2. The noise eliminator is valid only in control mode. 3. Refer to Figure 14-14 for an example of a noise eliminator. Remark fXXTM2: Clock of TM20 and TM21 selected by PRM02 register 716 User's Manual U14492EJ5V0UD CHAPTER 14 PORT FUNCTIONS (1) Timer 2 input filter mode registers 0 to 5 (FEM0 to FEM5) The FEMn registers are used to specify timer 2 input pin filtering and to set the clock source of noise elimination times and the input valid edge. These registers can be read/written in 8-bit or 1-bit units. Cautions 1. Even when using the TI2/INTP20, TO21/INTP21, TO22/INTP22, TO23/INTP23, TO24/INTP24, and TCLR2/INTP25 pins as INTP20, INTP21, INTP22, INTP23, INTP24, and INTP25 without using timer 2, be sure to clear the STFTE bit of timer 2 clock stop register 0 (STOPTE0) to 0. 2. Before setting the INTP2n pin to the trigger mode, set the PMC2 register. If the PMC2 register is set after the FEMn register has been set, an illegal interrupt may occur as soon as the PMC2 register is set (n = 0 to 5). 3. The noise elimination function starts operating by setting the CEEn bit of the TCRE0 register to 1 (enabling count operations). (1/2) 7 FEM0 DFEN00 6 0 5 0 4 0 3 2 1 0 TMS000 Address FFFFF630H Initial value 00H EDGE010 EDGE000 TMS010 INTP20 7 FEM1 DFEN01 6 0 5 0 4 0 3 2 1 0 TMS001 Address FFFFF631H Initial value 00H EDGE011 EDGE001 TMS011 INTP21 7 FEM2 DFEN02 6 0 5 0 4 0 3 2 1 0 TMS002 Address FFFFF632H Initial value 00H EDGE012 EDGE002 TMS012 INTP22 7 FEM3 DFEN03 6 0 5 0 4 0 3 2 1 0 TMS003 Address FFFFF633H Initial value 00H EDGE013 EDGE003 TMS013 INTP23 7 FEM4 DFEN04 6 0 5 0 4 0 3 2 1 0 TMS004 Address FFFFF634H Initial value 00H EDGE014 EDGE004 TMS014 INTP24 7 FEM5 DFEN05 6 0 5 0 4 0 3 2 1 0 TMS005 Address FFFFF635H Initial value 00H EDGE015 EDGE005 TMS015 INTP25 Bit position 7 Bit name DFEN0n Specifies the INTP2n pin filter. 0: Analog filter 1: Digital filter Function Caution When the DFEN0n bit = 1, the sampling clock of the digital filter is fXXTM2 (clock of TM20 and TM21 selected by PRM02 register). Remark n = 0 to 5 User's Manual U14492EJ5V0UD 717 CHAPTER 14 PORT FUNCTIONS (2/2) Bit position 3, 2 Bit name EDGE01n, EDGE00n EDGE01n EDGE00n 0 0 1 1 0 1 0 1 Interrupt due to INTCC2n Rising edge Falling edge Both rising and falling edges Operation Note Function Specifies the INTP2n pin valid edge. Note Specify when selecting INTCC2n according to match of TM20, TM21 and sub-channel compare registers (TMS01n, TMS00n bit settings) (n = 0 to 5). 1, 0 TMS01n, TMS00n TMS01n 0 0 1 1 TMS00n 0 1 0 1 Use as pin Digital filter (noise eliminator specification) Capture to sub-channel 1 according to timer Capture to sub-channel 2 according to timer Operation Selects capture input Note . Note Capture input according to INTCM100 and INTCM101 can be selected only for the FEM1 and FEM2 registers. Set the values of the TMS01m and TMS00m bits in the FEMm register to 00B or 01B. Settings other than these are prohibited (m = 1, 3 to 5). Capture according to INTP21, INTP22 and INTCM100, INTCM101 is possible for sub-channel 1 and sub-channel 2 of timer 2. Examples are shown below. (a) Capture sub-channel 1 on INTCM101 FEM1 register = xxxxxx10B TMIC0 register = 00000010B (b) Capture sub-channel 2 on INTCM101 FEM2 register = xxxxxx11B TMIC0 register = 00001000B Remark n = 0 to 5 718 User's Manual U14492EJ5V0UD CHAPTER 15 RESET FUNCTION When a low level is input to the RESET pin, there is a system reset and each hardware item of the V850E/IA1 is initialized to its initial status. When the RESET pin changes from low level to high level, reset status is released and the CPU starts program execution. Initialize the contents of various registers as needed within the program. 15.1 Features * Noise elimination using analog delay (approx. 60 ns) in reset pin (RESET) 15.2 Pin Functions During a system reset period, most pin output is high impedance (all pins except CLKOUTNote, RESET, X2, VDD5, VSS5, VDD3, VSS3, CVDD, CVSS, AVDD, AVREF0, AVREF1, and AVSS pins). Thus, if for example memory is extended externally, a pull-up (or pull-down) resistor must be attached to each pin of ports DH, DL, CS, CT, and CM. If there are no resistors, the external memory that is connected may be destroyed when these pins become high impedance. Similarly, perform pin processing so that on-chip peripheral I/O function signal output and output ports are not affected. Note In ROMless mode 0 or 1 and single-chip mode 1, CLKOUT signals also are output during a reset period. In single-chip mode 0, CLKOUT signals are not output until the PMCCM register is set. Table 15-1 shows the operation status of each pin during a reset period. Table 15-1. Operation Status of Each Pin During Reset Period Pin Name In Single-Chip Mode 0 A16 to A23, AD0 to AD15, CS0 to CS7, LWR, UWR, RD, ASTB, WAIT, HLDAK, HLDRQ CLKOUT Port pins Ports 0 to 4 Ports CM, CS, CT, DH, DL (Port mode) (Input) (Input) (Control mode) Operation (Port mode) Pin Status In Single-Chip Mode 1 High impedance In ROMless Mode 0 In ROMless Mode 1 User's Manual U14492EJ5V0UD 719 CHAPTER 15 RESET FUNCTION (1) Reset signal acknowledgment RESET Analog delay Analog delay Analog delay Elimination as noise Internal system reset signal Reset acknowledgment Note Reset release Note The internal system reset signal continues in active status for a period of at least 4 system clocks after the timing of a reset release by the RESET pin. (2) Reset at power-on A reset operation at power-on (power supply application) must guarantee oscillation stabilization time from power-on until reset acknowledgment due to the low level width of the RESET signal. VDD3, VDD5 RESET (input) Oscillation stabilization time Analog delay Reset release 720 User's Manual U14492EJ5V0UD CHAPTER 15 RESET FUNCTION 15.3 Initialization Initialize the contents of each register as needed within a program. Table 15-2 shows the initial values of the CPU, internal RAM, and on-chip peripheral I/O after reset. Table 15-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (1/6) On-Chip Hardware CPU Program registers Register Name General-purpose register (r0) General-purpose registers (r1 to r31) Program counter (PC) System registers Status saving register during interrupt (EIPC, EIPSW) Status saving register during NMI (FEPC, FEPSW) Interrupt source register (ECR) Program status word (PSW) Status saving register during CALLT execution (CTPC, CTPSW) Status saving register during exception/debug trap (DBPC, DBPSW) CALLT base pointer (CTBP) Internal RAM On-chip peripheral I/O Bus control function - Chip area selection control register n (CSCn) (n = 0, 1) Peripheral area selection control register (BPC) Bus size configuration register (BSC) System wait control register (VSWC) Memory control function Bus cycle type configuration register n (BCTn) (n = 0, 1) Data wait control register n (DWCn) (n = 0, 1) Address wait control register (AWC) Bus cycle control register (BCC) DMA function DMA source address register nL (DSAnL) (n = 0 to 3) DMA source address register nH (DSAnH) (n = 0 to 3) DMA destination address register nL (DDAnL) (n = 0 to 3) DMA destination address register nH (DDAnH) (n = 0 to 3) DMA transfer count register n (DBCn) (n = 0 to 3) DMA addressing control register n (DADCn) (n = 0 to 3) DMA channel control register n (DCHCn) (n = 0 to 3) DMA disable status register (DDIS) DMA restart register (DRST) DMA trigger factor register n (DTFRn) (n = 0 to 3) Interrupt/exception control function In-service priority register (ISPR) External interrupt mode register n (INTMn) (n = 0 to 2) Interrupt mask register n (IMRn) (n = 0 to 3) Interrupt mask register nL (IMRnL) (n = 0 to 3) Interrupt mask register nH (IMRnH) (n = 0 to 3) User's Manual U14492EJ5V0UD Initial Value After Reset 00000000H Undefined 00000000H Undefined Undefined 00000000H 00000020H Undefined Undefined Undefined Undefined 2C11H 0000H 0000H/5555H 77H CCCCH 3333H 0000H AAAAH Undefined Undefined Undefined Undefined Undefined 0000H 00H 00H 00H 00H 00H 00H FFFFH FFH FFH 721 CHAPTER 15 RESET FUNCTION Table 15-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (2/6) On-Chip Hardware On-chip peripheral I/O Interrupt/exception control function Register Name Signal edge selection register n (SESA1n) (n = 10, 11) Valid edge selection register (SESC) Timer 2 input filter mode register n (FEMn) (n = 0 to 5) Interrupt control registers (P0IC0 to P0IC6, DETIC0, DETIC1, TM0IC0, CM03IC0, TM0IC1, CM03IC1, CC10IC0, CC10IC1, CM10IC0, CM10IC1, CC11IC0, CC11IC1, CM11IC0, CM11IC1, TM2IC0, TM2IC1, CC2IC0 to CC2IC5, TM3IC0, CC3IC0, CC3IC1, CM4IC0, DMAIC0 to DMAIC3, CANIC0 to CANIC3, CSIIC0, CSIIC1, SRIC0 to SRIC2, STIC0 to STIC2, SEIC0, ADIC0, ADIC1) Power save control function Command register (PRCMD) Power save control register (PSC) Clock control register (CKC) Power save mode register (PSMR) Lock register (LOCKR) System control Peripheral command register (PHCMD) Peripheral status register (PHS) Timer 0 Dead-time timer reload register n (DTRRn) (n = 0, 1) Buffer registers CM0n, CM1n (BFCM0n, BFCM1n) (n = 0 to 3) Timer control register 0n (TMC0n) (n = 0, 1) Timer control register 0nL (TMC0nL) (n = 0, 1) Timer control register 0nH (TMC0nH) (n = 0, 1) Timer unit control register 0n (TUC0n) (n = 0, 1) Timer output mode register n (TOMRn) (n = 0, 1) PWM software timing output register n (PSTOn) (n = 0, 1) PWM output enable register n (POERn) (n = 0, 1) TOMR write enable register n (SPECn) (n = 0, 1) Timer 0 clock selection register (PRM01) Timer 1 Timer 1n (TM1n) (n = 0, 1) Compare register 1n (CM1n) (n = 00, 01, 10, 11) Capture/compare register 1n (CC1n) (n = 00, 01, 10, 11) Capture/compare control register n (CCRn) (n = 0, 1) Timer unit mode register n (TUMn) (n = 0, 1) Timer control register 1n (TMC1n) (n = 0, 1) Signal edge selection register 1n (SESA1n) (n = 0, 1) Prescaler mode register 1n (PRM1n) (n = 0, 1) Status register n (STATUSn) (n = 0, 1) Timer connection selection register 0 (TMIC0) Timer 1/timer 2 clock selection register (PRM02) CC1n1 capture input selection register (CSL1n) (n = 0, 1) Timer 1n noise elimination time selection register (NRC1n) (n = 0, 1) Initial Value After Reset 00H 00H 00H 47H Undefined 00H 00H 00H 0000000xB Undefined 00H 0FFFH FFFFH 0508H 08H 05H 01H 00H 00H 00H 0000H 00H 0000H 0000H 0000H 00H 00H 00H 00H 07H 00H 00H 00H 00H 00H 722 User's Manual U14492EJ5V0UD CHAPTER 15 RESET FUNCTION Table 15-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (3/6) On-Chip Hardware On-chip peripheral I/O Timer 2 Register Name Timer 2 clock stop register 0 (STOPTE0) Timer 2 clock stop register 0L (STOPTE0L) Timer 2 clock stop register 0H (STOPTE0H) Timer 2 count clock/control edge selection register 0 (CSE0) Timer 2 count clock/control edge selection register 0L (CSE0L) Timer 2 count clock/control edge selection register 0H (CSE0H) Timer 2 sub-channel input event edge selection register 0 (SESE0) Initial Value After Reset 0000H 00H 00H 0000H 00H 00H 0000H Timer 2 sub-channel input event edge selection register 0L (SESE0L) 00H Timer 2 sub-channel input event edge selection register 0H (SESE0H) Timer 2 time base control register 0 (TCRE0) Timer 2 time base control register 0L (TCRE0L) Timer 2 time base control register 0H (TCRE0H) Timer 2 output control register 0 (OCTLE0) Timer 2 output control register 0L (OCTLE0L) Timer 2 output control register 0H (OCTLE0H) Timer 2 sub-channel 0, 5 capture/compare control register (CMSE050) Timer 2 sub-channel 1, 2 capture/compare control register (CMSE120) Timer 2 sub-channel 3, 4 capture/compare control register (CMSE340) Timer 2 sub-channel n sub capture/compare register (CVSEn0) (n = 1 to 4) Timer 2 sub-channel n main capture/compare register (CVPEn0) (n = 1 to 4) Timer 2 sub-channel n capture/compare register (CVSEn0) (n = 0, 5) Timer 2 time base status register 0 (TBSTATE0) Timer 2 time base status register 0L (TBSTATE0L) Timer 2 time base status register 0H (TBSTATE0H) Timer 2 capture/compare 1 to 4 status register 0 (CCSTATE0) Timer 2 capture/compare 1 to 4 status register 0L (CCSTATE0L) Timer 2 capture/compare 1 to 4 status register 0H (CCSTATE0H) Timer 2 output delay register 0 (ODELE0) Timer 2 output delay register 0L (ODELE0L) Timer 2 output delay register 0H (ODELE0H) Timer 2 software event capture register (OSCE0) Timer 3 Timer 3 (TM3) Capture/compare register 3n (CC3n) (n = 0, 1) Timer control register 30 (TMC30) Timer control register 31 (TMC31) 00H 0000H 00H 00H 0000H 00H 00H 0000H 0000H 0000H 0000H 0000H 0000H 0101H 01H 01H 0000H 00H 00H 0000H 00H 00H 0000H 0000H 0000H 00H 20H User's Manual U14492EJ5V0UD 723 CHAPTER 15 RESET FUNCTION Table 15-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (4/6) On-Chip Hardware On-chip peripheral I/O Timer 3 Register Name Valid edge selection register (SESC) Timer 3 clock selection register (PRM03) Timer 3 noise elimination time selection register (NRC3) Timer 4 Timer 4 (TM4) Compare register 4 (CM4) Timer control register 4 (TMC4) Serial interface function (CSI0, CSI1) Clocked serial interface mode register n (CSIMn) (n = 0, 1) Clocked serial interface clock selection register n (CSICn) (n = 0, 1) Clocked serial interface receive buffer register n (SIRBn) (n = 0, 1) Clocked serial interface receive buffer register Ln (SIRBLn) (n = 0, 1) Clocked serial interface transmit buffer register n (SOTBn) (n = 0, 1) Clocked serial interface transmit buffer register Ln (SOTBLn) (n = 0, 1) Clocked serial interface read-only receive buffer register n (SIRBEn) (n = 0, 1) Clocked serial interface read-only receive buffer register Ln (SIRBELn) (n = 0, 1) Clocked serial interface initial transmit buffer register n (SOTBFn) (n = 0, 1) Clocked serial interface initial transmit buffer register Ln (SOTBFLn) (n = 0, 1) Serial I/O shift register n (SIOn) (n = 0, 1) Serial I/O shift register Ln (SIOLn) (n = 0, 1) Prescaler mode register (PRSM3) Prescaler compare register (PRSCM3) Serial interface function (UART0) Asynchronous serial interface mode register 0 (ASIM0) Receive buffer register 0 (RXB0) Asynchronous serial interface status register 0 (ASIS0) Transmit buffer register 0 (TXB0) Asynchronous serial interface transmit status register 0 (ASIF0) Baud rate generator control register 0 (BRGC0) Clock selection register 0 (CKSR0) Serial interface function (UART1, UART2) Asynchronous serial interface mode register n0 (ASIMn0) (n = 1, 2) Asynchronous serial interface mode register n1 (ASIMn1) (n = 1, 2) Asynchronous serial interface status register n (ASISn) (n = 1, 2) 2-frame continuous reception buffer register n (RXBn) (n = 1, 2) Receive buffer register Ln (RXBLn) (n = 1, 2) 2-frame continuous transmission shift register n (TXSn) (n = 1, 2) Initial Value After Reset 00H 00H 00H 0000H 0000H 00H 00H 00H 0000H 00H 0000H 00H 0000H 00H 0000H 00H 0000H 00H 00H 00H 01H FFH 00H FFH 00H FFH 00H 81H 00H 00H Undefined Undefined Undefined 724 User's Manual U14492EJ5V0UD CHAPTER 15 RESET FUNCTION Table 15-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (5/6) On-Chip Hardware On-chip peripheral I/O Serial interface function (UART1, UART2) Serial interface function (FCAN) Register Name Transmit shift register Ln (TXSLn) (n = 1, 2) Prescaler mode register n (PRSMn) (n = 1, 2) Prescaler compare register n (PRSCMn) (n = 1, 2) CAN message data length register n (M_DLCn) (n = 00 to 31) CAN message control register n (M_CTRLn) (n = 00 to 31) CAN message time stamp register n (M_TIMEn) (n = 00 to 31) CAN message data register nm (M_DATAnm) (n = 00 to 31, m = 0 to 7) CAN message ID register Ln, Hn (M_IDLn, M_IDHn) (n = 00 to 31) CAN message configuration register n (M_CONFn) (n = 00 to 31) CAN message status register n (M_STATn) (n = 00 to 31) CAN status set/clear register n (SC_STATn) (n = 00 to 31) CAN interrupt pending register (CCINTP) CAN global interrupt pending register (CGINTP) CAN1 interrupt pending register (C1INTP) CAN stop register (CSTOP) CAN global status register (CGST) CAN global interrupt enable register (CGIE) CAN main clock selection register (CGCS) CAN time stamp count register (CGTSC) CAN message search start/result register (CGMSS on write; CGMSR on read) CAN1 address mask n register L, H (C1MASKLn, C1MASKHn) (n = 0 to 3) CAN1 control register (C1CTRL) CAN1 definition register (C1DEF) CAN1 information register (C1LAST) CAN1 error count register (C1ERC) CAN1 interrupt enable register (C1IE) CAN1 bus active register (C1BA) CAN1 bit rate prescaler register (C1BRP) CAN1 bus diagnostic information register (C1DINF) CAN1 synchronization control register (C1SYNC) FCAN clock selection register (PRM04) A/D converter A/D scan mode register n0 (ADSCMn0) (n = 0, 1) A/D scan mode register n0L (ADSCMn0L) (n = 0, 1) A/D scan mode register n0H (ADSCMn0H) (n = 0, 1) A/D scan mode register n1 (ADSCMn1) (n = 0, 1) A/D scan mode register n1L (ADSCMn1L) (n = 0, 1) A/D scan mode register n1H (ADSCMn1H) (n = 0, 1) User's Manual U14492EJ5V0UD Initial Value After Reset Undefined 00H 00H Undefined Undefined Undefined Undefined Undefined Undefined Undefined 0000H 0000H 00H 00H 0000H 0100H 0A00H 7F05H 0000H 0000H Undefined 0101H 0000H 00FFH 0000H 0900H 00FFH 0000H 0000H 0218H 00H 0000H 00H 00H 0000H 00H 00H 725 CHAPTER 15 RESET FUNCTION Table 15-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (6/6) On-Chip Hardware On-chip peripheral I/O A/D converter Register Name A/D voltage detection mode register n (ADETMn) (n = 0, 1) A/D voltage detection mode register nL (ADETMnL) (n = 0, 1) A/D voltage detection mode register nH (ADETMnH) (n = 0, 1) A/D conversion result register 0n (ADCR0n) (n = 0 to 7) A/D conversion result register 1n (ADCR1n) (n = 0 to 7) A/D internal trigger selection register (ITRG0) Port function Ports (P0 to P4, PDH, PCS, PCT, PCM) Port (PDL) Port (PDLL) Port (PDLH) Mode registers (PM1 to PM4, PMDH, PMCS, PMCT, PMCM) Mode register (PMDL) Mode register (PMDLL) Mode register (PMDLH) Mode control registers (PMC1 to PMC4) Mode control registers (PMCDH, PMCCS) Mode control register (PMCDL) Mode control register (PMCDLL) Mode control register (PMCDLH) Mode control register (PMCCT) Mode control register (PMCCM) Function control registers (PFC1, PFC2) NBD function RAM access data buffer register L (NBDL) RAM access data buffer register LL (NBDLL) RAM access data buffer register LU (NBDLU) RAM access data buffer register H (NBDH) RAM access data buffer register HL (NBDHL) RAM access data buffer register HU (NBDHU) DMA source address setting register SL (NBDMSL) DMA source address setting register SH (NBDMSH) DMA destination address setting register DL (NBDMDL) DMA destination address setting register DH (NBDMDH) Flash memory Flash programming mode control register (FLPMC) Initial Value After Reset 0000H 00H 00H 0000H 0000H 00H Undefined Undefined Undefined Undefined FFH FFFFH FFH FFH 00H 00H/FFH 0000H/FFFFH 00H/FFH 00H/FFH 00H/53H 00H/0FH 00H 0000H 00H 00H 0000H 00H 00H Undefined Undefined Undefined Undefined 08H/0CH/00H Note Note PD703116: 00H PD70F3116: 08H or 0CH (For details, refer to 16.7.12 Flash programming mode control register (FLPMC).) Caution In the table above, "Undefined" means either undefined at the time of a power-on reset or undefined due to data destruction when RESET input and data write timing are synchronized. On a RESET other than this, data is maintained in its previous status. 726 User's Manual U14492EJ5V0UD CHAPTER 16 FLASH MEMORY (PD70F3116) The PD70F3116 is the flash memory version of the V850E/IA1 and it has an on-chip 256 KB flash memory configured as two 128 KB areas. Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass producing it with the mask ROM version, be sure to conduct sufficient evaluations on the commercial samples (CS) (not engineering samples (ES)) of the mask ROM versions. Writing to a flash memory can be performed with memory mounted on the target system (on board). dedicated flash programmer is connected to the target system to perform writing. The following can be considered as the development environment and the applications using a flash memory. * Software can be changed after the V850E/IA1 is solder mounted on the target system. * Small scale production of various models is made easier by differentiating software. * Data adjustment in starting mass production is made easier. The 16.1 Features * All area batch erase, or erase in area units (128 KB) * Communication through serial interface from the dedicated flash programmer * Erase/write voltage: VPP = 7.8 V * On-board programming * Flash memory programming is possible by the self-programming in area units (128 KB) 16.2 Writing by Flash Programmer Writing can be performed either on-board or off-board by the dedicated flash programmer. Caution When writing data with the flash programmer, the operation is always performed at the frequency multiplied by 5 in the PLL mode. (1) On-board programming The contents of the flash memory is rewritten after the V850E/IA1 is mounted on the target system. Mount connectors, etc., on the target system to connect the dedicated flash programmer. (2) Off-board programming Writing to a flash memory is performed by the dedicated program adapter (FA Series), etc., before mounting the V850E/IA1 on the target system. Remark The FA Series is a product of Naito Densei Machida Mfg. Co., Ltd. User's Manual U14492EJ5V0UD 727 CHAPTER 16 FLASH MEMORY (PD70F3116) When the flash programming adapter (FA-144GJ-8EU) is used for writing, connect the pins as follows. Table 16-1. Connection of V850E/IA1 Flash Programming Adapter (FA-144GJ-8EU) FA-144GJ-8EU Silk Name Pin Name SI SO SCK X1 X2 /RESET VPP RESERVE/HS LVDD Note 3 V850E/IA1 UART0 Pin No. 38 37 - X1 X2 RESET VPP/IC5 - VDD3 CVDD 53, 128 21 56, 91, 125 137 4 27 2, 135 54, 127 55, 90, 126 3, 136 22 26 28 111 25 23 24 Note 1 Note 1 CSI0 Pin Name SO0/P41 SI0/P40 SCK0/P42 X1 X2 RESET VPP/IC5 A16/PDH0 VDD3 CVDD VDD5 AVREF0 AVREF1 MODE1 AVDD VSS3 VSS5 AVSS CVSS MODE0 MODE2 NMI/P00 CKSEL Note 2 Pin No. 30 29 31 23 24 Note 1 Note 1 TXD0/P31 RXD0/P30 20 89 20 89 73 53, 128 21 56, 91, 125 137 4 27 2, 135 54, 127 55, 90, 126 3, 136 22 26 28 111 25 VDD VDD5 AVREF0 AVREF1 MODE1 AVDD GND VSS3 VSS5 AVSS CVSS MODE0 MODE2 NMI/P00 Note 4 CKSEL Notes 1. Configure the oscillator on the FA-144GJ-8EU board using a resonator and a capacitor. The following figure shows an example of the oscillator. Example CVSS X1 X2 2. 3. 4. Connection is not required for this pin when not using handshakes. The option of dual-power-supply adapter (FA-TVC) for generating 3.3 V is available. In PLL mode: In direct mode: GND VDD5 Remark -: Leave open User's Manual U14492EJ5V0UD 728 CHAPTER 16 FLASH MEMORY (PD70F3116) 16.3 Programming Environment The following shows the environment required for writing programs to the flash memory of the V850E/IA1. Figure 16-1. Environment for Writing Program to Flash Memory VPP1 VDD RS-232C XXXX YYYY XXXXXX VPP Regulator Regulator RESET VDD3 VDD5 VSS3 VSS5 UART0 CSI0 V850E/IA1 Axxxx Bxxxxx Cxxxxxx USB XXX YYY PG-FP4 (Flash Pro4) Host machine Dedicated flash programmer A host machine is required for controlling the dedicated flash programmer. UART0 or CSI0 is used for the interface between the dedicated flash programmer and the V850E/IA1 to perform writing, erasing, etc. A dedicated program adapter (FA Series) is required for off-board writing. Supply the operating clock of the V850E/IA1 via the oscillator configured on the V850E/IA1 board using a resonator and a capacitor. 16.4 Communication Mode (1) UART0 Transfer rate: 4,800 bps to 76,800 bps (LSB first) Figure 16-2. Communication with Dedicated Flash Programmer (UART0) VPP1 VDD XXXX YYYY XXXXX STATVE GND XXXX VPP Regulator Regulator VDD3 VDD5 VSS3 VSS5 Bxxxxx Cxxxxxx XXXXXX Axxxx XXX YYY PG-FP4 (Flash Pro4) Dedicated flash programmer XXXXX STATVE GND RESET SO SI XXXX RESET RXD0 TXD0 V850E/IA1 Caution Supply the operating clock of the V850E/IA1 via the oscillator configured on the V850E/IA1 board using a resonator and a capacitor. User's Manual U14492EJ5V0UD 729 CHAPTER 16 FLASH MEMORY (PD70F3116) (2) CSI0 Transfer rate: up to 2 MHz (MSB first) Figure 16-3. Communication with Dedicated Flash Programmer (CSI0) VPP1 VDD GND RESET Dedicated flash programmer SO SI SCK Regulator Regulator VPP VDD3 VDD5 VSS3 VSS5 RESET SI0 SO0 SCK0 V850E/IA1 XXXX YYYY Bxxxxx Cxxxxxx XXX YYY PG-FP4 (Flash Pro4) Caution Supply the operating clock of the V850E/IA1 via the oscillator configured on the V850E/IA1 board using a resonator and a capacitor. The dedicated flash programmer outputs transfer clocks and the V850E/IA1 operates as a slave. (3) Handshake-supported CSI communication Transfer rate: up to 2 MHz (MSB first) Figure 16-4. Communication with Dedicated Flash Programmer (Handshake-Supported CSI Communication) XXXXX STATVE XXXX XXXXXX Axxxx VPP1 VDD GND XXXX YYYY VPP Regulator Regulator VDD3 VDD5 VSS3 VSS5 Bxxxxx Cxxxxxx XXXX XXXXXX Axxxx XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE RESET SO SI SCK HS RESET SI0 SO0 SCK0 PDH0 V850E/IA1 Dedicated flash programmer Caution Supply the operating clock of the V850E/IA1 via the oscillator configured on the V850E/IA1 board using a resonator and a capacitor. 730 User's Manual U14492EJ5V0UD CHAPTER 16 FLASH MEMORY (PD70F3116) 16.5 Pin Connection When performing on-board writing, install a connector on the target system to connect to the dedicated flash programmer. Also, install a function on-board to switch from the normal operation mode (single-chip modes 0, 1 or ROMless modes 0, 1) to the flash memory programming mode. In the flash memory programming mode, all the pins not used for flash memory programming become the same status as they were immediately after reset in single-chip mode 0. Therefore, all the ports enter the output highimpedance status, so that pin handling is required when the external device does not acknowledge the output highimpedance status. 16.5.1 VPP pin In the normal operation mode, 0 V is input to the VPP pin. In the flash memory programming mode, 7.8 V writing voltage is supplied to the VPP pin. The following shows an example of the connection of the VPP pin. Figure 16-5. Connection Example of VPP Pin V850E/IA1 Dedicated flash programmer connection pin VPP Pull-down resistor (RVPP = 4.7 to 47 k) 16.5.2 Serial interface pin The following shows the pins used by each serial interface. Table 16-2. Pins Used by Each Serial Interface Serial Interface CSI0 CSI0 + HS UART0 Pins Used SO0, SI0, SCK0 SO0, SI0, SCK0, PDH0 TXD0, RXD0 When connecting a dedicated flash programmer to a serial interface pin that is connected to other devices onboard, care should be taken to avoid the conflict of signals and the malfunction of other devices, etc. (1) Conflict of signals When connecting a dedicated flash programmer (output) to a serial interface pin (input) which is connected to another device (output), a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. User's Manual U14492EJ5V0UD 731 CHAPTER 16 FLASH MEMORY (PD70F3116) Figure 16-6. Conflict of Signals (Serial Interface Input Pin) V850E/IA1 Conflict of signals Input pin Other device Output pin Dedicated flash programmer connection pin In the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals the other device outputs. Therefore, isolate the signals on the other device side. (2) Malfunction of the other device When connecting a dedicated flash programmer (output or input) to a serial interface pin (input or output) connected to another device (input), the signal output to the other device may cause the device to malfunction. To avoid this, isolate the connection to the other device or make the setting so that the input signal to the other device is ignored. Figure 16-7. Malfunction of Other Device V850E/IA1 Dedicated flash programmer connection pin Pin Other device Input pin In the flash memory programming mode, if the signal the V850E/IA1 outputs affects the other device, isolate the signal on the other device side. V850E/IA1 Dedicated flash programmer connection pin Pin Other device Input pin In the flash memory programming mode, if the signal the dedicated flash programmer outputs affects the other device, isolate the signal on the other device side. 732 User's Manual U14492EJ5V0UD CHAPTER 16 FLASH MEMORY (PD70F3116) 16.5.3 RESET pin When connecting the reset signals of the dedicated flash programmer to the RESET pin, which is connected, to the reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator. When the reset signal is input from the user system in flash memory programming mode, the programming operation will not be performed correctly. dedicated flash programmer. Figure 16-8. Conflict of Signals (RESET Pin) Therefore, do not input signals other than the reset signals from the V850E/IA1 Conflict of signals RESET Reset signal generator Output pin Dedicated flash programmer connection pin In the flash memory programming mode, the signal the reset signal generator outputs conflicts with the signal the dedicated flash programmer outputs. Therefore, isolate the signals on the reset signal generator side. 16.5.4 NMI pin Do not change the input signal to the NMI pin in flash memory programming mode. If it is changed in flash memory programming mode, programming may not be performed correctly. 16.5.5 MODE0 to MODE2 pins To shift to the flash memory programming mode, set MODE0 to high-level or low-level input, MODE1 to high-level input, and MODE2 to low-level input, apply the writing voltage (7.8 V) to the VPP pin, and release reset. 16.5.6 Port pins When the flash memory programming mode is set, all the port pins except the pins which communicate with the dedicated flash programmer become output high-impedance status. Nothing need be done to these port pins. If problems such as disabling output high-impedance status should occur to the external devices connected to the ports, connect them to VDD5 or VSS5 via resistors. 16.5.7 Other signal pins Connect X1 and X2 to the same status as in the normal operation mode. The amplitude is 3.3 V. User's Manual U14492EJ5V0UD 733 CHAPTER 16 FLASH MEMORY (PD70F3116) 16.5.8 Power supply Supply the power supply (VDD3, VSS3, VDD5, VSS5, AVDD, AVREF0, AVREF1, AVSS, CVDD, and CVSS) the same as in normal operation mode. Connect VDDNote and GND of the dedicated flash programmer to VDD3, VSS3, VDD5, and VSS5 (VDD of the dedicated flash programmer is provided with a power supply monitoring function). Note Connect VDD after converting the power supply to 3.3 V using a regulator. 16.6 Programming Method 16.6.1 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 16-9. Flash Memory Manipulating Procedure Start Supply RESET pulse Switch to flash memory programming mode Select communication mode Manipulate flash memory End? Yes No End 734 User's Manual U14492EJ5V0UD CHAPTER 16 FLASH MEMORY (PD70F3116) 16.6.2 Flash memory programming mode When rewriting the contents of flash memory using the dedicated flash programmer, set the V850E/IA1 in the flash memory programming mode. canceling reset. When performing on-board writing, change modes using a jumper, etc. * MODE0: High-level or low-level input * MODE1: High-level input * MODE2: Low-level input * VPP: 7.8 V Figure 16-10. Flash Memory Programming Mode To switch to this mode, set the MODE0, MODE1, MODE2, and VPP pins before Flash memory programming mode 7.8 V VPP 3.3 V 0V RESET 1 2 ... n 16.6.3 Selection of communication mode In the V850E/IA1, a communication mode is selected by inputting pulses (16 pulses max.) to VPP pin after switching to the flash memory programming mode. The VPP pulse is generated by the dedicated flash programmer. The following shows the relationship between the number of pulses and the communication mode. Table 16-3. List of Communication Mode VPP Pulse 0 3 8 Others Communication Mode CSI0 Handshake-supported CSI UART0 RFU (reserved) Communication rate: 9600 bps (after reset), LSB first Setting prohibited Remarks V850E/IA1 performs slave operation, MSB first User's Manual U14492EJ5V0UD 735 CHAPTER 16 FLASH MEMORY (PD70F3116) 16.6.4 Communication commands The V850E/IA1 communicates with the dedicated flash programmer by means of commands. A command sent from the dedicated flash programmer to the V850E/IA1 is called a "command". The response signal sent from the V850E/IA1 to the dedicated flash programmer is called the "response command". Figure 16-11. Communication Commands XXXX YYYY Bxxxxx Cxxxxxx XXX YYY PG-FP4 (Flash Pro4) XXXXX STATVE XXXX XXXXXX Axxxx Command Response command V850E/IA1 Dedicated flash programmer The following shows the commands for controlling flash memory of the V850E/IA1. All of these commands are issued from the dedicated flash programmer, and the V850E/IA1 performs the various processing corresponding to the commands. Table 16-4. Commands for Controlling Flash Memory Category Verify Command Name Batch verify command Function Compares the contents of the entire memory and the input data. Area verify command Compares the contents of the specified area and the input data. Erases the contents of the entire memory. Erases the contents of the specified area. Writes back the contents which were erased. Checks the erase state of the entire memory. Checks the erase state of the specified area. Writes data by the specification of the write address and the number of bytes to be written, and executes verify check. Continuous write command Writes data from the address following the highspeed write command executed immediately before, and executes verify check. System setting and control Status read out command Oscillation frequency setting command Erasing time setting command Writing time setting command Write back time setting command Silicon signature command Reset command Acquires the status of operations. Sets the oscillation frequency. Sets the erasing time of batch erase. Sets the writing time of data write. Sets the write back time. Reads outs the silicon signature information. Escapes from each state. Erase Batch erase command Area erase command Write back command Blank check Batch blank check command Area blank check command Data write High-speed write command 736 User's Manual U14492EJ5V0UD CHAPTER 16 FLASH MEMORY (PD70F3116) The V850E/IA1 sends back response commands for the commands issued from the dedicated flash programmer. The following shows the response commands the V850E/IA1 sends out. Table 16-5. Response Commands Response Command Name ACK (acknowledge) NAK (not acknowledge) Function Acknowledges command/data, etc. Acknowledges illegal command/data, etc. 16.7 Flash Memory Programming by Self-Programming The PD70F3116 supports a self-programming function to rewrite the flash memory using a user program. By using this function, the flash memory can be rewritten with a user application. This self-programming function can be also used to upgrade the program in the field. 16.7.1 Outline of self-programming Self-programming implements erasure and writing of the flash memory by calling the self-programming function (device's internal processing) on the program placed in the block 0 space (000000H to 1FFFFFH) and areas other than internal ROM area. To place the program in the block 0 space and internal ROM area, copy the program to areas other than 000000H to 1FFFFFH (e.g. internal RAM area) and execute the program to call the selfprogramming function. To call the self-programming function, change the operating mode from normal operation mode to selfprogramming mode using the flash programming mode control register (FLPMC). Figure 16-12. Outline of Self-Programming Normal operation mode Self-programming mode Flash memory 3FFFFH 3FFFFH Flash memory FLPMC 02H Erase areaNote (128 KB) Self-programming function (erase/write routine incorporated) 256 KB FLPMC 00H Erase areaNote (128 KB) 00000H 00000H Note Data is erased in area units (128 KB). User's Manual U14492EJ5V0UD 737 CHAPTER 16 FLASH MEMORY (PD70F3116) 16.7.2 Self-programming function The PD70F3116 provides self-programming functions, as shown in Table 16-6. By combining these functions, erasing/writing flash memory becomes possible. Table 16-6. Function List Type Erase Write Function Name Area erase Continuous write in word units Function Erases the specified area. Continuously writes the specified memory contents from the specified flash memory address, for the number of words specified in 4-byte units. Pre-write Check Erase verify Erase byte verify Internal verify Writes 0 to flash memory before erasure. Checks whether an over erase occurred after erasure. Checks whether erasure is complete. Checks whether the signal level of the post-write data in flash memory is appropriate. Writes back the flash memory area in which an over erase occurred. Reads out information about flash memory. Write back Area write back Acquire information Flash memory information read 16.7.3 Outline of self-programming interface To execute self-programming using the self-programming interface, the environmental conditions of the hardware and software for manipulating the flash memory must be satisfied. It is assumed that the self-programming interface is used in an assembly language. (1) Entry program This program is to call the internal processing of the device. It is a part of the application program, and must be executed in memory other than the block 0 space and internal ROM area (flash memory). (2) Device internal processing This is manipulation of the flash memory executed inside the device. This processing manipulates the flash memory after it has been called by the entry program. (3) RAM parameter This is a RAM area to which the parameters necessary for self-programming, such as write time and erase time, are written. It is set by the application program and referenced by the device internal processing. 738 User's Manual U14492EJ5V0UD CHAPTER 16 FLASH MEMORY (PD70F3116) The self-programming interface is outlined below. Figure 16-13. Outline of Self-Programming Interface Application program Entry program Self-programming interface Device internal processing RAM parameter Flash-memory manipulation Flash memory 16.7.4 Hardware environment To write or erase the flash memory, a high voltage must be applied to the VPP pin. To execute self-programming, a circuit that can generate a write voltage (VPP) and that can be controlled by software is necessary on the application system. An example of a circuit that can select a voltage to be applied to the VPP pin by manipulating a port is shown below. Figure 16-14. Example of Self-Programming Circuit Configuration VDD = 5.0 V 0.5 V VDD = 3.3 V 0.3 V VDD5, AVDD PD70F3116 VDD3, CVDD VPP VPP = 7.8 V 0.3 V IC for power supply OUTPUT 10 k ON/OFF VSS INPUT VIN Output port 10 k VSS3, VSS5, CVSS, AVSS User's Manual U14492EJ5V0UD 739 CHAPTER 16 FLASH MEMORY (PD70F3116) The voltage applied to the VPP pin must satisfy the following conditions: * Hold the voltage applied to the VPP pin at 0 V in the normal operation mode and hold the VPP voltage only while the flash memory is being manipulated. * The VPP voltage must be stable from before manipulation of the flash memory starts until manipulation is complete. Cautions 1. Apply 0 V to the VPP pin when reset is released. 2. Implement self-programming in single-chip mode 0 or 1. 3. Apply the voltage to the VPP pin in the entry program. 4. If both writing and erasing are executed by using the self-programming function and flash memory programmer on the target board, be sure to communicate with the programmer using CSI0 (do not use the handshake-supported CSI). Figure 16-15. Timing to Apply Voltage to VPP Pin VDD3 or VDD5 RESET signal 0V VPP VPP signal 0V Flash memory manipulation 740 User's Manual U14492EJ5V0UD CHAPTER 16 FLASH MEMORY (PD70F3116) 16.7.5 Software environment The following conditions must be satisfied before using the entry program to call the device internal processing. Table 16-7. Software Environmental Conditions Item Location of entry program Description Execute the entry program in memory other than the block 0 space and flash memory area. The device internal processing cannot be directly called by the program that is executed on the flash memory. The device internal processing cannot be called while an interrupt is being serviced (NP bit of PSW = 0, ID bit of PSW = 1). Mask all the maskable interrupts used. Mask each interrupt by using the corresponding interrupt control register. To mask a maskable interrupt, be sure to specify masking by using the corresponding interrupt control register. Mask the maskable interrupt even when the ID bit of the PSW = 1 (interrupts are disabled). Manipulation of VPP voltage Initialization of internal timer Stabilize the voltage applied to the VPP pin (VPP voltage) before starting manipulation of the flash memory. After completion of the manipulation, return the voltage of the VPP pin to 0 V. Do not use the internal timer while the flash memory is being manipulated. Because the internal timer is initialized after the flash memory has been used, initialize the timer with the application program to use the timer again. Do not input the reset signal while the flash memory is being manipulated. If the reset signal is input while the flash memory is being manipulated, the contents of the flash memory under manipulation become undefined. Do not input the NMI signal while the flash memory is being manipulated. If the NMI signal is input while the flash memory is being manipulated, the flash memory may not be correctly manipulated by the device internal processing. If an NMI occurs while the device internal processing is in progress, the occurrence of the NMI is reflected in the NMI flag of the RAM parameter. If manipulation of the flash memory is affected by the occurrence of the NMI, the function of each self-programming function is reflected in the return value. Reserving stack area The device internal processing takes over the stack used by the user program. It is necessary that an area of 300 bytes be reserved for the stack size of the user program when the device internal processing is called. r3 is used as the stack pointer. Saving general-purpose registers The device internal processing rewrites the contents of r6 to r14, r20, and r31 (lp). Save and restore these register contents as necessary. Execution status of program Masking interrupts Stopping reset signal input Stopping NMI signal input User's Manual U14492EJ5V0UD 741 CHAPTER 16 FLASH MEMORY (PD70F3116) 16.7.6 Self-programming function number To identify a self-programming function, the following numbers are assigned to the respective functions. These function numbers are used as parameters when the device internal processing is called. Table 16-8. Self-Programming Function Number Function No. 0 1 2 to 4 5 6 to 8 9 10 11 to 15 16 17 to 19 20 21 Other Function Name Acquiring flash information Erasing area RFU Area write back RFU Erase byte verify Erase verify RFU Continuous write in word units RFU Pre-write Internal verify Prohibited Remark RFU: Reserved for Future Use 742 User's Manual U14492EJ5V0UD CHAPTER 16 FLASH MEMORY (PD70F3116) 16.7.7 Calling parameters The arguments used to call the self-programming function are shown in the table below. In addition to these arguments, parameters such as the write time and erase time are set to the RAM parameters indicated by ep (r30). Table 16-9. Calling Parameters Function Name First Argument (r6) Function No. Acquiring flash information Erasing area 1 Area erase start address None (acts on erase manipulation area immediately before) Erase byte verify 9 Verify start address Number of bytes to be verified - - - 0: Normal completion Other than 0: Error 0: Normal completion Other than 0: Error - - - - 0: Normal completion Other than 0: Error None 0 Second Argument (r7) Option number Note 1 Third Argument (r8) - Fourth Argument (r9) - Return Value (r10) Note 1 Area write back 5 Erase verify 10 None (acts on erase manipulation area immediately before) Continuous write 16 Note 2 in word units Write start Note 3 address Number of words Start address of Note 3 write source data to be written (word units) Number of bytes to be written Number of bytes to be verified - - 0: Normal completion Other than 0: Error Pre-write 20 Write start address 0: Normal completion Other than 0: Error 0: Normal completion Other than 0: Error Internal verify 21 Verify start address Notes 1. 2. 3. Caution See 16.7.10 Flash information for details. Prepare write source data in memory other than the flash memory when data is written continuously in word units. This address must be at a 4-byte boundary. For all the functions, ep (r30) must indicate the first address of the RAM parameter. User's Manual U14492EJ5V0UD 743 CHAPTER 16 FLASH MEMORY (PD70F3116) 16.7.8 Contents of RAM parameters Reserve the following 48-byte area in the internal RAM or external RAM for the RAM parameters, and set the parameters to be input. Set the base addresses of these parameters to ep (r30). Table 16-10. Description of RAM Parameter Address ep+0 ep+4:Bit 5 Note 1 Size 4 bytes 1 bit I/O - Input For internal operations Description Operation flag (Be sure to set this flag to 1 before calling the device internal processing.) 0: Normal operation in progress 1: Self-programming in progress ep+4:Bit 7 Notes 2, 3 1 bit Output NMI flag 0: NMI not detected 1: NMI detected ep+8 4 bytes Input Erase time (unsigned 4 bytes) Expressed as 1 count value in units of the internal operation unit time (100 s). Set value = Erase time (s)/internal operation unit time (s) Example: If erase time is 0.4 s 0.4 x 1,000,000/100 = 4,000 (integer operation) ep+0xc 4 bytes Input Write back time (unsigned 4 bytes) Expressed as 1 count value in units of the internal operation unit time (100 s). Set value = Write back time (s)/internal operation unit time (s) Example: If write back time is 1 ms 1 x 1,000/100 = 10 (integer operation) ep+0x10 2 bytes Input Timer set value for creating internal operation unit time (unsigned 2 bytes) Write a set value that makes the value of timer 4 the internal operation unit time (100 s). Set value = Operating frequency (Hz)/1,000,000 x Internal operation unit time (s)/ Timer division ratio (4) + 1 Note 4 Example: If the operating frequency is 50 MHz 50,000,000/1,000,000 x 100/4 + 1 = 1,251 (integer operation) ep+0x12 2 bytes Input Timer set value for creating write time (unsigned 2 bytes) Write a set value that makes the value of timer 4 the write time. Set value = Operating frequency (Hz)/Write time (s)/Timer division ratio (4) + 1 Example: If the operating frequency is 50 MHz and the write time is 20 s 50,000,000/1,000,000 x 20/4 + 1 = 251 (integer operation) ep+0x14 28 bytes - For internal operations Note 4 Notes 1. 2. 3. 4. Fifth bit of address of ep+4 (least significant bit is bit 0.) Seventh bit of address of ep+4 (least significant bit is bit 0.) Clear the NMI flag by the user program because it is not cleared by the device internal processing. The device internal processing sets this value minus 1 to the timer. Because the fraction is rounded up, add 1 as indicated by the expression of the set value. Caution Be sure to reserve the RAM parameter area at a 4-byte boundary. 744 User's Manual U14492EJ5V0UD CHAPTER 16 FLASH MEMORY (PD70F3116) 16.7.9 Errors during self-programming The following errors related to manipulation of the flash memory may occur during self-programming. An error occurs if the return value (r10) of each function is not 0. Table 16-11. Errors During Self-Programming Error Overerase error Undererase error (blank check error) Verify error Erase verify Erase byte verify Function Description Excessive erasure occurs. Erasure is insufficient. needed. Additional erase operation is Continuous write in word units The written data cannot be correctly read. Either an attempt has been made to write to flash memory that has not been erased, or writing is not sufficient. Internal verify error Internal verify The written data is not at the correct signal level. Caution The overerase error and undererase error may simultaneously occur in the entire flash memory. 16.7.10 Flash information For the flash information acquisition function (function No. 0), the option number (r7) to be specified and the contents of the return value (r10) are as follows. To acquire all flash information, call the function as many times as required in accordance with the format shown below. Table 16-12. Flash Information Option No. (r7) 0 1 2 Specification prohibited Specification prohibited Bit representation of return value (MSB: bit 31) FFFFFFFFFFFFFFFFAAAAAAAAFFFFFFFF (LSB: bit 0) Bits 31 to 16: FFFFFFFFFFFFFFFF (reserved for future use) Mask bits 31 to 16 because they are not normally 0. Bits 15 to 8: AAAAAAAA (number of areas) (unsigned 8 bits) Bits 7 to 0: FFFFFFFF (reserved for future use) Mask bits 7 to 0 because they are not normally 0. Return Value (r10) 3+0 3+1 End address of area 0 End address of area 1 Cautions 1. The start address of area 0 is 0. The "end address + 1" of the preceding area is the start address of the next area. 2. The flash information acquisition function does not check values such as the maximum number of areas specified by the argument of an option. If an illegal value is specified, an undefined value is returned. User's Manual U14492EJ5V0UD 745 CHAPTER 16 FLASH MEMORY (PD70F3116) 16.7.11 Area number The area numbers and memory map of the PD70F3116 are shown below. Figure 16-16. Area Configuration 0 x 3 F F F F (End address of area 1) Area 1 (128 KB) 0 x 2 0 0 0 0 (Start address of area 1) 0 x 1 F F F F (End address of area 0) Area 0 (128 KB) 0 x 0 0 0 0 0 (Start address of area 0) 746 User's Manual U14492EJ5V0UD CHAPTER 16 FLASH MEMORY (PD70F3116) 16.7.12 Flash programming mode control register (FLPMC) The flash programming mode control register (FLPMC) is a register used to enable/disable writing to flash memory and to specify the self-programming mode. This register can be read/written in 8-bit or 1-bit units (the VPP bit (bit 2) is read-only). Cautions 1. Be sure to transfer control to the internal RAM or external memory beforehand to manipulate the FLSPM bit. However, in on-board programming mode set by the flash programmer, the specification of FLSPM bit is ignored. 2. Do not change the initial value of bits 0 and 4 to 7. 7 FLPMC 0 6 0 5 0 4 0 <3> VPPDIS <2> VPP <1> FLSPM 0 0 Address FFFFF8D4H Initial valueNote 08H/0CH/00H Note 08H: 00H: Bit position 3 When writing voltage is not applied to the VPP pin Product not provided with flash memory (PD703116) Bit name Function Enables/disables writing/erasing on-chip flash memory. When this bit is 1, writing/erasing on-chip flash memory is disabled even if a high voltage is applied to the VPP pin. 0: Enables writing/erasing flash memory 1: Disables writing/erasing flash memory 0CH: When writing voltage is applied to the VPP pin VPPDIS 2 VPP Indicates the voltage applied to the VPP pin reaches the writing-enabled level (readonly). This bit is used to check whether writing is possible or not in the selfprogramming mode. 0: Indicates high-voltage application to VPP pin is not detected (the voltage has not reached the writing voltage enable level) 1: Indicates high-voltage application to VPP pin is detected (the voltage has reached the writing voltage enable level) 1 FLSPM Controls switching between internal ROM and the self-programming interface. This bit can switch the mode between the normal mode set by the mode pin on the application system and the self-programming mode. The setting of this bit is valid only if the voltage applied to the VPP pin reaches the writing voltage enable level. 0: Normal mode (for all addresses, instruction fetch is performed from on-chip flash memory) 1: Self-programming mode (device internal processing is started) User's Manual U14492EJ5V0UD 747 CHAPTER 16 FLASH MEMORY (PD70F3116) Setting data to the flash programming mode control register (FLPMC) is performed in the following sequence. <1> Disable interrupts (set the NP bit and ID bit of the PSW to 1). <2> Prepare the data to be set in the specific register in a general-purpose register. <3> Write data to the peripheral command register (PHCMD). <4> Set the flash programming mode control register (FLPMC) by executing the following instructions. * Store instruction (ST/SST instructions) * Bit manipulation instruction (SET1/CLR1/NOT1 instructions) <5> Insert NOP instructions (5 instructions (<5> to <9>)). <10> Cancel the interrupt disabled state (reset the NP bit of the PSW to 0). [Description example] <1> LDSR <2> MOV <3> ST.B <4> ST.B <5> NOP <6> NOP <7> NOP <8> NOP <9> NOP <10> LDSR Remark rY, 5 rX, 5 0x02, r10 r10, PHCMD[r0] r10, FLPMC[r0] rX: Value written to the PSW rY: Value returned to the PSW No special sequence is required for reading a specific register. Cautions 1. If an interrupt is acknowledged between when PHCMD is issued (<3>) and writing to a specific register (<4>) immediately after issuing PHCMD, writing to the specific register may not be performed and a protection error may occur (the PRERR bit of the PHS register = 1). Therefore, set the NP bit of the PSW to 1 (<1>) to disable interrupt acknowledgment. Similarly, disable acknowledgment of interrupts when a bit manipulation instruction is used to set a specific register. 2. Use the same general-purpose register used to set a specific register (<3>) for writing to the PHCMD register (<4>) even though the data written to the PHCMD register is dummy data. This is the same as when a general-purpose register is used for addressing. 3. Before executing this processing, complete all DMA transfer operations. 748 User's Manual U14492EJ5V0UD CHAPTER 16 FLASH MEMORY (PD70F3116) 16.7.13 Calling device internal processing This section explains the procedure to call the device internal processing from the entry program. Before calling the device internal processing, make sure that all the conditions of the hardware and software environments are satisfied and that the necessary arguments and RAM parameters have been set. Call the device internal processing by setting the FLSPM bit of the flash programming mode control register (FLPMC) to 1 and then executing the trap 0x1f instruction. The processing is always called using the same procedure. It is assumed that the program of this interface is described in an assembly language. <1> Set the FLPMC register as follows: * VPPDIS bit = 0 (to enable writing/erasing flash memory) * FLSPM bit = 1 (to select self-programming mode) <2> Clear the NP bit of the PSW to 0 (to enable NMIs (only when NMIs are used on the application)). <3> Execute trap 0x1f to transfer the control to the device's internal processing. <4> Set the NP bit and ID bit of the PSW to 1 (to disable all interrupts). <5> Set the value to the peripheral command register (PHCMD) that is to be set to the FLPMC register. <6> Set the FLPMC register as follows: * VPPDIS bit = 1 (to disable writing/erasing flash memory) * FLSPM bit = 0 (to select normal operation mode) <7> Wait for the internal manipulation setup time (see 16.7.13 (5) Internal manipulation setup parameter). (1) Parameter r6: First argument (sets a self-programming function number) r7: Second argument r8: Third argument r9: Fourth argument ep: First address of RAM parameter (2) Return value r10: Return value (return value from device internal processing of 4 bytes) executed) 0: NMI did not occur while device internal processing was being executed. 1: NMI occurred while device internal processing was being executed. If an NMI occurs while control is being transferred to the device internal processing, the NMI request may never be reflected. Because the NMI flag is not internally reset, this bit must be cleared before calling the device internal processing. After the control returns from the device internal processing, NMI dummy processing can be executed by checking the status of this flag using software. (3) Description Transfer control to the device internal processing specified by a function number using the trap instruction. To do this, the hardware and software environmental conditions must be satisfied. Even if trap 0x1f is used in the user application program, trap 0x1f is treated as another operation after the FLPMC register has been set. Therefore, use of the trap instruction is not restricted on the application. ep+4:Bit 7: NMI flag (flag indicating whether an NMI occurred while the device internal processing was being User's Manual U14492EJ5V0UD 749 CHAPTER 16 FLASH MEMORY (PD70F3116) (4) Program example An example of a program in which the entry program is executed as a subroutine is shown below. In this example, the return address is saved to the stack and then the device internal processing is called. This program must be located in memory other than the block 0 space and flash memory area. ISETUP add st.w movea ldsr mov st.b st.b nop nop nop nop nop movea ldsr trap movea ldsr mov st.b st.b nop nop nop nop nop mov loop: divh add jne ld.w add jmp r6, r6 -1, lp loop 0[sp], lp 4, sp [lp] -- To kill time -- Decrement counter --- Reload lp -- Dispose -- Return to caller ISETUP, lp -- loop time = 130 lo(0x0020), r0, r10 r10, 5 0x1f lo(0x00a0), r0, r6 r6, 5 lo(0x08), r6 r6, PHCMD[r0] r6, FLPMC[r0] -- PHCMD = 8 -- VPPDIS = 1, FLSPM = 0 --- PSW = ID -- Device Internal Process --- PSW = NP, ID 130 -4, sp lp, 0[sp] lo(0x00a0), r0, r10 r10, 5 lo(0x0002), r10 r10, PHCMD[r0] r10, FLPMC[r0] -- Internal manipulation setup parameter -- Prepare -- Save return address --- PSW = NP, ID --- PHCMD = 2 -- VPPDIS = 0, FLSPM = 1 EntryProgram: 750 User's Manual U14492EJ5V0UD CHAPTER 16 FLASH MEMORY (PD70F3116) (5) Internal manipulation setup parameter If the self-programming mode is switched to the normal operation mode, the PD70F3116 must wait for 100 s before it accesses the flash memory. In the program example in (4) above, the elapse of this wait time is ensured by setting ISETUP to "130" (@ 50 MHz operation). The total number of execution clocks in this example is 39 clocks (divh instruction (35 clocks) + add instruction (1 clock) + jne instruction (3 clocks)). Ensure that a wait time of 100 s elapses by using the following expression. 39 clocks (total number of execution clocks) x 20 ns (@ 50 MHz operation) x 130 (ISETUP) = 101.4 s (wait time) User's Manual U14492EJ5V0UD 751 CHAPTER 16 FLASH MEMORY (PD70F3116) 16.7.14 Erasing flash memory flow The procedure to erase the flash memory is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure. Figure 16-17. Erasing Flash Memory Flow Erase Set RAM parameter. Mask interrupts. Set VPP voltage. Pre-write ... Function No. 20 Clear VPP voltage. Unmask interrupts. Write error Write error? No Erase area Erase byte verify Yes ... Function No. 1 ... Function No. 9 Maximum number of times of repeating erasure is exceeded? Yes Clear VPP voltage. Unmask interrupts. Undererase error No Undererase? No Erase verify Yes ... Function No. 10 Overerase? Yes Area write back Erase verify No ... Function No. 5 Clear VPP voltage. Unmask interrupts. Normal completion ... Function No. 10 Overerase? No Clear number of times write-back is repeated. Erase byte verify Yes Maximum number of times of repeating write-back is exceeded? Yes Clear VPP voltage. Unmask interrupts. Overerase error No ... Function No. 9 Undererase? Yes No Clear VPP voltage. Unmask interrupts. Normal completion 752 User's Manual U14492EJ5V0UD CHAPTER 16 FLASH MEMORY (PD70F3116) 16.7.15 Continuous writing flow The procedure to write data all at once to the flash memory by using the function to continuously write data in word units is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure. Figure 16-18. Continuous Writing Flow Continuous writing Set RAM parameter. Mask interrupts. Set VPP voltage. Continuous writing ... Function No. 16 Error? Yes Clear VPP voltage. Unmask interrupts. No Clear VPP voltage. Unmask interrupts. Write error Normal completion User's Manual U14492EJ5V0UD 753 CHAPTER 16 FLASH MEMORY (PD70F3116) 16.7.16 Internal verify flow The procedure of internal verification is illustrated below. executed in accordance with the specified calling procedure. Figure 16-19. Internal Verify Flow The processing of each function number must be Internal verify Set RAM parameter. Mask interrupts. Set VPP voltage. Internal verify ... Function No. 21 Error? Yes Clear VPP voltage. Unmask interrupts. No Clear VPP voltage. Unmask interrupts. Internal verify error Normal completion 754 User's Manual U14492EJ5V0UD CHAPTER 16 FLASH MEMORY (PD70F3116) 16.7.17 Acquiring flash information flow The procedure to acquire the flash information is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure. Figure 16-20. Acquiring Flash Information Flow Acquiring flash information Set RAM parameter. Mask interrupts. Set VPP voltage. Acquiring flash information ... Function No. 0 Clear VPP voltage. Unmask interrupts. End User's Manual U14492EJ5V0UD 755 CHAPTER 16 FLASH MEMORY (PD70F3116) 16.7.18 Self-programming library V850 Series Flash Memory Self-Programming User's Manual is available for reference when executing selfprogramming. In this manual, the library uses the self-programming interface of the V850 Series and can be used in C as a utility and as part of the application program. To use the library, thoroughly evaluate it on the application system. (1) Functional outline Figure 16-21 outlines the function of the self-programming library. In this figure, a rewriting module is located in area 0 and the data in area 1 is rewritten or erased. The rewriting module is a user program to rewrite the flash memory. The other areas can be also rewritten by using the flash functions included in this self-programming library. The flash functions expand the entry program in the external memory or internal RAM and call the device internal processing. When using the self-programming library, make sure that the hardware conditions, such as the write voltage, and the software conditions, such as interrupts, are satisfied. Figure 16-21. Functional Outline of Self-Programming Library Flash memory Area 1 Erase/write Rewriting module Flash rewriting program Rewriting module Flash function Flash environment Area 0 Self-programming library 756 User's Manual U14492EJ5V0UD CHAPTER 16 FLASH MEMORY (PD70F3116) The configuration of the self-programming library is outlined below. Figure 16-22. Outline of Self-Programming Library Configuration Application program C interface Self-programming library Entry program Self-programming interface Device internal processing Flash memory manipulation Flash memory RAM parameter User's Manual U14492EJ5V0UD 757 CHAPTER 16 FLASH MEMORY (PD70F3116) 16.8 How to Distinguish Flash Memory and Mask ROM Versions It is possible to distinguish a flash memory version (PD70F3116) and a mask ROM version (PD703116) by means of software, using the methods shown below. <1> Disable interrupts (set the NP bit of PSW to 1). <2> Write data to the peripheral command register (PHCMD). <3> Set the VPPDIS bit of the flash programming mode control register (FLPMC) to 1. <4> Insert NOP instructions (5 instructions (<4> to <8>)). <9> Cancel the interrupt disabled state (reset the NP bit of the PSW to 0). <10> Read the VPPDIS bit of the flash programming mode control register (FLPMC). * If the value read is 0: Mask ROM version (PD703116) * If the value read is 1: Flash memory version (PD70F3116) [Description example] <1> LDSR <2> ST.B <3> SET1 <4> NOP <5> NOP <6> NOP <7> NOP <8> NOP <9> LDSR <10> TST1 BNZ BR Remark rX: Value written to the PSW rY: Value returned to the PSW Cautions 1. If an interrupt is acknowledged between when PHCMD is issued (<2>) and writing to a specific register (<3>) immediately after issuing PHCMD, writing to a specific register may not be performed and a protection error may occur (the PRERR bit of the PHS register = 1). Therefore, set the NP bit of the PSW to 1 (<1>) to disable interrupt acknowledgment. Similarly, disable acknowledgment of interrupts when a bit manipulation instruction is used to set a specific register. 2. When a store instruction is used for setting a specific register, be sure to use the same general-purpose register used to set the specific register for writing to the PHCMD register even though the data written to the PHCMD register is dummy data. This is the same as when a general-purpose register is used for addressing. 3. Before executing this processing, complete all DMA transfer operations. rY, 5 3, FLPMC[r0] 758 User's Manual U14492EJ5V0UD CHAPTER 17 TURNING ON/OFF POWER The V850E/IA1 has three types of power supply pins: 3.3 V power supply pins for internal units (VDD3 and CVDD), 5 V power supply pins for external pins (VDD5 and AVDD), and a flash programming power supply pin (VPP)Note. This chapter explains the I/O pin status when power is turned ON/OFF. Note PD70F3116 only [Recommended timing of turning ON/OFF power] * To turn ON Keep the voltage on the VDD5 and AVDD pins at 0 V until the voltage on the VDD3 pin rises to the level at which the operation is guaranteed (3.0 to 3.6 V). * To turn OFF Keep the voltage on the VDD3 pin at the level at which the operation is guaranteed (3.0 to 3.6 V), until the voltage on the VDD5 and AVDD pins has dropped to 0 V. * When releasing reset status by RESET pin Release the reset status by the RESET pin after both the 3.3 V power supply and 5 V power supply have risen. Figure 17-1. Recommended Timing of Turning ON/OFF Power VDD3 0V VDD5, AVDD 0V RESET (input) 0V I/O pin 0V 3.0 V 3.0 V 4.5 V 4.5 V Depends on program setting Remark The broken line indicates a high-impedance state. User's Manual U14492EJ5V0UD 759 CHAPTER 17 TURNING ON/OFF POWER [Other timing] * If power is supplied to the VDD5 and AVDD pins before the voltage on the VDD3 pins rises to the level at which the operation is guaranteed (3.0 to 3.6 V), the status of the I/O pin is undefinedNote until the voltage on the VDD3 pin reaches 3.0 V. * If the voltage on the VDD3 pin drops below the level at which the operation is guaranteed (3.0 to 3.6 V) before the voltage on the VDD5 and AVDD pins drops to 0 V, the status of the I/O pin is undefinedNote. Note This means that the input or output mode of an I/O pin, or the output level of an output pin is not determined. Figure 17-2. Other Timing VDD3 0V VDD5, AVDD 0V RESET (input) 0V I/O pin 0V Undefined 3.0 V 3.0 V 4.5 V 4.5 V Depends on program setting Undefined Remark The broken line indicates a high-impedance state. 760 User's Manual U14492EJ5V0UD CHAPTER 18 ELECTRICAL SPECIFICATIONS 18.1 Normal Operation Mode Absolute Maximum Ratings (TA = 25C) Parameter Power supply voltage Symbol VDD3 VDD5 CVDD CVSS AVDD AVSS Input voltage VI1 VI2 VI3 VI4 Clock input voltage Analog input voltage VK VIAN VDD3 pin VDD5 pin CVDD pin CVSS pin AVDD pin AVSS pin Other than X1 pin and pins for NBD VPP pin, PD70F3116 Pins for NBD Note 2 Note 3 Note 2 Conditions Ratings -0.5 to +4.6 -0.5 to +7.0 -0.5 to +4.6 -0.5 to +0.5 -0.5 to VDD5 + 0.5 -0.5 to +0.5 -0.5 to VDD5 + 0.5 -0.5 to +8.5 -0.5 to VDD3 + 0.5 -0.5 to +6.0 -0.5 to VDD3 + 1.0 AVDD > VDD5 VDD5 AVDD AVDD > VDD5 VDD5 AVDD -0.5 to VDD5 + 0.5 Note 1 Note 1 Note 1 Note 1 Unit V V V V V V V V V V V V V V V mA RESET pin (when VDD3 is supplied) X1 pin ANI00 to ANI07 pins, ANI10 to ANI17 pins Note 1 -0.5 to AVDD + 0.5 -0.5 to VDD5 + 0.5 Note 1 Analog reference input voltage AVREF AVREF0 pin, AVREF1 pin Note 1 -0.5 to AVDD + 0.5 15 Note 1 Output current, low IOL Per pin for TO000 to TO005 and TO010 to TO015 pins Per pin other than for TO000 to TO005 and TO010 to TO015 pins Total for all pins 4.0 mA 210 -4.0 -100 -40 to +85 -40 to +110 -65 to +150 mA mA mA C C C Output current, high IOH Per pin Total for all pins Operating ambient temperature TA PD703116, 703116(A), PD70F3116, 70F3116(A) PD703116(A1), 70F3116(A1) Storage temperature Tstg User's Manual U14492EJ5V0UD 761 CHAPTER 18 ELECTRICAL SPECIFICATIONS Notes 1. 2. 3. Be sure not to exceed the absolute maximum ratings (MAX. value) of each power supply voltage. CLK_DBG, SYNC, AD0_DBG to AD3_DBG pins (PD70F3116 only) Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When power supply voltage rises VPP must exceed VDD3 and VDD5 10 s or more after VDD3 and VDD5 have reached the lower-limit value (VDD3: 3.0 V, VDD5: 4.5 V) of the operating voltage range (see a in the figure below). * When power supply voltage drops VDD3 and VDD5 must be lowered 10 s or more after VPP falls below the lower-limit value (VDD3: 3.0 V, VDD5: 4.5 V) of the operating voltage range of VDD3 and VDD5 (see b in the figure below). 4.5 V VDD5 0V a 3.0 V VDD3 0V a b b VPP 4.5 V VPP 3.0 V 0V Cautions 1. Do not directly connect output (or I/O) pins of IC products to each other, or to VDD, VCC, and GND. Open drain pins or open collector pins, however, can be directly connected to each other. Direct connection of the output pins between an IC product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions shown below for DC characteristics and AC characteristics are within the range for normal operation and quality assurance. 762 User's Manual U14492EJ5V0UD CHAPTER 18 ELECTRICAL SPECIFICATIONS Capacitance (TA = 25C, VDD3 = VDD5 = VSS3 = VSS5 = 0 V) Parameter Input capacitance I/O capacitance Output capacitance Symbol CI CIO CO fC = 1 MHz Unmeasured pins returned to 0 V. Conditions MIN. TYP. MAX. 15 15 15 Unit pF pF pF Operating Conditions Operation Mode Internal System Clock Frequency (fXX) Operating Ambient Temperature (TA) Direct mode Power Supply Voltage VDD3 3.3 V 0.3 V 3.3 V 0.3 V 3.3 V 0.3 V 3.3 V 0.3 V VDD5 5.0 V 0.5 V 5.0 V 0.5 V 5.0 V 0.5 V 5.0 V 0.5 V PD703116, 703116(A), 70F3116, 70F3116(A) 4 to 25 MHz -40 to +85C -40 to +110C -40 to +85C -40 to +110C PD703116(A1), 70F3116(A1) PLL mode 4 to 16 MHz 4 to 50 MHz PD703116, 703116(A), 70F3116, 70F3116(A) PD703116(A1), 70F3116(A1) 4 to 32 MHz Caution When interfacing to the external devices using the CLKOUT signal, make the internal system clock frequency (fXX) 32 MHz or lower. User's Manual U14492EJ5V0UD 763 CHAPTER 18 ELECTRICAL SPECIFICATIONS Clock Oscillator Characteristics (TA = -40 to +85C: PD703116, 703116(A), 70F3116, 70F3116(A), TA = -40 to +110C: PD703116(A1), 70F3116(A1)) (a) Ceramic resonator or crystal resonator connection X1 X2 Rd C1 C2 Parameter Oscillation frequency Symbol fX Conditions MIN. 4 TYP. MAX. 6.4 Unit MHz Remarks 1. Connect the oscillator as close to the X1 and X2 pins as possible. 2. Do not wire any other signal lines in the area indicated by the broken lines. 3. For the resonator selection and oscillator constant, customers are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. (b) External clock input X1 X2 Open High-speed CMOS inverter External clock Cautions 1. Connect the high-speed CMOS inverter as closely to the X1 pin as possible. 2. Thoroughly evaluate the matching between the V850E/IA1 and the high-speed CMOS inverter. 764 User's Manual U14492EJ5V0UD CHAPTER 18 ELECTRICAL SPECIFICATIONS Recommended Oscillator Constant (a) Ceramic resonator (i) Murata Mfg. Co., Ltd (TA = -40 to +85C: PD703116, 703116(A), 70F3116, 70F3116(A), TA = -40 to +110C: PD703116(A1), 70F3116(A1)) Type Product Name Oscillation Frequency fX (MHz) Surface mount CSTCR4M00G55-R0 CSTCR6M00G55-R0 4.0 6.0 C1 (pF) On-chip On-chip C2 (pF) On-chip On-chip Rd () 0 0 Recommended Circuit Constant Recommended Voltage Range MIN. (V) 3.0 3.0 MAX. (V) 3.6 3.6 Caution This oscillator constant is a reference value based on evaluation under a specific environment by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the V850E/IA1 so that the internal operating conditions are within the specifications of the DC and AC characteristics. User's Manual U14492EJ5V0UD 765 CHAPTER 18 ELECTRICAL SPECIFICATIONS DC Characteristics (TA = -40 to +85C: PD703116, 703116(A), 70F3116, 70F3116(A), TA = -40 to +110C: PD703116(A1), 70F3116(A1), VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V) (1/2) Parameter Input voltage, high Symbol VIH1 VIH2 VIH3 VIH4 VIH5 VIH6 Input voltage, low VIL1 VIL2 VIL3 VIL4 VIL5 VIL6 Output voltage, high VOH1 Conditions Pins for bus control Pins for NBD Port pins Note 3 Note 2 Note 1 MIN. 2.2 0.8VDD3 0.7VDD5 0.8VDD5 0.8VDD3 0.8VDD3 TYP. MAX. VDD5 VDD3 VDD5 VDD5 VDD3 +0.3 5.5 0.8 0.2VDD3 0.3VDD5 0.2VDD5 0.15VDD3 0.2VDD3 Unit V V V V V V V V V V V V V Port pins other than Notes 1, 2, 3 X1 pin RESET pin Pins for bus control Pins for NBD Port pins Note 3 Note 2 Note 1 0 0 0 0 -0.5 0 Port pins other than Notes 1, 2, 3 X1 pin RESET pin Pins other than Note 4 Note 4 IOH = -2.5 mA VDD5 -1.0 VOH2 Output voltage, low VOL1 Pins for NBD PWM output IOH = -2.5 mA IOL = 15 mA IOL = 2.5 mA VDD3 -1.0 2.0 0.4 0.4 V V V V Note 5 VOL2 Pins other than Notes 4, 5 Note 4 IOL = 2.5 mA VOL3 Input leakage current, high Input leakage current, low Output leakage current, high Output leakage current, low Analog pin input leakage current ILIH ILIL ILOH ILOL ILIAN Pins for NBD VI = VDD5 VI = 0 V VO = VDD5 VO = 0 V IOL = 2.5 mA 0.4 10 -10 10 -10 10 V A A A A A ANI00 to ANI07, ANI10 to ANI17 pins Notes 1. AD0/PDL0 to AD15/PDL15, A16/PDH0 to A23/PDH7, LWR/PCT0, UWR/PCT1, PCT2, PCT3, RD/PCT4, PCT5, ASTB/PCT6, PCT7, WAIT/PCM0, CLKOUT/PCM1, HLDAK/PCM2, HLDRQ/PCM3, PCM4, CS0/PCS0 to CS7/PCS7 pins 2. CLK_DBG, SYNC, AD0_DBG to AD3_DBG pins (PD70F3116 only) 3. P31/TXD0, P33/TXD1, P36/TXD2, P41/SO0, P44/SO1, P47/CTXD pins 4. AD0_DBG to AD3_DBG, TRIG_DBG pins (PD70F3116 only) 5. TO000 to TO005, TO010 to TO015 pins 766 User's Manual U14492EJ5V0UD CHAPTER 18 ELECTRICAL SPECIFICATIONS DC Characteristics (TA = -40 to +85C: PD703116, 703116(A), 70F3116, 70F3116(A), TA = -40 to +110C: PD703116(A1), 70F3116(A1), VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V) (2/2) Parameter Power supply Note 1 current In normal mode Symbol IDD1 Conditions MIN. Note 2 Note 3 Note 2 Note 3 Note 2 Note 3 Note 2 Note 3 TYP. 1.9fXX + 2.8 0.8fXX + 0.8 2.4fXX + 12 30 0.9fXX + 6.8 20 1.2fXX 20 3.0 Note 3 -40C TA +85C -40C TA +110C VDD5 Note 3 0.5 20 20 10 MAX. 2.5fXX + 5.0 1.0fXX 3.6fXX + 18 50 1.8fXX + 4.0 40 2.3fXX 40 10 2.0 1200 3500 120 Unit mA mA mA mA mA mA mA mA mA mA PD703116 VDD3 + CVDD VDD5 PD70F3116 VDD3 + CVDD VDD5 In HALT mode IDD2 PD703116 VDD3 + CVDD VDD5 PD70F3116 VDD3 + CVDD VDD5 In IDLE mode In STOP mode IDD3 VDD3 + CVDD VDD5 IDD4 VDD3 + CVDD A A A Notes 1. Value in the PLL mode 2. Determine the value by calculating fXX from the operating conditions. 3. The current of the TO000 to TO005 and TO010 to TO015 pins is not included. Remarks 1. fXX: Internal system clock frequency (MHz) 2. An example of calculating the power supply current is shown below. * Power supply current (TYP.) of the V850E/IA1 in normal mode when fXX = 32 MHz VDD3 + CVDD: IDD1 = 2.4fXX + 12 = 2.4 x 32 + 12 = 88.8 mA VDD5: IDD1 = 30 mA User's Manual U14492EJ5V0UD 767 CHAPTER 18 ELECTRICAL SPECIFICATIONS Data Retention Characteristics (TA = -40 to +85C: PD703116, 703116(A), 70F3116, 70F3116(A), TA = -40 to +110C: PD703116(A1), 70F3116(A1)) Parameter Data retention voltage Symbol VDDDR HVDDDR Data retention current IDDDR Conditions STOP mode, VDD3 = VDDDR STOP mode, VDD5 = HVDDDR VDD3 = VDDDR HIDDDR Power supply voltage rise time Power supply voltage fall time Power supply voltage retention time (from STOP mode setting) STOP release signal input time Data retention input voltage, high tDREL VIHDR Note 2 Note 3 Data retention input voltage, low VILDR Note 2 Note 3 0 0.8HVDDDR 0.8VDDDR 0 0 HVDDDR VDDDR 0.2HVDDDR 0.2VDDDR ns V V V V tRVD tFVD tHVD -40C TA +85C -40C TA +110C Note 1 200 200 0 MIN. 1.5 3.6 20 20 10 TYP. MAX. 3.6 5.5 1200 3500 120 Unit V V A A A s s ms VDD5 = HVDDDR Notes 1. 2. The current of the TO000 to TO005 and TO010 to TO015 pins is not included. P00/NMI, P01/ESO0/INTP0, P02/ESO1/INTP1, P03/ADTRG0/INTP2, P04/ADTRG1/INTP3, P05/INTP4 to P07/INTP6, P10/TIUD10/TO10, P11/TCUD10/INTP100, P12/TCLR10/INTP101, P13/TIUD11/TO11, P14/TCUD11/INTP110, P15/TCLR11/INTP111, P20/TI2/INTP20, P21/TO21/INTP21 to P24/TO24/INTP24, P25/TCLR2/INTP25, P26/TI3/TCLR3/INTP30, P27/TO3/INTP31, P30/RXD0, P32/RXD1, P34/ASCK1, P35/RXD2, P37/ASCK2, P40/SI0, P42/SCK0, P43/SI1, P45/SCK1, P46/CRXD, MODE0 to MODE2, CKSEL, RESET pins 3. Remark CLK_DBG, SYNC, AD0_DBG to AD3_DBG pins (PD70F3116 only) The TYP. value is a reference value for when TA = 25C. STOP mode setting VDD3, VDD5 tFVD tHVD V DDDR, HV DDDR tRVD tDREL RESET (input) V IHDR STOP mode release interrupt (NMI, etc.) (released by falling edge) V IHDR STOP mode release interrupt (NMI, etc.) (released by rising edge) V ILDR 768 User's Manual U14492EJ5V0UD CHAPTER 18 ELECTRICAL SPECIFICATIONS AC Characteristics (TA = -40 to +85C: PD703116, 703116(A), 70F3116, 70F3116(A), TA = -40 to +110C: PD703116(A1), 70F3116(A1), VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V, output pin load capacitance: CL = 50 pF) AC test input test points (a) Other than (b) to (d) below VDD5 0.8VDD5 Test points 0.2VDD5 0.8VDD5 0.2VDD5 0V (b) AD0/PDL0 to AD15/PDL15, A16/PDH0 to A23/PDH7, LWR/PCT0, UWR/PCT1, PCT2, PCT3, RD/PCT4, PCT5, ASTB/PCT6, PCT7, WAIT/PCM0, CLKOUT/PCM1, HLDAK/PCM2, HLDRQ/PCM3, PCM4, CS0/PCS0 to CS7/PCS7 pins VDD5 2.2 V Test points 0.8 V 2.2 V 0.8 V 0V (c) CLK_DBG Note , SYNCNote, AD0_DBG to AD3_DBGNote, RESET pins Note PD70F3116 only VDD3 0.8VDD3 Test points 0V 0.2VDD3 0.2VDD3 0.8VDD3 (d) X1 pin VDD3 0.8VDD3 Test points 0.15VDD3 0.8VDD3 0.15VDD3 0V User's Manual U14492EJ5V0UD 769 CHAPTER 18 ELECTRICAL SPECIFICATIONS AC test output test points (a) Pins other than (b) below VDD5 0.8VDD5 Test points 0.2VDD5 0.8VDD5 0.2VDD5 0V (b) AD0_DBG to AD3_DBG, TRIG_DBG pins (PD70F3116 only) VDD3 0.8VDD3 Test points 0.2VDD3 0.8VDD3 0.2VDD3 0V Load conditions DUT (Device under test) CL = 50 pF Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration, insert a buffer or other element to reduce the device's load capacitance to 50 pF or lower. 770 User's Manual U14492EJ5V0UD CHAPTER 18 ELECTRICAL SPECIFICATIONS (1) Clock timing (1/2) (TA = -40 to +85C: PD703116, 703116(A), 70F3116, 70F3116(A), TA = -40 to +110C: PD703116(A1), 70F3116(A1), VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V, output pin load capacitance: CL = 50 pF) Parameter X1 input cycle Symbol <1> tCYX Conditions Direct mode PLL mode Direct mode PLL mode X1 input high-level width <2> tWXH Direct mode PLL mode X1 input low-level width <3> tWXL Direct mode PLL mode X1 input rise time <4> tXR Direct mode PLL mode X1 input fall time <5> tXF Direct mode PLL mode CPU operation frequency - fXX Note 2 Note 1 CLKOUT signal used CLKOUT output cycle <6> tCYK Note 2 Note 1 CLKOUT signal used CLKOUT high-level width CLKOUT low-level width CLKOUT rise time CLKOUT fall time Delay time from X1 to CLKOUT <7> <8> <9> <10> <11> tWKH tWKL tKR tKF tDXK Direct mode Note 3 Note 3 MIN. 31.25 156 MAX. 125 250 125 250 Unit ns ns ns ns ns ns ns ns Note 1 Note 2 20 156 6 50 6 50 4 10 4 10 4 4 4 20 31.25 31.25 0.5T - 9 0.5T - 11 11 9 40 50 32 32 250 250 250 ns ns ns ns MHz MHz MHz ns ns ns ns ns ns ns ns Notes 1. -40C TA +110C 2. -40C TA +85C 3. When interfacing to the external devices using the CLKOUT signal, make the internal system clock frequency (fXX) 32 MHz or lower. Remark T = tCYK User's Manual U14492EJ5V0UD 771 CHAPTER 18 ELECTRICAL SPECIFICATIONS (1) Clock timing (2/2) <1> <2> <4> X1 (PLL mode) <1> <3> <5> <5> <3> <2> <4> X1 (direct mode) <11> <11> CLKOUT (output) <9> <10> <7> <6> <8> (2) Output waveform (except for CLKOUT) (TA = -40 to +85C: PD703116, 703116(A), 70F3116, 70F3116(A), TA = -40 to +110C: PD703116(A1), 70F3116(A1), VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V, output pin load capacitance: CL = 50 pF) Parameter Output rise time Output fall time Symbol <12> <13> tOR tOF Conditions MIN. MAX. 15 15 Unit ns ns <12> <13> Signals other than CLKOUT 772 User's Manual U14492EJ5V0UD CHAPTER 18 ELECTRICAL SPECIFICATIONS (3) Reset timing (TA = -40 to +85C: PD703116, 703116(A), 70F3116, 70F3116(A), TA = -40 to +110C: PD703116(A1), 70F3116(A1), VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V, CL = 50 pF) Parameter RESET pin high-level width RESET pin low-level width Symbol <14> <15> tWRSH tWRSL At power-on and at STOP mode release Other than at power-on and at STOP mode release 500 ns Conditions MIN. 500 500 + TOST MAX. Unit ns ns Caution Remark Thoroughly evaluate the oscillation stabilization time. TOST: Oscillation stabilization time <14> <15> RESET (input) User's Manual U14492EJ5V0UD 773 CHAPTER 18 ELECTRICAL SPECIFICATIONS (4) Multiplex bus timing (a) CLKOUT asynchronous (TA = -40 to +85C: PD703116, 703116(A), 70F3116, 70F3116(A), TA = -40 to +110C: PD703116(A1), 70F3116(A1), VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V, output pin load capacitance: CL = 50 pF) Parameter Address setup time (to ASTB) Address hold time (from ASTB) Address float delay time from RD Data input setup time from address Data input setup time from RD Delay time from ASTB to RD, LWR, UWR Data input hold time (from RD) Address output time from RD Delay time from RD, LWR, UWR to ASTB Delay time from RD to ASTB Symbol <16> <17> <18> <19> tSAST tHSTA tFRDA tSAID Conditions MIN. (0.5 + wAS)T - 16 (0.5 + wAH)T - 15 11 (2 + w + wAS + wAH)T - 40 <20> <21> <22> <23> <24> <25> tSRDID tDSTRDWR tHRDID tDRDA tDRDWRST tDRDST (0.5 + wAH)T - 15 0 (1 + i)T - 15 0.5T - 15 (1.5 + i + wAS)T - 15 RD, LWR, UWR low-level width ASTB high-level width Data output time from LWR, UWR Data output setup time (to LWR, UWR) Data output hold time (from LWR, UWR) WAIT setup time (to address) <26> <27> <28> <29> <30> <31> tWRDWRL tWSTH tDWROD tSODWR tHWROD tSAWT1 w1 (1 + w)T - 25 T - 20 (1.5 + wAS + wAH)T - 40 <32> tSAWT2 w1 (1.5 + w + wAS+wAH)T - 40 WAIT hold time (from address) <33> <34> WAIT setup time (to ASTB) <35> <36> tHAWT1 tHAWT2 tSSTWT1 tSSTWT2 w1 w1 (0.5 + w + wAS+wAH)T (1.5 + w + wAS+wAH)T (1 + wAH)T - 32 (1 + w + wAH)T - 32 WAIT hold time (from ASTB) <37> <38> HLDRQ high-level width HLDAK low-level width Delay time from address float to HLDAK Delay time from HLDAK to bus output Delay time from HLDRQ to HLDAK Delay time from HLDRQ to HLDAK <39> <40> <41> <42> <43> <44> tHSTWT1 tHSTWT2 tWHQH tWHAL tDFHA tDHAC tDHQHA1 tDHQHA2 (w + wAH)T (1 + w + wAH)T T + 10 T - 15 -12 -7 2T 0.5T 1.5T + 30 ns ns ns ns ns ns ns ns ns ns ns ns ns (1 + w)T - 22 (1 + wAS)T - 15 10 ns ns ns ns ns ns (1 + w)T - 40 ns ns ns ns ns ns MAX. Unit ns ns ns ns 774 User's Manual U14492EJ5V0UD CHAPTER 18 ELECTRICAL SPECIFICATIONS Remarks 1. T = tCYK 2. w: Number of wait clocks inserted in the bus cycle The sampling timing changes when a programmable wait is inserted. 3. i: Number of idle states inserted after the read cycle (0 or 1) 4. wAS: Number of address setup wait states (0 or 1) 5. wAH: Number of address hold wait states (0 or 1) 6. Observe at least either of the data input hold time tHKID or tHRDID. 7. For the number of wait clocks to be inserted, refer to 4.6.3 Relationship between programmable wait and external wait. (b) CLKOUT synchronous (TA = -40 to +85C: PD703116, 703116(A), 70F3116, 70F3116(A), TA = -40 to +110C: PD703116(A1), 70F3116(A1), VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V, output pin load capacitance: CL = 50 pF) Parameter Delay time from CLKOUT to address Delay time from CLKOUT to address float Delay time from CLKOUT to ASTB Delay time from CLKOUT to RD, LWR, UWR Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) Delay time from CLKOUT to data output WAIT setup time (to CLKOUT) WAIT hold time (from CLKOUT) HLDRQ setup time (to CLKOUT) HLDRQ hold time (from CLKOUT) Delay time from CLKOUT to HLDAK Delay time from CLKOUT to address float Symbol <45> <46> <47> <48> <49> <50> <51> <52> <53> <54> <55> <56> <57> tDKA tFKA tDKST tDKRDWR tSIDK tHKID tDKOD tSWTK tHKWT tSHQK tHKHQ tDKHA tDKF 21 5 21 5 19 19 Conditions MIN. -7 -12 -3 + wAHT -5 21 5 19 MAX. 19 15 19 + wAHT 19 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks 1. T = tCYK 2. wAH: Number of address hold wait states (0 or 1) 3. Observe at least either of the data input hold time tHKID or tHRDID. User's Manual U14492EJ5V0UD 775 CHAPTER 18 ELECTRICAL SPECIFICATIONS (c) Read cycle (CLKOUT synchronous/asynchronous, 1 wait) T1 T2 TW T3 CLKOUT (output) <45> A16 to A23 (output) CS0 to CS7 (output) <19> <49> <46> AD0 to AD15 (I/O) Address Hi-Z Data <50> <47> <16> <17> <47> <22> ASTB (output) <27> <48> <21> <18> <20> <24> <48> <23> <25> RD (output) <35> <52> <37> <36> <38> WAIT (input) <53> <26> <52> <53> <31> <33> <32> <34> Caution When interfacing with the external device using the CLKOUT signal, set the internal system clock frequency (fXX) to 32 MHz or lower. Remark LWR and UWR are high level. 776 User's Manual U14492EJ5V0UD CHAPTER 18 ELECTRICAL SPECIFICATIONS (d) Write cycle (CLKOUT synchronous/asynchronous, 1 wait) T1 T2 TW T3 CLKOUT (output) <45> A16 to A23 (output) CS0 to CS7 (output) <51> AD0 to AD15 (I/O) Address Data <47> <17> <16> <47> ASTB (output) <27> <48> <21> LWR (output) UWR (output) <24> <48> <28> <29> <30> <35> <52> <37> <36> <38> WAIT (input) <53> <26> <52> <53> <31> <33> <32> <34> Caution When interfacing with the external device using the CLKOUT signal, set the internal system clock frequency (fXX) to 32 MHz or lower. Remark RD is high level. User's Manual U14492EJ5V0UD 777 CHAPTER 18 ELECTRICAL SPECIFICATIONS (e) Bus hold TH CLKOUT (output) TH TH TI <54> <55> <54> <39> HLDRQ (input) <56> <43> <44> <56> HLDAK (output) <41> <57> A16 to A23 (output) CS0 to CS7 (output) <40> Hi-Z <42> AD0 to AD15 (I/O) Data Hi-Z ASTB (output) Hi-Z RD (output) LWR (output), UWR (output) Hi-Z Caution When interfacing with the external device using the CLKOUT signal, set the internal system clock frequency (fXX) to 32 MHz or lower. 778 User's Manual U14492EJ5V0UD CHAPTER 18 ELECTRICAL SPECIFICATIONS (5) Interrupt timing (TA = -40 to +85C: PD703116, 703116(A), 70F3116, 70F3116(A), TA = -40 to +110C: PD703116(A1), 70F3116(A1), VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V, CL = 50 pF) Parameter NMI high-level width NMI low-level width INTPn high-level width Symbol <58> <59> <60> tWNIH tWNIL tWITH n = 0 to 6 n = 100, 101, 110, 111, 30, 31 n = 20 to 25 (when analog filter specified) n = 20 to 25 (when digital filter specified) INTPn low-level width <61> tWITL n = 0 to 6 n = 100, 101, 110, 111, 30, 31 n = 20 to 25 (when analog filter specified) n = 20 to 25 (when digital filter specified) Conditions MIN. 500 500 500 5T + 10 500 5T + 10 500 5T + 10 500 5T + 10 MAX. Unit ns ns ns ns ns ns ns ns ns ns Remark T: Digital filter sampling clock T can be selected by setting the following registers. * INTP100, INTP101: Can be selected from fXXTM10, fXXTM10/2, fXXTM10/4, and fXXTM10/8 by setting the NRC101 and NRC100 bits of the timer 10 noise elimination time selection register (NRC10) (fXXTM10: clock selected with the timer 1/timer 2 clock selection register (PRM02)). * INTP110, INTP111: Can be selected from fXXTM11, fXXTM11/2, fXXTM11/4, and fXXTM11/8 by setting the NRC111 and NRC110 bits of the timer 11 noise elimination time selection register (NRC11) (fXXTM11: clock selected with the PRM02 register). * INTP30: Can be selected from fXXTM3/2, fXXTM3/4, fXXTM3/8, and fXXTM3/16 by setting the NRC31 and NRC30 bits of the timer 3 noise elimination time selection register (NRC3) (fXXTM3: clock selected with the timer 3 clock selection register (PRM03)). * INTP31: Can be selected from fXXTM3/32, fXXTM3/64, fXXTM3/128, and fXXTM3/256 by setting the NRC33 and NRC32 bits of the timer 3 noise elimination time selection register (NRC3) (fXXTM3: clock selected with the PRM03 register). <58> <59> NMI (input) <60> <61> INTPn (input) Remark n = 0 to 6, 100, 101, 110, 111, 20 to 25, 30, 31 User's Manual U14492EJ5V0UD 779 CHAPTER 18 ELECTRICAL SPECIFICATIONS (6) Timer input timing (TA = -40 to +85C: PD703116, 703116(A), 70F3116, 70F3116(A), TA = -40 to +110C: PD703116(A1), 70F3116(A1), VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V, CL = 50 pF) Parameter TIUDn, TCUDn high-/low-level width TIUDn, TCUDn input time difference TCLRn high-/low-level width <62> <63> <64> Symbol tWUDH, tWUDL tPHUD tWTCH, tWTCL Conditions n = 10, 11 n = 10, 11 n = 10, 11, 2 (other than for through input), 3 n = 2 (for through input TIn high-/low-level width <65> tWTIH, tWTIL Note MIN. 5T + 10 2T + 10 5T + 10 2T + 10 5T + 10 2T + 10 MAX. Unit ns ns ns ns ns ns ) n = 2 (other than for through input), 3 n = 2 (for through input Note ) Note When setting the timer 2 count clock/control edge selection register 0 (CSE0)'s CESE1 bit to 1 and CESE0 bit to 0. Remarks 1. T: Digital filter sampling clock T can be selected by setting the following registers. * When using TIUDn, TCUDn, and TCLRn (n = 10, 11), the following cycles can be selected by setting the NRCn1 and NRCn0 bits of timer n noise elimination time selection register (NRCn). When fXX/2 is selected for the timer n base clock: fXX/2, fXX/4, fXX/8, fXX/16 When fXX/4 is selected for the timer n base clock: fXX/4, fXX/8, fXX/16, fXX/32 * When using TCLR2 and TI2, the following cycles can be selected by setting the PRM2 bit of the timer 1/timer 2 clock selection register (PRM02). When fXX/2 is selected for the timer 2 base clock: fXX/2 When fXX/4 is selected for the timer 2 base clock: fXX/4 * When using TCLR3 and TI3, the following cycles can be selected by setting the NRC31 and NRC30 bits of timer 3 noise elimination time selection register (NRC3). When fXX is selected for the timer 3 base clock: fXX/2, fXX/4, fXX/8, fXX/16 When fXX/2 is selected for the timer 3 base clock: fXX/4, fXX/8, fXX/16, fXX/32 2. fXX: Internal system clock frequency <62> TIUDm (input) <63> <62> TCUDm (input) <63> <62> <63> <62> <63> <64> TCLRn (input) <64> <65> TIx (input) <65> Remark m = 10, 11 n = 10, 11, 2, 3 x = 2, 3 User's Manual U14492EJ5V0UD 780 CHAPTER 18 ELECTRICAL SPECIFICATIONS (7) Timer operating frequency (TA = -40 to +85C: PD703116, 703116(A), 70F3116, 70F3116(A), TA = -40 to +110C: PD703116(A1), 70F3116(A1), VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V, output pin load capacitance: CL = 50 pF) Parameter Timer 00, 01 operating frequency Symbol T0 Conditions -40C TA +85C -40C TA +110C Timer 10, 11 operating frequency Timer 20, 21 operating frequency Timer 3 operating frequency Note MIN. MAX. 40 32 16 16 32 Unit MHz MHz MHz MHz MHz T1 T2 T3 Notes 1. Setting the TESnE1 and TESnE0 bits of timer 2 count clock/control edge select register 0 (CSE0) to 11B (both rising/falling edges) is prohibited when the PRM2 bit of the timer 1/timer 2 clock selection register (PRM02) is 1B (fCLK = fXX/2) 2. Set the VSWC register to 15H when the PRM2 bit of the timer 1/timer 2 clock selection register (PRM02) = 0B (fCLK = fXX/4). (8) CSI timing (1/2) (a) Master mode (TA = -40 to +85C: PD703116, 703116(A), 70F3116, 70F3116(A), TA = -40 to +110C: PD703116(A1), 70F3116(A1), VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V, output pin load capacitance: CL = 50 pF) Parameter SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn) SIn hold time (from SCKn) SOn output delay time (from SCKn) SOn output hold time (from SCKn) Symbol <66> <67> <68> <69> <70> <71> <72> tCYSK1 tWSK1H tWSK1L tSSISK tHSKSI tDSKSO tHSKSO 0.5tCYSK1 - 20 Conditions Output Output Output MIN. 200 0.5tCYSK1 - 25 0.5tCYSK1 - 25 35 30 30 MAX. Unit ns ns ns ns ns ns ns Remark n = 0, 1 User's Manual U14492EJ5V0UD 781 CHAPTER 18 ELECTRICAL SPECIFICATIONS (8) CSI timing (2/2) (b) Slave mode (TA = -40 to +85C: PD703116, 703116(A), 70F3116, 70F3116(A), TA = -40 to +110C: PD703116(A1), 70F3116(A1), VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V, output pin load capacitance: CL = 50 pF) Parameter SCKn cycle SCKn high-level width SCKn low-level width SIn setup time (to SCKn) SIn hold time (from SCKn) SOn output delay time (from SCKn) SOn output hold time (from SCKn) Symbol <66> <67> <68> <69> <70> <71> <72> tCYSK1 tWSK1H tWSK1L tSSISK tHSKSI tDSKSO tHSKSO tWSK1H Conditions Input Input Input MIN. 200 90 90 50 50 55 MAX. Unit ns ns ns ns ns ns ns Remark n = 0, 1 <66> <68> <67> SCKn (I/O) <69> <70> SIn (input) Input data <71> <72> SOn (output) Output data Remarks 1. The broken lines indicate high impedance. 2. n = 0, 1 782 User's Manual U14492EJ5V0UD CHAPTER 18 ELECTRICAL SPECIFICATIONS (9) UART0 timing (TA = -40 to +85C: PD703116, 703116(A), 70F3116, 70F3116(A), TA = -40 to +110C: PD703116(A1), 70F3116(A1), VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V, output pin load capacitance: CL = 50 pF) Parameter UART0 baud rate generator input frequency Symbol fBRG Conditions MIN. MAX. 25 Unit MHz Remark fBRG (UART0 baud rate generator input frequency) can be selected from fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXX/64, fXX/128, fXX/256, fXX/512, fXX/1024, and fXX/2048 by setting the TPS3 to TPS0 bits of clock selection register 0 (CKSR0) (fXX: Internal system clock frequency). (10) UART1, UART2 timing (1/2) (a) Clocked master mode (TA = -40 to +85C: PD703116, 703116(A), 70F3116, 70F3116(A), TA = -40 to +110C: PD703116(A1), 70F3116(A1), VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V, output pin load capacitance: CL = 50 pF) Parameter ASCKn cycle ASCKn high-level width ASCKn low-level width RXDn setup time (to ASCKn) RXDn hold time (from ASCKn) TXDn output delay time (from ASCKn) TXDn output hold time (from ASCKn) <73> <74> <75> <76> <77> <78> <79> Symbol tCYSK0 tWSK0H tWSK0L tSRXSK tHSKRX tDSKTX tHSKTX (k + 1)T - 20 Conditions Output Output Output MIN. 1000 k T - 20 k T - 20 1.5 T + 35 0 T + 10 MAX. Unit ns ns ns ns ns ns ns Remarks 1. T = 2tCYK 2. k: Setting value of prescaler compare register n (PRSCMn) of UARTn 3. n = 1, 2 User's Manual U14492EJ5V0UD 783 CHAPTER 18 ELECTRICAL SPECIFICATIONS (10) UART1, UART2 timing (2/2) (b) Clocked slave mode (TA = -40 to +85C: PD703116, 703116(A), 70F3116, 70F3116(A), TA = -40 to +110C: PD703116(A1), 70F3116(A1), VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V, output pin load capacitance: CL = 50 pF) Parameter ASCKn cycle ASCKn high-level width ASCKn low-level width RXDn setup time (to ASCKn) RXDn hold time (from ASCKn) TXDn output delay time (from ASCKn) TXDn output hold time (from ASCKn) <73> <74> <75> <76> <77> <78> <79> Symbol tCYSK0 tWSK0H tWSK0L tSRXSK tHSKRX tDSKTX tHSKTX k T + 1.5 T Conditions Input Input Input MIN. 1000 4 T + 80 4 T + 80 T + 10 T + 10 2.5 T + 45 MAX. Unit ns ns ns ns ns ns ns Remarks 1. T = 2tCYK 2. k: Setting value of PRSCMn register of UARTn 3. n = 1, 2 <73> <75> <74> ASCKn (I/O) <76> <77> RXDn (input) Input data <78> <79> TXDn (output) Output data Remark n = 1, 2 784 User's Manual U14492EJ5V0UD CHAPTER 18 ELECTRICAL SPECIFICATIONS (11) NBD timing (PD70F3116 only) (TA = 0 to +40C, VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V, output pin load capacitance: CL = 100 pF) Parameter NBD cycle NBD cycle low-level width NBD data output delay time NBD data output hold time NBD data input setup time NBD data input hold time SYNC input setup time SYNC input hold time <80> <81> <82> <83> <84> <85> <86> <87> Symbol tNDCYC tNDL tNDD tNDHD tNDS tNDH tNDSYS tNDSYH Conditions MIN. 80 35 5 2 20 5 20 5 tNDCYC - 20 MAX. Unit ns ns ns ns ns ns ns ns <80> CLK_DBG (input) <81> <82> AD0_DBG to AD3_DBG (output) <83> <84> AD0_DBG to AD3_DBG (input) <85> <86> SYNC (input) <87> User's Manual U14492EJ5V0UD 785 CHAPTER 18 ELECTRICAL SPECIFICATIONS A/D Converter Characteristics (TA = -40 to +85C: PD703116, 703116(A), 70F3116, 70F3116(A), TA = -40 to +110C: PD703116(A1), 70F3116(A1), VDD3 = CVDD = 3.0 to 3.6 V, AVDD = VDD5 = 5 V 0.5 V, AVSS = VSS3 = VSS5 = CVSS = 0 V, CL = 50 pF) Parameter Resolution Overall error Note 1 Symbol - - - tCONV tSAMP Conditions MIN. 10 TYP. MAX. Unit bit 5 1/2 5 833 3 3 3 5 -0.3 AVREFn = AVDD 4.5 1 3 AVREFn + 0.3 5.5 2 6 10 LSB LSB Quantization error Conversion time Sampling time Zero-scale error Full-scale error Note 1 s ns LSB LSB LSB LSB V V mA mA - - Note 1 Note 1 Differential linearity error Integral linearity error Analog input voltage - - VIAN AVREF AIREF Note 1 Analog reference voltage AVREFn input current Note 2 AVDD power supply current Note 2 AIDD Notes 1. The quantization error (0.5 LSB) is not included. 2. The V850E/IA1 incorporates two A/D converters. This is the rated value for one converter. Remarks 1. LSB: Least Significant Bit 2. n = 0, 1 786 User's Manual U14492EJ5V0UD CHAPTER 18 ELECTRICAL SPECIFICATIONS 18.2 Flash Memory Programming Mode (PD70F3116 only) Basic Characteristics (TA = 0 to 70C (during rewrite), TA = -40 to +85C (except during rewrite): PD70F3116, 70F3116(A), TA = -40 to +110C (except during rewrite): PD70F3116(A1), VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V) Parameter Operating frequency VPP supply voltage fX VPP1 VPPL VPPM VPPH VDD3 supply current VPP supply current Step erase time Overall erase time per area Write-back time Number of write-backs per write-back command Number of erase/write-backs Step writing time Overall writing time per word IDD1 IPP tER tERA tWB CWB During flash memory programming VPP low-level detection VPP, VDD3 level detection VPP high-voltage level detection VPP = VPP1 VPP = 7.8 V Note 1 When the step erase time = 0.4 s, Note 2 Note 3 When the write-back time = 1 ms, Note 4 0.99 1 0.398 0.4 Symbol Conditions MIN. 4 7.5 -0.3 0.65VDD3 7.5 7.8 7.8 TYP. MAX. 50 8.1 0.2VDD3 VDD3 + 0.3 8.1 4.5fx 100 0.402 40 1.01 300 Unit MHz V V V V mA mA s s/area ms Count/writeback command Count CERWB tWT tWTW Note 5 When the step writing time = 20 s (1 word = 4 bytes), Note 6 1 erase + 1 write after erase = 1 rewrite, Note 7 18 20 20 16 22 200 s s/word Number of rewrites per area CERWR 100 Count/area Notes 1. 2. 3. 4. 5. 6. 7. The recommended setting value of the step erase time is 0.4 s. The prewrite time prior to erasure and the erase verify time (write-back time) are not included. The recommended setting value of the write-back time is 1 ms. Write-back is executed once by the issuance of the write-back command. Therefore, the retry count must be the maximum value minus the number of commands issued. The recommended setting value of the step writing time is 20 s. 20 s is added to the actual writing time per word. The internal verify time during and after the writing is not included. When writing initially to shipped products, it is counted as one rewrite for both "erase to write" and "write only". Example (P: Write, E: Erase) Shipped product P E P E P: 3 rewrites Shipped product E P E P E P: 3 rewrites Remarks 1. When the PG-FP4 is used, a time parameter required for writing/erasing by downloading parameter files is automatically set. Do not change the settings unless otherwise specified. 2. Area 0 = 00000H to 1FFFFH, area 1 = 20000H to 3FFFFH User's Manual U14492EJ5V0UD 787 CHAPTER 18 ELECTRICAL SPECIFICATIONS Serial Write Operation Characteristics (TA = 0 to 70C, VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V) Parameter VDD3, VDD5 to VPP set time VPP to RESET set time RESET to VPP count start time Count execution time VPP counter high-level width VPP counter low-level width VPP counter rise time VPP counter fall time VPP to VDD3, VDD5 reset time Symbol <88> <89> <90> <91> <92> <93> <94> <95> <96> tDRPSR tPSRRF tRFOF tCOUNT tCH tCL tR tF tPFDR 10 1 1 1 1 VPP = 7.8 V Conditions MIN. 10 1 10T + 1500 15 TYP. MAX. Unit s s ns ms s s s s s Remark T = tCYK 4.5 V VDD5 0V <88> 3.0 V VDD3 0V <88> <90> VPP VDD5 VDD3 <95> 0V <89> <93> <92> <91> <94> <96> <96> VPP RESET (input) VDD5 0V 788 User's Manual U14492EJ5V0UD CHAPTER 19 PACKAGE DRAWING 144-PIN PLASTIC LQFP (FINE PITCH) (20x20) A B 108 109 73 72 detail of lead end S C D R Q 144 1 37 36 F G H I M J P K S L M N NOTE S Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 22.00.2 20.00.2 20.00.2 22.00.2 1.25 1.25 0.220.05 0.08 0.5 (T.P.) 1.00.2 0.50.2 0.17 +0.03 -0.07 0.08 1.4 0.100.05 3 +4 -3 1.50.1 S144GJ-50-UEN User's Manual U14492EJ5V0UD 789 CHAPTER 20 RECOMMENDED SOLDERING CONDITIONS V850E/IA1 should be soldered and mounted under the following recommended conditions. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 20-1. Surface Mounting Type Soldering Conditions (1) PD703116GJ-xxx-UEN: 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 230C, Time: 30 seconds max. (at 210C or higher), Count: Two times or less, Exposure limit: 3 days 10 to 72 hours) VPS Note PD703116GJ(A)-xxx-UEN: PD703116GJ(A1)-xxx-UEN: PD70F3116GJ-UEN: PD70F3116GJ(A)-UEN: PD70F3116GJ(A1)-UEN: Soldering Method IR30-103-2 (after that, prebake at 125C for Package peak temperature: 215C, Time: 25 to 40 seconds (at 200C or higher), Count: Two times or less, Exposure limit: 3 days 10 to 72 hours) Note VP15-103-2 (after that, prebake at 125C for Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - (2) PD70F3116GJ-UEN-A: 144-pin plastic LQFP (fine pitch) (20 x 20) 144-pin plastic LQFP (fine pitch) (20 x 20) Soldering Conditions Recommended Condition Symbol PD70F3116GJ(A1)-UEN-A: Soldering Method Infrared reflow Package peak temperature: 260C, Time: 60 seconds max. (at 220C or higher), Count: Three times or less, Exposure limit: 3 days for 20 to 72 hours) Note IR60-203-3 (after that, prebake at 125C Wave soldering Partial heating For details, consult an NEC Electronics sales representative. Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - - Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Remarks 1. Products with -A at the end of the part number are lead-free products. 2. For soldering methods and conditions other than those recommended above, consult an NEC Electronics sales representative. 3. For soldering conditions for the PD703116GJ-xxx-UEN-A, 703116GJ(A)-xxx-UEN-A, 703116GJ(A1)-xxx-UEN-A, and representative. 70F3116GJ(A)-UEN-A, consult an NEC Electronics sales 790 User's Manual U14492EJ5V0UD APPENDIX A NOTES ON TARGET SYSTEM DESIGN The following shows a diagram of the connection conditions between the in-circuit emulator option board and conversion connector. Design your system making allowances for conditions such as the form of parts mounted on the target system based on this configuration. Figure A-1. 144-Pin Plastic LQFP (Fine Pitch) (20 x 20) Side view In-circuit emulator IE-V850E-MC In-circuit emulator option board IE-703116-MC-EM1 206.26 mm Note Target system Conversion connector YQGUIDE YQPACK144SD NQPACK144SD Note YQSOCKET144SDN (sold separately) can be inserted here to adjust the height (height: 3.2 mm). Top view IE-V850E-MC Target system IE-703116-MC-EM1 YQPACK144SD, NQPACK144SD, YQGUIDE Connection condition diagram IE-703116-MC-EM1 Connect to IE-V850E-MC 75 mm YQGUIDE YQPACK144SD NQPACK144SD 13.3 mm 31.84 mm 17.99 mm 27.205 mm 21.58 mm Target system User's Manual U14492EJ5V0UD 791 APPENDIX B REGISTER INDEX (1/11) Symbol ADCR00 ADCR01 ADCR02 ADCR03 ADCR04 ADCR05 ADCR06 ADCR07 ADCR10 ADCR11 ADCR12 ADCR13 ADCR14 ADCR15 ADCR16 ADCR17 ADETM0 ADETM0H ADETM0L ADETM1 ADETM1H ADETM1L ADIC0 ADIC1 ADSCM00 ADSCM00H ADSCM00L ADSCM01 ADSCM01H ADSCM01L ADSCM10 ADSCM10H ADSCM10L ADSCM11 ADSCM11H ADSCM11L ASIF0 ASIM0 Register Name A/D conversion result register 00 A/D conversion result register 01 A/D conversion result register 02 A/D conversion result register 03 A/D conversion result register 04 A/D conversion result register 05 A/D conversion result register 06 A/D conversion result register 07 A/D conversion result register 10 A/D conversion result register 11 A/D conversion result register 12 A/D conversion result register 13 A/D conversion result register 14 A/D conversion result register 15 A/D conversion result register 16 A/D conversion result register 17 A/D voltage detection mode register 0 A/D voltage detection mode register 0H A/D voltage detection mode register 0L A/D voltage detection mode register 1 A/D voltage detection mode register 1H A/D voltage detection mode register 1L Interrupt control register Interrupt control register A/D scan mode register 00 A/D scan mode register 00H A/D scan mode register 00L A/D scan mode register 01 A/D scan mode register 01H A/D scan mode register 01L A/D scan mode register 10 A/D scan mode register 10H A/D scan mode register 10L A/D scan mode register 11 A/D scan mode register 11H A/D scan mode register 11L Asynchronous serial interface transmit status register 0 Asynchronous serial interface mode register 0 Unit ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC INTC INTC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC UART0 UART0 Page 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 651 650 650 650 650 650 650 172 172 646 646 646 649 649 649 646 646 646 649 649 649 418 414 792 User's Manual U14492EJ5V0UD APPENDIX B REGISTER INDEX (2/11) Symbol ASIM10 ASIM11 ASIM20 ASIM21 ASIS0 ASIS1 ASIS2 AWC BCC BCT0 BCT1 BFCM00 BFCM01 BFCM02 BFCM03 BFCM10 BFCM11 BFCM12 BFCM13 BPC BRGC0 BSC C1BA C1BRP C1CTRL C1DEF C1DINF C1ERC C1IE C1INTP C1LAST C1MASKH0 C1MASKH1 C1MASKH2 C1MASKH3 C1MASKL0 C1MASKL1 C1MASKL2 C1MASKL3 C1SYNC CANIC0 Register Name Asynchronous serial interface mode register 10 Asynchronous serial interface mode register 11 Asynchronous serial interface mode register 20 Asynchronous serial interface mode register 21 Asynchronous serial interface status register 0 Asynchronous serial interface status register 1 Asynchronous serial interface status register 2 Address wait control register Bus cycle control register Bus cycle type configuration register 0 Bus cycle type configuration register 1 Buffer register CM00 Buffer register CM01 Buffer register CM02 Buffer register CM03 Buffer register CM10 Buffer register CM11 Buffer register CM12 Buffer register CM13 Peripheral area selection control register Baud rate generator control register 0 Bus size configuration register CAN1 bus active register CAN1 bit rate prescaler register CAN1 control register CAN1 definition register CAN1 bus diagnostic information register CAN1 error count register CAN1 interrupt enable register CAN1 interrupt pending register CAN1 information register CAN1 address mask 0 register H CAN1 address mask 1 register H CAN1 address mask 2 register H CAN1 address mask 3 register H CAN1 address mask 0 register L CAN1 address mask 1 register L CAN1 address mask 2 register L CAN1 address mask 3 register L CAN1 synchronization control register Interrupt control register User's Manual U14492EJ5V0UD Unit UART1 UART1 UART2 UART2 UART0 UART1 UART2 BCU BCU BCU BCU TM00 TM00 TM00 TM00 TM01 TM01 TM01 TM01 CPU UART0 BCU FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN FCAN INTC Page 445 447 445 447 417 448 448 115 117 105 105 224 224 224 225 224 224 224 225 82 436 107 589 590 576 580 593 585 586 563 584 574 574 574 574 574 574 574 574 594 172 793 APPENDIX B REGISTER INDEX (3/11) Symbol CANIC1 CANIC2 CANIC3 CC100 CC101 CC10IC0 CC10IC1 CC110 CC111 CC11IC0 CC11IC1 CC2IC0 CC2IC1 CC2IC2 CC2IC3 CC2IC4 CC2IC5 CC30 CC31 CC3IC0 CC3IC1 CCINTP CCR0 CCR1 CCSTATE0 CCSTATE0H CCSTATE0L CGCS CGIE CGINTP CGMSR CGMSS CGST CGTSC CKC CKSR0 CM000 CM001 CM002 CM003 CM010 Interrupt control register Interrupt control register Interrupt control register Capture/compare register 100 Capture/compare register 101 Interrupt control register Interrupt control register Capture/compare register 110 Capture/compare register 111 Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Capture/compare register 30 Capture/compare register 31 Interrupt control register Interrupt control register CAN interrupt pending register Capture/compare control register 0 Capture/compare control register 1 Timer 2 capture/compare 1 to 4 status register 0 Timer 2 capture/compare 1 to 4 status register 0H Timer 2 capture/compare 1 to 4 status register 0L CAN main clock selection register CAN global interrupt enable register CAN global interrupt pending register CAN message search result register CAN message search start register CAN global status register CAN time stamp count register Clock control register Clock selection register 0 Compare register 000 Compare register 001 Compare register 002 Compare register 003 Compare register 010 User's Manual U14492EJ5V0UD Register Name Unit INTC INTC INTC TM10 TM10 INTC INTC TM11 TM11 INTC INTC INTC INTC INTC INTC INTC INTC TM3 TM3 INTC INTC FCAN TM10 TM11 TM2 TM2 TM2 FCAN FCAN FCAN FCAN FCAN FCAN FCAN CG UART0 TM00 TM00 TM00 TM00 TM01 Page 172 172 172 311 312 172 172 311 312 172 172 172 172 172 172 172 172 377 377 172 172 561 303 303 349 349 349 569 568 562 572 572 565 571 200 435 223 223 223 224 223 794 APPENDIX B REGISTER INDEX (4/11) Symbol CM011 CM012 CM013 CM03IC0 CM03IC1 CM100 CM101 CM10IC0 CM10IC1 CM110 CM111 CM11IC0 CM11IC1 CM4 CM4IC0 CMSE050 CMSE120 CMSE340 CSC0 CSC1 CSCE0 CSE0 CSE0H CSE0L CSIC0 CSIC1 CSIIC0 CSIIC1 CSIM0 CSIM1 CSL10 CSL11 CSTOP CVPE10 CVPE20 CVPE30 CVPE40 CVSE00 CVSE10 CVSE20 CVSE30 Compare register 011 Compare register 012 Compare register 013 Interrupt control register Interrupt control register Compare register 100 Compare register 101 Interrupt control register Interrupt control register Compare register 110 Compare register 111 Interrupt control register Interrupt control register Compare register 4 Interrupt control register Timer 2 subchannel 0, 5 capture/compare control register Timer 2 subchannel 1, 2 capture/compare control register Timer 2 subchannel 3, 4 capture/compare control register Chip area selection control register 0 Chip area selection control register 1 Timer 2 software event capture register Timer 2 count clock/control edge selection register 0 Timer 2 count clock/control edge selection register 0H Timer 2 count clock/control edge selection register 0L Clocked serial interface clock selection register 0 Clocked serial interface clock selection register 1 Interrupt control register Interrupt control register Clocked serial interface mode register 0 Clocked serial interface mode register 1 CC101 capture input selection register CC111 capture input selection register CAN stop register Timer 2 subchannel 1 main capture/compare register Timer 2 subchannel 2 main capture/compare register Timer 2 subchannel 3 main capture/compare register Timer 2 subchannel 4 main capture/compare register Timer 2 subchannel 0 capture/compare register Timer 2 subchannel 1 sub capture/compare register Timer 2 subchannel 2 sub capture/compare register Timer 2 subchannel 3 sub capture/compare register User's Manual U14492EJ5V0UD Register Name Unit TM01 TM01 TM01 INTC INTC TM10 TM10 INTC INTC TM11 TM11 INTC INTC TM4 INTC TM2 TM2 TM2 BCU BCU TM2 TM2 TM2 TM2 CSI0 CSI1 INTC INTC CSI0 CSI1 TM10 TM11 FCAN TM2 TM2 TM2 TM2 TM2 TM2 TM2 TM2 Page 223 223 224 172 172 310 310 172 172 310 310 172 172 402 172 343 344 346 102 102 351 336 336 336 481 481 172 172 479 479 309 309 564 333 333 333 333 332 334 334 334 795 APPENDIX B REGISTER INDEX (5/11) Symbol CVSE40 CVSE50 DADC0 DADC1 DADC2 DADC3 DBC0 DBC1 DBC2 DBC3 DCHC0 DCHC1 DCHC2 DCHC3 DDA0H DDA0L DDA1H DDA1L DDA2H DDA2L DDA3H DDA3L DDIS DETIC0 DETIC1 DMAIC0 DMAIC1 DMAIC2 DMAIC3 DRST DSA0H DSA0L DSA1H DSA1L DSA2H DSA2L DSA3H DSA3L DTFR0 DTFR1 DTFR2 Register Name Timer 2 subchannel 4 sub capture/compare register Timer 2 subchannel 5 capture/compare register DMA addressing control register 0 DMA addressing control register 1 DMA addressing control register 2 DMA addressing control register 3 DMA transfer count register 0 DMA transfer count register 1 DMA transfer count register 2 DMA transfer count register 3 DMA channel control register 0 DMA channel control register 1 DMA channel control register 2 DMA channel control register 3 DMA destination address register 0H DMA destination address register 0L DMA destination address register 1H DMA destination address register 1L DMA destination address register 2H DMA destination address register 2L DMA destination address register 3H DMA destination address register 3L DMA disable status register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register DMA restart register DMA source address register 0H DMA source address register 0L DMA source address register 1H DMA source address register 1L DMA source address register 2H DMA source address register 2L DMA source address register 3H DMA source address register 3L DMA trigger factor register 0 DMA trigger factor register 1 DMA trigger factor register 2 User's Manual U14492EJ5V0UD Unit TM2 TM2 DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC INTC INTC INTC INTC INTC INTC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC DMAC Page 334 334 134 134 134 134 133 133 133 133 136 136 136 136 131 132 131 132 131 132 131 132 138 172 172 172 172 172 172 138 129 130 129 130 129 130 129 130 139 139 139 796 APPENDIX B REGISTER INDEX (6/11) Symbol DTFR3 DTM00 DTM01 DTM02 DTM10 DTM11 DTM12 DTRR0 DTRR1 DWC0 DWC1 FEM0 FEM1 FEM2 FEM3 FEM4 FEM5 FLPMC IMR0 IMR0H IMR0L IMR1 IMR1H IMR1L IMR2 IMR2H IMR2L IMR3 IMR3H IMR3L INTM0 INTM1 INTM2 ISPR ITRG0 LOCKR M_CONF00 to M_CONF31 M_CTRL00 to M_CTRL31 CAN message control registers 00 to 31 FCAN 547 DMA trigger factor register 3 Dead-time timer 00 Dead-time timer 01 Dead-time timer 02 Dead-time timer 10 Dead-time timer 11 Dead-time timer 12 Dead-time timer reload register 0 Dead-time timer reload register 1 Data wait control register 0 Data wait control register 1 Timer 2 input filter mode register 0 Timer 2 input filter mode register 1 Timer 2 input filter mode register 2 Timer 2 input filter mode register 3 Timer 2 input filter mode register 4 Timer 2 input filter mode register 5 Flash programming mode control register Interrupt mask register 0 Interrupt mask register 0H Interrupt mask register 0L Interrupt mask register 1 Interrupt mask register 1H Interrupt mask register 1L Interrupt mask register 2 Interrupt mask register 2H Interrupt mask register 2L Interrupt mask register 3 Interrupt mask register 3H Interrupt mask register 3L External interrupt mode register 0 External interrupt mode register 1 External interrupt mode register 2 In-service priority register A/D internal trigger selection register Lock register CAN message configuration registers 00 to 31 Register Name Unit DMAC TM00 TM00 TM00 TM01 TM01 TM01 TM00 TM01 TM2 TM2 TM2 TM2 TM2 TM2 TM2 TM2 CPU INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC ADC CPU FCAN Page 139 223 223 223 223 223 223 223 223 114 114 183, 717 183, 717 183, 717 183, 717 183, 717 183, 717 747 175 175 175 175 175 175 175 175 175 175 175 175 164 178 178 176 654 203 555 User's Manual U14492EJ5V0UD 797 APPENDIX B REGISTER INDEX (7/11) Symbol M_DATAn0 to M_DATAn7 M_DLC00 to M_DLC31 M_IDH00 to M_IDH31 M_IDL00 to M_IDL31 M_STAT00 to M_STAT31 M_TIME00 to M_TIME31 NBDH NBDHL NBDHU NBDL NBDLL NBDLU NBDMDH NBDMDL NBDMSH NBDMSL NRC10 NRC11 NRC3 OCTLE0 OCTLE0H OCTLE0L ODELE0 ODELE0H ODELE0L P0 P0IC0 P0IC1 P0IC2 P0IC3 P0IC4 P0IC5 P0IC6 P1 P2 P3 RAM access data buffer register H RAM access data buffer register HL RAM access data buffer register HU RAM access data buffer register L RAM access data buffer register LL RAM access data buffer register LU DMA destination address setting register DH DMA destination address setting register DL DMA source address setting register SH DMA source address setting register SL Timer 10 noise elimination time selection register Timer 11 noise elimination time selection register Timer 3 noise elimination time selection register Timer 2 output control register 0 Timer 2 output control register 0H Timer 2 output control register 0L Timer 2 output delay register 0 Timer 2 output delay register 0H Timer 2 output delay register 0L Port 0 Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Interrupt control register Port 1 Port 2 Port 3 NBD NBD NBD NBD NBD NBD NBD NBD NBD NBD TM10 TM11 TM3 TM2 TM2 TM2 TM2 TM2 TM2 Port INTC INTC INTC INTC INTC INTC INTC Port Port Port 634 634 634 634 634 634 636 636 635 635 714 714 715 341 341 341 350 350 350 689 172 172 172 172 172 172 172 690 693 696 CAN message time stamp registers 00 to 31 FCAN 550 CAN message status registers 00 to 31 FCAN 557 CAN message ID registers L00 to L31 FCAN 553 CAN message ID registers H00 to H31 FCAN 553 CAN message data length registers 00 to 31 FCAN 545 Register Name CAN message data registers n0 to n7 (n = 00 to 31) Unit FCAN Page 551 798 User's Manual U14492EJ5V0UD APPENDIX B REGISTER INDEX (8/11) Symbol P4 PCM PCS PCT PDH PDL PDLH PDLL PFC1 PFC2 PHCMD PHS PM1 PM2 PM3 PM4 PMC1 PMC2 PMC3 PMC4 PMCCM PMCCS PMCCT PMCDH PMCDL PMCDLH PMCDLL PMCM PMCS PMCT PMDH PMDL PMDLH PMDLL POER0 POER1 PRCMD PRM01 PRM02 PRM03 PRM04 Port 4 Port CM Port CS Port CT Port DH Port DL Port DLH Port DLL Port 1 function control register Port 2 function control register Peripheral command register Peripheral status register Port 1 mode register Port 2 mode register Port 3 mode register Port 4 mode register Port 1 mode control register Port 2 mode control register Port 3 mode control register Port 4 mode control register Port CM mode control register Port CS mode control register Port CT mode control register Port DH mode control register Port DL mode control register Port DL mode control register H Port DL mode control register L Port CM mode register Port CS mode register Port CT mode register Port DH mode register Port DL mode register Port DL mode register H Port DL mode register L PWM output enable register 0 PWM output enable register 1 Command register Timer 0 clock selection register Timer 1/timer 2 clock selection register Timer 3 clock selection register FCAN clock selection register User's Manual U14492EJ5V0UD Register Name Unit Port Port Port Port Port Port Port Port Port Port CPU CPU Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port TM00 TM01 CPU TM0 TM1/TM2 TM3 FCAN Page 698 708 704 706 700 702 702 702 692 695 199 202 690 693 696 698 691 694 697 699 709 705 707 701 703 703 703 708 705 706 700 703 703 703 239 239 207 226 299, 335 379 544 799 APPENDIX B REGISTER INDEX (9/11) Symbol PRM10 PRM11 PRSCM1 PRSCM2 PRSCM3 PRSM1 PRSM2 PRSM3 PSC PSMR PSTO0 PSTO1 RXB0 RXB1 RXB2 RXBL1 RXBL2 SC_STAT00 to SC_STAT31 SEIC0 SESA10 SESA11 SESC SESE0 SESE0H SESE0L SIO0 SIO1 SIOL0 SIOL1 SIRB0 SIRB1 SIRBE0 SIRBE1 SIRBEL0 SIRBEL1 SIRBL0 SIRBL1 SOTB0 SOTB1 SOTBF0 Interrupt control register Signal edge selection register 10 Signal edge selection register 11 Valid edge selection register Timer 2 sub-channel input event edge selection register 0 Timer 2 sub-channel input event edge selection register 0H Timer 2 sub-channel input event edge selection register 0L Serial I/O shift register 0 Serial I/O shift register 1 Serial I/O shift register L0 Serial I/O shift register L1 Clocked serial interface receive buffer register 0 Clocked serial interface receive buffer register 1 Clocked serial interface read-only receive buffer register 0 Clocked serial interface read-only receive buffer register 1 Clocked serial interface read-only receive buffer register L0 Clocked serial interface read-only receive buffer register L1 Clocked serial interface receive buffer register L0 Clocked serial interface receive buffer register L1 Clocked serial interface transmit buffer register 0 Clocked serial interface transmit buffer register 1 Clocked serial interface initial transmit buffer register 0 User's Manual U14492EJ5V0UD Register Name Prescaler mode register 10 Prescaler mode register 11 Prescaler compare register 1 Prescaler compare register 2 Prescaler compare register 3 Prescaler mode register 1 Prescaler mode register 2 Prescaler mode register 3 Power save control register Power save mode register PWM software timing output register 0 PWM software timing output register 1 Receive buffer register 0 2-frame continuous reception buffer register 1 2-frame continuous reception buffer register 2 Receive buffer register L1 Receive buffer register L2 CAN status set/clear registers 00 to 31 Unit TM10 TM11 UART1 UART2 CSI0, CSI1 UART1 UART2 CSI0, CSI1 CPU CPU TM00 TM01 UART0 UART1 UART2 UART1 UART2 FCAN Page 306 306 471 471 511 470 470 511 208 207 240 240 419 450 450 450 450 559 INTC INTC, TM10 INTC, TM11 INTC, TM3 TM2 TM2 TM2 CSI0 CSI1 CSI0 CSI1 CSI0 CSI1 CSI0 CSI1 CSI0 CSI1 CSI0 CSI1 CSI0 CSI1 CSI0 172 179, 304 179, 304 182, 384 337 337 337 491 491 492 492 483 483 485 485 486 486 484 484 487 487 489 800 APPENDIX B REGISTER INDEX (10/11) Symbol SOTBF1 SOTBFL0 SOTBFL1 SOTBL0 SOTBL1 SPEC0 SPEC1 SRIC0 SRIC1 SRIC2 STATUS0 STATUS1 STIC0 STIC1 STIC2 STOPTE0 STOPTE0H STOPTE0L TBSTATE0 TBSTATE0H TBSTATE0L TCRE0 TCRE0H TCRE0L TM00 TM01 TM0IC0 TM0IC1 TM10 TM11 TM20 TM21 TM2IC0 TM2IC1 TM3 TM3IC0 TM4 TMC00 TMC00H TMC00L TMC01 Register Name Clocked serial interface initial transmit buffer register 1 Clocked serial interface initial transmit buffer register L0 Clocked serial interface initial transmit buffer register L1 Clocked serial interface transmit buffer register L0 Clocked serial interface transmit buffer register L1 TOMR write enable register 0 TOMR write enable register 1 Interrupt control register Interrupt control register Interrupt control register Status register 0 Status register 1 Interrupt control register Interrupt control register Interrupt control register Timer 2 clock stop register 0 Timer 2 clock stop register 0H Timer 2 clock stop register 0L Timer 2 time base status register 0 Timer 2 time base status register 0H Timer 2 time base status register 0L Timer 2 time base control register 0 Timer 2 time base control register 0H Timer 2 time base control register 0L Timer 00 Timer 01 Interrupt control register Interrupt control register Timer 10 Timer 11 Timer 20 Timer 21 Interrupt control register Interrupt control register Timer 3 Interrupt control register Timer 4 Timer control register 00 Timer control register 00H Timer control register 00L Timer control register 01 User's Manual U14492EJ5V0UD Unit CSI1 CSI0 CSI1 CSI0 CSI1 TM00 TM01 INTC INTC INTC TM10 TM11 INTC INTC INTC TM2 TM2 TM2 TM2 TM2 TM2 TM2 TM2 TM2 TM00 TM01 INTC INTC TM10 TM11 TM2 TM2 INTC INTC TM3 INTC TM4 TM00 TM00 TM00 TM01 Page 489 490 490 488 488 249 249 172 172 172 308 308 172 172 172 335 335 335 348 348 348 338 338 338 222 222 172 172 297 297 332 332 172 172 375 172 401 227 227 227 227 801 APPENDIX B REGISTER INDEX (11/11) Symbol TMC01H TMC01L TMC10 TMC11 TMC30 TMC31 TMC4 TMIC0 TOMR0 TOMR1 TUC00 TUC01 TUM0 TUM1 TXB0 TXS1 TXS2 TXSL1 TXSL2 VSWC Timer control register 01H Timer control register 01L Timer control register 10 Timer control register 11 Timer control register 30 Timer control register 31 Timer control register 4 Timer connection selection register 0 Timer output mode register 0 Timer output mode register 1 Timer unit control register 00 Timer unit control register 01 Timer unit mode register 0 Timer unit mode register 1 Transmit buffer register 0 2-frame continuous transmission shift register 1 2-frame continuous transmission shift register 2 Transmit shift register L1 Transmit shift register L2 System wait control register Register Name Unit TM01 TM01 TM10 TM11 TM3 TM3 TM4 TM1/TM2 TM00 TM01 TM00 TM01 TM10 TM11 UART0 UART1 UART2 UART1 UART2 BCU Page 227 227 301 301 380 382 404 409 234 234 233 233 300 300 420 453 453 453 453 98 802 User's Manual U14492EJ5V0UD APPENDIX C INSTRUCTION SET LIST C.1 Functions (1) Symbols used in operand descriptions Symbol reg1 reg2 Explanation General-purpose register (Used as source register) General-purpose register (Usually used as destination register. Used as source register in some instructions.) General-purpose register (Usually stores remainder of division result or higher 32 bits of multiplication result.) bit#3 immX dispX regID vector cccc sp ep listx 3-bit data for bit number specification X-bit immediate data X-bit displacement data System register number 5-bit data that specifies a trap vector (00H to 1FH) 4-bit data that shows a condition code Stack pointer (r3) Element pointer (r30) X-item register list reg3 (2) Symbols used in operands Symbol R r w d I i cccc CCCC bbb L S Explanation 1 bit of data of code that specifies reg1 or regID 1 bit of data of code that specifies reg2 1 bit of data of code that specifies reg3 1 bit of data of a displacement 1 bit of immediate data (Shows higher bit of immediate data) 1 bit of immediate data 4-bit data that shows a condition code 4-bit data that shows condition code of Bcond instruction 3-bit data for bit number specification 1 bit of data that specifies a program register in a register list 1 bit of data that specifies a system register in a register list User's Manual U14492EJ5V0UD 803 APPENDIX C INSTRUCTION SET LIST (3) Symbols used in operations Symbol GR [ ] SR [ ] zero-extend (n) sign-extend (n) load-memory (a, b) store-memory (a, b, c) load-memory-bit (a, b) store-memory-bit (a, b, c) saturated (n) Assignment General-purpose register System register Zero-extend n to word length. Sign-extend n to word length. Read data of size "b" from address "a". Write data "b" of size "c" to address "a". Read bit "b" of address "a". Write "c" in bit "b" of address "a". Perform saturation processing of n (n is 2's complement). If n is a computation result and n 7FFFFFFFH, make n = 7FFFFFFFH. If n is a computation result and n 80000000H, make n = 80000000H. result Byte Half-word Word + - || x / % AND OR XOR NOT logically shift left by logically shift right by arithmetically shift right by Reflect result in flag. Byte (8 bits) Halfword (16 bits) Word (32 bits) Addition Subtraction Bit concatenation Multiplication Division Remainder of division result Logical product Logical sum Exclusive logical sum Logical negation Logical shift left Logical shift right Arithmetic shift right Explanation (4) Symbols used in execution clock Symbol i r | Explanation When executing another instruction immediately after instruction execution (issue) When repeating same instruction immediately after instruction execution (repeat) When using instruction execution result in instruction immediately after instruction execution (latency) 804 User's Manual U14492EJ5V0UD APPENDIX C INSTRUCTION SET LIST (5) Symbols used in flag operations Symbol (Blank) 0 x R No change Clear to 0. Set or cleared according to result. Previously saved value is restored. Explanation (6) Condition codes Condition Name (cond) V NV C/L 0000 1000 0001 Condition Code (cccc) OV = 1 OV = 0 CY = 1 Overflow No overflow Carry Lower (Less than) NC/NL 1001 CY = 0 No carry No lower (Greater than or equal) Z/E 0010 Z=1 Zero Equal NZ/NE 1010 Z=0 Not zero Not equal NH H N P T SA LT GE LE GT 0011 1011 0100 1100 0101 1101 0110 1110 0111 1111 SAT = 1 (S xor OV) = 1 (S xor OV) = 0 ((S xor OV) or Z) = 1 ((S xor OV) or Z) = 0 (CY or Z) = 1 (CY or Z) = 0 S=1 S=0 - Not higher (Less than or equal) Higher (Greater than) Negative Positive Always (Unconditional) Saturated Less than signed Greater than or equal signed Less than or equal signed Greater than signed Condition Expression Explanation User's Manual U14492EJ5V0UD 805 APPENDIX C INSTRUCTION SET LIST C.2 Instruction Set (Alphabetical Order) (1/5) Mnemonic Operands Opcode Operation Execution Clock i ADD reg1, reg2 imm5, reg2 ADDI imm16, reg1, reg2 AND ANDI reg1, reg2 imm16, reg1, reg2 Bcond disp9 r r r r r 0 0 1 1 1 0 R R R R R GR[reg2] GR[reg2] + GR[reg1] r r r r r 0 1 0 0 1 0 i i i i i GR[reg2] GR[reg2] + sign-extend (imm5) r r r r r 1 1 0 0 0 0 R R R R R GR[reg2] GR[reg1] + sign-extend (imm16) ii i i i i i i i i i i i i i i r r r r r 0 0 1 0 1 0 R R R R R GR[reg2] GR[reg2] AND GR[reg1] r r r r r 1 1 0 1 1 0 R R R R R GR[reg2] GR[reg1] AND zero-extend (imm16) iiiiiiiiiiiiiii i d d d d d 1 0 1 1 d d d c c c c if conditions are satisfied Note 1 then PC PC + sign-extend (disp9) Conditions satisfied Conditions not satisfied 1 1 1 1 1 1 0 0 1 1 1 r 1 1 1 I 1 1 1 CY OV Flags S Z SAT x x x x x x x x x x x x x 0 x x 3 Note 2 3 Note 2 3 Note 2 1 1 1 BSH reg2, reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 GR[reg3] GR[reg2] (23:16) || GR[reg2] (31:24) || w w w w w 0 1 1 0 1 0 0 0 0 1 0 GR[reg2] (7:0) || GR[reg2] (15:8) r r r r r 1 1 1 1 1 1 0 0 0 0 0 GR[reg3] GR[reg2] (7:0) || GR[reg2] (15:8) || GR w w w w w 0 1 1 0 1 0 0 0 0 0 0 [reg2] (23:16) || GR[reg2] (31:24) 0 0 0 0 0 0 1 0 0 0 i i i i i i CTPC PC + 2 (return PC) CTPSW PSW adr CTBP + zero-extend (imm6 logically shift left by 1) PC CTBP + zero-extend (Load-memory (adr, Halfword) 1 1 1 x x 0 x x x x BSW reg2, reg3 1 1 1 0 CALLT imm6 5 5 5 CLR1 bit#3, disp16[reg1] 1 0 b b b 1 1 1 1 1 0 R R R R R adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d d Z flag Not (Load-memory-bit (adr, bit#3)) Store-memory-bit (adr, bit#3, 0) 1 0 b b b 1 1 1 1 1 0 R R R R R adr GR[reg1] d d d d d d d d d d d d d d d d Z flag Not (Load-memory-bit (adr, reg2)) Store-memory-bit (adr, reg2, 0) r r r r r 1 1 1 1 1 1 i i i i i if conditions are satisfied w w w w w 0 1 1 0 0 0 c c c c 0 then GR[reg3] sign-extend (imm5) else GR[reg3] GR[reg2] r r r r r 1 1 1 1 1 1 R R R R R if conditions are satisfied w w w w w 0 1 1 0 0 1 c c c c 0 then GR[reg3] GR[reg1] else GR[reg3] GR[reg2] r r r r r 0 0 1 1 1 1 R R R R R result GR[reg2] - GR[reg1] r r r r r 0 1 0 0 1 1 i i i i i result GR[reg2] - sign-extend (imm5) 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PC CTPC 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 PSW CTPSW 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PC DBPC 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 0 PSW DBPSW 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 DBPC PC + 2 (return PC) DBPSW PSW PSW.NP 1 PSW.EP 1 PSW.ID 1 PC 00000060H 3 Note 3 3 Note 3 3 Note 3 x reg2, [reg1] 3 Note 3 3 Note 3 3 Note 3 x CMOV cccc, imm5, reg2, reg3 1 1 1 cccc, reg1, reg2, reg3 1 1 1 CMP reg1, reg2 imm5, reg2 1 1 4 1 1 4 1 1 4 x x R x x R x x R x x R R CTRET DBRET 4 4 4 R R R R R DBTRAP 4 4 4 DI 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PSW.ID 1 000000010110000 0 1 1 1 806 User's Manual U14492EJ5V0UD APPENDIX C INSTRUCTION SET LIST (2/5) Mnemonic Operands Opcode Operation Execution Clock i DISPOSE imm5, list12 0 0 0 0 0 1 1 0 0 1 i i i i i L sp sp + zero-extend (imm5 logically shift left by 2) L L L L L L L L L L L 0 0 0 0 0 GR[reg in list12] Load-memory (sp, Word) sp sp + 4 repeat 2 steps above until regs in list12 is loaded imm5, list12[reg1] 0 0 0 0 0 1 1 0 0 1 i i i i i L sp sp + zero-extend (imm5 logically shift left by 2) L L L L L L L L L L L R R R R R GR[reg in list12] Load-memory (sp, Word) Note 5 sp sp + 4 repeat 2 steps above until regs in list12 is loaded PC GR[reg1] DIV reg1, reg2, reg3 reg1, reg2 reg1, reg2, reg3 DIVHU reg1, reg2, reg3 reg1, reg2, reg3 EI r r r r r 1 1 1 1 1 1 R R R R R GR[reg2] GR[reg2] / GR[reg1] w w w w w 0 1 0 1 1 0 0 0 0 0 0 GR[reg3] GR[reg2]%GR[reg1] r r r r r 0 0 0 0 1 0 R R R R R GR[reg2] GR[reg2] / GR[reg1]Note 6 r r r r r 1 1 1 1 1 1 R R R R R GR[reg2] GR[reg2] / GR[reg1] w w w w w 0 1 0 1 0 0 0 0 0 0 0 GR[reg3] GR[reg2]%GR[reg1] r r r r r 1 1 1 1 1 1 R R R R R GR[reg2] GR[reg2] / GR[reg1]Note 6 w w w w w 0 1 0 1 0 0 0 0 0 1 0 GR[reg3] GR[reg2]%GR[reg1] r r r r r 1 1 1 1 1 1 R R R R R GR[reg2] GR[reg2] / GR[reg1] w w w w w 0 1 0 1 1 0 0 0 0 1 0 GR[reg3] GR[reg2]%GR[reg1] 1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PSW.ID 0 000000010110000 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 Stop 000000010010000 0 reg2, reg3 r r r r r 1 1 1 1 1 1 0 0 0 0 0 GR[reg3] GR[reg2] (15:0) || GR[reg2] (31:16) wwwww0110100010 0 r r r r r 1 1 1 1 0 d d d d d d GR[reg2] PC + 4 d d d d d d d d d d d d d d d 0 PC PC + sign-extend (disp22) Note 7 JMP JR [reg1] disp22 0 0 0 0 0 0 0 0 0 1 1 R R R R R PC GR[reg1] 0 0 0 0 0 1 1 1 1 0 d d d d d d PC PC + sign-extend (disp22) ddddddddddddddd 0 Note 7 r r r r r 1 1 1 0 0 0 R R R R R adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d d GR[reg2] sign-extend (Load-memory (adr, Byte)) r r r r r 1 1 1 1 0 b R R R R R adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d 1 GR[reg2] zero-extend (Load-memory (adr, Byte)) Notes 8, 10 LD.H disp16[reg1], reg2 r r r r r 1 1 1 0 0 1 R R R R R adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d 0 GR[reg2] sign-extend (Load-memory (adr, Note 8 Halfword)) r r r r r 1 1 1 1 1 1 R R R R R SR[regID] GR[reg2] 00 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Note 12 LD.HU disp16[reg1], reg2 Other than regID = PSW regID = PSW 1 1 Note 11 Note 6 Flags CY OV S Z SAT r n+1 Note 4 I n+1 Note 4 n+1 Note 4 n+3 Note 4 n+3 Note 4 n+3 Note 4 35 35 35 x x x x x x x x x x x x x x x DIVH 35 35 35 35 35 35 34 34 34 DIVU 34 34 34 1 1 1 HALT 1 1 1 HSW 1 1 1 x 0 x x JARL disp22, reg2 3 3 3 4 3 4 3 4 3 LD.B disp16[reg1], reg2 1 1 Note 11 LD.BU disp16[reg1], reg2 1 1 Note 11 LDSR reg2, regID 1 1 1 1 1 1 1 1 Note 11 x x x x x r r r r r 1 1 1 0 0 1 R R R R R adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d 1 GR[reg2] zero-extend (Load-memory (adr, Note 8 Halfword)) User's Manual U14492EJ5V0UD 807 APPENDIX C INSTRUCTION SET LIST (3/5) Mnemonic Operands Opcode Operation Execution Clock i LD.W disp16[reg1], reg2 r r r r r 1 1 1 0 0 1 R R R R R adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d 1 GR[reg2] Load-memory (adr, Word) Note 8 r r r r r 0 0 0 0 0 0 R R R R R GR[reg2] GR[reg1] r r r r r 0 1 0 0 0 0 i i i i i GR[reg2] sign-extend (imm5) 0 0 0 0 0 1 1 0 0 0 1 R R R R R GR[reg1] imm32 iiiiiiiiiiiiiii i IIIIIIIIIIIIIII I r r r r r 1 1 0 0 0 1 R R R R R GR[reg2] GR[reg1] + sign-extend (imm16) iiiiiiiiiiiiiii i r r r r r 1 1 0 0 1 0 R R R R R GR[reg2] GR[reg1] + (imm16 || 016) iiiiiiiiiiiiiii i r r r r r 1 1 1 1 1 1 R R R R R GR[reg3] || GR[reg2] GR[reg2] x GR[reg1] w w w w w 0 1 0 0 0 1 0 0 0 0 0 reg1 reg2 reg3, reg3 r0 r r r r r 1 1 1 1 1 1 i i i i i GR[reg3] || GR[reg2] GR[reg2] x sign-extend w w w w w 0 1 0 0 1 I I I I 0 0 (imm9) Note 13 MULH reg1, reg2 imm5, reg2 MULHI imm16, reg1, reg2 MULUNote 22 reg1, reg2, reg3 imm9, reg2, reg3 Note 6 x GR[reg1]Note 6 r r r r r 0 0 0 1 1 1 R R R R R GR[reg2] GR[reg2] Note 6 x sign-extend (imm5) r r r r r 0 1 0 1 1 1 i i i i i GR[reg2] GR[reg2] Note 6 x imm16 r r r r r 1 1 0 1 1 1 R R R R R GR[reg2] GR[reg1] iiiiiiiiiiiiiii i Flags CY OV S Z SAT r 1 I Note 11 1 MOV reg1, reg2 imm5, reg2 imm32, reg1 1 1 2 1 1 2 1 1 2 MOVEA imm16, reg1, reg2 1 1 1 MOVHI imm16, reg1, reg2 reg1, reg2, reg3 imm9, reg2, reg3 1 1 1 MULNote 22 1 2 Note 14 2 1 2 Note 14 2 1 1 1 1 1 1 2 2 2 r r r r r 1 1 1 1 1 1 R R R R R GR[reg3] || GR[reg2] GR[reg2] x GR[reg1] w w w w w 0 1 0 0 0 1 0 0 0 1 0 reg1 reg2 reg3, reg3 r0 r r r r r 1 1 1 1 1 1 i i i i i GR[reg3] || GR[reg2] GR[reg2] x zero-extend w w w w w 0 1 0 0 1 I I I I 1 0 (imm9) Note 13 1 2 Note 14 2 1 2 Note 14 2 NOP NOT NOT1 reg1, reg2 bit#3, disp16[reg1] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Passes at least 1 cycle doing nothing. r r r r r 0 0 0 0 0 1 R R R R R GR[reg2] NOT (GR[reg1]) 0 1 b b b 1 1 1 1 1 0 R R R R R adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d d Z flag Not (Load-memory-bit (adr, bit#3)) Store-memory-bit (adr, bit#3, Z flag) reg2, [reg1] r r r r r 1 1 1 1 1 1 R R R R R adr GR[reg1] 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 Z flag Not (Load-memory-bit (adr, reg2)) Store-memory-bit (adr, reg2, Z flag) r r r r r 0 0 1 0 0 0 R R R R R GR[reg2] GR[reg2] OR GR[reg1] r r r r r 1 1 0 1 0 0 R R R R R GR[reg2] GR[reg1] OR zero-extend (imm16) iiiiiiiiiiiiiii i 0 0 0 0 0 1 1 1 1 0 i i i i i L Store-memory (sp-4, GR[reg in list12], Word) L L L L L L L L L L L 0 0 0 0 1 sp sp-4 repeat 1 steps above until regs in list12 is stored sp sp-zero-extend (imm5) 0 0 0 0 0 1 1 1 1 0 i i i i i L Store-memory (sp-4, GR[reg in list12], Word) L L L L L L L L L L L f f 0 1 1 GR[reg in list12] Load-memory (sp, Word) sp sp + 4 imm16/imm32 Note 16 repeat 2 steps above until regs in list12 is loaded PC GR[reg1] 1 1 3 Note 3 1 1 3 Note 3 1 1 3 Note 3 0 x x x 3 Note 3 3 Note 3 3 Note 3 x OR ORI reg1, reg2 imm16, reg1, reg2 1 1 1 1 1 1 0 0 x x x x PREPARE list12, imm5 n+1 Note 4 n+1 Note 4 n+1 Note 4 list12, imm5, sp/immNote 15 n+2 Note 4 n+2 Note 4 n+2 Note 4 Note 17 Note 17 Note 17 808 User's Manual U14492EJ5V0UD APPENDIX C INSTRUCTION SET LIST (4/5) Mnemonic Operands Opcode Operation Execution Clock i RETI 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 if PSW.EP = 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 then PC EIPC PSW EIPSW else if PSW.NP = 1 then PC FEPC PSW FEPSW else PC EIPC PSW EIPSW SAR reg1, reg2 r r r r r 1 1 1 1 1 1 R R R R R GR[reg2] GR[reg2] arithmetically shift right by 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 GR[reg1] r r r r r 0 1 0 1 0 1 i i i i i GR[reg2] GR[reg2] arithmetically shift right by zeroextend (imm5) r r r r r 1 1 1 1 1 1 0 c c c c if conditions are satisfied 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 then GR[reg2] (GR[reg2] Logically shift left by 1) OR 00000001H else GR[reg2] (GR[reg2] Logically shift left by 1) OR 00000000H r r r r r 0 0 0 1 1 0 R R R R R GR[reg2] saturated (GR[reg2] + GR[reg1]) r r r r r 0 1 0 0 0 1 i i i i i GR[reg2] saturated (GR[reg2] + sign-extend (imm5)) r r r r r 0 0 0 1 0 1 R R R R R GR[reg2] saturated (GR[reg2] - GR[reg1]) r r r r r 1 1 0 0 1 1 R R R R R GR[reg2] saturated (GR[reg1] - sign-extend i i i i i i i i i i i i i i i i (imm16)) r r r r r 0 0 0 1 0 0 R R R R R GR[reg2] saturated (GR[reg1] - GR[reg2]) r r r r r 1 1 1 1 1 1 0 c c c c if conditions are satisfied 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 then GR[reg2] 00000001H else GR[reg2] 00000000H SET1 bit#3, disp16 [reg1] 0 0 b b b 1 1 1 1 1 0 R R R R R adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d d Z flag Not (Load-memory-bit (adr, bit#3)) Store-memory-bit (adr, bit#3, 1) r r r r r 1 1 1 1 1 1 R R R R R adr GR[reg1] 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 Z flag Not (Load-memory-bit (adr, reg2)) Store-memory-bit (adr, reg2, 1) SHL reg1, reg2 r r r r r 1 1 1 1 1 1 R R R R R GR[reg2] GR[reg2] logically shift left by GR[reg1] 000000001100000 0 imm5, reg2 r r r r r 0 1 0 1 1 0 i i i i i GR[reg2] GR[reg2] logically shift left by zero-extend (imm5) r r r r r 1 1 1 1 1 1 R R R R R GR[reg2] GR[reg2] logically shift right by GR[reg1] 000000001000000 0 imm5, reg2 r r r r r 0 1 0 1 0 0 i i i i i GR[reg2] GR[reg2] logically shift right by zero-extend (imm5) r r r r r 0 1 1 0 d d d d d d d adr ep + zero-extend (disp7) GR[reg2] sign-extend (Load-memory (adr, Byte)) r r r r r 0 0 0 0 1 1 0 d d d d adr ep + zero-extend (disp4) Note 18 GR[reg2] zero-extend (Load-memory (adr, Byte)) r r r r r 1 0 0 0 d d d d d d d adr ep + zero-extend (disp8) Note 19 GR[reg2] sign-extend (Load-memory (adr, Halfword)) 1 1 1 1 1 1 3 Note 3 Flags CY R OV R S R Z R SAT R r 4 I 4 4 1 1 1 x x 0 x x x x imm5, reg2 1 1 1 0 SASF cccc, reg2 1 1 1 SATADD reg1, reg2 imm5, reg2 1 1 1 1 1 1 1 1 1 1 1 1 x x x x x x x x x x x x x x x x x x x x x x x x x SATSUB SATSUBI reg1, reg2 imm16, reg1, reg2 reg1, reg2 cccc, reg2 SATSUBR SETF 1 1 1 1 1 1 3 Note 3 3 Note 3 x reg2, [reg1] 3 Note 3 3 Note 3 3 Note 3 x 1 1 1 x x x x 0 x x x x x x x x 0 SHR reg1, reg2 1 1 1 0 0 SLD.B disp7[ep], reg2 disp4[ep], reg2 disp8[ep], reg2 1 1 Note 9 SLD.BU 1 1 Note 9 SLD.H 1 1 Note 9 User's Manual U14492EJ5V0UD 809 APPENDIX C INSTRUCTION SET LIST (5/5) Mnemonic Operands Opcode Operation Execution Clock i SLD.HU disp5[ep], reg2 r r r r r 0 0 0 0 1 1 1 d d d d adr ep + zero-extend (disp5) Notes 18, 20 GR[reg2] zero-extend (Load-memory (adr, Halfword)) r r r r r 1 0 1 0 d d d d d d 0 adr ep + zero-extend (disp8) Note 21 GR[reg2] Load-memory (adr, Word) r r r r r 0 1 1 1 d d d d d d d adr ep + zero-extend (disp7) Store-memory (adr, GR[reg2], Byte) r r r r r 1 0 0 1 d d d d d d d adr ep + zero-extend (disp8) Note 19 Store-memory (adr, GR[reg2], Halfword) r r r r r 1 0 1 0 d d d d d d 1 adr ep + zero-extend (disp8) Note 21 Store-memory (adr, GR[reg2], Word) r r r r r 1 1 1 0 1 0 R R R R R adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d d Store-memory (adr, GR[reg2], Byte) r r r r r 1 1 1 0 1 1 R R R R R adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d 0 Store-memory (adr, GR[reg2], Halfword) Note 8 r r r r r 1 1 1 0 1 1 R R R R R adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d 1 Store-memory (adr, GR[reg2], Word) Note 8 r r r r r 1 1 1 1 1 1 R R R R R GR[reg2] SR[regID] 000000000100000 0 SUB SUBR SWITCH reg1, reg2 reg1, reg2 reg1 r r r r r 0 0 1 1 0 1 R R R R R GR[reg2] GR[reg2] - GR[reg1] r r r r r 0 0 1 1 0 0 R R R R R GR[reg2] GR[reg1] - GR[reg2] 0 0 0 0 0 0 0 0 0 1 0 R R R R R adr (PC + 2) + (GR[reg1] logically shift left by 1) PC (PC + 2) + (sign-extend (Load-memory (adr, Halfword))) logically shift left by 1 SXB SXH TRAP reg1 reg1 vector 0 0 0 0 0 0 0 0 1 0 1 R R R R R GR[reg1] sign-extend (GR[reg1] (7:0)) 0 0 0 0 0 0 0 0 1 1 1 R R R R R GR[reg1] sign-extend (GR[reg1] (15:0)) 0 0 0 0 0 1 1 1 1 1 1 i i i i i EIPC PC + 4 (return PC) PSW 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 EIPSW ECR.EICC exception code (40H to 4FH, 50H to 5FH) PSW.EP 1 PSW.ID 1 PC 00000040H (when vector is 00H to 0FH (exception code: 40H to 4FH)) 00000050H (when vector is 10H to 1FH (exception code: 50H to 5FH)) TST TST1 reg1, reg2 bit#3, disp16 [reg1] reg2, [reg1] r r r r r 0 0 1 0 1 1 R R R R R result GR[reg2] AND GR[reg1] 1 1 b b b 1 1 1 1 1 0 R R R R R adr GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d d Z flag Not (Load-memory-bit (adr, bit#3)) r r r r r 1 1 1 1 1 1 R R R R R adr GR[reg1] 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 Z flag Not (Load-memory-bit (adr, reg2)) r r r r r 0 0 1 0 0 1 R R R R R GR[reg2] GR[reg2] XOR GR[reg1] r r r r r 1 1 0 1 0 1 R R R R R GR[reg2] GR[reg1] XOR zero-extend (imm16) iiiiiiiiiiiiiii i 0 0 0 0 0 0 0 0 1 0 0 R R R R R GR[reg1] zero-extend (GR[reg1] (7:0)) 0 0 0 0 0 0 0 0 1 1 0 R R R R R GR[reg1] zero-extend (GR[reg1] (15:0)) 1 3 Note 3 Flags CY OV S Z SAT r 1 I Note 9 1 SLD.W disp8[ep], reg2 reg2, disp7[ep] reg2, disp8[ep] reg2, disp8[ep] reg2, disp16 [reg1] reg2, disp16 [reg1] 1 1 Note 9 SST.B 1 1 1 SST.H 1 1 1 SST.W 1 1 1 ST.B 1 1 1 ST.H 1 1 1 ST.W reg2, disp16 [reg1] 1 1 1 STSR regID, reg2 1 1 1 1 1 5 1 1 5 1 1 5 x x x x x x x x 1 1 4 1 1 4 1 1 4 1 3 Note 3 1 3 Note 3 0 x x x x 3 Note 3 3 Note 3 3 Note 3 XOR XORI reg1, reg2 imm16, reg1, reg2 reg1 reg1 1 1 1 1 1 1 0 0 x x x x ZXB ZXH 1 1 1 1 1 1 810 User's Manual U14492EJ5V0UD APPENDIX C INSTRUCTION SET LIST Notes 1. 2. 3. 4. 5. 6. 7. 8. 9. dddddddd is the higher 8 bits of disp9. 4 if there is an instruction to overwrite the contents of the PSW immediately before If there is no wait state (3 + number of read access wait states) n is the total number of load registers in list12. (According to the number of wait states. If there are no wait states, n is the number of registers in list12. When n = 0, the operation is the same as n = 1.) RRRRR: Other than 00000 Only the lower halfword of data is valid. ddddddddddddddddddddd is the higher 21 bits of disp22. ddddddddddddddd is the higher 15 bits of disp16. According to the number of wait states (1 if there are no wait states) 10. b: Bit 0 of disp16 11. According to the number of wait states (2 if there are no wait states) 12. In this instruction, although the source register is regarded as reg2 for convenience of the mnemonic description, the reg1 field is used in the opcode. Therefore, the meanings of register specifications assigned in the mnemonic description and in the opcode differ from those in other instructions. rrrrr = regID specification RRRRR = reg2 specification 13. iiiii: Lower 5 bits of imm9 IIII: Higher 4 bits of imm9 14. Shortened by 1 clock if reg2 = reg3 (lower 32 bits of result are not written to register) or reg3 = r0 (higher 32 bits of result are not written to register). 15. sp/imm: Specify in bits 19 and 20 of sub-opcode. 16. ff = 00: Load sp in ep. 01: Load sign-extended 16-bit immediate data (bits 47 to 32) in ep. 10: Load 16-bit immediate data (bits 47 to 32) logically shifted 16 bits to the left in ep. 11: Load 32-bit immediate data (bits 63 to 32) in ep. 17. n + 3 clocks when imm = imm32 18. rrrrr: Other than 00000 19. ddddddd is the higher 7 bits of disp8. 20. dddd is the higher 4 bits of disp5. 21. dddddd is the higher 6 bits of disp8. 22. Do not make a combination that satisfies all the following conditions when using the "MUL reg1, reg2, reg3" instruction and "MULU reg1, reg2, reg3" instruction. Operation is not guaranteed when an instruction that satisfies the following conditions is executed. * Reg1 = reg3 * Reg1 reg2 * Reg1 r0 * Reg3 r0 User's Manual U14492EJ5V0UD 811 APPENDIX D REVISION HISTORY D.1 Major Revisions in This Edition (1/2) Page Throughout * Addition of the following lead-free products Description PD703116GJ-xxx-UEN-A, 70F3116GJ-UEN-A, 703116GJ(A)-xxx-UEN-A, 70F3116GJ(A)-UEN-A, 703116GJ(A1)-xxx-UEN-A, 70F3116GJ(A1)-UEN-A p. 21 p. 51 pp. 52, 53, 55, 56 Change of number of instructions in 1.2 Features Addition of Note to Table 3-2 System Register Numbers Addition of 3.2.2 (1) Interrupt status saving registers (EIPC, EIPSW), (2) NMI status saving registers (FEPC, FEPSW), (5) CALLT execution status saving registers (CTPC, CTPSW), (6) Exception/debug trap status saving registers (DBPC, DBPSW), and (7) CALLT base pointer (CTBP) Addition of Figure 3-8 Example of Programmable Peripheral I/O Register Allocation Address Setting Change of bit units for manipulation and initial values in 3.4.9 Programmable peripheral I/O registers Modification of descriptions in table in 3.4.11 System wait control register (VSWC) Addition of 3.4.12 (2) Restriction on conflict between sld instruction and interrupt request Modification of description in 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) Modification of description in 6.3.7 DMA restart register (DRST) Modification of description and addition of Caution to 6.3.8 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) Addition of Figure 6-7 Block Transfer Example Modification of description of Caution in 6.5.1 Two-cycle transfer Addition of Note to Table 6-1 Relationship Between Transfer Type and Transfer Target Deletion of a part of description in 6.7 DMA Channel Priorities Modification of description in 6.8 Next Address Setting Function Addition of Figure 6-9 Example of Forcible Termination of DMA Transfer Modification of descriptions in 6.14 (2) Transfer of misaligned data and (4) DMA start factor Addition of 6.14 (5) Program execution and DMA transfer with internal RAM Addition of Caution to 7.1 Features Addition of Note and Remark to Table 7-1 Interrupt/Exception Source List Addition of Caution to 7.3.8 (4) Timer 2 input filter mode registers 0 to 5 (FEM0 to FEM5) Addition of Caution to 7.5.2 (2) Restore Modification of description in 7.8 Periods in Which CPU Does Not Acknowledge Interrupts Modification of descriptions in 8.5.2 (3) Power save control register (PSC) Addition of description to Table 8-4 Operation Status in IDLE Mode Addition of Caution to 8.5.4 (2) (a) Release by a non-maskable interrupt request or an unmasked maskable interrupt request Addition of description to Table 8-6 Operation Status in Software STOP Mode Addition of Caution to 8.5.5 (2) (a) Release by a non-maskable interrupt request or an unmasked maskable interrupt request p. 82 p. 97 p. 98 p. 99 pp. 136, 137 p. 138 pp. 139, 141 p. 145 p. 145 p. 146 p. 147 pp. 147, 148 p. 151 p. 154 p. 154 p. 156 pp. 157, 159 p. 183 p. 192 p. 196 p. 208 p. 212 p. 213 p. 214 p. 215 812 User's Manual U14492EJ5V0UD APPENDIX D REVISION HISTORY (2/2) Page p. 281 p. 282 p. 297 p. 299 Description Addition of 9.1.5 (4) [Output waveform width in respect to set value] (d) When BFCMnx = 0000H is set while DTMnx = 000H or TM0CEDn bit = 1 Addition of 9.1.5 (4) [Output waveform width in respect to set value] (e) When BFCMnx = CM0n3 = a is set Addition of Caution to 9.2.3 (1) Timers 10, 11 (TM10, TM11) Deletion of Note and modification of description in 9.2.4 (1) Timer 1/timer 2 clock selection register (PRM02) p. 307 p. 316 p. 335 p. 337 p. 342 p. 413 p. 417 p. 441 p. 441 p. 461 p. 562 p. 563 p. 714 p. 714 p. 715 p. 717 p. 790 p. 784 in previous edition Modification of description in table in 9.2.4 (6) (b) UDC mode (CMD bit of TUMn register = 1) Modification of description in Table 9-7 List of Count Operations in UDC Mode Deletion of Note and modification of description in 9.3.4 (1) Timer 1/timer 2 clock selection register (PRM02) Modification of description in 9.3.4 (3) Timer 2 count clock/control edge selection register 0 (CSE0) Addition of 9.3.4 (6) (a) Caution for PWM output change timing Addition of Remark to Figure 10-1 Asynchronous Serial Interface 0 Block Diagram Deletion of a part of description and addition of Caution to 10.2.3 (2) Asynchronous serial interface status register 0 (ASIS0) Addition of description to 10.2.6 (5) Transfer rate during continuous transmission Addition of description to 10.2.7 Precautions (2) Modification of Figure 10-19 Asynchronous Serial Interface Reception Completion Interrupt Timing Modification of description in 11.10 (11) CAN global interrupt pending register (CGINTP) Modification of description in 11.10 (12) CAN1 interrupt pending register (C1INTP) Addition of Caution to 14.5.2 (1) Timer 10 noise elimination time selection register (NRC10) Addition of Caution to 14.5.2 (2) Timer 11 noise elimination time selection register (NRC11) Addition of Caution to 14.5.2 (3) Timer 3 noise elimination time selection register (NRC3) Addition of Caution to 14.5.3 (1) Timer 2 input filter mode registers 0 to 5 (FEM0 to FEM5) Addition of (2) to Table 20-1 Surface Mounting Type Soldering Conditions Deletion of APPENDIX A NOTES User's Manual U14492EJ5V0UD 813 APPENDIX D REVISION HISTORY D.2 Revision History up to Previous Edition The following table shows the revision history up to the previous editions. The "Applied to:" column indicates the chapters of each edition in which the revision was applied. (1/13) Edition 2nd edition Major Revision from Previous Edition * Deletion of the following product Applied to: Throughout PD703117GJ-xxx-UEN * Addition of the following products PD703116GJ-xxx-UEN, 703116GJ(A)-xxx-UEN, 703116GJ(A1)-xxx-UEN, 70F3116GJ(A)-UEN, 70F3116GJ(A1)-UEN * Change of status of the following product from "under development" to "developed" PD70F3116GJ-UEN * Clarification of bits defined as reserved words in the device file (names of bits whose numbers are in angle brackets) Addition of Table 1-1 Differences Between V850E/IA1 and V850E/IA2 Addition of Table 1-2 Differences Between V850E/IA1 and V850E/IA2 Register Setting Values Modification of description in 1.3 Applications Modification of description in 1.4 Ordering Information Modification of Caution in 1.5 Pin Configuration Addition of 1.7 Differences Between Products Modification of pin status of ASTB (PCT6) and HLDRQ (PCM3) pins in 2.2 Pin Status Modification of description in 2.4 Types of Pin I/O Circuit and Connection of Unused Pins Modification of I/O circuit type from 5-K to 5-AC in 2.5 Pin I/O Circuits Modification of description in 3.4.5 (1) (a) Memory map Modification of description in 3.4.5 (2) Internal RAM area Addition of Note and modification of Caution in 3.4.5 (3) On-chip peripheral I/O area Deletion of part of description in 3.4.7 (1) Program space Modification of part of description in example of wrap-around application in 3.4.7 (2) Data space Modification of Figure 3-6 Recommended Memory Map Modification of description in 3.4.8 Peripheral I/O registers Modification of description in 3.4.9 Programmable peripheral I/O registers Modification of bit name in 3.4.9 (1) Peripheral area selection control register (BPC) Modification of description of programmable peripheral I/O register area in 3.4.9 Programmable peripheral I/O registers Modification of description on bits that can be manipulated, modification of description in table, and addition of Remark in 3.4.11 System wait control register (VSWC) Modification and addition of description in 4.2.1 Pin status during internal ROM, internal RAM, and peripheral I/O access Addition of Note in 4.3 Memory Block Function CHAPTER 4 BUS CONTROL FUNCTION CHAPTER 3 CPU FUNCTION CHAPTER 2 PIN FUNCTIONS CHAPTER 1 INTRODUCTION 814 User's Manual U14492EJ5V0UD APPENDIX D REVISION HISTORY (2/13) Edition 2nd edition Major Revision from Previous Edition Addition of Caution in 4.3.1 (1) Chip area selection control registers 0, 1 (CSC0, CSC1) Modification of description in table in 4.5.1 Number of access clocks Addition of Caution in 4.6.1 (2) Address wait control register (AWC) Modification of timing chart in Figure 4-2 Example of Wait Insertion Addition of description in 4.8.1 Function outline Modification of description in 4.9 Bus Priority Order Modification of description (1) in 4.10.1 Program space Modification of timing chart in Figure 5-1 SRAM, External ROM, External I/O Access Timing CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Addition of description in 6.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3) Addition of Caution and modification of bit settings in 6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) Modification of description and Caution in 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) Modification of description on bits that can be manipulated in 6.3.6 DMA disable status register (DDIS) Modification of description on bits that can be manipulated in 6.3.7 DMA restart register (DRST) Modification of description and addition of bit names and bit description in 6.3.8 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) Addition of description in 6.5.1 Single transfer mode Addition of description in 6.5.2 Single-step transfer mode Addition of Caution in 6.6.1 Two-cycle transfer Modification of description in 6.7.1 Transfer type and transfer target Modification of description in Table 6-1 Relationship Between Transfer Type and Transfer Target Addition and deletion of description in Table 6-2 External Bus Cycles During DMA Transfer (Two-Cycle Transfer) Addition of Caution in 6.8 DMA Channel Priorities Addition of part of description in Remark in 6.13 Forcible Termination Modification of description in 6.14 (3) Times related to DMA transfer Addition of 6.14 (5) DMA start factor Modification of description in CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Modification of description in Table 7-1 Interrupt/Exception Source List Modification of description in Figure 7-2 Acknowledging Non-Maskable Interrupt Request Addition of Caution in 7.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) Addition of Caution and modification of bit description in 7.3.8 (2) Signal edge selection registers 10, 11 (SESA10, SESA11) User's Manual U14492EJ5V0UD Applied to: CHAPTER 4 BUS CONTROL FUNCTION CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) CHAPTER 7 INTERRUPT/ EXCEPTION PROCESSING FUNCTION 815 APPENDIX D REVISION HISTORY (3/13) Edition 2nd edition Major Revision from Previous Edition Addition of Caution in 7.3.8 (3) Valid edge selection register (SESC) Addition of Caution and addition of Caution in bit description in 7.3.8 (4) Timer 2 input filter mode registers 0 to 5 (FEM0 to FEM5) Modification of description in Figure 7-14 Pipeline Operation at Interrupt Request Acknowledgement (Outline) Addition and modification of description in 7.8 Periods in Which Interrupts Are Not Acknowledged Modification of description in 8.3.1 Direct mode Addition of description on Caution in 8.3.2 PLL mode Modification of description on bit that can be manipulated and data setting sequence to CKC, and modification of Caution in 8.3.4 Clock control register (CKC) Modification of register symbol and initial value in 8.4 PLL Lockup Modification of Note in Figure 8-1 Power Save Mode State Transition Diagram Modification of data setting sequence to PSC and Caution in 8.5.2 (3) Power save control register (PSC) Modification of description in Table 8-4 Operation Status in IDLE Mode Addition of Note and addition and modification of description in 8.5.4 (2) Release of IDLE mode Modification of description in Table 8-6 Operation Status in Software STOP Mode Addition of Note and addition and modification of description in 8.5.5 (2) Release of software STOP mode Addition and modification of description and modification of timing chart in 8.6.1 (1) Securing the time using an on-chip time base counter Modification of timing chart in 8.6.1 (2) Securing the time according to the signal level width (RESET pin input) Modification of description in Table 8-8 Counting Time Examples (fXX = 10 x fX) Modification of Figure 9-1 Block Diagram of Timer 0 (Mode 0: Symmetric Triangular Wave, Mode 1: Asymmetric Triangular Wave) Modification of Figure 9-2 Block Diagram of Timer 0 (Mode 2: Sawtooth Wave) Addition of Caution in Table 9-1 Timer 0 Operation Modes Addition of Caution in 9.1.3 (3) Dead-time timer reload registers 0, 1 (DTRR0, DTRR1) Modification of bit names in 9.1.4 (2) Timer control registers 00, 01 (TMC00, TMC01) Addition of description, modification of bit names, and addition of Caution in bit description in 9.1.4 (3) Timer unit control registers 00, 01 (TUC00, TUC01) Addition of bit names and bit descriptions in 9.1.4 (4) Timer output mode registers 0, 1 (TOMR0, TOMR1) Addition of Figure 9-7 Output Waveforms of TO000 and TO001 in PWM Mode 0 (Symmetric Triangular Waves) (Without Dead Time (TM0CED0 Bit = 1)) Addition of Figure 9-8 Output Waveforms of TO000 and TO001 in PWM Mode 0 (Symmetric Triangular Waves) (With Dead Time (TM0CED0 Bit = 0)) Modification of bit names in 9.1.4 (5) PWM output enable registers 0, 1 (POER0, POER1) CHAPTER 9 TIMER/COUNTER FUNCTION (REALTIME PULSE UNIT) CHAPTER 8 CLOCK GENERATION FUNCTION Applied to: CHAPTER 7 INTERRUPT/ EXCEPTION PROCESSING FUNCTION 816 User's Manual U14492EJ5V0UD APPENDIX D REVISION HISTORY (4/13) Edition 2nd edition Major Revision from Previous Edition Addition of Caution, modification of bit names and bit descriptions, and addition of Figures 9-9 to 9-14 in 9.1.4 (6) PWM software timing output registers 0, 1 (PSTO0, PSTO1) Addition of Remark in 9.1.5 Operation Addition of Remark in Figure 9-30 Operation Timing in PWM Mode 2 (Sawtooth Wave) Modification of Figure 9-45 Block Diagram of Timer 1 Modification of bit names and addition of Caution in bit description in 9.2.4 (3) Timer control registers 10, 11 (TMC10, TMC11) Modification of bit description in 9.2.4 (5) Signal edge selection registers 10, 11 (SESA10, SESA11) Modification of bit names in 9.2.4 (7) Status registers 0, 1 (STATUS0, STATUS1) Modification of description in Table 9-8 Timer 2 Configuration List Addition of Table 9-9 Capture/Compare Operation Sources Addition of Table 9-10 Output Level Sources During Timer Output Modification of Figure 9-62 Block Diagram of Timer 2 Addition of Caution in 9.3.3 (3) Timer 2 sub-channel n main capture/compare register (CVPEn0) (n = 1 to 4) Addition of Caution in 9.3.3 (4) Timer 2 sub-channel n sub capture/compare register (CVSEn0) (n = 1 to 4) Modification of description on bits that can be manipulated in 9.3.4 (2) Timer 2 clock stop register 0 (STOPTE0) Modification of description on bits that can be manipulated in 9.3.4 (3) Timer 2 count clock/control edge selection register 0 (CSE0) Modification of description on bits that can be manipulated in 9.3.4 (4) Timer 2 subchannel input event edge selection register 0 (SESE0) Modification of description on bits that can be manipulated, addition of Caution, and addition of Caution in bit description in 9.3.4 (5) Timer 2 time base control register 0 (TCRE0) Modification of description on bits that can be manipulated in 9.3.4 (6) Timer 2 output control register 0 (OCTLE0) Addition of Caution in bit description in 9.3.4 (8) Timer 2 sub-channel 1, 2 capture/compare control register (CMSE120) Addition of Caution in bit description in 9.3.4 (9) Timer 2 sub-channel 3, 4 capture/compare control register (CMSE340) Modification of description on bits that can be manipulated and modification of initial value in 9.3.4 (10) Timer 2 time base status register 0 (TBSTATE0) Modification of description on bits that can be manipulated in 9.3.4 (11) Timer 2 capture/compare 1 to 4 status register 0 (CCSTATE0) Modification of description on bits that can be manipulated in 9.3.4 (12) Timer 2 output delay register 0 (ODELE0) Modification of Caution in 9.4.3 (1) (a) Selection of the external count clock Addition of Caution and modification of bit names in 9.4.4 (2) Timer control register 30 (TMC30) Addition of Caution in 9.4.5 (1) Count operation Applied to: CHAPTER 9 TIMER/COUNTER FUNCTION (REALTIME PULSE UNIT) User's Manual U14492EJ5V0UD 817 APPENDIX D REVISION HISTORY (5/13) Edition 2nd edition Major Revision from Previous Edition Modification of Figure 9-88 Compare Operation Example Addition of Note and deletion of Caution in Figure 9-95 Cycle Measurement Operation Timing Example Modification of Figure 9-97 Example of Timing During TM4 Operation Modification of bit names in 9.5.4 (1) Timer control register 4 (TMC4) Modification of Figure 9-98 TM4 Compare Operation Example Addition of Caution and modification of bit names and bit descriptions in 10.2.3 (1) Asynchronous serial interface mode register 0 (ASIM0) Modification of description on bits that can be manipulated in 10.2.3 (2) Asynchronous serial interface status register 0 (ASIS0) Modification of bit names and addition of Caution in bit description in 10.2.3 (3) Asynchronous serial interface transmission status register 0 (ASIF0) Modification of description on bits that can be manipulated in 10.2.3 (4) Reception buffer register 0 (RXB0) Modification of description on bits that can be manipulated in 10.2.3 (5) Transmission buffer register 0 (TXB0) Addition and modification of description in 10.2.5 (3) Continuous transmission operation Addition of Figure 10-4 Continuous Transmission Processing Flow Addition of Note and modification of description in table in Figure 10-5 Continuous Transmission Starting Procedure Modification of description in table in Figure 10-6 Continuous Transmission End Procedure Addition of Caution in Figure 10-7 Asynchronous Serial Interface Reception Completion Interrupt Timing Modification of description on bits that can be manipulated and addition of Caution in 10.2.6 (2) (a) Clock selection register 0 (CKSR0) Modification of description on bits that can be manipulated in 10.2.6 (2) (b) Baud rate generator control register 0 (BRGC0) Addition of baud rate item in Table 10-3 Baud Rate Generator Setting Data Addition of (2) in 10.2.7 Precautions Modification of bit names in 10.3.3 (1) Asynchronous serial interface mode registers 10, 20 (ASIM10, ASIM20) Modification of bit names in 10.3.3 (3) Asynchronous serial interface status registers 1, 2 (ASIS1, ASIS2) Modification of description on bits that can be manipulated in 10.3.3 (4) 2-frame continuous reception buffer registers 1, 2 (RXB1, RXB2)/reception buffer registers L1, L2 (RXBL1, RXBL2) Addition of Caution in 10.3.4 (1) Reception completion interrupt (INTSRn) Addition of 10.3.5 (3) Continuous transmission of 3 or more frames Modification of bit names in 10.3.7 (2) (b) Prescaler mode registers 1, 2 (PRSM1, PRSM2) CHAPTER 10 SERIAL INTERFACE FUNCTION Applied to: CHAPTER 9 TIMER/COUNTER FUNCTION (REALTIME PULSE UNIT) 818 User's Manual U14492EJ5V0UD APPENDIX D REVISION HISTORY (6/13) Edition 2nd edition Major Revision from Previous Edition Modification of description on bits that can be manipulated in 10.3.7 (2) (c) Prescaler compare registers 1, 2 (PRSCM1, PRSCM2) Addition of 10.3.7 (3) Allowable baud rate range during reception Addition of 10.3.7 (4) Transfer rate in 2-frame continuous reception Modification of bit names in 10.4.3 (1) Clocked serial interface mode registers 0, 1 (CSIM0, CSIM1) Modification of description on bits that can be manipulated in 10.4.3 (4) Clocked serial interface reception buffer registers L0, L1 (SIRBL0, SIRBL1) Modification of description on bits that can be manipulated in 10.4.3 (6) Clocked serial interface read-only reception buffer registers L0, L1 (SIRBEL0, SIRBEL1) Modification of description on bits that can be manipulated in 10.4.3 (8) Clocked serial interface transmission buffer registers L0, L1 (SOTBL0, SOTBL1) Modification of description on bits that can be manipulated in 10.4.3 (10) Clocked serial interface initial transmission buffer registers L0, L1 (SOTBFL0, SOTBFL1) Modification of description on bits that can be manipulated in 10.4.3 (12) Serial I/O shift registers L0, L1 (SIOL0, SIOL1) Modification of description on bits that can be manipulated in 10.4.6 (2) (c) Prescaler compare register 3 (PRSCM3) Modification of Figure 11-1 Block Diagram of FCAN Addition of description in 11.5 Message Processing Modification of description in Table 11-6 Data Length Code Settings Modification of description in 11.8.7 (1) Prescaler Modification of description in 11.8.7 (2) Nominal bit time (8 to 25 time quantum) Addition of Caution and modification of bit description in 11.10 (2) CAN message data length registers 00 to 31 (M_DLC00 to M_DLC31) Deletion of one of Notes for bits, addition of Caution and modification of bit description in 11.10 (3) CAN message control registers 00 to 31 (M_CTRL00 to M_CTRL31) Addition of Caution in bit description in 11.10 (4) CAN message time stamp registers 00 to 31 (M_TIME00 to M_TIME31) Modification of description in 11.10 (6) CAN message ID registers L00 to L31 and H00 to H31 (M_IDL00 to M_IDL31 and M_IDH00 to M_IDH31) Deletion of part of bit description in 11.10 (7) CAN message configuration registers 00 to 31 (M_CONF00 to M_CONF31) Addition of bit description in 11.10 (8) CAN message status registers 00 to 31 (M_STAT00 to M_STAT31) Modification of description on bits that can be manipulated, modification of Caution in bit description, and addition of Note in 11.10 (14) CAN global status register (CGST) Modification of description on bits that can be manipulated in 11.10 (15) CAN global interrupt enable register (CGIE) Modification of Figure 11-25 FCAN Clocks Modification of bit description in 11.10 (18) CAN message search start/result register (CGMSS (during write)/CGMSR (during read)) CHAPTER 11 FCAN CONTROLLER Applied to: CHAPTER 10 SERIAL INTERFACE FUNCTION User's Manual U14492EJ5V0UD 819 APPENDIX D REVISION HISTORY (7/13) Edition 2nd edition Major Revision from Previous Edition Addition of Caution and deletion of part of bit description in 11.10 (19) CAN1 address mask a registers L and H (C1MASKLa and C1MASKHa) Addition of Caution and addition of bit description in 11.10 (20) CAN1 control register (C1CTRL) Modification of description on bits that can be manipulated, addition and deletion of bit description, and deletion of Caution and modification of bit description in 11.10 (21) CAN1 definition register (C1DEF) Modification of description on bits that can be manipulated in 11.10 (24) CAN1 interrupt enable register (C1IE) Modification of bit settings in 11.10 (25) CAN1 bus active register (C1BA) Modification of Caution and bit settings in 11.10 (28) CAN1 synchronization control register (C1SYNC) Modification of Figure 11-28 CAN Global Interrupt Enable Register (CGIE) Settings Modification of Figure 11-35 CAN1 Address Mask a Registers L and H (C1MASKLa and C1MASKHa) (a = 0 to 3) Settings Modification of 11.11.3 Receive setting Modification of Figure 11-44 CAN Stop Mode Settings Modification of Figure 11-45 Clearing of CAN Stop Mode Modification of description in 11.12 Rules for Correct Setting of Baud Rate Modification of description in 11.14.2 Burst read mode Addition of description in 11.15.1 Interrupts that are generated for FCAN controller Modification of description in 11.15.2 Interrupts that are generated for global CAN interface Addition of <2> and <3> in 11.17 Cautions on Use Addition of description in 12.1 (2) Event detection function Modification of Figure 12-1 Image of NBD Space Addition of description in 12.4.1 (1) (b) Read command Addition of Caution in 12.4.2 (2) (b) NBD event address register (EVTU_A) Addition of description for NBDLL, modification of description on bits that can be manipulated, and deletion of part of Remark in 12.5 (1) RAM access data buffer register L (NBDL) Addition of description for NBDHL, modification of description on bits that can be manipulated, and deletion of part of Remark in 12.5 (2) RAM access data buffer register H (NBDH) Addition of description to (1) in 12.6.1 General restrictions Addition of description and Caution to (4) in 12.6.3 Restrictions related to NBD event trigger function Modification of description on bits that can be manipulated, modification of bit names, and addition of bit descriptions in 13.3 (1) A/D scan mode registers 00 and 10 (ADSCM00, ADSCM10) Modification of description on bits that can be manipulated and modification of bit description in 13.3 (2) A/D scan mode registers 01 and 11 (ADSCM01, ADSCM11) CHAPTER 13 A/D CONVERTER CHAPTER 12 NBD FUNCTION (PD70F3116) Applied to: CHAPTER 11 FCAN CONTROLLER 820 User's Manual U14492EJ5V0UD APPENDIX D REVISION HISTORY (8/13) Edition 2nd edition Major Revision from Previous Edition Modification of description on bits that can be manipulated and modification of bit names in 13.3 (3) A/D voltage detection mode registers 0 and 1 (ADETM0, ADETM1) Addition of description in 13.10.4 (1) HALT mode Modification of description in 13.10.4 (2) IDLE mode, software STOP mode Addition of 13.10.6 Timing that makes the A/D conversion result undefined Addition of 13.11 How to Read A/D Converter Characteristics Table Modification of block type and addition of Caution in 14.2 (1) Functions of each port Modification of Figure 14-2 Type B Block Diagram Modification of Figure 14-3 Type C Block Diagram Modification of Figure 14-4 Type D Block Diagram Addition of Figure 14-5 Type E Block Diagram Modification of Figure 14-8 Type H Block Diagram Modification of Figure 14-9 Type J Block Diagram Modification of Figure 14-10 Type M Block Diagram Modification of Figure 14-11 Type N Block Diagram Modification of Figure 14-12 Type O Block Diagram Addition of Figure 14-13 Type P Block Diagram Modification of block type in 14.3.2 (1) Operation in control mode Modification of block type in 14.3.6 (1) Operation in control mode Modification of block type in 14.3.9 (1) Operation in control mode Modification of block type in 14.3.10 (1) Operation in control mode Addition of Caution and addition of Caution in bit description in 14.4.3 (1) Timer 2 input filter mode registers 0 to 5 (FEM0 to FEM5) Addition and modification of description in Table 15-2 Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset Addition of Caution in 16.2 Writing by Flash Programmer Addition of Note in Table 16-1 Connection of V850E/IA1 Flash Programming Adapter (FA-144GJ-8EU) Addition of batch erase command in erase item in Table 16-4 Commands for Controlling Flash Memory Addition of 16.7.3 Outline of self-programming interface Addition of 16.7.5 Software environment Addition of 16.7.6 Self-programming function number Addition of 16.7.7 Calling parameters Addition of 16.7.8 Contents of RAM parameters Addition of 16.7.9 Errors during self-programming Addition of 16.7.10 Flash information Addition of 16.7.11 Area number CHAPTER 15 RESET FUNCTION CHAPTER 16 FLASH MEMORY (PD70F3116) CHAPTER 14 PORT FUNCTIONS Applied to: CHAPTER 13 A/D CONVERTER User's Manual U14492EJ5V0UD 821 APPENDIX D REVISION HISTORY (9/13) Edition 2nd edition Major Revision from Previous Edition Addition of initial value 00H and modification of Caution in 16.7.12 Flash programming mode control register (FLPMC) Addition of 16.7.13 Calling device internal processing Addition of 16.7.14 Erasing flash memory flow Addition of 16.7.15 Continuous writing flow Addition of 16.7.16 Internal verify flow Addition of 16.7.17 Acquiring flash information flow Addition of 16.7.18 Self-programming library Modification of Caution in 16.8 How to Distinguish Flash Memory and Mask ROM Versions Addition of CHAPTER 17 TURNING ON/OFF POWER CHAPTER 17 TURNING ON/OFF POWER Modification of description in B.2 Instruction Set (Alphabetical Order) APPENDIX B INSTRUCTION SET LIST 3rd edition Modification of description in 4.2.1 Pin status during internal ROM, internal RAM, and on-chip peripheral I/O access CHAPTER 4 BUS CONTROL FUNCTION Addition of description to 6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3) Addition of description to 6.3.1 (1) DMA source address registers 0H to 3H (DSA0H to DSA3H) Addition of description to 6.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3) Addition of description to 6.3.2 (1) DMA destination address registers 0H to 3H (DDA0H to DDA3H) Addition of description to 6.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3) Addition of description to 6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) Addition of description to 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) Addition and modification of description in 6.3.6 DMA disable status register (DDIS) Addition of description to 6.3.7 DMA restart register (DRST) Addition of description to 6.3.8 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) Modification of description in Table 6-1 Relationship Between Transfer Type and Transfer Target Modification of description in Remark in 6.7.1 Transfer type and transfer target Modification and addition of description in 6.9 Next Address Setting Function Modification of description in 6.11 Forcible Interruption Modification of description in 6.14 (4) Bus arbitration for CPU Addition of 6.14 (6) Execution of program and DMA transfer in internal RAM CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Applied to: CHAPTER 16 FLASH MEMORY (PD70F3116) 822 User's Manual U14492EJ5V0UD APPENDIX D REVISION HISTORY (10/13) Edition 3rd edition Major Revision from Previous Edition Addition of Caution to 7.3.4 Interrupt control register (xxICn) Applied to: CHAPTER 7 INTERRUPT/ EXCEPTION PROCESSING FUNCTION Addition of Caution to 7.3.6 In-service priority register (ISPR) Modification of description in Remark in 9.1.5 (2) PWM mode 0: Triangular wave modulation (right-left symmetric waveform control) CHAPTER 9 TIMER/COUNTER FUNCTION (REALTIME PULSE UNIT) Addition of Caution to 14.2 (1) Functions of each port Modification of description in Figure 14-14 Example of Noise Elimination Timing Addition of CHAPTER 18 ELECTRICAL SPECIFICATIONS CHAPTER 14 PORT FUNCTIONS CHAPTER 18 ELECTRICAL SPECIFICATIONS Addition of CHAPTER 19 PACKAGE DRAWING CHAPTER 19 PACKAGE DRAWING Addition of CHAPTER 20 RECOMMENDED SOLDERING CONDITIONS CHAPTER 20 RECOMMENDED SOLDERING CONDITIONS Addition of APPENDIX A NOTES ON TARGET SYSTEM DESIGN APPENDIX A NOTES ON TARGET SYSTEM DESIGN Addition of APPENDIX E REVISION HISTORY APPENDIX E REVISION HISTORY 4th edition Addition of Note to Table 1-1 Differences Between V850E/IA1 and V850E/IA2 Addition of Notes 1 and 2 to Table 1-2 Differences Between V850E/IA1 and V850E/IA2 Register Setting Values Addition of Note to 1.4 Ordering Information Addition of Note 3 to 1.5 Pin Configuration (Top View) Addition of Caution to 3.4.5 (3) On-chip peripheral I/O area Addition of Caution to 3.4.9 Programmable peripheral I/O registers and modification of bit units for manipulation and initial values Modification of description in 3.4.11 System wait control register (VSWC) Addition of Note to 4.4 (1) Bus cycle type configuration registers 0, 1 (BCT0, BCT1) CHAPTER 4 BUS CONTROL FUNCTION CHAPTER 3 CPU FUNCTION CHAPTER 1 INTRODUCTION User's Manual U14492EJ5V0UD 823 APPENDIX D REVISION HISTORY (11/13) Edition 4th edition Major Revision from Previous Edition Addition of Caution 2 to 6.3.1 (1) DMA source address registers 0H to 3H (DSA0H to DSA3H) Addition of Caution 2 to 6.3.2 (1) DMA destination address registers 0H to 3H (DDA0H to DDA3H) Addition of Cautions 1 and 2 to 6.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3) Modification and addition of description to Caution in 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) Deletion of Note from Table 6-2 External Bus Cycles During DMA Transfer (Two-Cycle Transfer) Modification of description in 6.9 Next Address Setting Function and addition of Note Addition of Cautions 1 and 2 to 6.10 DMA Transfer Start Factors Addition of 6.13.1 Restrictions related to DMA transfer forcible termination Modification of description in 6.14 Times Related to DMA Transfer Addition of 6.15 (5) Restrictions related to automatic clearing of TCn bit of DCHCn register and (6) Read values of DSAn and DDAn registers Modification of description in CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION CHAPTER 7 INTERRUPT/ EXCEPTION PROCESSING FUNCTION Addition of Caution 2 to 9.1.5 (2) PWM mode 0: Triangular wave modulation (right-left symmetric waveform control) Addition of Notes 1 and 2 to 9.2.4 (1) Timer 1/timer 2 clock selection register (PRM02) Addition of Notes 1 and 2 to 9.3.4 (1) Timer 1/timer 2 clock selection register (PRM02) Addition of Notes 1 and 2 to 9.3.4 (3) Timer 2 count clock/control edge selection register 0 (CSE0) Addition of 9.3.6 PWM output operation when timer 2 operates in compare mode Modification of description in Figure 9-92 TM3 Compare Operation Example (Set/Reset Output Mode) Addition of Caution 2 to 10.2.3 (1) Asynchronous serial interface mode register (ASIM0) Addition of Caution to 10.2.5 (3) Continuous transmission operation Addition of description of transfer rate to 10.3.1 Features Modification of description in Cautions 1 and 2 in 10.3.3 (1) Asynchronous serial interface mode registers 10, 20 (ASIM10, ASIM20) Addition of Caution 3 to 10.3.7 (2) (c) Prescaler compare registers 1, 2 (PRSCM1, PRSCM2) Modification of description in Table 10-8 Baud Rate Generator Setting Data (BRG = fXX/2) CHAPTER 10 SERIAL INTERFACE FUNCTION CHAPTER 9 TIMER/COUNTER FUNCTION (REALTIME PULSE UNIT) Applied to: CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 824 User's Manual U14492EJ5V0UD APPENDIX D REVISION HISTORY (12/13) Edition 4th edition Major Revision from Previous Edition Addition of Caution to Table 11-2 Configuration of Messages and Buffers Addition of description to 11.5 Message Processing Addition of description to Note in Figure 11-21 Nominal Bit Time Modification of description in 11.10 (2) CAN message data length registers 00 to 31 (M_DLC00 to M_DLC31) and addition of Note Modification of description in 11.10 (3) CAN message control registers 00 to 31 (M_CTRL00 to M_CTRL31) and addition of Note Modification of description in 11.10 (8) CAN message status registers 00 to 31 (M_STAT00 to M_STAT31) Modification of description in 11.10 (11) CAN global interrupt pending register (CGINTP) Modification of description in 11.10 (12) CAN1 interrupt pending register (C1INTP) Addition of Caution to 11.10 (13) CAN stop register (CSTOP) Modification of description in 11.10 (14) CAN global status register (CGST) and addition of description to Note and Caution Modification of description in 11.10 (16) CAN main clock selection register (CGCS) and addition of description to Note and Caution Addition of Caution to 11.10 (18) CAN message search start/result register (CGMSS (during write)/CGMSR (during read)) Addition of description to 11.10 (19) CAN1 address mask a registers L and H (C1MASKLa and C1MASKHa) Addition of description to Caution in 11.10 (20) CAN1 control register (C1CTRL) Addition of description to Caution in 11.10 (21) CAN1 definition register (C1DEF) Addition of description to 11.10 (24) CAN1 interrupt enable register (C1IE) Addition of description to 11.10 (28) CAN1 synchronization control register (C1SYNC) and addition of Note Addition of description to Figure 11-27 Initialization Processing Addition of Note to Figure 11-32 CAN1 Synchronization Control Register (C1SYNC) Settings Addition of description to Figure 11-37 Message Buffer Settings Addition of Figure 11-40 CAN Message Status Registers 00 to 31 (M_STAT00 to M_STAT31) Settings Modification of description in Figure 11-42 Setting of Receive Completion Interrupt and Reception Operation Using Reception Polling Addition of Figure 11-43 CAN Message Search Start/Result Register (CGMSS/CGMSR) Settings Addition of description to Figure 11-47 CAN Stop Mode Settings Addition of description to Figure 11-48 Clearing of CAN Stop Mode Modification of description in 11.12 Rules for Correct Setting of Baud Rate Modification of description in Figure 11-50 Sequential Data Read Addition of description to Caution in 11.13.2 Burst read mode Applied to: CHAPTER 11 FCAN CONTROLLER User's Manual U14492EJ5V0UD 825 APPENDIX D REVISION HISTORY (13/13) Edition 4th edition Major Revision from Previous Edition Addition of description to 11.16 Cautions on Use Applied to: CHAPTER 11 FCAN CONTROLLER Addition of 14.4 Operation of Port Function CHAPTER 14 PORT FUNCTIONS Addition of Caution to 18.1 (4) (c) Read cycle (CLKOUT synchronous/asynchronous, 1 wait) Addition of Caution to 18.1 (4) (d) Write cycle (CLKOUT synchronous/asynchronous, 1 wait) Addition of Caution to 18.1 (4) (e) Bus hold Addition of Notes 1 and 2 to 18.1 (7) Timer operating frequency Modification of description of VPP supply voltage (VPPL) in Basic Characteristics in 18.2 Flash Memory Programming Mode (PD70F3116 only) Addition of APPENDIX A NOTES Addition of Note 22 to MUL, MULU in APPENDIX D D.2 Instruction Set (Alphabetical Order) APPENDIX A NOTES APPENDIX D INSTRUCTION SET LIST Modification of description in APPENDIX E REVISION HISTORY APPENDIX E REVISION HISTORY CHAPTER 18 ELECTRICAL SPECIFICATIONS 826 User's Manual U14492EJ5V0UD |
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