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ICS650-41
Spread Spectrum Clock Synthesizer
Description
The ICS650-41 is a spread spectrum clock synthesizer intended for video projector applications. It generates an EMI optimized 50 MHz clock signal (EMI peak reduction of 7 to 14 dB on 3rd through 19th harmonics) through the use of Spread Spectrum techniques from a 25 MHz crystal or clock input. For the 50 MHz output, the modulation rate is 50 kHz. In addition to the EMI optimized clock signal, the device generates a 48 MHz clock for USB.
Features
* * * * * * *
Packaged in 16-pin TSSOP (173 mil) Supply voltages: VDD = 3.3 V, VDDO = 2.5 V Peak-to-peak jitter: 125 ps typ Output duty cycle 45/55% (worst case) Guarantees +85C operational condition 25 MHz crystal or reference clock input Zero (0) ppm frequency error on all output clocks
* Advanced, low-power CMOS process * Industrial temperature range
Block Diagram
VDD 25 MHz crystal or clock input X1/CLKIN Crystal OSC X2
External capacitors are required with a crystal input.
VDDO
3 PLL1 with Spread Spectrum
50M
FS3:0 SS_EN
Control Logic
PLL2
48M
GND
2 PDTS
MDS 650-41 F Integrated Circuit Systems, Inc.
1
525 Race Street, San Jose, CA 95126
Revision 082305 tel (408) 297-1201
www.icst.com
ICS650-41 Spread Spectrum Clock Synthesizer
Pin Assignment
X1/CLKIN FS0 FS1 SS_EN VDD GND FS3 48M 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X2 VDD PDTS FS2 VDD GND VDDO 50M
Spread Spectrum and Output Configuration Table
FS3 FS2 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Spread Type Center Center Center Center Center Center Center Center Down Down Down Down Down Down Down Down SS Out 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 -0.5 -0.75 -1.0 -1.25 -1.5 -1.75 -2.0 -2.25
16-pin (173 mil) TSSOP
MDS 650-41 F Integrated Circuit Systems, Inc.
2
525 Race Street, San Jose, CA 95126
Revision 082305 tel (408) 297-1201
www.icst.com
ICS650-41 Spread Spectrum Clock Synthesizer
Pin Descriptions
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name X1/CLKIN FS0 FS1 SS_EN VDD GND FS3 48M 50M VDDO GND VDD FS2 PDTS VDD X2 Pin Type Input Input Input Input Power Power Input Output Output Power Power Power Input Input Power Output Pin Description Crystal input. Connect this pin to a 25 MHz crystal or external input clock. Select pin 0. Internal pull-up resistor. See table on page 2. Select pin 1. Internal pull-up resistor. See table on page 2. Spread spectrum enable pin. Internal pull-up resistor. Enabled = high. Connect to +3.3 V. Connect to ground. Select pin 3. Internal pull-up resistor. See table on page 2. Fixed 48 MHz output. Weak internal pull-down when tri-state. Spread Spectrum output. Weak internal pull-down when tri-stated. Connect to +2.5 V. Connect to ground. Connect to +3.3 V. Select pin 2. Internal pull-up resistor. See table on page 2. Powers down entire chip. Tri-states CLK outputs when low. Internal pull-up. Connect to +3.3 V. Crystal Output. Connect this pin to a 25 MHz crystal. Do not connect if clock input is used.
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the ICS650-41 must be isolated from system power supply noise to perform optimally. A decoupling capacitor of 0.01F must be connected between each VDD and the PCB ground plane.
Crystal Load Capacitors
The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors must be connected from each of the pins X1 and X2 to ground. The value (in pF) of these crystal caps should equal (CL -6 pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 16 pF load capacitance, each crystal capacitor would be 20 pF [(16-6) x 2] = 20.
Series Termination Resistor
Clock output traces over one inch should use series termination. To series terminate a 50 trace (a commonly used trace impedance), place a 33 resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20.
MDS 650-41 F Integrated Circuit Systems, Inc.
3
525 Race Street, San Jose, CA 95126
Revision 082305 tel (408) 297-1201
www.icst.com
ICS650-41 Spread Spectrum Clock Synthesizer
PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) The 0.01F decoupling capacitors should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to VDD pins should be kept as short as possible, as should the PCB trace to the ground via. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) To minimize EMI, the 33 series termination resistor (if needed) should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS650-41. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
MDS 650-41 F Integrated Circuit Systems, Inc.
4
525 Race Street, San Jose, CA 95126
Revision 082305 tel (408) 297-1201
www.icst.com
ICS650-41 Spread Spectrum Clock Synthesizer
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-41. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD All Inputs and Outputs Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature (max. of 10 seconds) 7V
Rating
-0.5 V to VDD+0.5 V 0 to +85C -65 to +150C 125C 260C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Power Supply Voltage (VDDO) Power Supply Ramp Time, Figure 4
Min.
0 +3.135 +2.375
Typ.
- +3.3 +2.5
Max.
+85 +3.465 +2.625 4
Units
C V V ms
MDS 650-41 F Integrated Circuit Systems, Inc.
5
525 Race Street, San Jose, CA 95126
Revision 082305 tel (408) 297-1201
www.icst.com
ICS650-41 Spread Spectrum Clock Synthesizer
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, VDDO = 2.5 V 5% , Ambient Temperature 0 to +85C
Parameter
Symbol
IDD
Conditions
no load PDTS = 0, no load no load
Min.
Typ.
27 40 4 1
Max.
Units
mA uA mA uA V
Operating Supply Current IDDO Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Short Circuit Current Nominal Output Impedance Internal Pull-up Resistor Input Leakage Current Internal Pull-down Resistor Input Capacitance VIH VIL VIH VIL VOH VOL IOS ZO RPU II RPD CIN
PDTS = 0, no load FS3:0, PDTS, SS_EN FS3:0, PDTS, SS_EN X1/CLKIN X1/CLKIN IOH = -4 mA IOL = 4 mA 1.8 0.7 x VDD 2
0.8
V V
0.3 x VDD 0.6 50 20
V V V mA k uA k pF
FS3:0, PDTS, SS_EN FS3:0, PDTS, SS_EN, VIN=VDD CLK outputs Inputs
360 1 900 4
MDS 650-41 F Integrated Circuit Systems, Inc.
6
525 Race Street, San Jose, CA 95126
Revision 082305 tel (408) 297-1201
www.icst.com
ICS650-41 Spread Spectrum Clock Synthesizer
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, VDDO = 2.5 V 5%, Ambient Temperature 0 to +85 C
Parameter
Input Frequency Spread Spectrum Modulation Frequency Duty Cycle Output Fall Time Output Rise Time One Sigma Clock Period Jitter Absolute Jitter, Peak-to-Peak
Symbol
FIN
Conditions
Crystal or clock input
Min.
Typ.
25 50
Max. Units
MHz kHz 55 % ns ns ps ps
t2/t1 t3 t4
at VDD/2, Note 1 and Figures 1 and 2 80% to 20%, Note 1 and Figures 1 & 3 20% to 80%, Note 1 and Figures 1 & 3 Note 1 Deviation from mean, SS_EN=0, Note1 & Figures 1 and 6 PDTS high to PLL locked to within 1% of final value, Figure 5 PDTS low to tri-state, Figure 5 PLL lock-time from power-up to 1% of final value, Figure 4
45
50 1.5 1.5 30 125
tja
Output Enable Time
tEN
2.5
5
ms
Output Disable Time
tDIS tP
20 6 10
ns ms
Power-up Time Note 1: Measured with 15 pF load.
MDS 650-41 F Integrated Circuit Systems, Inc.
7
525 Race Street, San Jose, CA 95126
Revision 082305 tel (408) 297-1201
www.icst.com
ICS650-41 Spread Spectrum Clock Synthesizer
Timing Diagrams
VDDs 0.01F DUT GND C LOAD
Outputs
t2
t1 VDDO 50% of VD D O C lo c k 0V
Figure 1: Test and Measurement Setup Figure 2: Duty Cycle Definitions
t3
t4
Power Up Tim e
VCO Ram p Tim e
PLL Locked
VDDO 80% of VDDO
VDD
0V
Clock Output
20% of VDDO 0V
VDD
0V
Figure 3: Rise and Fall Time Definitions
0 ms
4 ms
10 m s
Figure 4: Power Up and PLL Lock Timing
PDTS
1.25 V 1% t EN t D IS
1 .2 5 V
C LK O utputs
VOH
Mean value
0V
Absolute jitter (p - p)
tJA
Figure 5: PDTS to Stable Clock Output Timing
Figure 6: Short Term Jitter Definition
MDS 650-41 F Integrated Circuit Systems, Inc.
8
525 Race Street, San Jose, CA 95126
Revision 082305 tel (408) 297-1201
www.icst.com
ICS650-41 Spread Spectrum Clock Synthesizer
Thermal Characteristics
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
78 70 68 37
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
Marking Diagram
16 9
650GI41L ###### YYWW
1 8
Notes: 1. ###### is the lot number. 2. YYWW is the last two digits of the year and the week number that the part was assembled.
MDS 650-41 F Integrated Circuit Systems, Inc.
9
525 Race Street, San Jose, CA 95126
Revision 082305 tel (408) 297-1201
www.icst.com
ICS650-41 Spread Spectrum Clock Synthesizer
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
16
Millimeters Symbol Min Max
Inches Min Max
E1 INDEX AREA
E
12 D
A A1 A2 b C D E E1 e L aaa
-1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0 8 -0.10
-0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0 8 -0.004
A2 A1
A
c
-Ce
b SEATING PLANE L
aaa C
Ordering Information
Part / Order Number
ICS650GI-41LF ICS650GI-41LFT
Marking
650GI41L 650GI41L
Shipping Packaging
Tubes Tape and Reel
Package
16-pin TSSOP 16-pin TSSOP
Temperature
0 to +85 C 0 to +85 C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 650-41 F Integrated Circuit Systems, Inc.
10
525 Race Street, San Jose, CA 95126
Revision 082305 tel (408) 297-1201
www.icst.com
ICS650-41 Spread Spectrum Clock Synthesizer
Revision History
Rev.
B
Originator
P.Griffith
Date
10/07/04
Description of Change
Changed the input frequency from 14.31818 to 25 MHz; changed Short Circuit Current from 70 to 50; added separate Pull-up resistor spec for SS_EN; added "I" to part ordering number Changed AC and DC parameters to reflect measured char values: IDD, IDDO, VIH, VIL, RPU, II, RPD, t1,.t2, t3, t4, tja, tEN, tDIS, tP. Added Figures for key parameters. Changed jitter spec to +/-150 ps and duty cycle to 45% min, 55% max. Renamed pin 1 to X1/CLKin on page2, improved jitter spec to +/-125 ps on front page and in electrical tables, changed rise and fall time to 1.5 ns typical to reflect balanced drive, changed typical ID spec to 4 ma, updated graphs on page 8 to reflect separate VDDO and correct bypass capacitor value, updated marking diagram and ordering table to reflect Pb-free device.
C D E
P. Griffith P. Griffith P. Griffith
11/15/04 12/06/04 1/17/05
MDS 650-41 F Integrated Circuit Systems, Inc.
11
525 Race Street, San Jose, CA 95126
Revision 082305 tel (408) 297-1201
www.icst.com

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