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ISL88016, ISL88017
Data Sheet December 22, 2006 FN6141.0
6-Pin Voltage Supervisors with PinSelectable Voltage Trip Points
The ISL88016, ISL88017 supervisors offer pin-selectable voltage trip points along with popular functions such as Power-on Reset control, Supply Voltage Supervision, and Manual Reset assertion in a small 6 Ld TSOT-23 package. By connecting the three VSET pins to VDD, GND or floating, users can program the voltage trip point from 1.60V to 2.85V in 50mV increments on the ISL88016 and from 2.15V to 4.65V in 100mV increments on the ISL88017. These userselectable reset threshold voltages are accurate to 2% over temperature and the reset signal is valid down to 1V. Intersil's proprietary TwinPinTM combines the active low reset out with the manual reset input into one pin. This provides device adjustability without sacrificing functionality. These parts are specifically designed for low power consumption and high threshold accuracy.
Features
* Pin-Selectable Single Voltage Monitoring Supervisors * User Pin-Selectable Voltage Trip Points - ISL88016: 1.60V to 2.85V in 50mV Steps - ISL88017: 2.15V to 4.65V in 100mV Steps * Reduce Inventory on Fixed Voltage Trip Point Options * Manual Reset Capability * Proprietary TwinPinTM Combines Active-Low Reset Output and Manual Reset Input Functions into One Pin * Reset Signal Valid Down to VDD = 0.8V * Voltage Threshold 2% Accuracy Over Temp * No External Components Necessary * Immune to Power-Supply Transients * Ultra Low 3A Supply Current * Small 6 Ld TSOT-23 Pb-Free Plus Anneal Available (RoHS Compliant)
Pinout
ISL88016, ISL88017 (6 LD TSOT-23) TOP VIEW
Applications
* Process Control Systems * Intelligent Instruments * Embedded Control Systems
VDD
1
6
RST/MR
GND
2
ISL88016 ISL88017
5
VSET3
* Computer Systems * Portable/Battery-Powered Equipment
VSET1
3
4
VSET2
* PDA and Hand-Held PC Devices
Ordering Information
PART NUMBER (Note) ISL88016IHTZ-T ISL88017IHTZ-T ISL88016IHTZ-TK ISL88017IHTZ-TK PART TAPE & MARKING REEL 016Z 017Z 016Z 017Z PACKAGE (Pb-Free) PKG. DWG. #
3k pcs 6 Ld TSOT-23 MDP0049 Tape & Reel 3k pcs 6 Ld TSOT-23 MDP0049 Tape & Reel 1k pcs 6 Ld TSOT-23 MDP0049 Tape & Reel 1k pcs 6 Ld TSOT-23 MDP0049 Tape & Reel
ISL88016/17EVAL1Z Evaluation Platform NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL88016, ISL88017 Functional Block Diagrams
VDD RST/MR VOLTAGE SETTING POR VREF VDD PB
VSET1 VSET2 VSET3
GND
ISL88016 ISL88017
Product Features Table
FUNCTION Active-Low Reset (RST) Manual Reset Input (MR) 1.60V to 2.85V (50mV Increments) Pin-Selectable Voltage Trip Range 2.15V to 4.65V (100mV Increments) Pin-Selectable Voltage Trip Range Pb-Free Package Option Available x ISL88016 x x x x x ISL88017 x x
Pin Descriptions
PIN 1 NAME VDD FUNCTION Supply Voltage and Monitored Input. The VDD pin is the IC power supply terminal and also the monitored input. The voltage at this pin is compared against the programmed voltage trip point, VTP. A reset is first asserted when the device is initially powered up to ensure that the power supply has stabilized. Thereafter, reset is again asserted whenever VDD falls below VTH. The device is designed with hysteresis to help prevent chattering due to noise and is immune to brief power-supply transients. Ground. Voltage Trip Point Select Pins 1, 2 and 3. These inputs are either tied either to GND or VDD or left floating in various combinations to program the falling voltage trip point. See Voltage Trip Point Setting Table on following page for programming configurations.
2 3 4 5 6
GND VSET1 VSET2 VSET3 RST/MR
Proprietary TwinPinTM technology combines Active-Low Reset Output and Manual Reset Input Functions into one pin. This dual function pin functions as both the reset output and a manual reset input. The RST output pin has an integrated 100k pull-up resistor to VDD that is pulled to GND (LOW) when reset is asserted, VDD < programmed voltage trip point. The MR input is an active-low debounced input to which a user can connect a push-button to add manual reset capability.
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FN6141.0 December 22, 2006
ISL88016, ISL88017 Power-On Reset Voltage Setting
VTH ISL88016 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 2.60 2.65 2.70 2.75 2.80 2.85 Reserved ISL88017 2.15 2.25 2.35 2.45 2.55 2.65 2.75 2.85 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 3.75 3.85 3.95 4.05 4.15 4.25 4.35 4.45 4.55 4.65 Reserved VSET1 GND FLOAT VDD GND FLOAT VDD GND FLOAT VDD GND FLOAT VDD GND FLOAT VDD GND FLOAT VDD GND FLOAT VDD GND FLOAT VDD GND FLOAT VDD VSET2 GND GND GND FLOAT FLOAT FLOAT VDD VDD VDD GND GND GND FLOAT FLOAT FLOAT VDD VDD VDD GND GND GND FLOAT FLOAT FLOAT VDD VDD VDD VSET3 GND GND GND GND GND GND GND GND GND FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT VDD VDD VDD VDD VDD VDD VDD VDD VDD
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FN6141.0 December 22, 2006
ISL88016, ISL88017
Absolute Maximum Ratings
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-40C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on Any Pin with Respect to GND . . . . . . . . . . . -1.0V to +7V D.C. Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . +300C
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Absolute Maximum Ratings indicate limits beyond which permanent damage to the device and impaired reliability may occur. These are stress ratings provided for information only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. For guaranteed specifications and test conditions, see Electrical Specifications. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Electrical Specifications
SYMBOL BIAS VDD IDD
Over the recommended operating conditions unless otherwise specified. TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER
Supply Voltage Range ISL88016 Supply Current VDD > VTH VDD = 5.0V VDD = 3.3V VDD = 2.5V VDD = 1.8V ISL88017 Supply Current VDD > VTH VDD = 5.0V VDD = 3.3V VDD = 2.5V VDD = 2.25V
1.6 4.3 3.1 3.1 2.5 4.0 3.2 3.2 3.0
5.5 6 4.9 4.5 4.4 8.5 8.5 6.5 5.4
V A A A A A A A A
VOLTAGE THRESHOLD VTH VTHHYST RESET VOL ISL88016 Reset Output Voltage Low ISL88017 Reset Output Voltage Low VOH tPOR tRST CLOAD Reset Output Voltage High POR Time-Out Delay VTH Low to Reset Asserted Delay Load Capacitance on Reset Pin VDD Open VDD < VTH, Sinking 0.225mA VDD < VTH, Sinking 0.225mA VDD > VTH 140 0.20 0.20 VDD 200 0.01 5 280 0.5 0.5 V V V ms s pF VDD Voltage Trip Point Hysteresis at VTH Input Temperature = +25C See Power-On Reset Voltage Setting Table on page 3 -2 1 +2 % %
MANUAL RESET VMR tMR RPU VSET IVSET VVSET VIL VIH VSET Current VSET Open Pin Voltage VSET Input Voltage Low VSET Input Voltage High 0.9 x VDD VSET = Open 0.5VDD 0.1VDD 1 A V V V MR Input Voltage MR Minimum Pulse Width Integrated RST/MR Pull-Up Resistor 10 100 100 mV s k
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FN6141.0 December 22, 2006
ISL88016, ISL88017
VTH / VPOR VDD 1V tPOR tRST tPOR tPOR
RST
MR
>tMR
FIGURE 1. VOLTAGE MONITORING TIMING DIAGRAM
Principles of Operation
The ISL88016 and ISL88017 devices provides a low cost solution for those voltage monitoring applications needing supply voltage supervision with power reset control, and manual reset assertion. By integrating these common features along with three pins of Vth programming into a small 6 Ld TSOT-23 package and using only 1A of supply current, the ISL88016 and ISL88017 devices can lower system cost, reduce board space requirements, and increase the reliability of a system while reducing inventory overhead costs.
RST/MR GND ISL88016 ISL88017 VDD VSET3
VSET1
VSET2
FIGURE 2. SETTING VPOR USING VSET INPUTS
Power-On Reset (POR)
Applying power to the ISL88016 and ISL88017 activates a POR circuit which asserts reset once VDD = 1 V. (i.e., RST goes LOW). This provides several benefits: * It prevents the system microprocessor from starting to operate with insufficient voltage. * It prevents the processor from operating prior to stabilization of the oscillator. * It ensures that the monitored device is held out of operation until internal registers are properly loaded. * It allows time for an FPGA to download its configuration prior to initialization of the circuit. The reset signal remains asserted until VDD rises above the minimum voltage sense level for time period tPOR. This ensures that the VDD voltage has stabilized. Optional VDD de-coupling capacitance can be added to filter transients if needed.
Low Voltage Monitoring
During normal operation, the ISL88016 and ISL88017 monitor the voltage level of VDD. The device asserts a reset (RST = LOW) if this voltage is less than the programmed voltage trip point. The reset signal prevents system operation during a power failure or brownout condition. This reset signal remains asserted until VDD exceeds the voltage threshold setting for the reset time delay period tPOR. (See Figure 1). The ISL88016 and ISL88017 allow users to customize the Power-On Reset voltage threshold level, which is the voltage at which the reset is deasserted. The three VSET inputs are either tied to VDD, GND or left open to program VTH. See the Power-On Reset Voltage Setting table on page 3 for specific voltage configuration. Also see Figure 2 for a schematic representation of the VSET pins being programmed, noting the minimum necessary components for IC operation. Do not attempt to reprogram a VTH while the IC is biased.
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FN6141.0 December 22, 2006
ISL88016, ISL88017
Manual Reset
The manual reset input (MR) allows the user to trigger a reset by using a push-button switch. The MR input is an active low debounced input. By connecting a push-button directly from MR to ground, the designer adds manual system reset capability (see Figure 3). Reset is asserted if the MR pin is pulled low to less than 100mV for 10s or longer while the push-button is closed. After MR is released, the reset outputs remain asserted for tPOR (200ms) and then released.
ISL88016 ISL88017
FIGURE 5. ISL88016/17EVAL1Z PHOTOGRAPH
RST/MR
0.1
TARGET 0%
PB
-0.1 VDD VTH (%) -0.3 -0.5 -0.7 -0.9
88017_3.55V 88017_4.55V 88016_2.80V
FIGURE 3. CONNECTING A MANUAL RESET PUSH-BUTTON
88016_2.25V
Using the ISL88016/17EVAL1Z Platform
The ISL88016/17EVAL1Z platform is provided with both an ISL88016 in the top and an ISL88017 in the bottom positions. Each IC is default programmed to VSET1, VSET2 and VSET3 = FLOAT but provided with jumpers to change the Vth level by individually connecting the three VSET pins to either VDD (1) or GND (0). To the left of the circuits is a VSET programming table for easy reference. Provide adequate bias to VDD to deassert RESET signal. See Figure 4 for the ISL88016/17EVAL1Z schematic and Figure 5 for its photograph.
88017_2.25V
-1.1 -1.3 -40 -30 -20 -10 0 10 25 35 45
88016_1.75V
55
65
75
85
(C) TEMPERATURE (oC)
FIGURE 6. SAMPLED VTH% TO TARGET OVER TEMP
6.00 BIAS CURRENT (uA) 5.00 4.00
VDD = 2.5V
VDD = 5V
3.00 2.00 1.00 0.00 -40 -30 -20 -10 0 10 25 35
o
VDD = 1.8V
VDD = 3.3V
45
55
65
75
85
TEMPERATURE ( C)
FIGURE 7. IDD OVER TEMP
204 203 202 201 200 199 198 197 196 195 194 193 -40
VDD = 5V
tPOR (ms)
VDD = 3.3V
FIGURE 4. ISL88016/17EVAL1Z SCHEMATIC
-30
-20
-10
0
10
25
35
45
55
65
75
85
T EM P ERAT URE (o C)
FIGURE 8. tPOR OVER TEMP
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FN6141.0 December 22, 2006
ISL88016, ISL88017 TSOT Package Family
e1 A N 6 4
MDP0049
D
TSOT PACKAGE FAMILY SYMBOL A A1 A2 TSOT5 1.00 0.05 0.87 0.38 0.127 2.90 2.80 1.60 0.95 1.90 0.40 0.60 0.20 5 TSOT6 1.00 0.05 0.87 0.38 0.127 2.90 2.80 1.60 0.95 1.90 0.40 0.60 0.20 6 TSOT8 1.00 0.05 0.87 0.29 0.127 2.90 2.80 1.60 0.65 1.95 0.40 0.60 0.13 8 TOLERANCE Max 0.05 0.03 0.07 +0.07/-0.007 Basic Basic Basic Basic Basic 0.10 Reference Reference Rev. A 12/02 NOTES:
E1 2 3
E
b c D
0.15 C D 2X 5 e B b NX ddd M 1 2 (N/2) 0.25 C 2X N/2 TIPS C A-B D
E E1 e e1 L L1 ddd N
0.15 C A-B 2X C D
1
3
A2 SEATING PLANE 0.10 C NX A1
1. Plastic or metal protrusions of 0.15mm maximum per side are not included. 2. Plastic interlead protrusions of 0.15mm maximum per side are not included. 3. This dimension is measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (TSOT6 AND TSOT8 only).
(L1)
H
6. TSOT5 version has no center lead (shown as a dashed line).
A
GAUGE PLANE c L 4 4
0.25
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 7
FN6141.0 December 22, 2006

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