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HANBit
HSD8M32B4
Synchronous DRAM Module 32Mbyte ( 8M x 32-Bit ) 144pin SO-DIMM based on 4Mx16, 4Banks, 4K Ref., 3.3V Part No. HSD8M32B4 GENERAL DESCRIPTION
The HSD8M32B4 is a 8M x 32 bit Synchronous Dynamic RAM high density memory module. The module consists of four CMOS 1M x 16 bit x 4banks Synchronous DRAMs in TSOP-II packages mounted on a 144-pin, FR-4-printed circuit board. Two 0.01uF decoupling capacitor is mounted on the printed circuit board in parallel for each SDRAM. The HSD8M32B4 is a SO-DIMM designed. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
* Part Identification HSD8M32B4-10 : 100MHz ( CL=2) HSD8M32B4-10L : 100MHz ( CL=3) HSD8M32B4-12 : 125MHz ( CL=3) HSD8M32B4-13 :133MHz ( CL=3)
* Burst mode operation * Auto & self refresh capability (4096 Cycles/64ms) * LVTTL compatible inputs and outputs * Single 3.3V 0.3V power supply * MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * FR4-PCB design * The used device is K4S641632D-TC
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PIN ASSIGNMENT
PIN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 Front Vss DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ4 DQ6 DQ7 Vss DQM0 DQM1 VCC A0 A1 A2 Vss DQ8 DQ9 DQ10 DQ11 VCC DQ12 PIN 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 Back Vss NC NC NC NC VCC NC NC NC NC Vss NC NC VCC A3 A4 A5 Vss NC NC NC NC VCC NC PIN 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 Frontl DQ13 DQ14 DQ15 Vss NC NC CLK0 VCC /RAS /WE /CS0 /CS1 DU Vss NC NC VCC DQ16 DQ17 DQ18 DQ19 Vss DQ20 DQ21 PIN 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 Back NC NC NC Vss NC NC CKE0 VCC /CAS NC NC NC CLK1 Vss NC NC VCC NC NC NC NC Vss NC NC PIN 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 Front DQ22 DQ23 VCC A6 A8 Vss A9 A10 VCC DQM2 DQM3 Vss DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 Vss SDA VCC
HSD8M32B4
PIN 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
Back NC NC VCC A7 BA0 Vss BA1 A11 VCC NC NC Vss NC NC NC NC VCC NC NC NC NC Vss SCL VCC
*Pin Names
Pin Name A0 ~ A11 DQ0 ~ DQ31 CKE0 /RAS /WE Vcc SDA DU Function Address input (Multiplexed) Data input/output Clock enable input Row address strobe Write enable Power supply (3.3V) Serial data I/O Do t use Pin Name BA0 ~ BA1 CLK0,CLK1 /CS0, /CS1 CAS DQM0 ~ 3 Vss SCL NC Function Select bank Clock input Chip select input Column address strobe DQM Ground Serial clock No connection
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FUNCTIONAL BLOCK DIAGRAM
DQ0-31
HSD8M32B4
CKE CKE0 CAS /CAS RAS /RAS /CE0 CE WE A0-A11
CLK
U1
DQ0-15 LDQM UDQM BA0-1
CLK
DQM0 DQM1
CKE CAS RAS CE WE A0-A11
CLK
U3
DQ16-31 LDQM UDQM BA0-1 DQM2 DQM3
CKE CAS RAS CE /CE1 WE A0-A11
CLK
U2
DQ8-15 LDQM DQM0 UDQM BA0-1 DQM1
CKE CAS RAS CE WE A0-A11
CLK
U4
DQ16-31 LDQM UDQM BA0-1 DQM2 DQM3
/WE A0 - A11 BA0-1
Vcc Vss
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Two 0.01uF Capacitor per each SDRAM
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PIN FUNCTION DESCRIPTION
Pin CLK /CE Name System clock Chip enable Input Function Active on the positive going edge to sample all inputs.
HSD8M32B4
Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command.
A0 ~ A11
Address
Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8
BA0 ~ BA1
Bank select address
Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time.
/RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge.
/CAS
Column strobe
address
Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active.
/WE
Write enable
DQM0 ~ 3
Data mask
input/output
Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic.
DQ0 ~ 31 VDD/VSS
Data input/output Power supply/ground
ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN ,OUT Vcc PD TSTG RATING -1V to 4.6V -1V to 4.6V 4W -55oC to 150oC
Short Circuit Output Current IOS 50mA Notes : Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) ) PARAMETER Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage SYMBOL Vcc VIH VIL VOH VOL MIN 3.0 2.0 -0.3 2.4 TYP. 3.3 3.0 0 MAX 3.6 Vcc+0.3 0.8 0.4
HSD8M32B4
UNIT V V V V V
NOTE
1 2 IOH = -2mA IOL = 2mA 3
Input leakage current I LI -10 10 uA Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VCC = 3.3V, TA = 23C, f = 1MHz, VREF =1.4V 200 mV) DESCRIPTION Address(A0~A11, BA0~BA1) /RAS, /CAS, /WE CKE(CKE0) Clock (CLK0) /CE (/CE1) DQM (DQM0 ~ DQM3) DQ (DQ0 ~ DQ31) Notes : 1. -13 only specify a maximum value of 3.5pF 2. -13 only specify a maximum value of 3.8pF SYMBOL CADD C IN CCKE CCLK CCS CDQM COUT MIN 10 10 10 10 10 10 16 MAX 20 20 20 16 20 20 26 UNIT pF pF pF pF pF pF pF NOTE 2 2 2 1 2 2 3
3. - 13 only specify a maximum value of 6.0pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) TEST PARAMETER SYMBOL CONDITION Burst length = 1 Operating current (One bank active) ICC1 tRC tRC(min) IO = 0mA ICC2P CKE VIL(max) tCC=10ns CKE & CLK VIL(max) tCC= 4 mA
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VERSION UNIT -13 -12 -10 -10L NOTE
440
440
400
400
mA
1
4
mA
Precharge standby current in power-down mode
ICC2PS
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CKE VIH(min) ICC2N Precharge standby current in one time during 20ns non power-down mode ICC2NS CKE VIH(min) CLK VIL(max), tCC= 24 CS* VIH(min), tCC=10ns 60
HSD8M32B4
Input signals are changed mA
Input signals are stable Active standby current in ICC3P ICC3PS CKE VIL(max), tCC=10ns CKE&CLK VIL(max) tCC= CKEVIH(min), ICC3N CS*VIH(min), tCC=10ns 100 mA 12 mA 12
power-down mode
Active standby current in non power-down mode (One bank active)
Input signals are changed one time during 20ns CKEVIH(min)
ICC3NS
CLK VIL(max),
tCC=
60
Input signals are stable IO = 0 mA Operating current (Burst mode) ICC4 Page burst 540 4Banks Activated tCCD = 2CLKs Refresh current Self refresh current ICC5 ICC6 tRC tRC(min) CKE 0.2V 540 520 4 1.6 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). 500 500 mA mA mA 2 G F 520 500 500 mA 1
AC OPERATING TEST CONDITIONS
(vcc = 3.3V 0.3V, TA = 0 to 70C) PARAMETER AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2 UNIT V V ns V
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HSD8M32B4
+3.3V Vtt=1.4V 1200 DOUT 870 50pF*
DOUT
50 Z0=50 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) VERSION PARAMETER Row active to row active delay RAS to CAS delay Row precharge time Row active time SYMBOL -13 tRRD(min) tRP(min) tRP(min) tRAS(min) tRAS(max)
tRC(min)
UNIT -12 16 20 20 48 100 65 68 2 2 CLK + 20 ns 1 1 1 2 ea CLK CLK CLK 70 70 -10 20 20 20 50 -10L 20 20 20 50 ns ns ns ns ns ns CLK 15 20 20 45
NOTE 1 1 1 1
Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data
1 2.5
tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 -
2 2 3 4
1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop.
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AC CHARACTERISTICS
(AC operating conditions unless otherwise noted) -A PARAMETER CLK cycle time CAS 7.5 latency=3 tCC CAS latency=2 CLK to valid output delay CAS 5.4 latency=3 tSAC CAS latency=2 Output data hold time CAS 2.7 latency=3 tOH CAS latency=2 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS 5.4 latency=3 tSHZ CAS latency=2 6 6 6 tCH tCL tSS tSH tSLZ 2.5 2.5 1.5 0.8 1 3 3 2 1 1 3 3 2 1 1 3 3 2 1 1 3 3 3 3 3 6 6 6 10 12 1000 1000 1000 8 10 10 SYMBOL MIN MAX MIN MAX MIN MAX MIN -8 -H
HSD8M32B4
-L UNIT MAX NOTE
1000
ns
1
6 ns 7 1,2
ns
2
ns ns ns ns ns 6 ns
3 3 3 3 3 2
7
ns
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to the parameter.
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SIMPLIFIED TRUTH TABLE
CKE n-1 H H L H CKE n X H L H X /C S L L L H L /R A S L L H X L /C A S L L H X H /W E L H H X H D Q M X X X X V BA 0,1
HSD8M32B4
COMMAND Register Mode register set Auto refresh Refresh Self refresh Entry Exit
A10/ AP OP code X X
A11 A9~A0
NOTE 1,2 3 3 3 3
Bank active & row addr. Read & column address Auto disable Auto disable Auto disable Auto disable Burst Stop Precharge Bank selection All banks Entry Exit Entry Exit precharge precharge precharge precharge
Row address L Column Address H (A0 ~ A9) Column L Address (A0 ~ A9) H 4,5 X 6 X 4 4,5 4
H
X
L
H
L
H
X
V
Write & column address
H
X
L
H
L
L
X
V
H H H L H L H H
X X L H L H
L L H L X H L H L H L
L L X V X X H X V X X H
H H X V X X H X V X H
L L X V X X H X V X H
X X X X X V X L H
Clock suspend or active power down
X
Precharge down mode DQM
power
X X V X X X 7
No operation command
X
(V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
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TIMING DIAGRAMS
Please refer to timing diagram chart (II)
HSD8M32B4
PACKAGING INFORMATION
107.95 20 17.8 0.2 10.16
3.38 3.2
10.16 6.35 2.03
44.45
1.27
1.00
95.25 6.35 6.35
2.54 MIN 0.25 MAX
Gold: 1.040.10 Solder: 0.9140.10 1.27
1.270.08mm
(Solder & Gold Plating)
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HSD8M32B4
ORDERING INFORMATION
Part Number
Density
Org.
Package 144 Pin SO-DIMM 144 Pin SO-DIMM 144 Pin SO-DIMM 144 Pin SO-DIMM
Ref.
Vcc
CL
MAX.frq
HSD8M32B4-10 HSD8M32B4-10L HSD8M32B4-12 HSD8M32B4-13
32MByte 32MByte 32MByte 32MByte
8Mx 32 8Mx 32 8Mx 32 8Mx 32
4K 4K 4K 4K
3.3V 3.3V 3.3V 3.3V
CL=2 CL=3 CL=3 CL=3
100MHz 100MHz 125MHz 133MHz
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