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| Data Sheet No.PD94717 revC IR3623MPBF HIGH FREQUENCY 2-PHASE, SINGLE OR DUAL OUTPUT SYNCHRONOUS STEP DOWN CONTROLLER WITH OUTPUT TRACKING AND SEQUENCING Description Features * * * * * * * * * * * * * * * * * * * * * * * 12V Dual Synchronous Controller with 180o Out of Phase Operation Configurable to 2-Independent Outputs or Current Share Single Output Output Voltage Tracking Power up /down Sequencing Current Sharing Using Inductor's DCR +/-1% Accurate Reference Voltage Programmable Switching Frequency up 1200kHz Programmable Over Current Protection Hiccup Current Limit Using MOSFET RDS(on) sensing Latched Overvoltage Protection Dual Programmable Soft-Starts Enable Pre-Bias Start-up Dual Power Good Outputs On Board Regulator External Frequency Synchronization Thermal Protection 32-Lead MLPQ Package Embedded Telecom Systems Distributed Point of Load Power Architectures Computing Peripheral Voltage Regulator Graphics Card General DC/DC Converters The IR3623 IC integrates a dual synchronous Buck controller, along with IP2003A it is providing a high performance and flexible solution. The IR3623 can be configured as 2-independent outputs or as current share single output. The current share configuration is ideal for high current applications. IR3623 enables output tracking and sequencing of multiple rails in either ratiometric or simultaneous fashion. The IR3623 features 180o out of phase operation which reduces the required input/output capacitance and results to few number of capacitor quantity. The switching frequency is programmable from 200kHz to 1200kHz per phase using one external resistor, in addition IR3623 also allows the switching frequency to be synchronized to an external clock signal. Other key features offered by this device include two independent programmable soft starts, two independent power good outputs, precision enable input and under voltage lockout function. The current limit is provided by sensing the lower MOSFET's on-resistance for optimum cost and performance. The output voltages are monitored through dedicated pins protect against open circuit and enhance faster response to an overvoltage event. Applications Vo1 Vo2 C6 Vo1 Vo2 5V_sns Vcc C1 VOUT3 C7 Vdd Vin Enable Seq Track1 Sync Track2 VP1 VREF VP2 Rt R2 R3 Comp1 Comp2 Vout1 R10 Ph_En1 PWM1 R4 Enable1 IP2003A PWM1 SW1 Vsns1 Fb1 Fb2 Vsns2 R5 SW1 L1 Vout1 R6 Vsns1 R7 Fb1 R7 R6 C9 PRDY1 PGnd Ratiometric Powerup Ratiometric Powerdown R11 R1 C2 C3 OCSet1 IR3623 Vsns1 Fb1 Fb2 Gnd 12V Vo1 Vin C8 Vo1 Vo2 Vsns2 OCSet2 SW2 Vdd PRDY2 Enable2 PWM2 PGnd Gnd Vo2 L2 OVP_Output PGood1,2 OVP_Output PGood1,2 SS1 / SD SS2 / SD C5 Ph_En2 PWM2 OCGnd SW2 Vout2 IP2003A R8 Vsns2 R9 Fb2 R9 R8 C10 C4 SGnd Gnd Simultaneous Powerup Simultaneous Powerdown Fig. 1: Power Up /Down Sequencing ORDERING INFORMATION PKG DESIG M M PACKAGE DESCRIPTION IR3623MPBF IR3623MTRPbF PIN PARTS PARTS COUNT PER TUBE PER REEL 32 73 ------32 -------6000 T&R ORIANTAION Fig A www.irf.com IR3623MPBF ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND) *Vcc Supply Voltage .................................................. -0.5V to 16V *PWM1, PWM2 ................................................. -0.5V to 16V *PGood .......... ............................................... -0.5V to 16V *Gnd to SGnd ................................................ +/- 0.3V *Storage Temperature Range .................................... -65C To 150C *Operating Junction Temperature Range .................. -40C To 125C *ESD Classification .......................................... JEDEC, JESD22-A114 Caution: Stresses above those listed in "Absolute Maximum Rating" may cause permanent damage to the device. These are stress ratings only and function of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to "Absolute Maximum Rating" conditions for extended periods may affect device reliability. Package Information 5V _sn s En ab le Rt Gn d SG nd VR EF 2 32 PGood1 1 PGood2 2 Track2 3 VSEN2 4 OVP_Output 5 31 30 29 28 27 VP 26 25 24 Seq 23 Sync 22 Track1 VP 1 Pad 21 VSEN1 20 19 OCGnd Fb1 Fb2 6 Comp2 7 SS2/SD2/Mode 8 9 10 11 12 C 18 Comp1 17 SS1/SD1 13 UT 3 14 15 16 OC Se t2 Ph _E n2 PW M2 VC JA = 36o C/W JC = 1o C/W *Exposed pad on underside is connected to a copper pad through vias for 4-layer PCB board design www.irf.com PW M1 Ph _E n1 OC Se t1 VO 2 IR3623MPBF Recommended Operating Conditions Symbol Vcc Fs Tj Definition Supply Voltage Operating frequency Junction temperature Min 8.5 200 -40 Max 14.5 1200 125 Units V kHz o C Electrical Specifications Unless otherwise specified, these specification apply over Vcc=12V, 0oC FB1, FB2 Voltage Accuracy -40 C SYM Test Condition Min TYP MAX Units VFB -1 -2.5 0.8 +1 +1.35 V % % Supply Current VCC Supply Current (Static) ICC (Static) SS=0V, No Switching 10 17 mA Under Voltage Lockout VCC-Threshold VCC-Hysteresis Enable-Threshold Enable-Hysteresis 5V_sns-Threshold 5V_sns_Hysteresis VCC_UVLO(R) VCC_UVLO(F) Vcc-Hyst En_UVLO(R) En_UVLO(F) En_Hyst 5V_sns_UVLO(R) 5V_sns_UVLO(F) 5V_sns_Hyst I(drive) Supply ramping up Supply ramping down Supply ramping up / down Supply ramping up Supply ramping down Supply ramping up / down Supply ramping up Supply ramping down Supply ramping up / down 7.6 6.9 400 1.2 1.0 4.55 4.3 8.00 7.4 600 1.2 100 4.6 100 10 Vout3 -1 0.8 8.4 7.9 800 1.4 1.35 4.85 4.8 V V mV V V mV V V mV mA V V Ph_En, PWM 1,2 Drive Current Input Voltage High Input Voltage Low Internal Regulator Output Accuracy Output Curret Vout3 Io FS Fs(range) Vramp Dmin Dmin(ctrl) Dmax Rt=51K See Figure 16 Note1 Fb=1V FS=300kHz, Note1 FS=300kHz, Fb=0.6V 20% above free running Freq 200 Note1 Note1 2 0.8 300 85 2400 7.6V Frequency Frequency Range Ramp Amplitude Min Duty Cycle Min Pulse Width Max duty Cycle Sync Frequency Range Sync Pulse Duration Sync High Level Threshold Sync Low Level Threshold www.irf.com 3 IR3623MPBF Electrical Specifications Parameter Error Amplifier Fb Voltage Input Bias Current E/A Source/Sink Current Transconductance Input offset Voltage VP Voltage Range Track Voltage Range IFB I(source/Sink) gm1,2 Voffset VP Track Fb to Vref Note1 Note1 SS=3V 120 2800 -3 0.4 0 -0.1 200 -0.5 280 4400 +3 Vcc-2 Vcc A A mho mV V V SYM Test Condition Min TYP MAX Units Soft Start/SD Soft Start Current Shutdown Output Threshold OCSET Current Hiccup Current Hiccup Duty Cycle ISS SD Source / Sink 17 22 27 0.25 A V Over Current Protection IOCSET IHiccup Hiccup(duty) 17 Note1 IHiccup/IOCSET, Note1 22 3 15 27 A uA % Over Voltage Protection OVP Trip Threshold OVP Fault Prop Delay OVP_Output Current OVP(trip) OVP(delay) Output Forced to 1.125Vref 10 20 1.1Vref 1.15Vref 1.2Vref 5 V s mA Thermal Shutdown Thermal shutdown Thermal shutdown Hysteresis Note1 135 20 o o C C Seq Input Seq Threshold Seq On Off Vsen Ramping Down IPGood=2mA 2.0 0.3 0.8Vref 0.9Vref 0.1 0.95Vref 0.5 V V V Power Good Vsen Lower Trip point PGood Output Low Voltage Vsen(trip) PG(voltage) Note1: Guaranteed by design but not test in production Note2: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production www.irf.com 4 IR3623MPBF Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 www.irf.com Pin Name PGood1 PGood2 Track2 VSEN2 OVP-Output Fb2 Comp2 SS2/SD2/Mode OCSet2 Ph_En2 PWM2 Vcc Vout3 PWM1 Ph_En1 OCSet1 SS1/SD1 Comp1 Fb1 OCGnd VSEN1 Track1 Sync Seq VP1 VP2 VREF SGnd Gnd Rt Enable 5V_sns Description Power Good pin out put for channel 1, open collector. This pin needs to be externally pulled high Power Good pin out put for channel 2, open collector. This pin needs to be externally pulled high Sets the type of power up / down sequencing (ratiometric or simultaneously). If it is not used connect this pin to Vout3. Sense pin for OVP2 and Power Good 2, Channel 2 OVP output, goes high when OVP condition occurs Inverting inputs to the error amplifier2 Compensation pin for the error amplifier2 Soft start for channel 2, can be used as SD pin. Float this pin for current share single output application Current limit set point for channel2 Phase Enable pin for channel2 PWM output for channel2 Supply Voltage for the internal blocks of the IC Output of the internal regulator PWM output for channel1 Phase Enable pin for channel1 Current limit set point for Channel 1 Soft start for channel 1, can be used as SD pin Compensation pin for the error amplifier1 Inverting input to the error amplifier1 Ground connection for OCset circuit Sense pin for OVP1 and Power Good, Channel 1 Sets the type of power up / down sequencing (ratiometric or simultaneously). If it is not used connect this pin to Vout3. External synchronization pin Enable pin for tracking and sequencing Non inverting input of error amplifier1 Non inverting input of error amplifier2 Reference Voltage Signal Ground IC's Ground Connecting a resistor from this pin to ground sets the Switching frequency Enable pin, recycling this pin will rest OV, SS and Prebias latch Sensing either external 5V or the Vout3 5 IR3623MPBF Block Diagram SS1 3uA Enable Vcc 25uA 25uA 64uA Max Mode SS2 0.8V Mode Control POR Mode 3V 0.8V OC1 SS1 SS2 Mode Hiccup Control 20uA OCGnd OCSet1 Bias Generator SS2 / SD/MODE SS1 / SD 64uA UVLO OC2 OCGnd OCSet2 5V_Sns POR POR Mode OC1,2 SS1,2 T.S POR SS2 3uA 20uA Track1 VP1 Fb1 Comp1 Rt Sync VREF Track2 VP2 Fb2 Comp2 VSEN1 VSEN2 0.8V Error Amp1 Ctrl1 Fault Ctrl Ctrl2 0.3V Thermal Shutdown PWM1 Ctrl1 Tri-State VOUT3 S Ctrl1 Q SS1 POR R Ph_En1 VOUT3 PWM1 Ramp1 Two Phase Oscillator Error Amp2 Ramp2 OVP1 PWM2 OVP2 Ctrl2 Tri_State VOUT3 PWM2 VOUT3 0.3V OVP1 OVP2 PGood / OVP POR R Q S Ctrl2 Ph_En2 SS2 PGood1 PGood2 Seq Sequencing SS1 / SD Vcc OVP_Output 5V_sns 5V_sns VOUT3 Gnd SGnd Regulator Fig. 2: Simplified block diagram of the IR3623 www.irf.com 6 IR3623MPBF TYPICAL OPERATING CHARACTERISTICS VFb1 vs Tem perature 0.804 0.802 0.800 Vfb1 (V) Vfb2 (V) 0.804 0.802 0.800 0.798 0.796 0.794 0.792 VFb2 vs Tem perature 0.798 0.796 0.794 0.792 0.790 -40 -15 10 35 60 85 110 0.790 -40 -15 10 35 60 85 110 Tem perature (C) Tem perature (C) SS1 Current vs Tem perature -15.0 -16.0 SS1 Current (uA) -17.0 -18.0 -19.0 -20.0 -21.0 -22.0 -23.0 -40 -15 10 35 60 85 110 SS2 Current (uA) -15.0 -16.0 -17.0 -18.0 -19.0 -20.0 -21.0 -22.0 -23.0 -40 SS2 Current vs Tem perature -15 10 35 60 85 110 Tem perature (C) Tem perature (C) Vcc_UVLO vs Tem perature 8.08 8.06 8.04 8.02 8.00 7.98 7.96 7.94 7.92 7.90 7.88 -40 5.18 5.17 VO3 (V) 5.16 5.15 5.14 5.13 -40 VO3 vs Tem perature Vcc_UVLO (V) -15 10 35 60 85 110 -15 10 35 60 85 110 Tem perature (C) Tem perature (C) www.irf.com 7 IR3623MPBF TYPICAL OPERATING CHARACTERISTICS IOCSET1 vs Tem perature 23.0 22.0 IOCSET1 (uA) 21.0 20.0 19.0 18.0 17.0 -40 IOCSET2 vs Tem perature 23.0 22.0 IOCSET2 (uA) 21.0 20.0 19.0 18.0 17.0 -40 -15 10 35 60 85 110 -15 10 35 60 85 110 Tem perature (C) Tem perature (C) GM vs Tem perature 3600 PWM FREQ 600KHz vs Tem perature 615 610 605 600 595 590 585 580 575 570 -40 3400 3300 3200 3100 3000 -40 -15 10 35 60 85 110 PWM1 Freq (KHz) 3500 GM1 (umho) -15 10 35 60 85 110 Tem perature (C) Tem perature (C) Max Duty Cycle vs Temperature 600kHz M a x D u t y C y c le ( % ) M a x D u t y C y c le ( % ) Max Duty Cycle vs Temperature 1.2MHz 58.0 57.0 56.0 55.0 54.0 -40 -15 10 35 60 85 110 80 79 78 77 76 75 -40 -15 10 35 60 85 110 Temperature (C) Temperature (C) www.irf.com 8 IR3623MPBF Circuit Description THEORY OF OPEARTION Introduction The IR3623 is a versatile device for high performance buck converters. It consists of two synchronous buck controllers which can be operated either in two independent outputs mode or in current share single output mode for high current applications. The timing of the IC is provided by an internal oscillator circuit which generates two-180o-out-ofphase clock that can be externally programmed up to 1200kHz per phase. The IR3623 along with IR's IP2003A family offers a compact and efficient solution where the integration and power density are required. 5V_sns IR3623 integrates an internal LDO for powering the external module without need for an external supply. For a correct start up sequence the external module needs to be biased first prior to the controller IC. The Vout3 ramps up as soon as Vcc is applied but the POR (Power On Ready) is not enabled until the Vout3 reached the 5V threshold set by 5V_sns pin. Enable The enable features another level of flexibility for start up. The Enable has precise threshold which is internally monitored by under-voltage lockout circuit. It's threshold can be externally programmed to desired level by using two external resistors, so the converter doesn't start up until the input voltage is sufficiently high. Under-Voltage Lockout The under-voltage lockout circuit monitors three signals (Vcc, Enable and 5V_sns). This ensures the correct operation of the converter during power up and power down sequence. The PWM outputs remain in the off state whenever one of these signals drop below set thresholds. Normal operation resumes once these signals rise above the set values. Figure 3 shows a typical start up sequence. 11V 12V 12V 8.0V 4.7V Vbus 5.2V Vcc Vout3 Vout3 OK Vcc OK Enable OK (IC's POR) 3V Enable 5V_sns SS Seq Fig. 3: Normal Start up, Enable threshold is externally set to 11V www.irf.com 9 IR3623MPBF Internal Regulator IR3623 features an on-board regulator capable of sourcing current up to 200mA. This integrated regulator can be used to generate the necessary bias voltage for the IP2003A, an example of how this can be used to power IP2003A is shown in figure 22. The output of regulator is protected for short circuit and thermal shutdown. In addition, the 180o out of phase contributes to input current cancellation. This result in much smaller input capacitor's RMS current and reduces the input capacitor quantity. Figure 5 shows the equivalent RMS current. RMS Current Normalized (IRMS/Iout) Single Phase Out-of-Phase Operation The IR3623 drives its two output stages 180o outof-phase. In current share mode single output, the two inductor ripple currents cancel each other and result in a reduction of the output current ripple and yield a smaller output capacitor for the same ripple voltage requirement. Figure 4 shows two channels inductor current and the resulting voltage ripple at output. 2 Phase Duty Cycle (Vo/Vin) HDRV1 Fig. 5: Input RMS value vs. Duty Cycle Mode Selection 0 DT T HDRV2 IL1 IL2 The IR3623 can operate as a dual output independently regulated buck converter, or as a 2 phase single output buck converter (current share mode). The SS2 pin is used for mode selection. In current share mode this pin should be floating and in dual output mode a soft start capacitor must be connected from this pin to ground to program the start time for the second output. Independent Mode Ic Io Fig. 4: Current ripple cancellation for output In this mode the IR3623 provides control to two independent output power supplies with either common or different input voltages. The output voltage of each individual channel is set and controlled by the output of the error amplifier, which is the amplified error signal from the sensed output voltage and the reference voltage. The error amplifier output voltage is compared to the ramp signal thus generating fixed frequency pulses of variable duty-cycle, (PWM) which are applied to the external MOSEFT drivers. Figure 23 shows a typical schematic for such application. www.irf.com 10 IR3623MPBF Current Share Mode This feature allows to connect both outputs together to increase current handling capability of the converter to support a common load. In current sharing mode, error amplifier 1 becomes the master which regulates the common output voltage and the error amplifier 2 performs the current sharing function, figure 6 shows the configuration of error amplifiers. In this mode IR3623 make sure the master channel starts first followed by slave channel to prevent any glitch during start up. This is done by clamping the output of slave's error amplifier until the master channel generates the first PWM signal. At no load condition the slave channel may be kept off depends on the offset of error amplifier. Vin Master Phase IL1 L1 + RL1 VL1 (s) C1 + VC1(s) VP2 VOUT Q2 R1 FB2 Vin Q3 R2 C2 RL2 L2 Q4 Slave Phase Lossless Inductor Current Sensing The IR3623 uses a lossless current sensing for current share purposes. The inductor current is sensed by connecting a series resistor and a capacitor network in parallel with inductor and measuring the voltage across the capacitor, this voltage is proportional to the inductor current. As shown in figure 6 the voltage across the inductor's DCR can be expressed by: Fig. 6: Loss Less inductor current sensing and current sharing the sense circuit can be treated as if only a sense resistor with the value RL1 was used. If : R 1 * C 1 = L1 R L1 V RL 1 ( s ) = (V in - V out ) * R L1 R L1 * sL 1 - - - -(1 ) VC ( s ) I L1 * R L1 The mismatch of the time constant does not affect the measurements of inductor DC current, but affects the AC component of the inductor current. V RL 1 ( s ) = I L1 * R L1 - - - -( 2 ) The voltage across the C1 can expressed by: VC 1 ( s ) = (V in - V out sC 1 )* R1 * 1 sC 1 1 Soft-Start - - - -( 3 ) The IR3623 has programmable soft-start to control the output voltage rise and limit the inrush current during start-up. It provides a separate Soft-start function for each outputs. This will enable to sequence the outputs by controlling the rise time of each outputs through selection of different value soft-start capacitors. To ensure correct start-up, the soft-start sequence initiates when the Vcc, Enable and 5V_sns rise above their threshold and generate the Power On Reset (POR) signal. Soft-start function operates by sourcing an internal current to charge an external capacitor to about 3V. Initially, the soft-start function clamps the error amplifier's output of the PWM converter. Combining equations (1),(2) and (3) result to the following expression for VC1: VC 1 ( s ) = I L1 * R L1 + sL 1 1 + sR 1 * C 1 - - - -( 4 ) Usually the resistor R1 and C1 are chosen so that the time constant of R1 and C1 equals the time constant of the inductor which is the inductance L1 over the inductor's DCR (RL1). If the two time constants match, the voltage across C1 is proportional to the current through L1, and www.irf.com 11 IR3623MPBF Soft-Start (cont.) During power up, the converter output starts at zero and thus the voltage at Fb is about 0V. A current (64uA) injects into the Fb pin and generates a voltage about 1.6V (64ux25K) across the negative input of error amplifier, see figure 7. The magnitude of this current is inversely proportional to the voltage at soft-start pin. The 28uA current source starts to charge up the external capacitor. In the mean time, the softstart voltage ramps up, the current flowing into Fb pin starts to decrease linearly and so does the voltage at negative input of error amplifier. When the soft-start capacitor is around 1V, the voltage at the negative input of the error amplifier is approximately 0.8V. As the soft-start capacitor voltage charges up, the current flowing into the Fb pin keeps decreasing. The feedback voltage increases linearly as the injecting current goes down. The injecting current drops to zero when soft-start voltage is around 1.8V and the output voltage goes into steady state. Figure 8 shows the theoretical operational waveforms during soft-start. The output start-up time is the time period when soft-start capacitor voltage increases from 1V to 2V. The start-up time will be dependent on the size of the external soft-start capacitor. The startup time can be estimated by: 28A Tstart = 1.8V - 1V Css 64uA 64uA 3V ISS1 = 28uA SS1/SD1 Ihiccup1 = 3uA POR OCP1 Seq E/A1 Fb1 VP1 3V ISS2 = 28uA SS2/SD2 OCP2 POR Ihiccup2 = 3uA E/A2 Fb2 VP2 Track Fig. 7: Soft-Start circuit for IR3623 Output of POR 3V For a given start up time, the soft-start capacitor (nF) can be estimated as: 1.8V Soft-Start Voltage Current flowing into Fb pin 1V 0V 64uA 0uA C SS 20 ( A ) * T start ( ms ) 0 . 8 (V ) - - - -( 5 ) For normal start up the Seq pin should be pulled high (usually can be connected to Vout3). Voltage at negative input 1.6V of Error Amp 0.8V 0.8V Voltage at Fb pin 0V Fig. 8: Theoretical operation waveforms during soft-start www.irf.com 12 IR3623MPBF Output Voltage Sequencing Tracking and In general the RA and RB set the output voltage for the first output and RC and RD set the output voltage for the second output. For simultaneously vs. ratiometric, RE and RF can be selected according to the table below: Track Pin RE RF simultaneously RC RD ratiometric RA RB The IR3623 can accommodate a full spectrum of user programmable tracking and sequencing options using Track, Seq, Enable and Power Good pins. Through these pins both simple voltage tracking such as that required by the DDR memory application or more sophisticated sequencing such ratiometric or simultaneously can be implemented. The Seq pin controls the internal current sources to set the power up or down sequencing, toggle this pin high for power up and toggle this pin low for power down. The Track pin is used to determine the second channel output for either ratiometric or simultaneously by using two external resistors. Figure 9 shows how these pins are configured for different sequencing mode. 3V ISS1 = 28uA 64uA SS1/SD1 OCP1 CSS1 Ihiccup1 = 3uA POR Seq Vo1 RA Fb1 E/A1 Fig. 10: Simultaneously Power up /down RB VP1 VREF 3V ISS2 = 28uA 64uA SS2/SD2 Floating OCP2 Vo2 RC RD Vo1 RE RF Fb2 POR Ihiccup2 = 3uA Fig. 11: Ratiometric Power Up / down The Track pin must be connected to Vout3 if it is not used. For current share mode, high output voltage application (e.g. 5V) this pin needs to be connected to Vcc. E/A2 Track2 VP2 Floating Fig. 9: Sequencing using Track pin www.irf.com 13 IR3623MPBF Fault Protection The IR3623 monitors the output voltage for over voltage protection and power good indication. It senses the Rds(on) of low side MOSFET for over current protection. It also protects the output for prebias conditions. Figure below shows the IC's operating waveforms under different fault conditions. POR Ph_Enable 3V 1.8V 1.0V SS Tri_State PWM Set Voltage 90%Vfb Pre_Bias Voltage Vo PGood OCP Threshold Iout OV_Output t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Fig. 12: Fault Conditions t0 - t1: Vcc, 5V_sns and Enable signals passed their respective UVLO threshold. Ph_Enable goes high and PWM switches high from tri-state. Soft start sequence starts. t1 - t2: Power Good signal flags high. t1 - t3: Output voltage ramps up and reaches the set voltage. t4 - t5: OC event, SS ramps down, Ph-Enable pulls low and PWM tri-states. IC in Hiccup mode. t5- t6: OC is removed, recovery sequence, fresh SS. t6 -t7: Ph_Enable goes high and PWM switches high from tri-state. Output voltage reaches the set voltage. t8: OVP event. Ph_Enable is kept high and PWM is pulled low. OVP-Output flags high to indicate OV event. t9 -t10: Manually recycled the Vcc after latched OVP. PreBias start up. The Ph_Enable goes high after first internal PWM pulse is generated. The PWM output is kept in tri-state until Ph-Enable goes high. www.irf.com 14 IR3623MPBF Over-Current Protection The over current protection is performed by sensing current through the RDS(on) of low side MOSFET. This method enhances the converter's efficiency and reduce cost by eliminating a current sense resistor. As shown in figure 13, an external resistor (RSET) is connected between OCSet pin and the drain of low side MOSFET (Q2) which sets the current limit set point. The internal current source develops a voltage across RSET. When the low side MOSFET is turned on, the inductor current flows through the Q2 and results a voltage which is given by: 28uA 22uA OCP SS1 / SD 20 3uA Fig. 14: 3uA current source for discharging soft-start capacitor during hiccup The OCP circuit starts sampling current 200ns (typical) after PWM signal goes high. The OCSet pin is internally clamped to prevent false trigging, figure 15 shows the OCSet pin during one switching cycle. VOCSet = (IOCSet ROCSet ) - (RDS(on) IL ) - - - -( 6 ) IOCSET IP200x Q1 OCSet RSET Q2 L1 VOUT IR3623 Hiccup Control OCGnd Fig. 13: Connection of over current sensing resistor IOCset* ROCset The critical inductor current can be calculated by setting: VOCSet = (IOCSet ROCSet ) - (RDS(on) IL ) = 0 ISET = IL(critical) = ROCSet IOCSet RDS(on) - - - -(7 ) Fig. 15: OCset pin during normal condition Ch1: Inductor point, Ch2:Ldrv, Ch3:OCSet The value of RSET should be checked in an actual circuit to ensure that the over current protection circuit activates as expected. The IR3623 current limit is designed primarily as disaster preventing, "no blow up" circuit, and doesn't operate as a precision current regulator. When the SS2 is floating over current on either phase would result to hiccup of output voltage. An over current is detected if the OCSet pin goes below ground. This trips the OCP comparator and cycles the soft start function in hiccup mode. The hiccup is performed by charging and discharging the soft-start capacitor in certain slope rate. As shown in figure 14 a 3uA current source is used to discharge the soft-start capacitor. The OCP comparator resets after every soft start cycles, the converter stays in this mode until the overload or short circuit is removed. The converter will automatically recover. During this fault condition the Ph_En signal is low and PWM output is on Tri-state, see figure 12. www.irf.com 15 IR3623MPBF Ph_En and Pre-Bias For a correct start up the driver section needs to be powered up before the PWM signal is applied. IR3623 features a dedicated pin (Ph_En) which can be used for this purposes. Figure 22 shows how this pin is used to enable IP2003A. During normal start up the PWM is in Tri-state mode until the Ph_En goes high, each channel has own Ph_En pins. During the Pre-Bias start up the Ph_En is kept low and the PWM output is in Tri-state mode. The Ph_En will be enabled as soon as the internal PWM signal is generated. Fsw(kHZ) Operating Frequency Selection The switching frequency is determined by connecting an external resistor (Rt) to ground. Figure 16 provides a graph of oscillator frequency versus Rt. The maximum recommended channel frequency is 1.2MHz. Switching Frequency vs R T 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 25 50 75 100 125 150 175 200 225 Over Voltage Protection Over-voltage is sensed through two dedicated sense pins VSEN1, VSEN2. A separate OVP circuit is provided for each channel. The OVP threshold is user programmable and can be set by two external resistors. Upon overvoltage condition of either one of the outputs, the OVP forces a latched shutdown on the fault output and pulls low the PWM signal. IR3623 features an OVP output signal, high status of this pin indicates the OVP event for either of the channels. This pin has 10mA current capability which can be used to drive an external switch. Reset is performed by recycling the Vcc or Enable. RT (kOhm) Fig. 16: Switching Frequency vs. External Resistor (Rt) Frequency Synchronization The IR3623 is capable of accepting an external digital synchronization signal. Synchronization will be enabled by the rising edge at an external clock. Per -channel switching frequency is set by external resistor (Rt). The free running frequency oscillator frequency is twice the perchannel frequency. During synchronization, Rt is selected such that the free running frequency is 20% below the synchronization frequency. Synchronization capability is provided for both single output current share mode and dual output configuration. When unused, the sync pin will remain floating and is noise immune. Power Good The IR3623 provides two separate open collector power good signals which report the status of the outputs. The outputs are sensed through the two dedicated VSEN1 and VSEN2 pins. Once the IR3623 is enabled and the outputs reach the set value (90% of set value) the power good signals go open and stay open as long as the outputs stay within the set values. These pins need to be externally pulled high. Thermal Shutdown Temperature sensing is provided inside IR3623. The trip threshold is typically set to 135oC. When trip threshold is exceeded, thermal shutdown turns off both MOSFETs. Thermal shutdown is not latched and automatic restart is initiated when the sensed temperature drops to normal range. There is a 20oC hysteresis in the shutdown threshold. Shutdown using Soft Start pins The outputs can be shutdown by pulling the softstart pin below 0.3V. This can be easily done by using an external small signal transistor. During shutdown both MOSFET drivers will be turned off. Normal operation will resume by cycling soft start pin. www.irf.com 16 IR3623MPBF Application Information Design Example: The following example is a typical application for IR3623. The application circuit is shown in page24. Vin = 12V , (13.2V , max) Vo = 1.8V Io = 40 A Soft-Start Programming The soft-start timing can be programmed by selecting the soft-start capacitance value. The start-up time of the converter can be calculated by using: CSS 20A * Tstart - - - -(10 ) Where Tstart is the desired start-up time (ms) For a start-up time of 5ms, the soft-start capacitor will be 0.1uF. Choose a ceramic capacitor at 0.1uF. Vo 30 mV Fs = 600 kHz Output Voltage Programming Output voltage is programmed by reference voltage and external voltage divider. The Fb pin is the inverting input of the error amplifier, which is internally referenced to 0.8V. The divider is ratioed to provide 0.8V at the Fb pin when the output is at its desired value. The output voltage is defined by using the following equation: R Vo = VREF 1 + 6 R5 - - - -( 8 ) Input Capacitor Selection The 180o out of phase will reduce the RMS value of the ripple current seen by input capacitors. This reduces numbers of input capacitors. The input capacitors must be selected that can handle both the maximum ripple RMS at highest ambient temperature as well as the maximum input voltage. The RMS value of current ripple for duty cycle under 50% is expressed by: IRMS = (I D (1 - D ) + I D (1 - D ) - 2I I D D ) 2 1 1 1 2 2 2 2 12 1 2 - - - -(11) When an external resistor divider is connected to the output as shown in figure 17. VOUT IR3623 Fb1 R5 R6 Where: -IRMS is the RMS value of the input capacitor current -D1 and D2 are the duty cycle for each channel -I1 and I2 are the output current for each channel For Io=40A and D=0.13, the IRMS= 17.8A. Ceramic capacitors are recommended due to their peak current capabilities, they also feature low ESR and ESL at higher frequency which enhance better efficiency, Use 15x22uF, 16V ceramic capacitor from TDK (C3225X5R1C226M). For the single output application when the duty cycle is larger than 50% the following equation can be used to calculate the total RMS value input capacitor current: Fig. 17: Typical application of the IR3623 for programming the output voltage Equation (8) can be rewritten as: V R5 = R6 ref V -V o ref - - - -( 9 ) For the calculated values of R5 and R6 see feedback compensation section. IRMS = IO (2D(1 - D) + (2 - 2D)) D > 0.5 www.irf.com 17 IR3623MPBF Inductor Selection The inductor is selected based on output power, operating frequency and efficiency requirements. Low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. Generally, the selection of inductor value can be reduced to desired maximum ripple current in the inductor ( i ) . The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for desired operating ripple current can be determined using the following relation: Vin - Vo = L L = (Vin - Vo ) Output Capacitor Selection The voltage ripple and transient requirements determines the output capacitors types and values. The criteria is normally based on the value of the Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing components, these components can be described as: Vo = Vo(ESR) + Vo(ESL) + Vo(C ) Vo(ESR) = IL * ESR Vo(ESL) = Vin * ESL L - - - -(13) i 1 ; t = D Fs t - - - -(12 ) Vo Vin i * Fs Vo(C ) = IL 8 * Co * Fs Where: Vin = Maximum input voltage Vo = Output Voltage Vo = Output voltage ripple IL = Inductor ripple current Since the output capacitor has major role in overall performance of converter and determine the result of transient response, selection of capacitor is critical. The IR3623 can perform well with all types of capacitors. As a rule the capacitor must have low enough ESR to meet output ripple and load transient requirements, yet have high enough ESR to satisfy stability requirements. The goal for this design is to meet the voltage ripple requirement in smallest possible capacitor size. Therefore ceramic capacitor is selected due to low ESR and small size. Panasonic ECJ2FB0J226M (22uF, 6.3V, X5R and EIA 0805 case size) is a good choice. In the case of tantalum or low ESR electrolytic capacitors, the ESR dominates the output voltage ripple, equation (13) can be used to calculate the required ESR for the specific voltage ripple. i = Inductor ripple current F s= Switching frequency t = Turn on time D = Duty cycle For 2-phase single output application the inductor ripple current is chosen between 10-40% of maximum phase current If i 35%(Io ) , then the output inductor will be: L = 0.37uH The Panasonic ETQP4LR36WFC (L1=0.34uH, 24A, RL1=1.1mOhm) provides a low profile inductor suitable for this application. Use the following equation to calculate C12 and R12 for current sensing: R 12 * C 12 = L1 R L1 This results to C12=0.33uF and R12=1.1K www.irf.com 18 IR3623MPBF Feedback Compensation The IR3623 is a voltage mode controller; the control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency and adequate phase margin (greater than 45o). The output LC filter introduces a double pole, - 40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180o (see figure 18). The resonant frequency of the LC filter expressed as follows: FLC = 1 2 Lo Co - - - -(14) 1 2 * ESR * Co FESR = - - - -(15) VOUT R6 Fb R5 VREF Gain(dB) E/A Comp Ve C9 R4 CPOLE H(s) dB FZ Frequency figure 16 shows gain and phase of the LC filter. Since we already have 180o phase shift just from the output filter, the system risks being unstable. Gain 0dB -40dB/decade Phase 0 Fig. 19: TypeII compensation network and its asymptotic gain plot The transfer function (Ve/Vo) is given by: R5 1 + sR4C9 * H(s) = gm * R5 + R6 sC9 - - - -(16) The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: FLC Frequency -180 FLC Frequency Fig. 18: Gain and Phase of LC filter The IR3623's error amplifier is a differential-input transconductance amplifier. The output is available for DC gain control or AC phase compensation. The E/A can be compensated either in type II or typeIII compensation. When it is used in typeII compensation the transconductance properties of the E/A become evident and can be used to cancel one of the output filter poles. This will be accomplished with a series RC circuit from Comp pin to ground as shown in figure 19. This method requires that the output capacitor should have enough ESR to satisfy stability requirements. In general the output capacitor's ESR generates a zero typically at 5kHz to 50kHz which is essential for an acceptable phase margin. The ESR zero of the output capacitor expressed as follows: www.irf.com [H(s)] = g Fz = m * R5 * R4 R5 + R6 - - - -(18) - - - -(17) 1 2 * R4 * C9 The gain is determined by the voltage divider and E/A's transconductance gain. First select the desired zero-crossover frequency (Fo): Fo > FESR and Fo (1/5 ~ 1/10) * Fs Use the following equation to calculate R4: R4 = Vosc * Fo * FESR * (R5 + R6 ) 2 Vin * FLC * R5 * gm - - - -(19) Where: Vin = Maximum Input Voltage Vosc = Oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter gm = Error Amplifier Transconductance 19 IR3623MPBF To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: Fz = 75%FLC Fz = 0.75 * 1 2 Lo * Co - - - -(20) ZIN C10 R8 VOUT R7 R6 Fb R5 C12 C11 Zf Using equations (18) and (20) to calculate C9. C9 = 1 2 * R4 * Fz Gain(dB) E/A Comp Ve One more capacitor is sometimes added in parallel with C9 and R4. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by: FP = 1 C *C 2 * R4 * 9 POLE C9 + CPOLE VREF H(s) dB FZ1 FZ2 FP2 FP3 Frequency The pole sets to one half of switching frequency which results in the capacitor CPOLE: CPOLE = 1 Fig. 20: Compensation network with local feedback and its asymptotic gain plot As known, transconductance amplifier has high impedance (current source) output, therefore, consider should be taken when loading the E/A output. It may exceed its source/sink output current capability, so that the amplifier will not be able to swing its output voltage over the necessary range. The compensation network has three poles and two zeros and they are expressed as follows: FP1 = 0 FP 2 = FP 3 = 1 2 * R8 * C10 * R4 * Fs - Fs 2 1 C9 1 * R4 * Fs For FP << For a general solution for unconditionally stability for any type of output capacitors, in a wide range of ESR values we should implement local feedback with a compensation network (typeIII). The typically used compensation network for voltage-mode controller is shown in figure 20. In such configuration, the transfer function is given by: Ve 1 - g m Zf = Vo 1 + g m ZIN The error amplifier gain is independent of the transconductance under the following condition: 1 1 C11 * C12 2 * R7 * C12 2 * R7 C + C 11 12 1 Fz1 = 2 * R7 * C11 Fz 2 = 1 1 2 * C10 * (R6 + R8 ) 2 * C10 * R6 g m * Zf >> 1 and g m * Zin >> 1 - - - -(21) By replacing Zin and Zf according to figure 15, the transformer function can be expressed as: (1 + sR7C11 ) * [1 + sC10 (R6 + R8 )] 1 * H (s ) = sR6 (C11 + C12 ) C11 * C12 1 + sR7 C + C * (1 + sR8C10 ) 11 12 www.irf.com Cross over frequency is expressed as: Fo = R7 * C10 * Vin 1 * Vosc 2 * Lo * Co 20 IR3623MPBF Based on the frequency of the zero generated by output capacitor and its ESR versus crossover frequency, the compensation type can be different. The table below shows the compensation types and location of crossover frequency. Compensator type TypII(PI) FESR vs. Fo Output capacitor Electrolytic , Tantalum Tantalum, ceramic Ceramic FLC The following design rules will give a crossover frequency approximately one-sixth of the switching frequency. The higher the band width, the potentially faster the load transient response. The DC gain will be large enough to provide high DC-regulation accuracy (typically -5dB to -12dB). The phase margin should be greater than 45o for overall stability. Desired Phase Margin: max = 3 1 - Sin FZ 2 = Fo * 1 + Sin FZ 2 = 26.79kHz 1 + Sin 1 - Sin FP 2 = 373.21kHz FP 2 = Fo * Select : FZ1 = 0.5 * FZ 2 and FP3 = 0.5 * Fs R7 2 ; R7 0.72K ; Select : R7 = 10K gm Table1- The compensation type and location of FESR versus Fo The details of these compensation types are discussed in application note AN-1043 which can be downloaded from IR Web-Site. For this design we have: Vin=13.2V Vo=1.8V Vosc=1.25V Vref=0.8V gm=2800umoh Lo=0.34uH, DCR=1.1mOhm Co=15x22uF, ESR= 0.33mOhm Fs=600kHz These result to: FLC=15kHz FESR=1.46MHz Fs/2=300kHz Calculate C11 , C12 and C10 : C11 = 1 ; C11 = 1.19nF, Select : C11 = 1.2nF 2 * FZ1 * R 7 1 ; C12 = 53pF, Select : C12 = 47 pF 2 * FP 3 * R7 2 * Fo * Lo * Co * Vosc ; C10 = 0.67nF, R7 * Vin C12 = C10 = Select : C10 = 0.68nF Calculate R8 , R6 and R5 : R8 = 1 ; R8 = 0.63K, Select : R8 = 0.68K 2 * C10 * FP 2 1 - R8 ; R6 = 8.05K, Select : R6 = 8.06K 2 * C10 * FZ 2 Vref * R6 ; R5 = 6.45K , Select : R5 = 6.49K Vo - Vref Select crossover frequency: Fo < FESR and Fo (1/5 ~ 1/10) * Fs Fo=100kHz Since: FLC R5 = www.irf.com 21 IR3623MPBF Compensation for (slave channel) Current Loop The slave error amplifier is differential transconductance amplifier, in 2-phase configuration the main goal for the slave channel feedback loop is to control the inductor current to match the master channel inductor current as well provides highest bandwidth and adequate phase margin for overall stability. The following analysis is valid for both using external current sense resistors and using DCR of inductor. The transfer function of power stage is expressed by: G(s) = IL2 (s) Vin = Ve sL2 * Vosc - - - -( 22 ) Select a zero frequency for current loop (Fo2) 1.25 times larger than zero cross frequency for voltage loop (Fo1). FO2 1.25% * FO1 H(FO2 ) = gm * Rs1 * R2 * Vin =1 2 * FO2 * L2 * Vosc - - - -( 24 ) From (24), R2 can be expressed as: 1 2 * FO2 * L2 * Vosc * gm * Rs1 Vin R2 = - - - -( 25 ) Where: Vin=Input voltage L2=Output inductor Vosc=Oscillator Peak Voltage As shown the G(s) is a function of inductor current. The transfer function for compensation network is given by equation (23), when using a series RC circuit as shown in figure21. IL2 L2 Fb2 RS2 Vp2 RS1 L1 IL1 E/A2 Comp2 Ve R2 C2 Vin=13.2V Vosc=1.25V gm=2800umoh L2=0.34uH Rs1=DCR=1.1mOhm Fo2=125kHz This results to : R2=8.2K The power stage of current loop has a dominant pole (Fp) at frequency expressed by: FP = Req 2 * L2 Where Req is the total resistance of the power stage which includes the Rds(on) of MOSFET switches, the DCR of inductor and shunt resistance (if it used). Req = Rds(on) + RL + Rs Fig. 21: The Compensation network for current loop V (s) R 1 + sC2R2 D(s) = e = gm * s1 * Rs2 Rs 2 sC2 Req=9.4mOhm Set the zero of compensator at 10 times the dominant pole frequency FP, the compensator capacitor, C2 can be expressed as: Fz = 10 * FP C2 = 1 2 * R2 * Fz - - - -( 23 ) The loop gain function is: H(s) = [G(s) * D(s) * Rs2 ] R 1 + sR2C2 Vin * H(s) = Rs2 * gm * s1 * Rs2 sC2 sL2 * Vosc C2=0.47nF All design should be tested for stability to verify the calculated values. www.irf.com 22 IR3623MPBF Programming the Current-Limit The Current-Limit threshold can be set by connecting a resistor (RSET) from drain of low side MOSFET to the OCSet pin. The resistor can be calculated by using equation (7). The RDS(on) has a positive temperature coefficient and it should be considered for the worse case operation. This resistor must be placed close to the IC, place a small ceramic capacitor from this pin to ground for noise rejection purposes. ROCSet IOCSet RDS(on) Layout Consideration The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Start to place the power components, make all the connection in the top layer with wide, copper filled areas. The inductor, output capacitor should be close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place input capacitor close to IP2003A's input pin, to reduce the ESR replace the single input capacitor with two parallel units. The feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the IC. In multilayer PCB use one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. The exposed pad of IC should be connected to analog ground. Layout guidelines for IP2003A can be found in IP2003A data sheet. ISET = IL(critical) = - - - -(7 ) RDS( on ) = 1.8 m 1.5 = 2.7 m ISET Io ( LIM ) = 20 A 1.5 = 30 A (50% over nominal output current) ROCSet = R3 = R4 = 4K www.irf.com 23 IR3623MPBF Typical Application 12V 5V_sns Vcc C1 Enable Seq Sync Track1 Track2 VP1 VREF C12 Fb1 C11 C2 R7 R2 Rt Comp1 Comp2 OVP_Output PGood1,2 SS1 / SD C4 SS2 / SD SGnd VOUT3 C6 Vdd Ph_En1 PWM1 Fb1 OCSet1 R4 SW1 Gnd Enable1 PWM1 PRDY1 PGnd SW1 Vin C7 L1 VOUT3 R12 Vp2 C12 R1 IR3623 VP2 Fb2 Ph_En2 Vsns1 Vsns2 OCSet2 Vsns R3 SW2 IP2003A 12V Vdd PRDY2 Enable2 PWM2 PGnd Gnd SW2 R12 Fb2 L2 R6 Vin C8 R5 Fb1 C10 R8 Vsns R10 R9 C9 Vout OVP_Output PGood1,2 PWM2 OCGnd Gnd C12 IP2003A Fig. 22: Application circuit for 13.2V to 1.8V @ 40A www.irf.com 24 IR3623MPBF Typical Application 12V 5V_sns Vcc C1 Vout1 R10 VOUT3 Enable Seq Track1 Sync Track2 VP1 VREF VP2 Rt R2 R3 Comp1 Comp2 OVP_Output PGood1,2 SS1 / SD C4 C5 SS2 / SD SGnd VOUT3 C6 Vdd Ph_En1 PWM1 R4 SW1 Vsns1 Fb1 Fb2 Vsns2 R5 SW2 Vdd PRDY2 Enable2 PWM2 PGnd Gnd SW2 Vin 12V Enable1 Vin C7 IP2003A PWM1 PRDY1 PGnd Gnd SW1 L1 Vout1 R6 Vsns1 Fb1 R6 C9 R11 R1 C2 C3 OVP_Output PGood1,2 OCSet1 IR3623 Vsns1 Fb1 Fb2 Vsns2 OCSet2 Ph_En2 PWM2 OCGnd Gnd R7 R7 C8 L2 Vout2 R8 Vsns2 R9 Fb2 R8 C10 IP2003A R9 Fig. 23: Application circuit for Dual output application Tracking and sequencing using Track pin www.irf.com 25 IR3623MPBF (IR3623M) MLPQ Package; 5x5-32 Lead IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Industrial market. Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 3/27/2006 www.irf.com 26 |
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