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| FEDD51V4400E-01 This version : Aug. 2000 Semiconductor MSM51V4400E 1,048,576-Word x 4-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM51V4400E is a 1,048,576-word x 4-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM51V4400E achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM51V4400E is available in a 26/20-pin plastic SOJ, 26/20-pin plastic TSOP. FEATURES * * * * * * * * * 1,048,576-word x 4-bit configuration Single 3.3V power supply, 0.3V tolerance Input Output Refresh : LVTTL compatible, low input capacitance : LVTTL compatible, 3-state : 1024 cycles/16 ms Fast page mode, read modify write capability CAS before RAS refresh, hidden refresh, RAS-only refresh capability Multi-bit test mode capability Package options: 26/20-pin 300mil plastic SOJ 26/20-pin 300mil plastic TSOP (SOJ26/20-P-300-1.27) (TSOPII26/20-P-300-1.27-K) (Product : MSM51V4400E-xxSJ) (Product : MSM51V4400E-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family MSM51V4400E-70 MSM51V4400E-10 Access Time (Max.) tRAC 70ns 100ns tAA 35ns 50ns tCAC 20ns 25ns tOEA 20ns 25ns Power Dissipation Cycle Time (Min.) Operating (Max.) Standby (Max.) 130ns 180ns 234mW 198mW 1.8mW 1/14 FEDD51V4400E-01 MSM51V4400E PIN CONFIGRATION (TOP VIEW) DQ1 DQ2 WE RAS A9 1 2 3 4 5 26 25 24 23 22 VSS DQ4 DQ3 CAS OE DQ1 DQ2 WE RAS A9 1 2 3 4 5 26 25 24 23 22 VSS DQ4 DQ3 CAS OE A0 9 A1 10 A2 11 A3 12 VCC 13 18 17 16 15 14 A8 A7 A6 A5 A4 A0 9 A1 10 A2 11 A3 12 VCC 13 18 17 16 15 14 A8 A7 A6 A5 A4 26/20-Pin Plastic SOJ 26/20-Pin Plastic TSOP (K Type) Pin Name A0-A9 RAS CAS DQ1-DQ4 OE WE VCC VSS Function Address Input Row Address Strobe Column Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (3.3 V) Ground (0 V) Note : The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/14 FEDD51V4400E-01 MSM51V4400E BLOCK DIAGRAM Timing Generator Timing Generator RAS CAS 10 Column Address Buffers 10 Column decoders Write Clock Generator 4 WE OE Output Buffers 4 4 4 Input Buffers 4 A0-A9 Internal Address Counter Refresh Control Clock Sense Amplifiers 4 I/O Selector 4 DQ1-DQ4 10 Row Address Buffers 10 Row Decoders Word Drivers Memory Cells VCC On Chip VBB Generator VSS 3/14 FEDD51V4400E-01 MSM51V4400E ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Voltage on Any Pin Relative to VSS Short Circuit Output Current Power Dissipation Operating Temperature Storage Temperature Symbol VT IOS PD* Topr Tstg Rating - 0.5 to 4.6 50 1 - 10 to 70 - 55 to 150 Unit V mA W C C *: Ta = 25C Recommended Operating Conditions (Ta = - 10 C to 70 C) Parameter Power Supply Voltage Input High Voltage Input Low Voltage Symbol Min. 3.0 0 2.0 - 0.3 *2 Typ. 3.3 0 Max. 3.6 0 Vcc + 0.3 0.8 *1 Unit V V V V VCC VSS VIH VIL Notes: *1. The input voltage is VCC + 1.0V when the pulse width is less than 20ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS - 1.0V when the pulse width is less than 20ns (the pulse width respect to the point at which VSS is applied). Capacitance (Vcc = 3.3V 0.3V, Ta = 25C, f=1MHz) Parameter Input Capacitance (A0 - A9) Input Capacitance (RAS, CAS, WE, OE) Output Capacitance (DQ1 - DQ4) Symbol Typ. Max. 5 7 7 Unit pF pF pF CIN1 CIN2 CI/O 4/14 FEDD51V4400E-01 MSM51V4400E DC Characteristics (Vcc = 3.3V 0.3V, Ta = - 10C to 70C) MSM51V4400 E-70 Min. Output High Voltage Output Low Voltage VOH VOL ILI IOH = -2.0mA IOL = 2.0mA 0V VI VCC+0.3V; Input Leakage Current All other pins not under test = 0V DQ disable 0V VO VCC RAS, CAS cycling, tRC = Min. RAS, CAS = VIH ICC2 RAS, CAS VCC -0.2V RAS cycling, ICC3 CAS = VIH, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable Average Power Supply Current (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) ICC6 RAS = cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tPC = Min. 50 40 mA 1, 3 65 55 mA 1, 2 2 2 mA 1 65 55 mA 1, 2 -10 10 -10 10 A 2.4 0 Max. VCC 0.4 MSM51V4400 E-10 Min. 2.4 0 Max. VCC 0.4 V V Parameter Symbol Condition Unit Note Output Leakage Current Average Power Supply Current (Operating) Power Supply Current (Standby) Average Power Supply Current (RAS-only Refresh) Power Supply Current (Standby) ILO -10 10 -10 10 A ICC1 65 55 mA 1, 2 2 0.5 2 0.5 mA 1 Notes: 1. 2. 3. ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. 5/14 FEDD51V4400E-01 MSM51V4400E AC Characteristic (1/2) (Vcc = 3.3V 0.3V, Ta = - 10C to 70C) Note1,2,3,11,12 Parameter Symbol tRC tRWC tPC tPRWC tRAC tCAC tAA tCPA tOEA tCLZ tOFF tOEZ tT tREF tRP tRAS tRASP tRSH tROH tCP tCAS tCSH tCRP tRHCP tRCD tRAD tASR tRAH tASC MSM51V4400 E-70 Min. Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address Access Time from CAS Precharge Access Time from OE Output Low Impedance Time from CAS CAS to Data Output Buffer Turn-off Delay Time OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period RAS Precharge Time RAS Pulse Width RAS Pulse Width (Fast Page Mode) RAS Hold Time RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode) CAS Pulse Width CAS Hold Time CAS to RAS Precharge Time RAS Hold Time from CAS Precharge RAS to CAS Delay Time RAS to Column Address Delay Time Row Address Set-up Time Row Address Hold Time Column Address Set-up Time 130 185 45 100 0 0 0 3 50 70 70 20 20 10 20 70 5 40 20 15 0 10 0 Max. 70 20 35 40 20 20 20 50 16 10,000 100,000 10,000 50 35 MSM51V4400 E-10 Min. 180 240 60 120 0 0 0 3 70 100 100 25 25 10 25 100 5 50 25 20 0 15 0 Max. 100 25 50 55 25 25 25 50 16 10,000 100,000 10,000 75 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 4, 5, 6 4, 5 4, 6 4 4 4 7 7 3 unit Note 6/14 FEDD51V4400E-01 MSM51V4400E AC Characteristic (2/2) (Vcc = 3.3V 0.3V, Ta = - 10C to 70C) Note1,2,3,11,12 Parameter Symbol tCAH tRAL tRCS tRCH tRRH tWCS tWCH tWP tOEH tRWL tCWL tDS tDH tOED tCWD tAWD tRWD tCPWD tRPC tCSR tCHR tWRP tWRH tWTS tWRH MSM51V4400 E-70 Min. Column Address Hold Time Column Address to RAS Lead Time Read Command Set-up Time Read Command Hold Time Read Command Hold Time referenced to RAS Write Command Set-up Time Write Command Hold Time Write Command Pulse Width OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time CAS Precharge WE Delay Time CAS Active Delay Time from RAS Precharge RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) WE to RAS Precharge time (CAS before RAS) WE Hold Time (CAS before RAS) WE Set-up Time (Test mode) WE Hold Time (Test mode) 15 35 0 0 0 0 10 10 20 20 20 0 15 20 45 60 100 70 5 5 10 10 10 10 10 Max. MSM51V4400 E-10 Min. 20 50 0 0 0 0 15 15 25 25 25 0 20 25 55 85 130 80 5 5 10 10 10 10 10 Max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 9 9 10 10 8 8 9 unit Note 7/14 FEDD51V4400E-01 MSM51V4400E Notes: 1. A start-up delay of 200s is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. The AC characteristics assume tT = 5ns. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. This parameter is measured with a load circuit equivalent to 1 TTL load and 100pF. The output timing reference levels are VOH = 2.0V (IOH = -2mA) and VOL = 0.8V (IOL = 2mA) Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieved the open circuit condition and are not referenced to output voltage levels. tRCH or tRRH must be satisfied for a read cycle. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.), tRWD tRWD(Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 2. 3. 4. 5. 6. 7. 8. 9. 10. These parameters are referenced to the CAS, leading edges in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet in a 2-bit parallel test function. CA0 is not used. In read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 12. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 8/14 FEDD51V4400E-01 MSM51V4400E Timing Chart * Read Cycle RAS VIH VIL tCRP tRCD tRAD tRC tRAS tRP tCSH tRSH tCAS tRAL tASR tRAH tASC tCAH tCRP CAS VIH VIL Address VIH VIL VIH VIL VIH VIL Row Column tRCS tAA tROH tOEA tCAC tRAC tRRH tRCH WE OE tOFF tOEZ DQ VOH VOL tCLZ Open Valid Data-out "H" or "L" * Write Cycle (Early Write) RAS VIH VIL tCRP tRCD tRAD tRC tRAS tRP tCSH tRSH tCAS tRAL tASR tRAH tASC tCAH Column tCRP CAS VIH VIL Address VIH VIL Row tCWL tWCS tWP tWCH WE VIH VIL VIH VIL VIH VIL tRWL OE tDS tD Open DQ Valid Data-in "H" or "L" 9/14 FEDD51V4400E-01 MSM51V4400E * Read Modify Write Cycle tRWC RAS VIH VIL tCRP CAS VIH VIL tASR Address VIH VIL tRAD tRAH tASC Column tRAS tRP tCSH tRCD tRSH tCAS tCWL tRWL tCRP tCAH Row tRCS tRWD tCWD tWP tAWD WE VIH VIL VIH VIL tRAC tCLZ tCAC tOEZ Valid Data-out tAA tOEA tOED tOEH OE tD tDS Valid Data-in DQ VI/OH VI/OL "H" or "L" 10/14 FEDD51V4400E-01 MSM51V4400E * Fast Page Mode Cycle tRASP RAS VIH VIL tCRP CAS VIH VIL tASR Address VIH VIL VIH VIL VIH VIL tRAC tCAC DQ VOH VOL tCLZ tCPA tOFF tOEZ Valid Data-out tRP tPC tRHCP tCP tCAS tRSH tCAS tRAL tASC Column tRCD tCAS tRAD tCSH tRAH tASC tCP tCRP tCAH tASC tCAH tCAH Row Column Column tRCS WE tAA tRCH tAA tOEA tRCS tRCH tAA tRCS tRCH tOEA tCPA tOFF tOEZ Valid Data-out tOEA tRRH OE tCAC tCLZ tCAC tCLZ tOEZ Valid Data-out tOFF "H" or "L" * Fast Page Mode Write Cycle (Early Write) tRASP RAS VIH VIL VIH VIL tASR Address VIH VIL Row tRP tPC tRHPC tCP tCAS tRSH tCAS tRAL tCAH Column tCRP tRCD tCAS tRAD tRAH tASC tCSH tCAH tCP tCRP CAS tASC tCAH tASC Column Column tCWL tWCS tWCH tWP tD Valid Data-in tCWL tWCS tWCH tWP tD Valid Data-in tCWL tRWL tWCS tWP tWCH WE VIH VIL tDS tDS tDS Valid Data-in tD DQ VIH VIL Note: OE = "H" or "L" "H" or "L" 11/14 FEDD51V4400E-01 MSM51V4400E * Fast Page Mode Read Modify Write Cycle tRASP RAS VIH VIL VIH VIL tRAH tASR Address VIH VIL Row tCSH tRCD tRAD tASC Column tPRWC tCAS tCP tCAS tCAH tCAH tCWL tASC tCWL Column Column tRSH tCP tCAS tCAH tASC tCRP tRP CAS tRAL tRCS WE VIH VIL tRAC tAA tRWD tCWD tAWD tWP tDH tDS tOEA tRCS tCPWD tCWD tAWD tCPA tAA tOEA tOED tOEZ Out tCLZ In tCLZ tWP tDS tD tAA tRCS tCPWD tCWD tAWD tROH tCPA tOEA tOED tOEZ Out In tCWL tRWL tWP tD tDS OE VIH VIL tCAC VI/OH VI/OL tCLZ tOED tOEZ Out In tCAC tCAC DQ Note: In = Valid Data-in, Out = Valid Data-out "H" or "L" * RAS-only Refresh Cycle tRC RAS VIH VIL tCRP CAS VIH VIL VIH VIL VOH VOL tAS tRA tRPC tRAS tRP Address Row tOFF Open DQ Note: WE, OE = "H" or "L" "H" or "L" 12/14 FEDD51V4400E-01 MSM51V4400E * CAS before RAS Refresh Cycle tRP RAS VIH VIL tRPC tCP tCSR tCHR tWR tWR tRAS tRC tRP tRPC CAS VIH VIL VIH VIL VOH VOL tOFF tWR WE DQ Open Note: WE, OE, Address = "H" or "L" "H" or "L" * Hidden Refresh Read Cycle tRC RAS VIH VIL VIH VIL tASR Address VIH VIL VIH VIL tRAL tAA tROH OE VIH VIL VOH VOL Open tRAS tCRP tRCD tRAD tRAH Row tRC tRAS tRSH tRP tCHR tRP CAS tASC Column tCAH tRCS WE tCAC tRRH tOFF tOEA tRAC tCLZ Valid Data-out "H" or "L" tOEZ DQ 13/14 FEDD51V4400E-01 MSM51V4400E * Hidden Refresh Write Cycle tRC RAS VIH VIL VIH VIL tASR Address VIH VIL VIH VIL VIH VIL VIH VIL tDS tD tRAD tRAH Row tRC tRAS tRSH tRP tCHR tRP tRAS tCRP tRCD CAS tASC tRAL tCAH Column tWCS WE tWCH tWP tWR tWR OE DQ Valid Data-in "H" or "L" * Test Mode Initiate Cycle tRC tRP RAS VIH VIL VIH VIL tWTS WE VIH VIL VIH VIL tOFF Open Note: OE, Address = "H" or "L" "H" or "L" tRAS tRPC tCP tCSR tCHR CAS tWTH DQ 14/14 |
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