View APL5312-17BI-TR_643032.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

APL5312
Ultra-Low-Noise, High PSRR, Low-Dropout, 300mA Linear Regulator
Features
* * * * * * * * * * * * * Wide Operating Voltage: 2.3V~6V Low Dropout Voltage: 290mV @ 3V/300mA Fixed Output Voltages: 1.5V~3.5V with step 100mV, 2.85V Guaranteed 300mA Output Current High PSRR: 74dB before 10KHz Low Output Noise: 36VRMS at 100Hz to 100KHz Current Limit Protection Controlled Short Circuit Current: 50mA Over Temperature Protection Stable with 1F Capacitor for Any Load Excellent Load/Line Transient SOT23-5 and SC70-5 Packages Lead Free Available (RoHS Compliant)
General Description
The APL5312 is a ultra low noise, low dropout linear regulator, which operate from 2.3V to 6V input voltage and deliver up to 300mA. Typical dropout voltage is only 290mV at 300mA loading. Designed for use in RF applications, the high PSRR 74dB and low noise 36VRMS makes it an ideal choice. Design with an internal P-channel MOSET pass element, the APL5312 maintain a low supply current, independent of the load current and dropout voltage. Other features include thermal-shutdown protection and current limit protection to ensure specified output current and controlled short-circuit current. The APL5312 regulator come in a miniature SOT23-5 and SC70-5 package.
Pin Configuration
SOT23-5/ SC70-5 V IN 1 2 3 4 BP 5 V OUT
Applications
* * * * Cellular Phones Portable and Battery-Powered Equipment Wireless LANs GPS
GND SHDN
APL5312
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Sep., 2005 1 www.anpec.com.tw
APL5312
Ordering and Marking Information
APL5312
Lead Free Code Handling Code Temp. Range Package Code Voltage Code Package Code B : SOT23-5 S5 : SC70-5 Operating Ambient Temp. Range I : -40 to 85 C Handling Code TR : Tape & Reel Voltage Code 15 : 1.5V 30 : 3.0V Lead Free Code L : Lead Free Device Blank : Original Device
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature.
SOT23-5 packages
Product Name Marking Product Name Marking Product Name Marking Product Name Marking APL5312-15/B 339X APL5312-16/B 33AX APL5312-17/B 33BX APL5312-18/B 33CX APL5312-19/B 33DX APL5312-20/B 33EX APL5312-21/B 33FX APL5312-22/B 33GX APL5312-23/B 33HX APL5312-24/B 33IX APL5312-25/B 33JX APL5312-26/B 33KX APL5312-27/B 33LX APL5312-28/B 33MX APL5312-29/B 33NX APL5312-30/B 33OX APL5312-31/B 33PX APL5312-32/B 33QX APL5312-33/B 33RX APL5312-34/B 33SX APL5312-35/B 33TX APL5312-285/B 33X
SC70-5 packages
Product Name Marking Product Name Marking APL5312-15/S5 339 APL5312-16/S5 33A APL5312-19/S5 33D APL5312-20/S5 33E APL5312-23/S5 33H APL5312-24/S5 33I APL5312-27/S5 33L APL5312-28/S5 33M APL5312-31/S5 33P APL5312-32/S5 33Q APL5312-35/S5 33T APL5312-285/S 33 5 Product Name Marking Product Name Marking APL5312-17/S5 33B APL5312-18/S5 33C APL5312-21/S5 33F APL5312-22/S5 33G APL5312-25/S5 33J APL5312-26/S5 33K APL5312-29/S5 33N APL5312-30/S5 33O APL5312-33/S5 33R APL5312-34/S5 33S
Pin Description
PIN No. 1 2 3 4 5 Name VIN GND SHDN BP VOUT I/O I I I O Description Voltage supply input pin GND pin Shutdown control pin, low = off, high = normal Bypass signal pin in fixed output type device Regulator output pin
2 www.anpec.com.tw
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Sep., 2005
APL5312
Block Diagram
VIN Thermal Shutdown & Current Limit
SHDN
Shutdown
BP
VREF
_
MOS Driver
+
VOUT
GND
Absolute Maximum Ratings
Symbol VIN, VOUT Parameter Input Voltage or Out Voltage Thermal Resistance-Junction to Ambient (Note) SOT23-5 SC70-5 Power Dissipation, TA = 25X (Note) C SOT23-5 SC70-5 Operating Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10 second) Rating 6.5 6.5 240 325 410 310 0 to 125 -65 to +150 260 Unit V V X /W C
SHDN/BP VOUT Shutdown Control Pin/Bypass Signal Pin RTH,JA
PD TJ TSTG TL
mW X C X C X C
Note: When mounted on a (Copper foil area 50%, 45x45x1.6tmm) glass epoxy board.
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Sep., 2005
3
www.anpec.com.tw
APL5312
Electrical Characteristics
Unless otherwise noted these specifications apply over full temperature, VIN = VOUT+1V, CIN = COUT = 1 F,
TA = -40 to 85C .Typical values refer to TA = 25C.
Symbol VIN VOUT ILIMIT IQ IOUT
Parameter Input Voltage Output Voltage Accuracy Output Voltage Range Circuit Current Limit Quiescent Current Load Current VIN = 5V
Test Condition
APL5312 Min. 2.3 -2 1.5 450 500 120 120 300 0.1 0.8 520 430 290 73 74 55 50 36 1.6 -0.3 0.1 0.1 100 160 20 100 1 0.025 1 VIN+0.3 0.4 1 1 Typ. Max. 6 2 3.5 550 160 160 0.3 1.5 680 560 380
Unit V % V mA A mA % %
IOUT = 0mA IOUT = 300mA VOUT+0.5VREGLINE Line Regulation REGLOAD Load Regulation
VDROP
Dropout Voltage (Note)
mV
PSRR
Ripple Rejection
dB
ISHORT
Short Current Noise High Threshold Voltage Low Threshold Voltage
mA VRMS V A A S X C X C ppm/ X C F
en
VSHDN ISHDN IQSHDN TEXIT OTS
Shutdown Input Bias Current VSHDN = VIN SHDN = Low, Shutdown Supply Current VIN = VOUT+1V Shutdown Exit Delay VOUT = 90%, RLOAD = 50 Over Temperature Shutdown Over Temperature Shutdown Hysteresis Output Voltage Temperature TJ = -40~125X C Coefficient Output Capacitor ESR
TC
COUT
Note: Dropout voltage definition: VIN-V OUT when V OUT is 2% below the value of VOUT for VIN= VOUT +1V.
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Sep., 2005 4 www.anpec.com.tw
APL5312
Typical Application Circuit
VIN SHDN CIN 1 F GND
V OUT BP C OUT CBP 10 nF 1 F
Typical Characteristics
Quiescent Current vs. Ambient Temperature
125 180 160 140 120
Quiescent Current vs. Output Current
Quiescent Current (uA)
Quiescent Current (uA)
120
115
VIN=5.5V
110
VIN=4.5V
100 80 60
105
100 -40 -15 10 35 60 85
0
50
100
150
200
250
300
Ambient Temperature (C)
Output Current (mA)
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Sep., 2005
5
www.anpec.com.tw
APL5312
Typical Characteristics (Cont.)
Quiescent Current vs. Input Voltage
200 180 400 350
Dropout Voltage vs.Output Current
VOUT=2.5V
300 250 200 150 100 50 0
Quiescent Current (uA)
160 140 120 100 80 60 40 20 0 0 1 2 3 4 5 6
IOUT=0mA
Droput Voltage (mv)
TA=85C
TA=25C
0
50
100
150
200
250
300
Input Voltage (V)
Output Current (mA)
Dropout Voltage vs. Output Current
600 500
Load Transient
Dropout Voltage (mV)
400 300 200 100 0 0 50 100
VOUT=1.5V
VOUT(50mv/div)
VOUT=2.2V
IOUT(1~300mA) Tr=1S
VOUT=3.3V
150
200
250
300
Output Current (mA)
Time (0.1ms/div)
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Sep., 2005
6
www.anpec.com.tw
APL5312
Typical Characteristics (Cont.)
Line Transient
Exiting Shutdown Waveform
IOUT=100mA CBP=10nF
VIN=4.5V~5.5V
SHDN(1V/div)
VOUT(50mv/div) IOUT=10mA
VOUT(1V/div)
Time (0.1ms/div)
Time (50us/div)
Entering Shutdown Delay
140
Shutdown Exit Delay
Shutdown Exit Delay (uS)
IOUT=100mA CBP=10nF
120 100 80 60 40 20 0 1.5 1.8 2.1 2.4 2.7 3 3.3
CBP=10nF
SHDN(1V/div)
VOUT(1V/div)
Time (0.1ms/div)
Output Voltage (V)
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Sep., 2005
7
www.anpec.com.tw
APL5312
Typical Characteristics (Cont.)
PSRR vs. Frequency
-0 2 -0 3 T
Current Limit vs. Input Volatge
560 540
IOUT=10mA
Current Limit (mA)
-0 4
520 500 480 460 440 420 400
TA=25 C
PSRR (dB)
-0 5 -0 6 -0 7 -0 8 -0 9 -0 10 -1 10 2 0 10 0 1 k 10k 10 20 0k 0k
VIN=5V
TA=85 C
VIN=4.5V
4
4.5
5
5.5
6
Frequency (Hz)
Input Voltage (V)
Output Noise vs. BP Capacitance
160 140
Maximun Power Dissipation vs. Ambient Temperature Maximum Power Dissipation (mW)
450 400 350 300 250 200 150 100 50 0 0 25 50 75 100 125 SC70-5 SOT23-5
Output Noise (VRMS)
120 100 80 60
IOUT=100mA
40 20 0 1 10 100
IOUT=10mA
BP Capacitance (nF)
Ambient Temperature (C)
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Sep., 2005
8
www.anpec.com.tw
APL5312
Typical Characteristics (Cont.)
Region of Stable COUT ESR vs. Load Current
100
10
COUT ESR ()
Instable
1
VOUT=2.5V CIN=COUT=1uF,Y5V
0.1
Stable Instable
50 100 150 200 250 300
0.01 0
Output Current (mA)
Application Information
Output Voltage Selection The APL5312 are supplied with factory-set output voltages from 1.5V to 3.5V. Capacitor Selection and Regulation Stability The APL5312 uses at least a 1F capacitor on the input. This capacitor can use Aluminum, Tantalum or Ceramic capacitors. Input capacitor with large value and low ESR provides better PSRR and line-transient response. The output capacitor also can use Aluminum, Tantalum or Ceramic capacitor, and its proper values is at least 1F, ESR must be above 25m. Large output capacitor values can reduce noise and improve load-transient response, stability, and PSRR. With X5R and Y5V dielectrics, 1F is sufficient at all operating temperatures. The selection of output capacitor' is s important because it with COUT form a zero to provide the sufficient phase margin (see the Figure COUT ESR
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Sep., 2005 9
vs. Load Current). Bypass Capacitor Use a 10nF bypass capacitor at BP for low-output voltage noise. The leakage current going into the BP pin should be less than 10nA. Increasing the capacitance slightly decreases the output noise. Value above 0.1F and below 1nF are not recommended (see the Figure Output Noise vs. BP Capacitance). Noise, PSRR, and Load-Transient Response The APL5312 is designed to deliver ultra-low noise and high PSRR, as well as low dropout and low quiescent currents in battery-powered systems. When operating from sources other than batteries, improve PSRR and transient response can be achieved by increasing input and output capacitors, and bypass capacitor to from the passive filtering
www.anpec.com.tw
APL5312
Application Information (Cont.)
Noise, PSRR, and Load-Transient Response (Cont.) techniques (see the Figure Output Noise vs. BP Capacitance). Shutdown The APL5312 has an active high enable function. Force SHDN high (>1.6V) enables the VOUT, SHDN low (<0.4V) disables the VOUT. Enter the shutdown mode, it also causes the output voltage to discharge through a 500 resistance to ground. In shutdown mode, the quiescent current can reduce to 0.1uA. The SHDN pin cannot be floating, a floating SHDN pin may cause an indeterminate state on the output. If it is no use, connect to V IN for normal operation. Input-Output (Dropout) Voltage The minimum input-output voltage differential (dropout) determines the lowest usable supply voltage. The dropout voltage is a function of drain-to-source on resistance multiplied by the load current. Current Limit APL5312 includes a current-limit circuitry for linear regulator. The current limit protection, which sense the current flows the P-channel MOSFET, and controls the output voltage. The point where limiting occurs is IOUT = 500mA . The output can be shorted to ground for an indefinite amount of time without damaging to the part. Thermal Protection Thermal protection limits total power dissipation in the APL5312. When the junction temperature exceeds TJ = +160C, the thermal sensor generate a logic signal to turn off the pass element and let IC to cool. When the IC' junction temperature cools by 20C, s the thermal sensor will turn the pass element on again, resulting in a pulsed output during continuous thermal
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Sep., 2005 10
protection. Thermal protection is designed to protect the IC in the event of fault conditions. Operating Region and Power Dissipation The thermal resistance of the case and circuit board, ambient and junction air temperature, and the rate of air flow all control the APL5312' maximum power s dissipation. The power dissipation across the device is P = I OUT (VIN-VOUT). The maximum power dissipation is: PMAX = (TJ - TA) / (JC + CA ) JA = JC + CA where T J - TA is the temperature difference between the junction and ambient air. JC is the thermal resistance of the package, CA is the thermal resistance through the printed circuit board, copper traces, and other materials to the surrounding air, JA = is the thermal resistance between Junction and ambient air. For continual operation, do not exceed the absolute maximum junction Temperature rating of TJ = 125C. For example: The SOT23-5 package has maximum power dissipation 300mW at TA= 55C, relatively 225mW at SC70-5 package (see the Figure Maximum Power Dissipation vs. Ambient Temperature). VIN = 5V, IOUT = 250mA, VOUT = 3.3V, PD = (5-3.3)V x 150mA = 255mW According the power dissipation issue, we should adapt the SOT23-5 package. It could reduce the thermal resistance to maintain the IC longer life. The GND pin provides an electrical connection to ground and channeling heat away. The printed circuit board (PCB) forms a heat sink and dissipates most of the heat into ambient air.
www.anpec.com.tw
APL5312
Packaging Information
SOT-23-5
e1
5
4 E1 E
1
2
3
e
b
D
A2
A
a
L1
A1
L2
L
Dim A A1 A2 b D E E1 e e1 L L1 L2 a
Millimeters Min. 0.95 0.05 0.90 0.35 2.8 2.6 1.5 0.95 1.90 0.35 0.20 BSC 0.5 0 0.7 10
11
Inches Max. 1.45 0.15 1.30 0.55 3.00 3.00 1.70 Min. 0.037 0.002 0.035 0.0138 0.110 0.102 0.059 0.037 0.075 0.55 0.014 0.008 BSC 0.020 0 0.028 10
www.anpec.com.tw
Max. 0.057 0.006 0.051 0.0217 0.118 0.118 0.067
0.022
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Sep., 2005
APL5312
Packaging Information
SC70-5
D e1 c e L
E1
E
c1
L1 b A1 C 0.20
A2
A
Symbol A A1 A2 b c D E E1 e e1 L L1 1
Dimensions In Millimeters Min. Max. 0.80 1.10 0.00 0.10 0.80 1.00 0.15 0.30 0.08 0.25 1.90 2.15 1.15 1.35 2.00 2.20 0.65TYP 1.20 1.40 0.53REF 0.26 0.46 0 8 4 10
Dimensions In Inches Min. Max. 0.031 0.043 0.000 0.004 0.031 0.039 0.008 0.012 0.003 0.010 0.074 0.084 0.045 0.053 0.078 0.086 0.026TYP 0.047 0.055 0.021PEF 0.010 0.018 0 8 4 10
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Sep., 2005
12
www.anpec.com.tw
APL5312
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
TP
(IR/Convection or VPR Reflow)
tp Critical Zone T L to T P
Ramp-up
Temperature
TL Tsmax
tL
Tsmin Ramp-down ts Preheat
25
t 25 C to Peak
Time
Classification Reflow Profiles
Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3C/second max. 100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds Pb-Free Assembly 3C/second max. 150C 200C 60-180 seconds 217C 60-150 seconds See table 2 20-40 seconds
6C/second max. 6C/second max. 6 minutes max. 8 minutes max. Time 25C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface.
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Sep., 2005 13 www.anpec.com.tw
APL5312
Classification Reflow Profiles(Cont.)
Table 1. SnPb Entectic Process - Package Peak Reflow Temperature s Package Thickness Volume mm 3 Volume mm 3 <350 350 <2.5 mm 240 +0/-5C 225 +0/-5C 2.5 mm 225 +0/-5C 225 +0/-5C
Table 2. Pb-free Process - Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0C* 260 +0C* 260 +0C* 1.6 mm - 2.5 mm 260 +0C* 250 +0C* 245 +0C* 2.5 mm 250 +0C* 245 +0C* 245 +0C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level.
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C, 5 SEC 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1 tr > 100mA
Carrier Tape
t P P1 D Po E
F W
Bo
Ao
Ko D1
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Sep., 2005
14
www.anpec.com.tw
APL5312
Carrier Tape (Cont.)
T2
J C A B
T1
Application
A 1781
B 72 1.0 D 1.5 +0.1 B
C
J
T1 8.4 2 P1
T2 1.5 0.3 Ao
13.0 + 0.2 2.5 0.15 D1 1.5 +0.1 C Po
W 8.0+ 0.3 - 0.3 Bo
P 4 0.1 Ko 1.4 0.1 P 4 0.1 Ko
E 1.75 0.1 t 0.20.03 E 1.75 0.1 t
SOT23-5
F 3.5 0.05
4.0 0.1 2.0 0.1 3.15 0.1 3.2 0.1 J T1 T2 2.8 0.2 Ao W 8.0+ 0.3 - 0.1 Bo
Application
A 1781
14.4 0.4 13.0 + 0.2 1.15 0.1 12. 0.2 D D1 Po P1
SC70-5
F
3.5 0.05 1.55 0.05 1.00 +0.25 4.0 0.1 2.0 0.05 2.4 0.1
2.4 0.1 1.19 0.1 0.250.013
(mm)
Cover Tape Dimensions
Application SOT23-5 SC70-5 Carrier Width 8 8 Cover Tape Width 5.3 5.3 Devices Per Reel 3000 3000
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Sep., 2005 15 www.anpec.com.tw

▲Up To Search▲

Price & Availability of APL5312-17BI-TR

	To Download APL5312-17BI-TR Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .