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HANBit
HMD8M36M24EG
32Mbyte(8Mx36) 72-pin EDO with Parity MODE 2K Ref. SIMM Design 5V Part No. HMD8M36M24EG
GENERAL DESCRIPTION
The HMD8M36M24EG is a 8M x 36bit dynamic RAM high density memory module. The module consists of twenty four CMOS 4M x 4bit DRAM in 24-pin SOJ packages mounted on a 72 -pin, double-sided, FR-4-printed circuit board. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM components. The module is a single In-line Memory Module with edge connections and is intended for mounting in to 72 -pin edge connector sockets. All module components may be powe red from a single 5V DC power supply and all inputs and outputs are TTL -compatible.
FEATURES
w Part Identification HMD8M36M24E---- 2048 Cycles/32ms Ref. Solder HMD8M36M24EG- 2048 Cycles/32ms Ref. Gold w Access times : 50, 60ns w High-density 32MByte design w Single + 5V 0.5V power supply w JEDEC standard PDpin and pinout w EDO mode operation w TTL compatible inputs and outputs w FR4-PCB design PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 60ns NC Vss Vss NC 19 20 21 22 23 24 SYMBOL Vss DQ0 DQ18 DQ1 DQ19 DQ2 DQ20 DQ3 DQ21 Vcc NC A0 A1 A2 A3 A4 A5 A6 A10 DQ4 DQ22 DQ5 DQ23 DQ6
PIN ASSIGNMENT
PIN 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SIMM TRC 90ns 110ns tHPC 26ns 30ns SYMBOL DQ24 DQ7 DQ25 A7 A11 Vcc A8 A9 NC NC DQ26 DQ8 DQ17 DQ35 Vss /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 /RAS1 NC /WE NC TOP VIEW PIN 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 SYMBOL DQ9 DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 Vcc DQ32 DQ14 DQ33 DQ15 DQ34 DQ16 NC PD1 PD2 PD3 PD4 NC Vss
OPTIONS
w Timing 50ns access 60ns access w Packages 72-pin SIMM
MARKING
-5 -6 M
PRESENCE DETECT PINS
Pin PD1 PD2 PD3 PD4 50ns NC Vss Vss Vss
PERFORMANCE RANGE
Speed 5 6 tRAC 50ns 60ns tCAC 13ns 15ns
URL:www.hbe.co.kr REV.1.0 (March.2004)
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FUNCTIONAL BLOCK DIAGRAM
/RAS0 /RAS1 DQ[0-3] A[0-11] /CAS0 /WE /RAS DQ[0-3] A[0-11] /CAS /WE /OE /RAS DQ[0-3] A[0-11] /CAS /WE /OE /RAS DQ0 A[0-11] /CAS /WE /OE /RAS DQ[0-3] A[0-11] /CAS /WE /OE /RAS DQ[0-3] A[0-11] /CAS /WE /OE /RAS DQ0 A[0-11] /CAS /WE /OE DQ[18-21] A[0-11] /CAS2 /WE /RAS DQ[0-3] A[0-11] /CAS /WE /OE /RAS DQ[0-3] A[0-11] /CAS /WE /OE /RAS DQ0 A[0-11] /CAS /WE /OE
HMD8M36M24EG
U1
U13
U2
/RAS DQ[0-3] A[0-11] /CAS /WE /OE /RAS DQ[0-3] A[0-11] /CAS /WE /OE /RAS DQ0 A[0-11] /CAS /WE /OE
U14
DQ[4-7] A[0-11] /CAS0 /WE
U3
U15
DQ[22-25] A[0-11] /CAS2 /WE
U4
U16
DQ8 A[0-11] /CAS0 /WE
U9
U21
DQ26 A[0-11] /CAS2 /WE
U11
U23
DQ[9-12] A[0-11] /CAS1 /WE
/RAS DQ[0-3] A[0-11] /CAS /WE /OE /RAS DQ[0-3] A[0-11] /CAS /WE /OE /RAS DQ0 A[0-11] /CAS /WE /OE
U5
/RAS DQ[0-3] A[0-11] /CAS /WE /OE /RAS DQ[0-3] A[0-11] /CAS /WE /OE /RAS DQ0 A[0-11] /CAS /WE /OE
U17
DQ[27-30] A[0-11] /CAS3 /WE
/RAS DQ[0-3] A[0-11] /CAS /WE /OE /RAS DQ[0-3] A[0-11] /CAS /WE /OE /RAS DQ0 A[0-11] /CAS /WE /OE
U6
/RAS DQ[0-3] A[0-11] /CAS /WE /OE /RAS DQ[0-3] A[0-11] /CAS /WE /OE /RAS DQ0 A[0-11] /CAS /WE /OE
U18
DQ[13-16] A[0-11] /CAS1 /WE
U7
U19
DQ[31-34] A[0-11] /CAS3 /WE
U8
U20
DQ17 A[0-11] /CAS1 /WE
U10
U22
DQ35 A[0-11] /CAS3 /WE
U12
U24
URL:www.hbe.co.kr REV.1.0 (March.2004)
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Absolute Maximum Ratings
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature SYMBOL VIN ,OUT Vcc PD TSTG
HMD8M36M24EG
RATING -1V to 7.0V -1V to 7.0V 18W -55oC to 150oC
Short Circuit Output Current IOS 50mA w Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the o perational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( Voltage reference to V SS, TA=0 to 70 o C ) PARAMETER Supply Voltage Ground Input High Voltage Input Low Voltage SYMBOL Vcc Vss VIH VIL MIN 4.5 0 2.4 -1.0 TYP. 5.0 0 MAX 5.5 0 Vcc+1 0.8 UNIT V V V V
DC AND OPERATING CHARACTERISTICS
SYMBOL ICC1 SPEED -5 -6 ICC2 ICC3 Don't care -5 -6 ICC4 -5 -6 ICC5 ICC6 Don't care -5 -6 Il(L) IO(L) VOH VOL ICC1 : Operating Current * (/RAS , /CAS , Address cycling ICC2 : Standby Current ( /RAS=/CAS=V IH ) ICC3 : /RAS Only Refresh Current * ( /CAS=V IH, /RAS, Address cycling @t RC=min ) ICC4 : EDO Mode Current * (/RAS=V IL, /CAS, Address cycling @t PC=min )
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MIN -80 -10 2.4 @t RC=min.)
MAX 816 736 32 816 736 896 816 16 816 736 80 10 0.4
UNITS mA mA mA mA mA mA mA mA mA mA mA mA V V
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ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @t RC=min ) IIL : Input Leakage Current (Any input 0V VIN 6.5V, all other pins not under test = 0V) IOL : Output Leakage Current (Data out is disabled, 0V VOUT 5.5V VOH : Output High Voltage Level (I OH= -5mA ) VOL : Output Low Voltage Level (I OL = 4.2mA )
HMD8M36M24EG
* NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. I CC is specified as an average current. In I CC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle.
CAPACITANCE
( TA=25 C, Vcc = 5V, f = 1Mz ) SYMBOL CIN1 C IN2 CIN3 CIN4 CDQ1
o
o
DESCRIPTION Input Capacitance (A0-A11) Input Capacitance (/W) Input Capacitance (/RAS0) Input Capacitance (/CAS0-/CAS3) Input/Output Capacitance (DQ0-31)
MIN -
MAX 100 130 40 30 20
UNITS pF pF pF pF pF
AC CHARACTERISTICS
( 0 C TA 70oC , Vcc = 5V10%, See notes 1,2.) -5 MIN 90 50 13 25 3 3 2 30 50 13 38 8 20 15 5 0 10 0 10K 37 25 10K 13 50 3 3 2 40 60 15 45 10 20 15 5 0 10 0 10K 45 30 10K 13 50 MAX MIN 110 60 15 30 -6 MAX
STANDARD OPERATION Random read or write cycle time Access time from /RAS Access time from /CAS Access time from column addr ess /CAS to output in Low-Z Output buffer turn-off delay Transition time (rise and fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS to /CAS delay time /RAS to column address delay time /CAS to /RAS precharge time Row address set-up time Row address hold time Column address set-up time
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SYMBOL tRC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Column address hold time Column Address to /RAS lead time Read command set-up time Read command hold referenced to /CAS Read command hold referenced to /RAS Write command hold time Write command hold referenced to /RAS Write command pulse width Write command to /RAS lead time Write command to /CAS lead time Data-in set-up time Data-in hold time Refresh period Write command set-up time /CAS setup time (C-B-R refresh) /CAS hold time (C-B-R refresh) /RAS precharge to /CAS hold time Access time from /CAS precharge /CAS precharge time (Fast page) /RAS pulse width (Fast page ) /W to /RAS precharge time (C-B-R refresh) /W to /RAS hold time (C-B-R refresh) NOTES tWRH 10 10 tCAH tRAL tRCS tRCH tRRH tWCH tWCR tWP tRWL tCWL tDS tDH tREF tWCS tCSR tCHR tRPC tCPA tCP tRASP tWRP 8 50 10 200K 0 5 10 5 30 10 60 10 8 25 0 0 0 10 50 10 13 8 0 8 32 0 5 10 5 10 30 0 0 0 10 55 10 10 10 0 10
HMD8M36M24EG
ns ns ns ns ns ns ns ns ns ns ns ns 32 ns ns ns ns ns 35 ns ns 200K ns ns
ns
1.An initial pause of 200ms is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles
before proper device operation is achieved.
2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(min) and VIL(max) and are assumed to be 5ns for all inputs.
3.Measured with a load equivalent to 1TTL loads and 100pF 4.Operation within the t RCD(max) limit insures that t RAC(max) can be met. t RCD(max) is specified as a reference point only. If t RCD
is greater than the specified t RCD(max) limit, then access time is controlled exclusively by t CAC.
5.Assumes that t RCD tRCD(max)
6. tAR, tWCR, tDHR are referenced to t RAD(max) 7.This parameter defines the time at which the output achieves the open circuit conditi on and is not referenced to V OH or VOL. 8. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameter. They are included in the data sheet as electrical characteristic only. If t WCS tWCS(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. Either tRCH or tRRH must be satisfied for a read cycle. 10. These parameters are referenced to the /CAS leading edge in early write cycles and to the /W leading edge in read write cycles.
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HMD8M36M24EG
11. Operation within the t RAD(max) limit insures that t RAC(max) can be met. t RAD(max) is specified as a reference point only. If t RAD is greater than the specified t RAD(max) limit. then access time is controlled by t AA.
TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE
/RAS VIHVILtCRP /CAS VIHVILA VIHVIL/W VIHVIL/OE VIHVILDQ0-DQ7 V OHVOLOPEN
tRC tRAS tRCD tRAD tASR tRAH tASC tCAH
COLUMN ADDRESS
tRP
tCSH
tRSH tCAS tRAL
tCRP
ROW ADDRESS
tRCS tAA tOEA tCAC tRAC tCLZ
tRRH
tRCH tWEZ tCEZ
tOEZ
tREZ
DATA-OUT
TIMING WAVEFORM OF WRITE CYCLE (EARLY WRITE) NOTE : Dout = Open
tRC tRAS tCRP tRCD tRAD tASR tRAH tASC tCAH
COLUMN ADDRESS
/RAS
VIHVILVIHVIL-
tRP
tCSH
tRSH tCAS tRAL
tCRP
/CAS
A VIHVIL-
ROW ADDRESS
tCWL tRWL tWCS tWP tWCH
/W VIHVIL/OE VIHVILDQ0-DQ7
tDS VOHVOL-6DATA-IN
tDH
URL:www.hbe.co.kr REV.1.0 (March.2004)
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PACKAGING INFORMATION
SIMM Design (Front)
HMD8M36M24EG
0.25mm MAX
2.54 mm MAX
1.27 mm
Gold: 1.040.10 mm Solder: 0.9140.10 mm
(Solder & Gold Plating)
PCB Thickness : 1.27
0.10 mm
ORDERING INFORMATION
Part Number Density Org. Package Component Number 24EA 24EA Vcc Access Time
HMD8M36M24EG-5 HMD8M36M24EG-6
32MByte 32MByte
8MX 36bit 8MX 36bit
72Pin-SIMM 72Pin-SIMM
5V 5V
50ns 60ns
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