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STCCP27A
1.8V/2.8V High speed dual differential line receivers, Compact camera port decoder, I2C control line
Feature summary
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SUB-Low voltage differential signaling inputs: VID = 100mV with RT = 100, CL =10pF High signaling rate: fIN = 416MHz max (D+,D-, CLK+, CLK-) fOUT = 52MHz max (D1-D8, CLK) Very high speed: tpLH~tpHL=3.5ns (typ) at VDD=2.8V; VL=1.8V Operating voltage range: VDD(OPR) = 2.65V to 3.6V VL(OPR) =1.65V to 1.95V Symmetrical output impedance (D1-D8, H-SYNC, V-SYNC, CLK): IIOHI=IOL=8mA (min) at VDD=2.65V;VL=1.8V Low power dissipation (Disabled: EN=Gnd): ISOFF = IDD + IL = 10A (max) CMOS logic input threshold (EN, SYNC_SEL): VIL = 0.3xVDD; VDD =2.65V to 3.6V VIH = 0.7xVDD; VDD =2.65V to 3.6V Bidirectional level translator line (I/OVDD, I/OVL) for I2C communications: 400kHz max frequency IIOHI= 20A (min.) at VDD=2.8V;VL=1.8V IOL = 1 mA (min.) at VDD=2.8V;VL=1.8V 3.6V Tolerant on inputs (EN, SYNC_SEL) Leadfree TFBGA package (RoHS restriction of hazardous substances) .
TFBGA25
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Description
The STCCP27A receiver converts the subLVDS clock/datastream (up to 416 Mbps throughput bandwidth) back into parallel 8 bits of CMOS/ LVTTL. The device recognizes the CCP 32bit start of frame (SOF), end of frame (EOF), start of line (SOL) and end of line (EOL) sequences to generate the H-SYNC and V-SYNC signals. Output LVTTL clock (up to 52 MHz) is transmitted in parallel with data. Input and Output data are rising edge strobe. This chipset is an ideal means to link mobile camera modules to baseband processors. In order to minimize static current consumption, it is possible to shut down the device when the interface is not being used by a power-down (EN) pin that reduces to 10A the Maximum Current Consumption making this device ideal for portable applications like Mobile Phone, Portable Battery Equipment. Two dedicated I2C lines are provided to translate bidirectional controls from camera and C devices. The STCCP27A is offered in a TFBGA package to optimize PCB space. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity from transient excess voltage. The STCCP27A is characterized for operation over the commercial temperature range -40C to 85C.
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Order code
Part number STCCP27ATBR April 2006 Temperature Range -40 to 85 C Package TFBGA25 3x3mm (Tape & Reel) Rev. 1 Comments 3000 parts per reel 1/19
www.st.com 19
STCCP27A
Contents
1 2 3 4 5 6 7 Schematic diagram ......................................... 3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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STCCP27A
Schematic diagram
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Figure 1.
Schematic diagram
Simplified application block diagram
Figure 2.
Block diagram
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Schematic diagram Figure 3. Simplified I2C line block diagram
STCCP27A
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STCCP27A
Pin configuration
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Figure 4.
Pin configuration
Pin configuration (top through view - bumps are on the other side)
Table 1.
Pin n D5 E5 D4 E4 D2 E2 D1 E1 A2, A1 A5, A4 B3 D3 C3 B2 A3, E3 C5 B4 C1 B1, C2 B5, C4
Pin description
Symbol D1 D2 D3 D4 D5 D6 D7 D8 D+, DCLK+, CLKEN CLK H-SYNC V-SYNC GND VDD SYNC SEL VL I/OVL1, I/OVL2 I/OVDD1, I/OVDD2 Name and function Decoder Output (LSB) Decoder Output Decoder Output Decoder Output Decoder Output Decoder Output Decoder Output Decoder Output (MSB) Differential Data Receiver Inputs Differential CLK Receiver Inputs Receivers Enable Input Clock Output Horizontal Sync Output Vertical Sync Output Ground Main Supply Voltage Select Sync Input Secondary Supply Voltage I2C Line (VL Referred) I2C Line (VDD Referred)
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Pin configuration Table 2.
Input Enable SYNC_SEL L H H H H H X H H H H L D+ DCLK+ CLKV-SYNC L H L No change No change L X X X X SOF (FFH 00H 00H 02H) EOF(FFH 00H 00H 03H) SOL(FFH 00H 00H 00H) EOL(FFH 00H 00H 01H) X X X X
STCCP27A Main function table
Output H-SYNC L H L H L L D1-D8 L CLK L Function
CCP disabled Start of frame End of frame See detailed timing diagram Start of line End of line See Disabled sync detailed (D1-D8 will get out D+, Dtiming data, including diagram sync code)
Z = High Impedance, L = Low Voltage Level, H = High Voltage Level, X = Don't care
Table 3.
Enable X X X X
I2C Bus function table
I/O Input I/OVDD L VDD Open VDD I/OVL L VL VL Open Function I2C Comm. I2C Comm. I2C Comm. I2C Comm.
Open: If I/OVDD is not driven then the I/OVL will go in high level VL by embedded 10k pull-up resistor; If I/OVL is not driven then the I/OVCC will go in high level VDD by embedded 10K pull-up resistor
Figure 5.
Frame structure In VGA case (allowed synchronization codes sequence)
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STCCP27A
Maximum ratings
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Maximum ratings
Table 4. Absolute maximum ratings
Parameter Main supply voltage Secondary supply voltage SubLVDS data bus input voltage (D+, D-) SubLVDS clock bus input voltage (CLK+, CLK-) DC input voltage (SYNC_SEL, EN) DC output voltage (D1-D8, H-SYNC, V-SYNC, CLK, I/OVDD) DC output voltage (I/OVL) Storage temperature range Electrostatic discharge protection HBM Human body model (all pins) Value -0.5 to 4.6 -0.5 to 4.6 -0.5 to 4.6 -0.5 to 4.6 -0.5 to 4.6 -0.5 to (VDD + 0.5) -0.5 to (VL + 0.5) -65 to +150 2 Unit V V V V V V V C kV
Symbol VDD VL VD VCLK VI VO VI/OVL TSTG ESD
Note:
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. Table 5. Recommended operating conditions
Parameter Min. 2.65 1.65 0.1 0.5 Typ. 2.8 1.8 0.9 Max. 3.6 1.95 0.4 1.3 3.6 VDD VL 120 85 125 600 Unit V V V V V V V pF C C ns
Symbol VDD VL VID VCM VIC
Main supply voltage Secondary supply voltage Differential level input voltage (D+, D-, CLK1+, CLK1-) Common level input voltage (D+, D-, CLK1+, CLK1-) Level input voltage (SYNC_SEL, EN) VI/OVDD Level input voltage (I/OVDD) VI/OVL Level input voltage (I/OVL) RT Termination resistance (per pair differential input line) CL Termination capacitance (per line vs gnd pin) TA Operating ambient temperature range TJ Operating junction temperature range tR, tF Rise and fall time (I/OVDD, I/OVL; 10% to 90%; 90% to 10%)
80 -40 -40
100 10
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Electrical characteristics
STCCP27A
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Electrical characteristics
Table 6. Electrical characteristics (Over recommended operating conditions unless otherwise noted. All typical values are at TA = 25C, and VDD = 2.8V, VL = 1.8V)
Test conditions RT = 100 1% VI = 0.4V VI = 1.4V EN=VDD, I/OVL = VL, I/OVDD = VDD, D+, CLK+ = Gnd or VDD, D+, CLK+ = VDD or Gnd EN=Gnd, VDD=2.65V to 3.6V VL=1.65V to 1.95V VDD = 2.65V to 3.6V VL = 1.65V to 1.95V VDD = 2.65V to 3.6V VL = 1.65V to 1.95V VIH = 0.7xVDD VIL= 0.3xVDD IOH = -8mA IOH = -4mA IOL = +8mA VDD = 2.65V to 3.6V VL = 1.65V to 1.95V VDD = 2.65V to 3.6V VL = 1.65V to 1.95V VDD = 2.65V to 3.6V VL = 1.65V to 1.95V VDD = 2.65V to 3.6V VL = 1.65V to 1.95V IOH = -20A VI/OVDD = VDD IOH = -20A VI/OVL = VL IOL= +1mA, VI/OVLor VI/OVDD = Gnd 0.7xVL 0.7xVDD 0 0 VL-0.4 VDD-0.4 0.35 0.25 0.25 2.0 2.4 0.60 Min. 0.5 Typ. 0.9 Max. 1.3 10 10 3.6 7.0 Unit V A A mA
Symbol VCM II
Parameter Common mode input voltage (see fig.1) Input leakage current (D+, D-, CLK1+, CLK1-) Supply current (IL + IDD) Shutdown supply current (IL+ IDD) HIGH Level input voltage (SYNC_SEL, EN) LOW Level input voltage (SYNC_SEL, EN) HIGH Level input current (SYNC_SEL, EN) LOW Level input current (SYNC_SEL, EN) HIGH Level output voltage (D1-D8, H-SYNC, V-SYNC, CLK) LOW Level output voltage (D1-D8, H-SYNC, V-SYNC, CLK) HIGH Level input voltage (I/OVL1, I/OVL2) HIGH Level input voltage (I/OVDD1, I/OVDD2) LOW Level input voltage (I/OVL1, I/OVL2) LOW Level input voltage (I/OVDD1, I/OVDD2) HIGH Level output voltage (I/OVL1, I/OVL2) HIGH Level output voltage (I/OVDD1, I/OVDD2) LOW Level output voltage (I/OVL1, I/OVL2, I/OVDD1, I/OVDD2)
IS
ISOFF VIH VIL IIH IIL VOH
10 0.7xVDD 0 3.6 0.3xVDD 10 10
A V V A A V V V V V V V V V V
VOL
VIH2
VIL2
VOH2
VOL2
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STCCP27A Table 7.
Electrical characteristics Switching characteristics (RT = 100 1%, CL = 10pF, over recommended operating conditions unless otherwise noted. Typical values are referred to TA = 25C and VDD = 2.8V, VL = 1.8V)
Test conditions Min. Typ. 3.1 2.0 Max. 4.0 4.0 320 20 6.5 6.5 6.5 6.5 8.5 8.5 8.5 8.5 100 Unit ns ns ns ns ns ns ns ns ns
Symbol tr tf tr I/O tf I/O tpLH tpHL tpLH tpHL tpLH
Parameter Rise time LVTTL Output voltage (10% to 90%) Fall time LVTTL output voltage (90% to 10%) Rise time I2C input/output voltage (20% to 80%) Fall time I2C input/output voltage (80% to 20%) Propagation delay time (CLK to VSYNC, H-SYNC) (low to high) Propagation delay time (CLK to VSYNC, H-SYNC) (high to low) Propagation delay time (CLK to D1-D8) (low to high) Propagation delay time (CLK to D1-D8) (high to low) Propagation delay time I2C input/output voltage (50% to 50%) (Low to High) Propagation delay time I2C input/output voltage (50% to 50%) (High to Low) Enable delay time (EN to V-SYNC, H-SYNC: tPZL, tPZH) Disable delay time (EN to VSYNC, H-SYNC: tPLZ, tPHZ) Operating frequency
tpHL tEN tDIS
10 trEN = 2.0ns (10% to 90%) tfEN = 2.0ns (90% to 10%) trEN = 2.0ns (10% to 90%) tfEN = 2.0ns (90% to 10%) trD,CLK = 400ps (10% to 90%) tfD,CLK = 400ps (90% to 10%) VCM D,CLK = 0.9V, VDD,CLK = 150mV 20 1000
ns s ns
fOPR TCLK
1 2.4 0.6 1.0
416 1000
MHz ns ns ns
Clock Period Setup time (D to CLK) (low to high tSUD-CLK or high to low vs positive CLK edge) (note 1) (see fig. 6) Hold time (CLK to D) (positive CLK tHCLK-D edge to D) (note 1) (see fig. 6)
Note:
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50% VDIN to 50% VDOUT Table 8. Capacitive characteristics
Test condition Value TA = 25C Min. VL = 1.65V to 1.95V, VI = GND or VDD Typ. 3.5 Max. pF Unit
Symbol
Parameter Input Capacitance (SYNC_SEL, EN)
VDD (V) 2.65 to 3.6
CIN
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Timing diagram
STCCP27A
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Timing diagram
(unless otherwise specified TA = 25C)
Figure 6.
tSUD-CLK , tHCLK-D (Differential input signals D+,D- and CLK+,CLK-)
Figure 7.
Bit order in synchronization codes and data, LSB first (example start of frame), image frame structure
Note:
LSB (bytewise Least Significant Bit first)
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STCCP27A
Timing diagram
Figure 8.
Disabled sync mode free running clock IN (SYNC_SEL=GND) (D1-D8 will get out input data DIN, including sync code)
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Timing diagram
STCCP27A
Figure 9.
Enabled sync mode free running clock IN (SYNC_SEL=VDD) (D1-D8 will get out input data DIN only, excluding sync code)
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STCCP27A
Timing diagram
Figure 10. Enabled sync mode gated clock IN (SYNC_SEL=VDD) (D1-D8 will get out input data DIN only, excluding sync code)
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Timing diagram
STCCP27A
Figure 11. Enabled sync mode free running clock IN (SYNC_SEL=VDD) (D1-D8 will get out input data DIN only, excluding sync code
Figure 12. Disabled sync mode free running clock IN (SYNC_SEL=Gnd) (D1-D8 will get out input data DIN only, excluding sync code)
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STCCP27A
Package mechanical data
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Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Package mechanical data
STCCP27A
TFBGA25 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b D D1 E E1 e SE 2.9 0.78 0.25 2.9 0.30 3.0 2 3.0 2 0.5 0.25 3.1 114.2 1.0 TYP 1.1 MAX. 1.16 0.25 0.86 0.35 3.1 30.7 9.8 114.2 11.8 118.1 78.8 118.1 78.8 19.7 9.8 122.0 MIN. 39.4 TYP. 43.3 MAX. 45.7 9.8 33.9 13.8 122.0 mils
7539979/A
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STCCP27A
Package mechanical data
Tape & Reel TFBGA25 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 3.9 7.9 3.3 3.3 1.60 4.1 8.1 0.153 0.311 12.8 20.2 60 14.4 0.130 0.130 0.063 0.161 0.319 TYP MAX. 330 13.2 0.504 0.795 2.362 0.567 MIN. TYP. MAX. 12.992 0.519 inch
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Revision history
STCCP27A
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Table 9.
Date
Revision history
Revision history
Revision 1 Initial release. Changes
12-Apr-2006
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STCCP27A
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