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AX88172 L USB to Fast Ethernet/HomePNA Controller
USB to Fast Ethernet/HomePNA Controller
Document No.: AX172-4/ V1.4 / DEC, 20/02
Features
Single chip USB to 10/100Mbps Fast Ethernet and 1/10Mbps HomePNA and HomePlug Network Controller * Compliant with USB specification 1.0 and 1.1 and 2.0 * Full/High Speed USB Device with bus power capability * Support 4 endpoints on USB * IEEE 802.3u 100BASE-T, TX, and T4 Compatible * Embedded 7K*16 bit SRAM, 256*16 bit SRAM and 8 FIFOs * Support both full-duplex or half-duplex operation on Fast Ethernet * Provides a MII port for both Ethernet and HomePNA/ HomePlug PHY interface *
* * * * * * *
Supports suspended mode and remote wakeup (link_up or magic packet or external pin) Optional PHY power down mode for power saving Support (94c56/93c66) 256/512 bytes serial EEPROM (used for saving USB Descriptors) Support automatic loading of Ethernet ID, USB Descriptors and Adapter Configuration from EEPROM on power-on initialization External PHY loop-back diagnostic capability Small form factor with 80-pin LQFP package Single 12MHz clock input, pure 3.3V operation
*IEEE is a registered trademark of the Institute of Electrical and Electronic Engineers, Inc. *All other trademarks and registered trademark are the property of their respective holders.
Product description
The AX88172 USB to Fast Ethernet/HomePNA/HomePlug Controller is a high performance and highly integrated Controller with embedded 7K*16 bit SRAM. The AX88172 contains a USB interface to host CPU and compliant with USB Standard V1.0, V1.1 and V2.0. The AX88172 could be used for both 10M/100Mbps Fast Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard and 1M/10M HomePNA standard. The AX88172 supports media-independent interface (MII) to simplify the design on implementing Fast Ethernet and HomePNA functions.
System Block Diagram
RJ45 RJ11
MAGNETIC
MAGNETIC
10/100 Mbps Ethernet PHY/TxRx
1/10 Mbps Home LAN PHY
AX88172
EEPROM
USB I/F
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
Frist Released Date: Dec/20/2001
http://www.asix.com.tw
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C. FAX: 886-3-579-9558 TEL: 886-3-579-9500
AX88172
CONTENTS
PRELIMINARY
1.0 INTRODUCTION....................................................................................................................... 4 1.1 GENERAL DESCRIPTION:............................................................................................................. 4 1.2 AX88172 BLOCK DIAGRAM:...................................................................................................... 4 1.3 AX88172 PIN CONNECTION DIAGRAM....................................................................................... 5 2.0 SIGNAL DESCRIPTION........................................................................................................... 6 3.0 EEPROM MEMORY MAPPING............................................................................................ 9 4.0 USB COMMANDS ................................................................................................................... 11 4.1 USB STANDARD COMMANDS .................................................................................................... 11 4.2 USB VENDOR COMMANDS....................................................................................................... 12 5.0 USB CONFIGURATION STRUCTURE .............................................................................. 14 5.1 USB CONFIGURATION. ............................................................................................................. 14 5.2 USB INTERFACE....................................................................................................................... 14 5.3 USB ENDPOINTS. ..................................................................................................................... 14 6.0 ELECTRICAL SPECIFICATION AND TIMINGS ............................................................ 15 6.1 ABSOLUTE MAXIMUM RATINGS ............................................................................................... 15 6.2 GENERAL OPERATION CONDITIONS .......................................................................................... 15 6.3 DC CHARACTERISTICS ............................................................................................................. 15 6.4 A.C. TIMING CHARACTERISTICS............................................................................................... 16 6.4.1 12M_XIN ........................................................................................................................... 16 6.4.2 Reset Timing ...................................................................................................................... 16 6.4.3 MII Timing......................................................................................................................... 17 6.4.4 STATION MANAGEMENT TIMING................................................................................. 18 6.4.5 SERIAL EEPROM TIMING .............................................................................................. 19 7.0 PACKAGE INFORMATION.................................................................................................. 20 APPENDIX A: SYSTEM APPLICATIONS ................................................................................ 21 A.1 USB TO FAST ETHERNET CONVERTER .................................................................................... 21 A.2 USB TO FAST ETHERNET AND/OR HOMELAN COMBO SOLUTION ........................................... 21 DEMONSTRATION CIRCUIT A: AX88172 (ED2 VERSION) + ETHERNET PHY(8201L) ........................................................................................................................................................... 22 DEMONSTRATION CIRCUIT B: AX88172 (ED3 VERSION) + ETHERNET PHY (8201LBL) ........................................................................................................................................ 24 REMARK: ....................................................................................................................................... 26 REVISIONS HISTORY ................................................................................................................. 27
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AX88172 FIGURES
PRELIMINARY
FIG - 1 AX88172 BLOCK DIAGRAM ...................................................................................................................................4 FIG - 2 AX88172 PIN CONNECTION DIAGRAM ...................................................................................................................5
TABLES
TAB - 1 PIN SIGNALS ..........................................................................................................................................................8 TAB - 2 EEPROM MEMORY MAPPING ..............................................................................................................................9
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AX88172
PRELIMINARY
1.0 Introduction
1.1 General Description:
The AX88172 USB to Fast Ethernet Controller is a high performance and highly integrated USB bus Ethernet Controller with embedded 7K*16 bit SRAM. The AX88172 supported Full/High Speed USB Device with bus power capability. The AX88172 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3/ IEEE802.3u LAN standard. The AX88172 supports media-independent interface (MII) to simplify the design on implementing Fast Ethernet and HomePNA functions. AX88172 uses 80-pin LQFP low profile package, 12MHz operation for USB and 25MHz operation for Ethernet, CMOS process with pure 3.3V operation.
1.2 AX88172 Block Diagram:
MDC MDIO STA 7K* 16 SRAM Memory Arbiter
EECS EECK EEDI EEDO
SEEPROM Loader I/F
USB to Ethernet Bridge
MAC Core MII /IF
USB Core and Interface
DM/DP Fig - 1 AX88172 Block Diagram
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AX88172 1.3 AX88172 Pin Connection Diagram
The AX88172 is housed in the 80-pin plastic light quad flat pack.
PRELIMINARY
PHYRSTN
PHYRSTP
GPIO1
GPIO0
TEST0
GPIO2
TEST1
VDD
EEDI
EECS
EECK
EEDO
59
VSS
60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1
VSS
LED
VDD
NC
NC
NC
NC
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41 40 39 38 37 36 35
VDD RST_TYPE NC NC NC NC NC ANA_XIQ VDD CLKI TESTMODE RESET/RESET VSS VDD PVDD PVSS VC EPTEST XIN12M XOUT12M
VSS RXDV RXER VDD RXD3 RXD2 RXD1 RXD0 RXCLK VDD TXEN TXD3 TXD2 TXD1 TXD0 CRS TXCLK VBUS COL VDD
ASIX AX88172
ED3
34 33 32 31 30 29 28 27 26 25 24 23 22 21
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R1
AVDD
AVSS
AVSS
Fig - 2 AX88172 Pin Connection Diagram
DP
AVSS
DM
AVSS
AVDD
EXTWAKEUPN
NC
NC
NC
NC
NC
NC
VDD
MDC
MDIO
VSS
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AX88172
PRELIMINARY
2.0 Signal Description
The following terms describe the AX88172 pin-out: All pin names with the "/" suffix are asserted low. The following abbreviations are used in following Tables.
I O I/O OD
Input Output Input/Output Open Drain
TYPE I
PU PD P
Internal Pull Up (100K) Internal Pull Down (100K) Power Pin
SIGNAL R1
AVDD AVSS AVSS DP AVSS DM AVSS AVDD /EXTWAKEUP NC NC VDD MDC
MDIO
NC NC NC NC VSS VDD COL NC TX_CLK
CRS TXD[3:0]
PIN NO. DESCRIPTION 1 Constant-votage pin A 6.2K 1% resistors is connected to AVSS. Be sure to make the line between R1 and each resistor as short as possible. P 2 Power supply pin for analog circuits +3.3V DC P 3 Power supply pin for analog circuits Ground P 4 Power supply pin for analog circuits Ground B 5 USB data line Data+ P 6 Power supply pin for analog circuits Ground B 7 USB data line DataP 8 Power supply pin for analog circuits Ground P 9 Power supply pin for analog circuits +3.3V DC I/PU 10 Remote-wakeup trigger from external pin. It active low and should be keep low over 2 clocks (12MHz) B 11 For testing B 12 For testing P 13 Power Supply for logic circuits: +3.3V DC. O 14 Station Management Data Clock: The timing reference for MDIO. All data transfers on MDIO are synchronized to the rising edge of this clock. MDC is a 2.5MHz frequency clock output. I/O/PU 15 Station Management Data Input/Output: Serial data input/output transfers from/to the PHYs. The transfer protocol conforms to the IEEE 802.3u MII specification. O 16 For testing O 17 For testing O 18 For testing O 19 For testing P 20 Power Supply: +0V DC or Ground Power. P 21 Power Supply for logic circuits: +3.3V DC. I 22 Collision: this signal is driven by PHY when collision is detected. 23 No connection I 24 Transmit Clock: TX_CLK is a continuous clock from PHY. It provides the timing reference for the transfer of the TX_EN and TXD[3:0] signals from the MII port to the PHY. I 25 Carrier Sense: Asynchronous signal CRS is asserted by the PHY when either the transmit or receive medium is non-idle. O 29, 28, 27, Transmit Data: TXD[3:0] is transition synchronously with respect to 26 the rising edge of TX_CLK. For each TX_CLK period in which TX_EN is asserted, TXD[3:0] are accepted for transmission by the PHY.
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AX88172
TX_EN O 30
PRELIMINARY
VDD RX_CLK
RXD[3:0] VDD RX_ER
RX_DV
VSS VDD TEST0 TEST1 GPIO[2:0] /PHYRST PHYRST VSS NC NC LED
VDD NC NC EECS EECK EEDI EEDO VSS VDD RST_TYPE
NC ANA_XIQ
VDD CLKI TESTMODE
Transmit Enable: TX_EN is transition synchronously with respect to the rising edge of TX_CLK. TX_EN indicates that the port is presenting nibbles on TXD [3:0] for transmission. P 31 Power Supply for logic circuits: +3.3V DC. I 32 Receive Clock: RX_CLK is a continuous clock that provides the timing reference for the transfer of the RX_DV, RXD[3:0] and RX_ER signals from the PHY to the MII port of the MAC. I 36, 35, 34, Receive Data: RXD[3:0] is driven by the PHY synchronously with 33 respect to RX_CLK. P 37 Power Supply for logic circuits: +3.3V DC. I 38 Receive Error: RX_ER is driven by PHY and synchronous to RX_CLK, is asserted for one or more RX_CLK periods to indicate to the port that an error has detected. I 39 Receive Data Valid: RX_DV is driven by the PHY synchronously with respect to RX_CLK. Asserted high when valid data is present on RXD [3:0]. P 40 Power Supply: +0V DC or Ground Power. P 41 Power Supply for logic circuits: +3.3V DC. I/PU 42 Test Pin: This pin for test purpose only. Pull up the pin or keep no connection for normal operation. I/PU 43 Test Pin: This pin for test purpose only. Pull up the pin or keep no connection for normal operation. I/O/PU 46, 45, 44 General Purpose Input/ Output Pins. O 47 Output for reset PHY active low O 48 Output for reset PHY active high P 49 Power Supply: +0V DC or Ground Power. I/PD 50 For testing I/PD 51 For testing O 52 LED indicator: When link FS, drives logic high always. When link HS, the pin drives logic low. and it will drives high/low a period when line has activity (data transfer). P 53 Power Supply for logic circuits: +3.3V DC. I/PD 54 For testing ID 55 For testing O 56 EEPROM Chip Select: EEPROM chip select signal. O 57 EEPROM Clock: Signal connected to EEPROM clock pin. O 58 EEPROM Data In: Signal connected to EEPROM data input pin. I/PD 59 EEPROM Data Out: Signal connected to EEPROM data output pin. P 60 Power Supply: +0V DC or Ground Power. P 61 Power Supply for logic circuits: +3.3V DC. I/PU 62 This pin define the assert level of Reset (pin 72) When ='1' or NC, reset signal is active High When ='0', reset signal is active Low I/PD 63, 64, 65, For testing 66, 67 I 68 Sets the IQ mode This pin is used during testing. It must be set to low in IQ measurement mode. 0: IQ mode 1: Normal operation mode P 69 Power Supply for logic circuits: +3.3V DC. I/PD 70 External 60MHz input I/PD 71 For testing (TESTMODE) 0: Normal operation mode 1: External clock Synchronization mode
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AX88172
RESET/RESET I 72
PRELIMINARY
Reset/Reset Reset is active high/low depend on RST_TYPE (pin 62) definition. When assert, place AX88172 into reset mode immediately. Reset complete loads the EEPROM data. Power Supply: +0V DC or Ground Power. Power Supply for logic circuits: +3.3V DC. Power supply pin for PLL and oscillator circuits +3.3V DC Power supply pin for PLL and oscillator circuits +0V DC or Ground Powe Monitor pin for two PLL charge pumps Connect to GND on PCB when actually using Charge pump monitor ON/OFF: Connect to GND on PCB when actually using 12M crystal oscillator input 12M crystal oscillator output
VSS VDD PVDD PVSS VC PTEST XIN12M XOUT12M Tab - 1 PIN signals
P P P P I I I O
73 74 75 76 77 78 79 80
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AX88172
PRELIMINARY
3.0 EEPROM Memory Mapping
EEPROM OFFSET 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H-1FH HIGH BYTE RESERVED LOW BYTE WORD COUNT FOR PRELOAD *FLAG HIGH-SPEED LENGTH OF DEVICE HIGH-SPEED EEPROM OFFSET OF DEVICE DESCRIPTOR (BYTE) DESCRIPTOR HIGH-SPEED LENGTH OF CONFIGURATION HIGH-SPEED EEPROM OFFSET OF DESCRIPTOR (BYTE) CONFIGURATION DESCRIPTOR NODE ID 1 NODE ID 0 NODE ID 3 NODE ID 2 NODE ID 5 NODE ID 4 LANGUAGE ID HIGH BYTE LANGUAGE ID LOW BYTE LENGTH OF STRING INDEX 1 EEPROM OFFSET OF STRING INDEX 1 LENGTH OF STRING INDEX 2 EEPROM OFFSET OF STRING INDEX 2 LENGTH OF STRING INDEX 3 EEPROM OFFSET OF STRING INDEX 3 LENGTH OF STRING INDEX 4 EEPROM OFFSET OF STRING INDEX 4 LENGTH OF STRING INDEX 5 EEPROM OFFSET OF STRING INDEX 5 LENGTH OF STRING INDEX 6 EEPROM OFFSET OF STRING INDEX 6 LENGTH OF STRING INDEX 7 EEPROM OFFSET OF STRING INDEX 7 RESERVED RESERVED MAX PACKETSIZE HIGH BYTE MAX PACKET LOW BYTE **(PHY TYPE[7:5]) (SECONDARY PHY **(PHY TYPE[7:5])(FIRST PHY ID[4:0] ) ID[4:0]) PAUSE PACKET HIGH WATER LEVEL PAUSE PACKET LOW WATER LEVEL FULL-SPEED LENGTH OF DEVICE FULL-SPEED EEPROM OFFSET OF DEVICE DESCRIPTOR (BYTE) DESCRIPTOR FULL-SPEED LENGTH OF CONFIGURATION FULL-SPEED EEPROM OFFSET OF DESCRIPTOR (BYTE) CONFIGURATION DESCRIPTOR RESERVED RESERVED
Tab - 2 EEPROM Memory Mapping Note: *FLAG: Bit0 Self Powered (for USB GetStatus) 1: self power ; 0 : bus power Bit 1 Reserved Bit 2 RemoteWakeUP support Bit 3 1 Bit 4 -5 Reserved Bit 6 RX drop CRC Enable Bit 7 TX append CRC enable Bit 8 Capture Effective Mode Bit 9 - F Reserved
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AX88172
PRELIMINARY
** PHY TYPE[7:5] 3'b000 = 10/100 Ethernet PHY or 1M HOME PHY (Link report as normal case) 3'b100 = special case 1 (Link report always active) 3'b101 = reserved 3'b111 = No supported PHY FOR EXAMPLE: EEPROM OFFSET 11 HIGH BYTE IS "E0" MEAN IS NO SUPPORTED SECONDARY PHY. ***Unicode MAC Address: If the MAC's NODE ID is 01,23,45,67,89,ABh respect to NODE ID 0, NODE ID 1, ... NODE ID5 Then the unicode will be 30-31,32-33,34-35,36-37,38-39,41-42h respects to BYTE 1 OF UNICODE MAC ADDRESS- BYTE 2 OF UNICODE MAC ADDRESS, ...-BYTE 12 OF UNICODE MAC ADDRESS. Isolate 2 PHY step procedure by hardware when every hardware reset 1. write 0 PHY_ID isolate and power down 2. write PRIMARILY PHY ID isolate and power down 3. write SECONDARY PHY ID isolate and power down
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AX88172
PRELIMINARY
4.0 USB Commands
There are three command groups for Endpoint 0 in AX88172: The USB standard commands USB Communication Class commands USB vendor commands.
4.1 USB standard commands
The Language ID is 0x0904 for English PPLL means buffer length CC means configuration number I I means Interface number SETUP COMMAND 80 06 00 01 00 00 LL PP 80 06 00 02 00 00 LL PP 80 06 00 03 00 00 LL PP 80 06 01 03 09 04 LL PP 80 06 02 03 09 04 LL PP 80 06 03 03 09 04 LL PP 80 06 04 03 09 04 LL PP 80 06 05 03 09 04 LL PP 80 06 06 03 09 04 LL PP 80 06 07 03 09 04 LL PP 80 06 08 03 09 04 LL PP 80 08 00 00 00 00 01 00 00 09 CC 00 00 00 00 00 81 0A 00 00 I I 00 01 00 01 0B AS 00 00 00 00 00 Tab - 3 USB stabdard commands DATA IN/OUT Data PPLL bytes Data PPLL bytes Data 2 bytes Data PPLL bytes Data PPLL bytes Data PPLL bytes Data PPLL bytes Data PPLL bytes Data PPLL bytes Data PPLL bytes Data 12 bytes Data 1 bytes No Data Data 1 byte No Data DESCRIPTION Get Device Descriptor Get Configuration Descriptor Get Supported Language ID Get Manufacture String Get Product String Get Serial Number String Get Configuration String Get Interface 0 String Get Interface 1/0 String Get Interface 1/1 Stirng Get Ethernet Address String Get Configuration Set Configuration Get Interface Set Interface
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ASIX ELECTRONICS CORPORATION
AX88172 4.2 USB Vendor Commands
SETUP COMMAND C0 02 XX YY 0M 00 02 00 40 03 XX YY PP QQ 00 00 40 04 XX YY PP QQ 00 00 40 06 00 00 00 00 00 00 C0 07 PI 00 RG 00 02 00 40 08 PI 00 RG 00 02 00 C0 09 00 00 00 00 01 00 40 0A 00 00 00 00 00 00 C0 0B DR 00 00 00 02 00 40 0C DR 00 MM SS 00 00 40 0D 00 00 00 00 00 00 40 0E 00 00 00 00 00 00 C0 0F 00 00 00 00 02 00 40 10 RR 00 00 00 00 00 C0 11 00 00 00 00 03 00 40 12 II 00 00 00 00 00 40 13 II 00 00 00 00 00 40 14 II 00 00 00 00 00 C0 15 00 00 00 00 08 00 40 16 00 00 00 00 08 00 C0 17 00 00 00 00 06 00 C0 19 00 00 00 00 02 00 C0 1A 00 00 00 00 01 00 40 1B MM 00 00 00 00 00 C0 1C 00 00 00 00 01 00 40 1D MM 00 00 00 00 00 C0 1E 00 00 00 00 01 00 40 1F MM 00 00 00 00 00 DATA IN/OUT Data 2 bytes No Data No Data No Data Data 2 Bytes Data 2 Bytes Data 1 Bytes No Data Data 2 Bytes No Data No Data No Data Data 2 Bytes No Data Data 3 Bytes No Data No Data No Data Data 8 Bytes Data 8 Bytes Data 6 Bytes Data 2 Bytes (*) Data 1 Byte No Data Data 1 Byte No Data Data 1 Byte No Data
PRELIMINARY
DESCRIPTION Read Rx/Tx SRAM M = 0 : Rx, M=1 : Tx Write Rx SRAM Write Tx SRAM Software MII Operation Read MII Register Write MII Register Read MII Operation Mode Hardware MII Operation Read SROM Write SROM Write SROM Enable Write SROM Disable Read Rx Control Register Write Rx Control Register Read IPG/IPG1/IPG2 Register Write IPG Register Write IPG1 Register Write IPG2 Register Read Multi-Filter Array Write Multi-Filter Array Read Node ID Read Ethernet/HomePNA PhyID Read Medium Status (**) Write Medium Mode (**) Get Monitor Mode Status (***) Set Monitor Mode On/Off (***) Read GPIOs (****) Write GPIOs (****)
* Note1: read 1st byte is Secondary PHY ID; 2nd byte is Primarily PHY ID ** Read / Write Medium status Bit7 Bit6 Bit5 Bit4 Read X X X Flow_Control_En Write X X X Flow_Control_En *** Read / Write Monitor Mode Bit7-5 Bit4 Bit3 Read 3'b101 HS/FS X Write X X X **** Read / Write GPIO Bit7 Bit6 Read Write
Bit3 X
Bit2 TxAbortAllow TxAbortAllow
Bit1 Full_Duplex Full_Duplex
Bit0 X
Bit2 Magic_Packet_En Magic_Packet_En
Bit1 Link_UP_Wake Link_UP_Wake
Bit0 Monitor_Mode Monitor_Mode
Bit5 GPI2 GPO2
Bit4 GPO2EN GPO2EN
Bit3 GPI1 GPO1
Bit2 GPO1EN GPO1EN
Bit1 GPI0 GPO0
Bit0 GPO0EN GPO0EN
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AX88172
Interrupt endpoint frame format Byte Number Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7
PRELIMINARY
A1 Fixed value 00 00 Fixed value 00 NN Bit_1: SECONDARY PHY Link state (active high), Bit_0: PRIMARILY PHY LINK STATE 00 Fixed value 00 00 Fixed value 00 80 90h 00 Fixed value 00 00 Fixed value
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AX88172
PRELIMINARY
5.0 USB Configuration Structure
5.1 USB Configuration.
The AX88172 supports 1 Configuration only.
5.2 USB Interface.
The AX88172 supports 2 interfaces, the interface 0 is Data Interface and interface 1 is for Communication Interface.
5.3 USB Endpoints.
The AX88172 supports 4 endpoints. Endpoint 0 Control endpoint, it is for configuring device. Endpoint 1 (optional) Interrupt endpoint, it is for reporting status Endpoint 2 Bulk Out endpoint, it is for Transmitting Ethernet Packet. Endpoint 3 Bulk In endpoint, it is for Receiving Ethernet Packet.
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AX88172
PRELIMINARY
6.0 Electrical Specification and Timings
6.1 Absolute Maximum Ratings
Description SYM Min Max Units Operating Temperature Ta 0 +85 C Storage Temperature Ts -65 +150 C Supply Voltage Vdd -0.3 +3.6 V Input Voltage Vin -0.3 Vdd+0.3 V Output Voltage Vout -0.3 Vdd+0.3 V Lead Temperature (soldering 10 seconds maximum) Tl -55 +240 C Note: Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability.
6.2 General Operation Conditions
Description Operating Temperature Supply Voltage SYM Min Ta 0 Vdd +3.0 Tpy 25 +3.30 Max +70 +3.6 Units C V
6.3 DC Characteristics
(Vdd=3.0V to 3.6V, Vss=0V, Ta=0C to 70C) Description Low Input Voltage High Input Voltage Low Output Voltage High Output Voltage Input Leakage Current Output Leakage Current Input Pull-up / down resistance Description Power Consumption (3.3V) SYM Vil Vih Vol Voh Iil Iol Ri SYM SPt3v Min 0.7*Vdd 2.4 -1 -10 75 Min 150 Tpy Max Tpy Max 0.3*Vdd 0.4 +1 +10 Units V V V V uA uA K ohm Units mA
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AX88172
PRELIMINARY
6.4 A.C. Timing Characteristics
6.4.1 12M_XIN (CL=16pF, +/-50ppm)
Thigh 12M_XIN
Tr
Tf Tcyc
Tlow
Symbol
Tcyc Thigh Tlow Tr/Tf CYCLE TIME CLK HIGH TIME CLK LOW TIME CLK SLEW RATE
Description
Min 34.71 34.71 1
Typ. 83.33 41.66 41.66 -
Max 49.99 49.99 4
Units ns ns ns ns
6.4.2 Reset Timing
12M_XIN RESET/RESET
Symbol
Trst
Description
Reset pulse width (6ms ~10ms)
Min 100
Typ. -
Max -
Units 12M _XIN
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AX88172
6.4.3 MII Timing
Ttclk Ttch Ttcl
PRELIMINARY
TXCLK(in) Ttv TXD<3:0>(out) Tth
TXEN(out) Trclk Trch Trcl
RXCLK(in) Trs RXD<3:0>(in) Trh
RXDV(in) Trs1 RXER(in)
CRS(in)
Symbol
Ttclk Ttclk Ttch Ttch Trch Trch Ttv Tth Trclk Trclk Trch Trch Trcl Trcl Trs Trh Trs1 Cycle time(100Mbps) Cycle time(10Mbps) high time(100Mbps) high time(10Mbps) low time(100Mbps) low time(10Mbps) Clock to data valid Data output hold time Cycle time(100Mbps) Cycle time(10Mbps) high time(100Mbps) high time(10Mbps) low time(100Mbps) low time(10Mbps) data setup time data hold time RXER data setup time
Description
Min 14 140 14 140 3 3 14 140 14 140 6 6 6
Typ. 40 400 40 400 -
Max 26 260 26 260 10 10 26 260 26 260 -
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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AX88172
PRELIMINARY
6.4.4 STATION MANAGEMENT TIMING
Tclk
MDC
Tch Tcl Tod
MDIO (output)
Ts
Th
MDIO (input)
Symbol Tclk Tch Tcl Tod Ts Th
Description MDC Clock Cycle Time MDC Clock High Time MDC Clock Low Time Clock Falling Edge to Output Valid Delay Data In Setup Time Data In Hold Time
Min
Typ. 375 1328 1328
Max
0 10 100
2
Units KHz ns ns ns ns ns
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AX88172
6.4.5 SERIAL EEPROM TIMING
Tclk
PRELIMINARY
EECK
Tch Tdv Tcl Tod VALID Thcs Tlcs
EEDI (output)
VALID Tscs
EECS
Ts Th
EEDO (input)
DATA VALID
Symbol Tclk Tch Tcl Tdv Tod Tscs Thcs Tlcs Ts Th
Description EECK Clock Cycle Time EECK Clock High Time EECK Clock Low Time EEDI Data Valid Output to EECK High Time EECK High to EEDI Data Output Delay Time EECS Valid to EECK High Time EECK Low to EECS Invalid Time Minimum EECS Low Time Data Input Setup Time Data Input Hold Time
Min
Typ. 187.5 2666 2666
Max
2666 2666 2666 0 23904 10 100
Units KHz ns ns ns ns ns ns ns ns ns
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AX88172
PRELIMINARY
7.0 Package Information
He E A A2 A1
Hd
D
pin 1
b
e
SYMBOL MIN.
A1 A2 A b D E e Hd He L L1 0 13.6 13.6 0.3 0.175 11.9 11.9 0.05 1.3
MILIMETER NOM
0.1 1.40
MAX
0.15 1.5 1.70
0.18 12.00 12.00 0.5 14.00 14.00 0.50 1.00
0.28 12.1 12.1
14.4 14.4 0.7
10
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L
L1
AX88172 Appendix A: System Applications
Some typical applications for AX88170 are illustrated bellow.
PRELIMINARY
A.1 USB to Fast Ethernet Converter
RJ45
MAGNETIC
10/100 PHY/TxRx
AX88172
USB I/F
EEPROM
A.2 USB to Fast Ethernet and/or HomeLAN Combo solution
RJ45 RJ11
MAGNETIC
MAGNETIC
10/100 Mbps Ethernet PHY/TxRx
1/10 Mbps Home LAN PHY
AX88172
USB I/F
EEPROM
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AX88172
USB to Fast Ethernet/HomePNA Controller
Demonstration Circuit A: AX88172 (ED2 version) + Ethernet PHY(8201L)
USB Port Link/Act LED
VDD3L D1 R1 1K LED /PHY_RST VDD5 D2 L1 VDD3L F.BEAD. C1 L3 U1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VSS EEDO EEDI EECK EECS NC SPEEDUP VDD LED ATPGEN NC VSS PHYRSTP PHYRSTN GPIO2 GPIO1 GPIO0 TEST1 TEST0 VDD F.BEAD. 1000P L4 F.BEAD. L2 F.BEAD. C2 0.1u 3 2 1 J1 DIODE DC POWER JACK
OPTION
DC 5.0V POWER
TXD0 1206 & DIP TXD1 TXD2 TXD3 TX_CLK TXEN RXD0 RXD1 TXD0 TXD1 TXD2 TXD3 TX_CLK TXEN RXD0 RXD1 RXD2 RXD3 RX_CLK RXDV RXER /PHY_RST MDC MDIO COL CRS VDD3 GND
GND EEDO EEDI EECK EECS
VDD3L LED
OPTION 1 / NC : PIN72 RESET ACTIVE HIGH. 0 : PIN72 RESET ACTIVE LOW.
GND
R2 0 VDD3L R3 10K
VDD3L
VDD3L 60MHz VDD3L RST GND
C4 0.1u
R1 AVDD AVSS AVSS DP AVSS DM AVSS AVDD EXTWAKEUPN NC NC VDD MDC MDIO NC NC NC NC VSS
VDD3 PVDD PVSS GND GND
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
C6 0.1u C7
VDD RST_TYPE NC NC NC NC NC ANA_XIQ VDD CLKI TESTMODE RESET VSS VDD PVDD PVSS VC PTEST XIN12M XOUT12M
AX88172
VSS RXDV RXER VDD RXD3 RXD2 RXD1 RXD0 RXCLK VDD TXEN TXD3 TXD2 TXD1 TXD0 CRS TXCLK NC COL VDD
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
GND RXDV RXER VDD3L RXD3 RXD2 RXD1 RXD0 RX_CLK VDD3L TXEN TXD3 TXD2 TXD1 TXD0 CRS TX_CLK COL VDD3L
J2 S
RXD2 RXD3 U2 EECS EECK EEDI EEDO 1 2 3 4 CS SK DI DO 93C56 VCC NC NC GND 8 7 6 5 VDD3 C3 0.1u RX_CLK RXDV RXER /PHY_RST MDC MDIO C5 0.01u COL CRS VDD3 GND
DPLUS DMINUS
4 1 3 2
GND VDD5 D+ D-
1
4
2
3 S
USB-CON
OPTION (Next version chip)
AX88172
AVDD AVSS AVSS DPLUS AVSS DMINUS AVSS AVDD
VDD3L MDC MDIO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
24P C8 Y1 12.000MHz R5 24P 220
R4 1M
GND
OPTION
VDD3
OPTION RESET ACTIVE HIGH : USED "U2" ONLY. LOW : USED "R8" ONLY.
R6 6.2K 1% C9 0.1u 0.1u C12 C11 0.1u VDD3 0.1u L5 VDD3L L6 C17 C16 + 10u/16V 47u/16V 1206 & DIP 0.1u + C20 F.BEAD. C14 0.1u C15 0.1u 60MHz VDD3 F.BEAD. 8 VCC OUT GND 5 4 0.47uF U4 R8 33 60MHz C13 C10 S1 R7 SW PUSHBUTTON 15K
RESET ACTIVE
U3 : TOREX / XC74UL14AAMR
U3 1 2 3 NC A GND XC74UL14 Y 4 RST VCC 5 VDD3
1206 & DIP VDD5 C19 + C18 47u/16V 0.01u 3
U5 VOUT VIN ADJ/GND AMS1117 2 1
1206 & DIP
R9
0
AVSS and PVSS : Single-point ground
L8 AVDD VDD3 C32 0.1u C33 0.01u AVSS C34 0.1u GND + C35 22u C37 0.1u 0.01u PVSS Size B F.BEAD. PVDD C36 Title
VDD3L VDD3 C21 0.1u GND GND C22 0.1u C23 0.1u C24 0.1u C25 0.1u C26 0.1u C27 0.1u C28 0.1u C29 0.1u
L7
F.BEAD. + C30
C31 0.1u
22u
AX88172 DEMO Board
Document Number
AX88172
Friday, May 31, 2002 Sheet 1 of 2
Rev 2.1
1206 & DIP
1206 & DIP
Date:
22
ASIX ELECTRONICS CORPORATION
AX88172
MDC VDD3 R10 1.5K U6 MDIO TXD0 TXD1 TXD2 TXD3 TXEN TX_CLK RXDV RXD0 RXD1 RXD2 RXD3 RX_CLK COL CRS RXER MDIO TXD0 TXD1 TXD2 TXD3 TXEN TXC RXDV RXD0 RXD1 RXD2 RXD3 RXC COL CRS RXER X1 X2 R15 2K LED0 LED1 LED2 LED3 LED4 DVDD0 VDD3 GND 25 26 6 5 4 3 2 7 22 21 20 19 18 16 1 23 24 46 47 9 10 12 13 15 8 14 11 17 MDC MDIO TXD0 TXD1 TXD2 TXD3 TXEN TXC RXDV RXD0 RXD1 RXD2 RXD3 RXC COL CRS RXER X1 X2 MDC
USB to Fast Ethernet/HomePNA Controller
U5 REALTEK RTL8201
AVDD0 AVDD1 AVDD2
32 36 48 29 35 45
AVDD0 AVDD1 AVDD2 GND GND GND
VDD3
RTL 8201
R13
20
AGND AGND AGND
R11 49.9
R12
U6 : BOTHHAND / TS6121A
49.9 U7 1 2 3 6 7 8 R16 R19 R20 R25 R26 R27 R28 R29 /PHY_RST 2K 1% 1K 1K 1K 1K 1K 1K 1K R18 49.9 C38 0.01u VDD3 C40 0.01u /PHY_RST C42 0.01u C39 0.01u 1 2 3 6 7 8 TS6121A R21 75 R22 75 R23 75 R24 75 16 15 14 11 10 9 16 15 14 11 10 9 TX+ TXRX+ RX27 34 33 31 30 28 43 40 39 38 37 41 44 42
RTT3/VCTRL TPTX+ TPTXTPRX+ TPRXRTSET ISOLATE REPT SPEED DUPLEX ANE LDPS MII/SNIB RESETB
J3 1 2 3 6 4 5 7 8 RJ45 S S
R14
20
LED0/PHYA0 LED1/PHYA1 LED2/PHYA2 LED3/PHYA3 LED3/PHYA4 DVDD0 DVDD1 DGND DGND RTL8201
R17 49.9
C41 0.01u/2KV
( CONNECT TO CHASIS GND ) Set PHY ADDRESS TO 00011
VDD3 L9 VDD3 C43 0.1u F.BEAD. AVDD2 C44 0.1u L10 F.BEAD. AVDD1 C45 LED0 0.1u LED R32 4.7K D4 L11 VDD3 C46 0.1u F.BEAD. DVDD0 C47 0.1u L12 F.BEAD. AVDD0 C48 0.1u D5 LED2 LED R36 VDD3 1206 & DIP VDD3 C49 + 10uF/16V GND C50 Y2 0.1u X1 C51 20P C52 20P LED4 LED CRYSTAL 25.000 MHz R39 0 X2 R37 1M D6 LED3 LED R40 D7 4.7K R41 510 R38 510 4.7K R34 4.7K R35 510 LED1 R33 510 LED R31 510 R30 4.7K D3
Link LED
FULL LED
Link 10-Active
Link 100-Active
COLL
Title
AX88172 DEMO Board
Size B Date: Document Number
RTL8201-TS6121A
Friday, May 31, 2002 Sheet 2 of 2
Rev 2.1
23
ASIX ELECTRONICS CORPORATION
AX88172
USB Port Link/Act LED
VDD3L D1 R1 1K LED
USB to Fast Ethernet/HomePNA Controller
TXD0 TXD1 VDD5 /PHY_RST L1 VDD3L F.BEAD. C1 L2 U2 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VSS EEDO EEDI EECK EECS NC SPEEDUP VDD LED ATPGEN NC VSS PHYRSTP PHYRSTN GPIO2 GPIO1 GPIO0 TEST1 TEST0 VDD F.BEAD. 1000P TXD2 TXD3 TX_CLK TXEN RXD0 RXD1 VSS RXDV RXER VDD RXD3 RXD2 RXD1 RXD0 RXCLK VDD TXEN TXD3 TXD2 TXD1 TXD0 CRS TXCLK NC COL VDD 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND RXDV RXER VDD3L RXD3 RXD2 RXD1 RXD0 RX_CLK VDD3L TXEN TXD3 TXD2 TXD1 TXD0 CRS TX_CLK COL VDD3L J1 S RXD2 RXD3 RX_CLK RXDV 2 3 RXER S /PHY_RST MDC MDIO C4 0.01u COL CRS VDD3 AX88172 GND TXD0 TXD1 TXD2 TXD3 TX_CLK TXEN RXD0 RXD1 RXD2 RXD3 RX_CLK RXDV RXER /PHY_RST MDC MDIO COL CRS VDD3 GND
Demonstration Circuit B: AX88172 (ED3 version) + Ethernet PHY (8201LBL)
GND EEDO EEDI EECK EECS
VDD3L LED
R2 0 VDD3L 10K R3
VDD3L
VDD3L RST GND C3 0.1u VDD3 PVDD PVSS GND GND
C5 0.1u C6
AVDD AVSS AVSS DPLUS AVSS DMINUS AVSS AVDD
VDD3L MDC MDIO
24P C7 Y1 12.000MHz R7 24P 220
R6 1M R8
GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
R1 AVDD AVSS AVSS DP AVSS DM AVSS AVDD EXTWAKEUPN NC NC VDD MDC MDIO NC NC NC NC VSS
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
VDD RST_TYPE NC NC NC NC NC ANA_XIQ VDD CLKI TESTMODE RESET VSS VDD PVDD PVSS VC PTEST XIN12M XOUT12M
GND
AX88172
DPLUS DMINUS
4 1 3 2
GND VDD5 D+ D-
1
4
USB-CON
U1 EECS EECK EEDI EEDO 1 2 3 4 CS SK DI DO 93C56 VCC NC NC GND 8 7 6 5 VDD3 C2 0.1u
VDD3 6.2K 1% C8 0.1u 0.1u C11 C10 0.1u VDD3 0.1u VDD3L C14 L4 C16 C15 + 10u/16V 47u/16V 1206 & DIP 0.1u + C19 F.BEAD. 0.47uF R11 RST 0 R9 15K C9
1206 & DIP VDD5 C18 + C17 47u/16V 0.01u 3
U4 VOUT VIN ADJ/GND AMS1117 2 1
1206 & DIP
AVSS and PVSS : Single-point ground
VDD3L VDD3 C20 0.1u GND GND C21 0.1u C22 0.1u C23 0.1u C24 0.1u C25 0.1u C26 0.1u C27 0.1u C28 0.1u
L5
F.BEAD. AVDD + C29 C31 0.1u C32 0.01u AVSS VDD3
L6
F.BEAD. PVDD C35
C30 0.1u
22u
C33 0.1u GND
+ C34 22u
C36 0.1u 0.01u PVSS
Title
AX88172 DEMO Board ED3
Size B Document Number
AX88172
Friday, October 04, 2002 Sheet 1 of 2
Rev 2.2
1206 & DIP
1206 & DIP
Date:
24
ASIX ELECTRONICS CORPORATION
AX88172
VDD3 MDC R12 1.5K MDC U5 MDIO TXD0 TXD1 TXD2 TXD3 TXEN TX_CLK RXDV RXD0 RXD1 RXD2 RXD3 RX_CLK COL CRS RXER MDIO TXD0 TXD1 TXD2 TXD3 TXEN R15 20 RXDV RXD0 RXD1 RXD2 RXD3 R16 20 COL CRS RXER X1 X2 R17 2K LED0/PHYAD0 LED1/PHYAD1 LED2/PHYAD2 LED3/PHYAD3 LED4/PHYAD4 DVDD25 VDD3 VDD3 TXC 25 26 6 5 4 3 2 7 22 21 20 19 18 16 1 23 24 46 47 9 10 12 13 15 8 14 48 11 17 45 GND MDC MDIO TXD0 TXD1 TXD2 TXD3 TXEN TXC RXDV RXD0 RXD1 RXD2 RXD3 RXC COL CRS RXER/FXEN X1 X2
USB to Fast Ethernet/HomePNA Controller
C37 AVDD25 AVDD33 AGND AGND 32 36 29 35 GND 27 1 2 TPRX+ TPRXTPTXTPTX+ RTSET ISOLATE RPTR SPEED DUPLEX ANE LDPS MII/SNIB/RTT3 RESETB 31 30 33 34 28 43 40 39 38 37 41 44 42 3 15 14 16 RD+ RDCT TDCT TD+ PE68515 R18 50 R20 5.6K (1%) PHY_RST GND C41 0.1U GND R25 5.1K R26 5.1K C42 0.01U/3KV RTL8201BL LQFP48 R19 50 R21 75 R22 75 R23 75 R24 75 RX+ CT RXTXCMT TX+ 7 2 5 3 6 4 11 5 12 6 10 7 8 AVDD25 AVDD3 AVDD25 0.1U GND R13 50 R14 50 U6 NC 1 U7 TX+ TXRX+ N/C N/C RXN/C N/C RJ8-45 CH_GND GND 9 C40 0.1U GND C39 0.1U GND C38 0.1U GND
for EMI supression
RXC
RTL8201BL
LED0/PHYAD0 LED1/PHYAD1 LED2/PHYAD2 LED3/PHYAD3 LED4/PHYAD4 DVDD25 DVDD33 DVDD33 DGND DGND AGND
(CONNECT TO CHASSIS GND)
Hardwire Configuration network:
GND
R18 value need fine tune, the range may from 2K to 5.6K
R27 5.1K R28 5.1K R29 5.1K R30 5.1K R31 5.1K
1. This configuration shows Enable: Auto negotiation, Full duplex, 100Mbps, Link Down Power Saving, MII interface Disable: Isolate, Repeater mode 2. These senven configuration pins could be connected to VDD or GND directly.
Set PHY ADDRESS TO 00011
R32 4.7K D2 LED0 R34 510 LED R36 4.7K D3 LED1 R37 510 LED R38 D4 LED2 LED R40 D5 LED3 LED R42 D6 LED4 LED 4.7K 4.7K R41 510 4.7K R39 510
VDD3 R33 1M
VDD3
Link LED
Y2 X1
CRYSTAL 25.000 MHz R35 C44 20P
0 X2 L7 AVDD25 DVDD25 BEAD C45 22U GND C46 0.1U GND C47 0.1U GND
C43 20P
U1/pin14
U1/pin48
VDD3
FULL LED
VDD3
L8 AVDD3 BEAD C48 0.1U GND C49 0.1U GND C50 0.1U GND VDD3
Link 10-Active
RTL8201BL has built in 3.3V to 2.5V regulator, and pin 8(AVDD25) sources out 2.5V. A 22uF capacitir and a 0.1uF capacitor are recommended between AVDD25 and GND. Place C14, C15, L4 close to AVDD25 and place C11 close to DVDD25.
Place L2, C17, C18, C19 as close to each power pin as possible.
Link 100-Active
Title R43 510 RTL8201BL application circuit - interface with MAC(MII)
COLL
Size B Date:
Document Number RTL8201BL MII1.0 Friday, December 20, 2002 Sheet 2 of 2
Rev 2.2
25
ASIX ELECTRONICS CORPORATION
AX88172
Remark:
PRELIMINARY
The schematic change between ED2 and ED3 are shown following: 1. 2. 3. 4. 60MHZ oscillator is no longer needed AX88172 Pin 23 need coonect to VBUS in ED3 Pin 70 (CLKI) changes from 60MHz OSC to NC, Pin 71 (test mode) from VDD3L to NC.
26
AX88172
Revisions history
Revision Date Comment
PRELIMINARY
V. 1.0 V.1.1
V.1.2
V.1.3
V.1.4
Initial Release Pin 62 change from "SROM size to NC" R1 change from 6K +/-1% to 6.2K+/-1% Power on reset specific 6ms ~10ms "Primary"PHY ID change to "First" PHY ID in EEPROM memory mapping 2002/2/25 Pin 62 change from "NC" to "RST_TYPE" Pin 72 change from "RESET" to"RESET/RESET" On page 12 modify following: USB vendor command modify from "disable H/W MII operation" to "Software MII operation" USB vendor command modify from "Enable H/W MII operation" to "Hardware MII operation" Read/write Mointor mode at read bit 7-5 change from 100 to 101" Add /Reset timing Reference design schematic updated BOM update 2002/5/7 Chip ED2 new schematic with external 60 MHZ Add RTl 8201 BL version schematic Remove BOM 2002/12/20 Add ED3 reference design with RTL 8201BL version PHY and remark the difference Add 12M osc spec
12/25/01 12/28/01
27
AX88172
PRELIMINARY
4F, NO.8, HSIN ANN RD., SCIENCE-BASED INDUSTRIAL PARK, HSINCHU, TAIWAN, R.O.C.
TEL: 886-3-5799500 FAX: 886-3-5799558
Email: support@asix.com.tw Web: http://www.asix.com.tw
28

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