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| R EM MICROELECTRONIC - MARIN SA EM6607 Ultra-low power microcontroller with 4 high drive outputs Features Low Power typical 1.8A active mode typical 0.5A standby mode typical 0.1A sleep mode @ 1.5V, 32kHz, 25 C Figure 1. Architecture V DD VREG V SS Low Voltage 1.2 to 3.3 V ROM 2k x 16 (Mask Programmed) RAM 96 x 4 (User Read/Write) 2 clocks per instruction cycle RISC architecture 5 software configurable 4-bit ports 1 High drive output port Up to 20 inputs (5 ports) Up to 16 outputs (4 ports) buzzer three tone Serial Write buffer - SWB Supply Voltage level detection (SVLD). Analogue and timer watchdog 8 bit timer / event counter Internal interrupt sources (timer, event counter, prescaler) External interrupt sources (portA + portC) 32KHz Crystal Osc ROM 2k X 16Bit RAM 96 X 4Bit Power Supply VLD 3 Levels Power on Reset Prescaler 8-Bit Event Count/Timer Core EM6600 3 Tone Buzzer Interrupt Controller Serial Write Buffer Watchdog Timer Port A 0 123 Port B 0123 High Drive Outputs Port C 0123 Port D 0123 Clk Data Port E 0123 Buzzer Description The EM6607 is a single chip low power, mask programmed CMOS 4-bit microcontroller. It contains ROM, RAM, watchdog timer, oscillation detection circuit, combined timer / event counter, prescaler, voltage level detector and a number of clock functions. Its low voltage and low power operation make it the most suitable controller for battery, stand alone and mobile equipment. The EM6607 microcontroller is manufactured using EM's Advanced Low Power CMOS Process. In 24 Pin package it is direct replacement for EM6603. Figure 2. PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 TEST 1 2 3 4 5 6 7 8 9 Pin Configuration 24 VDD 23 VREG 22 RESET 21 PD3 20 PD2 PA0 PA1 PA2 PA3 PE0 PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 28 27 26 25 24 23 VDD VREG RESET PE3 PD3 PD2 PD1 PD0 PE2 PC3 PC2 PC1 PC0 STB/RST Typical Applications sensor interfaces domestic appliances clocks security systems bicycle computers automotive controls TV & audio remote controls measurement equipment R/F and IR. control motor driving EM6607 19 PD1 18 PD0 17 PC3 16 15 14 13 EM6607 22 21 20 19 PC2 PC1 PC0 STB/RST QOUT 10 QIN 11 VSS 12 PE1 10 TEST 11 QOUT 12 QIN 13 VSS 14 EM6680 18 17 16 15 (TS)SOP-24 (TS)SOP-28 Copyright (c) 2005, EM Microelectronic-Marin SA 1 www.emmicroelectronic.com R EM6607 EM6607 at a glance Power Supply - Low Voltage, low power architecture including internal voltage regulator - 1.2V ... 3.3 V battery voltage - 1.8A in active mode - 0.5A in standby mode - 0.1A in sleep mode @ 1.5V, 32kHz, 25 C - 32 kHz Oscillator or external clock RAM - 96 x 4 bit, direct addressable ROM - 2048 x 16 bit metal mask programmable CPU - 4 bit RISC architecture - 2 clock cycles per instruction - 72 basic instructions Main Operating Modes and Resets - Active mode (CPU is running) - Standby mode (CPU in Halt) - Sleep mode (No clock, Reset State) - Initial reset on Power-On (POR) - External reset pin - Watchdog timer (time-out) reset - Oscillation detection watchdog reset - Reset with input combination on PortA 4-Bit Input PortA - Direct input read - Debounced or direct input selectable (reg.) - Interrupt request on input's rising or falling edge, selectable by register. - Pull-down or Pull-up selectable by metal mask - Software test variables for conditional jumps - PA3 input for the event counter - Reset with input combination on PortA (metal option) 4-Bit Input/Output PortB - Separate input or output selection by register - Pull-up, Pull-down or none, selectable by metal mask if used as Input 4-Bit Input/Output PortD - Input or Output port as a whole port - Pull-up, Pull-down or none, selectable by metal mask if used as Input - CMOS or N-channel open drain mode - Serial Write Buffer clock and data output 4-Bit Input/Output PortE - Separate input or output selection by register - Pull-up, Pull-down or none, selectable by metal mask if used as Input Serial (output) Write Buffer - max. 256 bits long clocked with 16/8/2/1kHz - automatic send mode - interactive send mode : interrupt request when buffer is empty Buzzer Output - if used output on PB0 (24 pin) or PE0 (28 pin) - 3 tone buzzer - 1kHz, 2kHz, 2.66kHz/4kHz (TBC) Prescaler - 32kHz output possible on the STB/RST pin - 15 stage system clock divider down to 1 Hz - 3 interrupt requests: 1Hz/8Hz/32Hz - Prescaler reset (from 8kHz to 1Hz) 8-bit Timer / Event Counter - 8-bit auto-reload count-down timer - 6 different clocks from prescaler - or event counter from the PA3 input - parallel load - interrupt request when comes to 00 hex. Supply Voltage Level Detector - 3 software selectable levels (1.3V, 2.0V, 2.3V or user defined between 1.3V and 3.0V) - Busy flag during measure - Active only on request during measurement to reduce power consumption Interrupt Controller - Buzzer output on PB0 (24-pin) / PE0 (28-pin) 4-Bit Input/Output PortC - Input or Output port as a whole port - Debounced or direct input selectable (reg.) - Interrupt request on input's rising or falling edge, selectable by register. - Pull-up, pull-down or none, selectable by metal mask if used as input - CMOS or N-channel open drain mode - 9 external interrupt sources: 4 from PortA, 4 from PortC. - 3 internal interrupt sources, prescaler, timer and Serial Write Buffer - Each interrupt request is individually selectable - Interrupt request flag is cleared automatically on register read Copyright (c) 2005, EM Microelectronic-Marin SA 2 www.emmicroelectronic.com R EM6607 Table of Contents 1 2 2.1 2.2 2.3 3 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 5 5.1 6 7 7.1 7.2 7.3 7.4 7.5 8 8.1 9 9.1 PIN DESCRIPTION FOR EM6607 0H 5 7 7 7 7 1H 2H 3H 4H 18.7 OSCILLATOR 18.8 INPUT TIMING CHARACTERISTICS 56H 57H 43 43 44 58H OPERATING MODES ACTIVE MODE STANDBY MODE SLEEP MODE POWER SUPPLY 5H 19 20 PAD LOCATION DIAGRAM PACKAGE DIMENSIONS 59H 60H 45 47 47 47 61H 62H 8 9 9 9 10 10 10 11 11 6H 7H 8H 9H 10H 1H 12H 13H 21 ORDERING INFORMATION 21.1 PACKAGE MARKING 21.2 CUSTOMER MARKING RESET OSCILLATION DETECTION CIRCUIT RESET PIN INPUT PORT (PA0..PA3) RESET WATCHDOG TIMER RESET SOFTWARE POWER-ON-RESET CPU STATE AFTER RESET POR WITH POWER-CHECK RESET OSCILLATOR PRESCALER 14H 15H Table of Figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Architecture Pin Configuration Typical Configuration: VDD 1.4V up to 3.3V Typical Configuration: VDD 1.2V up to 1.8V Mode Transition Diagram System reset generation Port A Port B Port C Port D Port E Timer / Event Counter Interrupt Request generation Serial write buffer Automatic Serial Write Buffer transmission Interactive Serial Write Buffer transmission Dimensions of SOP24 Package SOIC Dimensions of TSSOP24 Package Dimensions of SOP28 Package SOIC Dimensions of TSSOP28 Package 69H 70H 71H 72H 73H 74H 75H 76H 7H 78H 79H 80H 81H 82H 12 12 12 16H WATCHDOG TIMER INPUT AND OUTPUT PORTS PORTA 17H 18H 13 13 14 19H 7.1.1 7.2.1 7.3.1 7.4.1 7.5.1 PortA registers 20H PORTB PortB registers 15 15 21H PORTC 2H 16 16 23H PortC registers 24H PORTD PortD registers 18 18 25H 1 1 6 6 7 9 14 15 17 18 19 21 24 27 28 29 45 45 46 46 63H 64H 65H 6H 67H 68H PORTE 26H 19 19 27H PortE registers 28H BUZZER BUZZER REGISTER 29H 20 20 21 22 30H 31H TIMER/EVENT COUNTER TIMER/COUNTER REGISTERS 32H 10 INTERRUPT CONTROLLER 10.1 INTERRUPT CONTROL REGISTERS 3H 23 23 34H 11 SUPPLY VOLTAGE LEVEL DETECTOR (SVLD) 25 26 28 29 35H 36H 37H 12 SERIAL WRITE BUFFER - SWB 12.1 SWB AUTOMATIC SEND MODE 12.2 SWB INTERACTIVE SEND MODE 13 14 15 STROBE / RESET OUTPUT 38H 30 9H TEST AT EM - ACTIVE SUPPLY CURRENT TEST330 METAL MASK OPTIONS 40H 31 32 32 32 41H 42H 43H 15.1.1 15.1.2 15.1.3 Power-Check Level Option PortA reset Option, see paragraph 3.3 SVLD levels Option, see paragraph 10.0 SVLD 4H 16 17 17.1 17.2 17.3 18 18.1 18.2 18.3 18.4 18.5 18.6 PERIPHERAL MEMORY MAP TEMPERATURE AND VOLTAGE BEHAVIOURS IDD CURRENT (TYPICAL) PULL-DOWN RESISTANCE (TYPICAL) OUTPUT CURRENTS (TYPICAL) 45H 46H 47H 48H 33 36 36 37 38 40 40 40 40 40 42 49H 50H 51H 52H 53H 54H ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS STANDARD OPERATING CONDITIONS HANDLING PROCEDURES DC CHARACTERISTICS - POWER SUPPLY PINS DC CHARACTERISTICS - INPUT/OUTPUT PINS DC CHARACTERISTICS - SUPPLY VOLTAGE DETECTOR LEVELS 5H 43 3 www.emmicroelectronic.com Copyright (c) 2005, EM Microelectronic-Marin SA R EM6607 Table of Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. IntRq register 7 8 Watchdog register - WD Internal state in Active, Stand-by and Sleep mode 8 PortA Inputs RESET options (metal Hardware option) 10 10 Watchdog-Timer Option (software option) Software Power-On-Reset 10 Initial Value after RESET 11 12 Prescaler interrupts source Prescaler control register - PRESC 12 Watchdog register - WD 12 13 Input / Output Ports Overview Option register - Option 13 PortA input status register - PortA 14 14 PortA Interrupt request register - IRQpA PortA interrupt mask register - MportA 14 PortB input/output status register - PortB 15 15 PortB Input/Output control register - CIOportB Ports A&C Interrupt 16 PortC input/output register - PortC 16 PortC Interrupt request register - IRQpC 16 16 PortC interrupt mask register - MportC Option2 register - Option2 17 PortD Input/Output register - PortD 18 18 Ports control register - CPIOB PortE Input/Output status register - PortE 19 PortE Input/Output control register - CIOPortE 19 20 Buzzer control register - BEEP Buzzer output pad allocation 20 PB0 & PE0 function used with BUen and BuzzerPE0 control bits 20 Timer Clock Selection 22 Timer control register - TimCtr 22 LOW Timer Load/Status register - LTimLS (4 low bits) 22 HIGH Timer Load/Status register - HTimLS (4 high bits) 22 22 PA3 counter input selection register - PA3cnt PA3 counter input selection 22 Main Interrupt request register - IntRq (Read Only)* 23 24 Register - CIRQD SVLD Level selection 25 SVLD control register - SVLD 25 26 SWB clock selection SWB clock selection register - ClkSWB 26 PortD status 26 SWB buffer register - SWbuff 27 27 SWB Low size register - LowSWB SWB High size register - HighSWB 27 input/output Ports 31 31 PortB Hi Current Drive capability 83H 84H 85H 86H 87H 8H 89H 90H 91H 92H 93H 94H 95H 96H 97H 98H 9H 10H 10H 102H 103H 104H 105H 106H 107H 108H 109H 10H 1H 12H 13H 14H 15H 16H 17H 18H 19H 120H 12H 12H 123H 124H 125H 126H 127H 128H 129H Copyright (c) 2005, EM Microelectronic-Marin SA 4 www.emmicroelectronic.com R EM6607 1 Pin Description for EM6607 Pin Nb Pin Name 28 pin 1 port A, 0 2 port A, 1 3 port A, 2 4 port A, 3 5 port E, 0 6 port B, 0 7 port B, 1 8 port B, 2 9 port B, 3 10 port E, 1 11 test 12 Qout/osc 1 13 Qin/osc 2 14 VSS 15 STB/RST 16 port C, 0 17 port C, 1 18 port C, 2 19 port C, 3 20 port E, 2 21 port D, 0 22 port D, 1 23 port D, 2 24 port D, 3 25 port E, 3 26 RESET 27 VREG 28 VDD Pin Description Function Remarks Pin Nb 24 pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Table 1. input 0 port A input 1 port A input 2 port A input 3 port A input / output 0 port E input / output 0 port B input / output 1 port B input / output 2 port B input / output 3 port B input / output 1 port E test input terminal crystal terminal 1 crystal terminal 2 (input) negative power supply terminal strobe / reset status input / output 0 port C input / output 1 port C input / output 2 port C input / output 3 port C input / output 2 port E input / output 0 port D input / output 1 port D input / output 2 port D input / output 3 port D input / output 3 port E reset terminal internal voltage regulator positive power supply terminal interrupt request; tvar 1 interrupt request; tvar 2 interrupt request; tvar 3 interrupt request; event counter input buzzer output in 28 pin package buzzer output in 24 pin package for EM test purpose only (internal pull-down) Can accept trimming capacitor tw. VSS C reset state + port B, C, D write interrupt request interrupt request interrupt request interrupt request SWB Serial Clock Output SWB Serial Data Output Active high (internal pull-down) Needs typ. 100nF capacitor tw. VSS Copyright (c) 2005, EM Microelectronic-Marin SA 5 www.emmicroelectronic.com R EM6607 Figure 3. Typical Configuration: VDD 1.4V up to 3.3V QIN VDD QOUT PA V. Regulator SLEEP Oscillator PB PC VREG + C + C Logic ROM RAM POR VSS I/O Drivers SVLD SWB PD PE Reset Strb/Rst Test Figure 4. Typical Configuration: VDD 1.2V up to 1.8V QIN VDD QOUT PA V. Regulator SLEEP Oscillator PB PC VREG + C Logic ROM RAM POR VSS I/O Drivers SVLD SWB PD PE Reset Strb/Rst Test Copyright (c) 2005, EM Microelectronic-Marin SA 6 www.emmicroelectronic.com R EM6607 2 Operating modes The EM6607 has two low power dissipation modes: STANDBY and SLEEP. Figure 5 is a transition diagram for these modes. 2.1 Active Mode The active mode is the actual CPU running mode. Instructions are read from the internal ROM and executed by the CPU. Leaving active mode via the halt instruction to go into standby mode, the Sleep bit write to go into Sleep mode or a reset from port A to go into reset mode. 2.2 STANDBY Mode Executing a HALT instruction puts the EM6607 into STANDBY mode. The voltage regulator, oscillator, Watchdog timer, interrupts and timer/event counter are operating. However, the CPU stops since the clock related to instruction execution stops. Registers, RAM, and I/O pins retain their states prior to STANDBY mode. A RESET or an Interrupt request cancel STANDBY mode. 2.3 SLEEP MODE Halt instruction IRQ Active Sleep bit write Writing the SLEEP* bit in the IntRq* register puts the EM6607 in SLEEP mode. The oscillator stops and most functions of the EM6607 are inactive. To be able to write the SLEEP bit, the SLmask bit must be first set to 1 in register WD. In SLEEP mode only the voltage regulator and RESET input are active. The RAM data integrity is maintained. SLEEP mode may be cancelled only by a RESET at the terminal pin of the EM6607 or by the selected port A input reset combination. This combination is a metal option, see paragraph 15.1.2. The RESET port must be high for at least 10sec. 130H Standby Reset=1 Reset=0 Sleep Reset=1 Reset=1 Reset Figure 5. Mode Transition Diagram Due to the cold start characteristics of the oscillator, waking up from SLEEP mode may take some time to guarantee that the oscillator has started correctly. During this time the circuit is in RESET state and the strobe output STB/RST is high. Waking up from SLEEP mode clears the SLEEP flag but not the SLmask bit. By reading SLmask it can therefore determine if the EM6607 was powered up (SLmask = 0), or woken from SLEEP mode (SLmask = 1). Table 1. Bit 3 2 1 0 2 IntRq register Name INTPR INTTE INTPC INTPA SLEEP Reset 0 0 0 0 0 R/W R R R R W* Description Prescaler interrupt request Timer/counter interrupt request PortC Interrupt request PortA Interrupt request SLEEP mode flag * Write bit 2 only if SLmask=1 Copyright (c) 2005, EM Microelectronic-Marin SA 7 www.emmicroelectronic.com R EM6607 Table 2. Bit 3 2 1 0 Watchdog register - WD Name WDRST Slmask WD1 WD0 Reset 0 0 R/W R/W R/W R R Description Watchdog timer reset SLEEP mask bit WD Timer data 1/4 Hz WD Timer data 1/2 Hz Table 3 shows the status of different EM6607 blocks in these three main operating modes. 13H Table 3. Internal state in Active, Stand-by and Sleep mode ACTIVE mode On On On On Running "On" "On" "On" can be activated Yes Yes - possible On / Off (soft selectable) On/Off (soft select.) STAND-BY mode On On On On In HALT - Stopped "On" retain value retain value "On" if activated before can not be activated Yes Yes - possible On / Off (soft selectable) "On" if activated before SLEEP mode On On (Low-Power) Off Off Stopped retain value retain value stopped Off No No - not possible No Off Peripheral /// EM6607 mode POR (static) Voltage regulator Quartz 32768 Hz oscillator Clocks (Prescaler & RC divider) CPU Peripheral register RAM Timer/Counter Supply Voltage Level Det.=SVLD PortA /C, Reset pad debounced Interrupts / events Watch-Dog timer Analogue Watchdog (osc.detect) 3 Power Supply The EM6607 is supplied by a single external power supply between VDD and VSS, the circuit reference being at VSS (ground). A built-in voltage regulator generates VREG providing regulated voltage for the oscillator and internal logic. Output drivers are supplied directly from the external supply VDD. A typical connection configuration is shown in figure 4. For VDD less then 1.4V it is recommended that VDD is connected directly to VREG connected For VDD >1.8V then the configuration shown in Figure 4 should be used. 132H *registers are marked in bold and underlined like *Bits/Flags in registers are marked in bold only like IntRq SLEEP Copyright (c) 2005, EM Microelectronic-Marin SA 8 www.emmicroelectronic.com R EM6607 4 Reset To initialize the EM6607, a system RESET must be executed. There are five methods of doing this: (1) (2) (3) (4) (5) Initial RESET from the oscillation detection circuit. External RESET from the RESET PIN. External RESET by simultaneous high input to terminals PA0..PA3. (Combinations defined by metal option) Watchdog RESET (software option). Software Power-On-Reset by writing S0ftPOR bit in Option2 register to "1" During any of these RESET's the STB/RST output pin is high. Figure 6. System reset generation 4.1 Oscillation detection circuit At power on, the built-in voltage regulator starts to follow the supply voltage until VDD becomes higher than VREG. Since it is VREG which supplies the oscillator and this needs time to stabilise, Power-On-Reset with the oscillation detection circuit therefore counts the first 32768 oscillator clocks after power-on and holds the system in RESET. The system will consequently remain in RESET for at least one second after power up. After power up the Analogue Watchdog circuit monitors the oscillator. If it stops for any reason other then SLEEP mode, then a RESET is generated and the STB/RST pin is driven high. 4.2 Reset Pin During active or STANDBY mode the RESET terminal has a debouncer to reject noise and therefore must be active high for at least 2ms or 16ms (CLK = 32kHz) - software selectable by DebCK in CIRQD register. (See Table 37) When cancelling sleep mode, the debouncer is not active (no clock), however, reset passes through an analogue filter with a time constant of typical. 5s. In this case Reset pin must be high for at least 10 s to generate a system reset. Copyright (c) 2005, EM Microelectronic-Marin SA 9 www.emmicroelectronic.com R EM6607 4.3 Input port (PA0..PA3) RESET With a mask option it is possible to choose from eleven PortA reset combinations. The selected ports must be simultaneously high for at least 2ms/16ms (CLK = 32kHz) due to the presence of debouncers. Note also, that RESET with port A is not possible during SLEEP mode. Below are the combinations of Port A (PA0..PA3) inputs, which can be used to generate a RESET. They can be selected by metal PortA RESET mask option, described in chapter 14. Table 4. PortA Inputs RESET options (metal Hardware option) Opt. Code rstpa_no rstpa_3h rstpa_5h rstpa_6h rstpa_7h rstpa_9h rstpa_ah rstpa_bh rstpa_ch rstpa_dh rstpa_eh rstpa_fh Function NO inputs RESET RESET = PA0 AND PA1 RESET = PA0 AND PA2 RESET = PA1 AND PA2 RESET = PA0 AND PA1 AND PA2 RESET = PA0 AND PA3 RESET = PA1 AND PA3 RESET = PA0 AND PA1 AND PA3 RESET = PA2 AND PA3 RESET = PA0 AND PA2 AND PA3 RESET = PA1 AND PA2 AND PA3 RESET = PA0 AND PA1 AND PA2 AND PA3 4.4 Watchdog Timer RESET The Watchdog Timer RESET is a software option and if used it will generate a RESET if it is not cleared. See section 5. Watchdog timer for details. Table 5. Watchdog-Timer Option (software option) NoWD bit in Option register Watchdog Function Without Watchdog Time-out reset With Watchdog Time-out reset 1 0 4.5 Software Power-On-Reset This is software generation of POR, which can be used mainly to reset the circuit and start again the Power-Check function if enabled to be sure that VDD supply is high enough when circuit will start to work again due to increased VDD. When VDD starts to decrease due to any reason and software by periodically testing the VDD min by SVLD function detects this, user can generate POR at VDD min and like that the circuit will go in Reset until Power-Check level is satisfied again to guarantee the proper circuit operation, not to fall in a grey zone below VDD min until Static POR does it job at typ. 0.9V. Table 6. Software Power-On-Reset SoftPOR in RegSoftPOR register Software POR function Software POR start No Software POR 1 0 Copyright (c) 2005, EM Microelectronic-Marin SA 10 www.emmicroelectronic.com R EM6607 4.6 CPU State after RESET RESET initialises the CPU as shown in the table below. Table 7. Initial Value after RESET bits 12 12 12 2 7 1 1 1 16 4 symbol PC0 PC1 PC2 SP IX CY Z HALT IR initial value $000 (as a result of Jump 0) undefined undefined SP(0) selected undefined undefined undefined 0 Jump 0 see peripheral memory map name Program counter 0 Program counter 1 Program counter 2 stack pointer index register Carry flag Zero flag HALT Instruction register periphery registers 4.7 POR with Power-Check Reset POR and Power-Check are supervising the VREG (digital) which follows more or less the VDD supply voltage on start-up to guarantee proper operation after Power-On. The resetcold signal is released when the VDD supply voltage is high enough for the IC to function correctly. During power-up of the EM6607 static POR (Power-On-Reset) cell supervising the VREG with level of typ. 0.9V is checked to give initial reset. Reset can be prolonged also with Power-Check function if enabled by metal option. In this case VDD must come above VL1 of the SVLD described in Chapter 11 Supply Voltage Level Detector (SVLD) to release the circuit reset signal and starts to execute instructions. 13H 134H When Power-Check is enabled a power-check logic is switched-on with POR signal high and starts to check periodically VDD against the SVLD-VL1 level which keeps resetcold active high until VDD > VL1. When used with external quartz first VDD check starts in the middle of quartz Cold-Start sequence - after first 16384 system clocks with the same timing as in normal SVLD operation. If VDD > VL1 Power-Check condition is met and system reset will wait until first 32768 clocks needed for Quartz Cold-Start is finished and release System reset. In case VDD < VL1, comparison will be repeated with every next 8 Hz system clock until VDD > VL1. In case of a very slow rising VDD, it might happen that Quartz Cold-Start is finished. System reset will keep the EM6607 under reset until first time VDD becomes higher as VL1 to guarantee good operating conditions (oscillator stabilized during its Cold-Start delay and VDD is high enough to avoid "grey" zone between static POR and VL1). IMPORTANT: special care should be taken, when Power Supply starts to fall close to or below VDD min. Frequent checking of the SVLD VL1 (1.3V) must be done. Between minimum VDD supply of 1.2V and static POR level of 0.9V there is a grey zone, which must be avoided for proper operation. Copyright (c) 2005, EM Microelectronic-Marin SA 11 www.emmicroelectronic.com R EM6607 5 Oscillator A built-in crystal oscillator circuit generates the system-operating clock for the CPU and peripheral circuits from an externally connected crystal (typ. 32.768kHz) and trimmer capacitor (from Qin tw. VSS). The regulated voltage, VREG, supplies the oscillator circuit. In SLEEP mode the oscillator is stopped. With Fout bit in PA3cnt register we can put the system 32.768 Hz frequency on STB/RST pin as output. 5.1 Prescaler Table 8. Prescaler interrupts source PSF1 0 0 1 1 PSF0 0 1 0 1 Interrupt frequency mask(no interrupt) 1 Hz 8 Hz 32 Hz The input to the prescaler is the system clock signal. The prescaler consists of a fifteen (15) element divider chain which delivers clock signals for the peripheral circuits such as the timer/counter, buzzer, I/O debouncers and edge detectors, as well as generating prescaler interrupts. The frequency of prescaler interrupts is software selectable, as shown in Table 8. Table 9. Bit 3 2 1 0 Prescaler control register - PRESC Name MTim PRST PSF1 PSF0 Reset 0 0 0 R/W R/W R/W R/W R/W Description Timer/Counter Interrupt Mask Prescaler reset Prescaler Interrupt select 1 Prescaler Interrupt select 0 6 Watchdog timer If for any reason the CPU crashes, then the watchdog timer can detect this situation and output a system reset signal. This function can be used to detect program overrun. For normal operation the watchdog timer must be reset periodically by software at least once every three seconds (CLK = 32kHz) or a system reset signal is generated to CPU and periphery. The watchdog is active during STANDBY. Setting the NoWD bit to 1 in the Option register deactivates the watchdog-reset function. In worst case because of prescaler reset function WD time-out can come down to 2 seconds. Writing 1 to the WDRST bit resets the watchdog timer. Writing 0 to WDRST has no effect. The watchdog timer also operates in STANDBY mode. It is therefore necessary to reset it if this mode continues for more than three seconds. One method to do so is to use the prescaler 1Hz interrupt such, that the watchdog is reset every second. Table 10. Bit 3 2 1 0 Watchdog register - WD Name WDRST Slmask WD1 WD0 Reset 0 0 R/W R/W R/W R R Description Watchdog timer reset SLEEP mask bit WD Timer data 1/4 Hz WD Timer data 1/2 Hz Copyright (c) 2005, EM Microelectronic-Marin SA 12 www.emmicroelectronic.com R EM6607 7 INPUT and OUTPUT ports The EM6607 has five independent 4-bit ports, as shown in Table below Table 11. Port PA(0:3) Input / Output Ports Overview Mode Input Mask Options Pull-Up/Down (*)Debouncer (*) + or - IRQ edge RESET combination Nch open drain output Pull-Up/Down on input Function(s) Input Interrupt Software Test Variable PA3 input for event counter RESET input(s) Input or Output PB0 for buzzer output in 24-pin version High Current outputs Input or Output Port Interrupt PB(0:3) PC(0:3) Individual input or output (high Current) Port input or output PD(0:3) PE(0:3) Port input or Output Individual input or output Pull-Up/Down (*)+ or - IRQ edge (*)Debouncer Nch open drain output Pull-Up/Down on Input Nch open drain output Pull-Up/Down on Input Nch open drain output Input or Output Port PD0 -SWB serial clock output PD1 -SWB serial data output Input or Output Port PE0 for buzzer output in 28-pin version (*) Some options can be set also by Option register. Table 12. Bit 3 2 1 0 Option register - Option Name IRQedgeR debPCN debPAN NoWD Reset 0 0 0 0 R/W R/W R/W R/W R/W Description Rising edge interrupt for portA&C PortC without/with debouncer PortA without/with debouncer WatchDog timer Off IRQedgeR : debPAN : debPCN : NoWD : Valid for both PortA and PortC input interrupt edge. By default interrupt are active on a falling edge. When set to 1 the rising edge is active. By default (after a reset) debouncers are enabled on whole PortA. Writing 1 removes the debouncers from the PortA. By default debouncers are enabled on whole PortC. Writing 1 removes the debouncers from the PortC. By default Watchdog timer is On (NoWD=0). Writing 1 removes the watchdog timer. 7.1 PortA The EM6607 has one 4-bit general purpose input port. Each of the input port terminals PA3..PA0 has an internal pullUp/Down resistor, which can be selected with mask options. Port information is directly read from the pin into a register. On inputs PA0, PA1, PA2 and PA3 debouncers for noise rejection are added by default. For interrupt generation, either direct input and debounced input can be chosen. With the debPAN written to 0 in the Option register all the PortA inputs are debounced and with the debPAN bit at 1 none of the PortA inputs are debounced. With the debouncer selected the input must be stable for two rising edges of 1024Hz or 128Hz clocks (at 32kHz). This corresponds to a worst case of 1.95ms or 15.62msec. PortA terminals PA0, PA1 and PA2 are also used as input conditions for conditional software branches as shown on the next page: Copyright (c) 2005, EM Microelectronic-Marin SA 13 www.emmicroelectronic.com R EM6607 Debounced PA0 is connected to CPU TestVar1 Debounced PA1 is connected to CPU TestVar2 Debounced PA2 is connected to CPU TestVar3 Vdd debPAN 1 IRQedgeR 1 0 PA[3:0] 1 Mask option Debouncer 0 0 Mask option CPU Testvar DebCK PortA RD Figure 7. Port A Additionally, PA3 can also be used as the input terminal for the event counter. The input port PA(0:3) has also individually selectable interrupts. Each port has its own interrupt mask bit in the MPortA register. When an interrupt occurs, reading of the IRQpA and the IntRq registers allows identifying the source of the interrupt. The IRQpA register is automatically cleared by reading the register or by a RESET,. Reading IRQpA register also clears the INTPA flag in IntRq register. At initial RESET the MPortA is set to 0, thus disabling any input interrupts. See paragraph 9 for further details about the interrupt controller. 7.1.1 Table 13. Bit 3 2 1 0 Table 14. Bit 3 2 1 0 Table 15. Bit 3 2 1 0 PortA registers PortA input status register - PortA Name PA3 PA2 PA1 PA0 Reset R/W R R R R Description PA3 input status PA2 input status PA1 input status PA0 input status PortA Interrupt request register - IRQpA Name IRQpa3 IRQpa2 IRQpa1 IRQpa0 Reset 0 0 0 0 R/W R R R R Description input PA3 interrupt request flag input PA2 interrupt request flag input PA1 interrupt request flag input PA0 interrupt request flag PortA interrupt mask register - MportA Name MPA3 MPA2 MPA1 MPA0 Reset 0 0 0 0 R/W R/W R/W R/W R/W Description interrupt mask for input PA3 interrupt mask for input PA2 interrupt mask for input PA1 interrupt mask for input PA0 Copyright (c) 2005, EM Microelectronic-Marin SA 14 www.emmicroelectronic.com data bus DB[3:0] Interrupt Request IRQpA R EM6607 7.2 PortB Port B is a 4-bit general-purpose I/O port. Outputs on this port are high current outputs. Each bit PB(0:3) can be separately configured by software to be either input or output by writing to the corresponding bit of the CIOPortB control register. The PortB register is used to read data when in input mode and to write data when in output mode. On each terminal controlled Pull-Up/Down resistor can be selected by metal option, which are active only when selected as input. Special case is when we want to use internal Strong Pull-Up resistor also when PortB terminal is declared as N-channel open drain output and internal Pull-Up resistor is used to pull up the output (not-controlled Pull-Up). This is a special option "sod" = strong Pull-Up for Open drain- active all the time (when terminal is input or output). Writing 0 to the corresponding bit in the CIOPortB register sets input mode. This results in a high impedance state with the status of the pin being read from register PortB. Writing 1 to the corresponding bit in the CIOPortB register sets output mode. Consequently the output terminal follows the status of the bits in the PortB register. At initial RESET the CIOPortB register is set to 0, thus setting the port to input. Additionally, PB0 can also be used as a three-tone buzzer output. For details see section 7, Buzzer. 7.2.1 Table 16. Bit 3 2 1 0 PortB registers PortB input/output status register - PortB Name PB3 PB2 PB1 PB0 Reset R/W R/W R /W R/W R /W Description PB3 I/O data PB2 I/O data PB1 I/O data PB0 I/O data Table 17. Bit 3 2 1 0 PortB Input/Output control register - CIOportB Name CIOPB3 CIOPB2 CIOPB1 CIOPB0 Reset 0 0 0 0 R/W R/W R/W R/W R/W Description PB3 Input/Output select PB2 Input/Output select PB1 Input/Output select PB0 Input/Output select Vdd Mask option Mask option PG NG D OE Port B Sleep OEBsleepRes 2Y PB[3:0] 0 Mask option 2N 1 Mask option CIOportB 3Y 3N Mask option Mask option PortB RD Figure 8. Port B If metal mask option 3Y (Input blocked when Output) is used and port is declared as Output (CIOPortB = 1111b) the real port information cannot be read directly. In this case no direct logic operations (like AND PortB) on Output ports are possible. This logic operation can be made with an image of the Port saved in the RAM which we store after on the output port. This is valid for PortB, PortC and PortD when declared as output and the metal Option 3Y is used. In the case of metal option 3N selected direct logic operations on output ports are possible. If OEBsleepRes bit in Option2 register is set to "1" (Output Hi-Z in SLEEP mode) the active Output will go tri-state when the circuit goes into SLEEP mode. In the case of OEBsleepRes at "0", output stays active also in the SLEEP mode. Copyright (c) 2005, EM Microelectronic-Marin SA 15 www.emmicroelectronic.com data bus DB[3:0] R EM6607 7.3 PortC This port can be configured as either input or output (but it is not bitwise selectable). When in input mode it implements the identical interrupt functions as PortA. The PortC register is used to read data when input mode and to write data when in output mode. Input mode is set by writing 0 in the I/O control bit CIOPC in register CPIOB, the input becomes high impedance. On each terminal controlled Pull-Up/Down resistor can be selected by metal option, which are active only when port is input. When we want to use internal Strong pull-up resistor also when PortC terminal is declared as N-channel open drain output and internal pull-up resistor is used to pull up the output (not-controlled pull-up). This is a special option "sod" = strong pull-up for Open drain- active all the time (when terminal is input or output). The output mode is selected by writing 1 to CIOPC bit, and the terminal follows the bits in the PortC register. When PortC is used as an input, interrupt functions as described for PortA can be enabled. Input to the interrupt logic can be direct or via a debounced input. With the debPCN bit at 0 in the Option register all the PortC inputs are debounced and with the debPCN bit at 1 none of the PortC inputs are debounced. MPortC is the interrupt mask register for this port and IRQpC is the portC interrupt request register. See also section 9. By writing the PA&C bit in the CPIOB data register it is possible to combine PortA and PortC interrupt requests (logic AND) as shown in Table 17 Table 18. IRQPA 0 0 1 1 0 1 1 Ports A&C Interrupt IRQPC 0 1 0 1 1 0 1 PA&C X 0 0 0 1 1 1 Request to CPU No Yes Yes Yes No No Yes At initial reset, the CPIOC control register is set to 0, and the port is in input mode. The MPortC register is also set to 0, therefore disabling interrupts. 7.3.1 Table 19. Bit 3 2 1 0 PortC registers PortC input/output register - PortC Name PC3 PC2 PC1 PC0 Reset R/W R/W R /W R/W R /W Description PC3 I/O data PC2 I/O data PC1 I/O data PC0 I/O data Table 20. Bit 3 2 1 0 PortC Interrupt request register - IRQpC Name IRQpc3 IRQpc2 IRQpc1 IRQpc0 Reset 0 0 0 0 R/W R R R R Description input PC3 interrupt request flag input PC2 interrupt request flag input PC1 interrupt request flag input PC0 interrupt request flag Table 21. Bit 3 2 1 0 PortC interrupt mask register - MportC Name MPC3 MPC2 MPC1 MPC0 Reset 0 0 0 0 R/W R/W R/W R/W R/W Description interrupt mask for input PC3 interrupt mask for input PC2 interrupt mask for input PC1 interrupt mask for input PC0 Copyright (c) 2005, EM Microelectronic-Marin SA 16 www.emmicroelectronic.com R EM6607 debPCN 1 0 IRQedgeR 1 0 Interrupt Request IRQpC Debouncer Vdd DebCK Port C Sleep OECsleepRes PG NG D OE 2Y PC[3:0] 0 Mask option Mask option Mask option 2N 1 Mask option CIOPC 3Y 3N Mask option Mask option PortC RD Figure 9. Port C If OECsleepRes bit in Option2 register is set to "1" (=6Y (Output Hi-Z in SLEEP mode)) the active Output will go tri-state when the circuit goes into SLEEP mode. In the case of 6N - OECsleepRes at "0", output stay active also in the SLEEP mode. Table 22. Bit 3 2 1 0 Option2 register - Option2 Name OEDsleepRes OECsleepRes OEBsleepRes BuzzerPE0 Reset 0 0 0 0 R/W W W W W Description PortD Output Enable reset by Sleep mode PortC Output Enable reset by Sleep mode PortB Output Enable reset by Sleep mode Buzzer on PE0 if 1, on PB0 if 0 Copyright (c) 2005, EM Microelectronic-Marin SA 17 www.emmicroelectronic.com data bus DB[3:0] R EM6607 7.4 PortD The EM6607 has one all purpose I/O port similar to PortC but without interrupt capability. The PortD register is used to read input data when an input and to write output data for output. The input line can be pulled Up/Down (metal option) when the port is used as input. Input mode is set by writing 0 to the I/O control bit CIOPD in register CPIOB, and the terminal becomes high impedance. On each terminal controlled Pull-Up/Down resistor can be selected by metal option which are active only when selected as input. Special case is when we want to use internal Strong pull-up resistor also when PortC terminal is declared as N-channel open drain output and internal pull-up resistor is used to pull up the output (not-controlled pull-up). This is a special option "sod" = strong pull-up for Open drain- active all the time (when terminal is input or output). Output mode is set by writing 1 to the control bit CIOPD. Consequently, the terminal follows the status of the bits in the PortD register. If Serial Write Buffer function is enabled PD0 and PD1 terminals of PortD output serial clock and serial data respectively. For details see 11.0 Serial Write Buffer. 7.4.1 Table 23. Bit 3 2 1 0 Table 24. Bit 3 2 1 0 PortD registers PortD Input/Output register - PortD Name PD3 PD2 PD1 PD0 Reset 0 0 0 0 R/W R/W R/W R/W R/W Description PD3 I/O data PD2 I/O data PD1 I/O data PD0 I/O data Ports control register - CPIOB Name CIOPD CIOPC PA&C Reset 0 0 0 R/W R/W R/W R/W R/W Description not used I/O PortD select I/O PortC select Logical AND of IRQ's from PortA & PortC Vdd Mask option Mask option PG NG D OE Port D Sleep OEBsleepRes 2Y PD[3:0] 0 Mask option 2N 1 Mask option CIOPD 3Y 3N Mask option Mask option PortD RD Figure 10. Port D If OEDsleepRes bit in Option2 register is set to "1" (Output Hi-Z in SLEEP mode) the active Output will go tri-state when the circuit goes into SLEEP mode. In the case of OEDsleepRes at "0", output stay active also in the SLEEP mode. Copyright (c) 2005, EM Microelectronic-Marin SA 18 www.emmicroelectronic.com data bus DB[3:0] R EM6607 7.5 PortE PortE is a 4-bit I/O port where each pad PE(0:3) can be separately configured by software to be either input or output by writing to the corresponding bit of the CIOPortE control register. The PortE register is used to read data when in input mode and to write data when in output mode. On each terminal controlled Pull-Up/Down resistor can be selected by metal option which are active only when selected as input. Special case is when we want to use internal Strong pull-up resistor also when PortC terminal is declared as N-channel open drain output and internal pull-up resistor is used to pull up the output (notcontrolled pull-up). This is a special option "sod" = strong pull-up for Open drain- active all the time (when terminal is input or output). Input mode is set by writing 0 to the corresponding bit in the CIOPortE register. This results in a high impedance state with the status of the pin being read from register PortE. Output mode is set by writing 1 to the corresponding bit in the CIOPortE register. Consequently the output terminal follows the status of the bits in the PortE register. At initial RESET the CIOPortE register is set to 0, thus setting the port to an input. 7.5.1 Table 25. Bit 3 2 1 0 Table 26. Bit 3 2 1 0 PortE registers PortE Input/Output status register - PortE Name PE3 PE2 PE1 PE0 Reset R/W R/W R /W R/W R /W Description PE3 I/O data PE2 I/O data PE1 I/O data PE0 I/O data PortE Input/Output control register - CIOPortE Name CIOPE3 CIOPE2 CIOPE1 CIOPE0 Reset 0 0 0 0 R/W R/W R/W R/W R/W Description PE3 Input/Output select PE2 Input/Output select PE1 Input/Output select PE0 Input/Output select Vdd Mask option Mask option PG NG D OE Port E 2Y PE[3:0] 0 Mask option 2N 1 Mask option CIOPE PortE RD Figure 11. Port E Copyright (c) 2005, EM Microelectronic-Marin SA 19 www.emmicroelectronic.com data bus DB[3:0] R EM6607 8 BUZZER The EM6607 has one 50% duty cycle output with three different frequencies, which can be used to drive a buzzer. I/O terminal PB0 in 24-pin package or PE0 in 28-pin package (BuzzerPE0 option) is used for this function when the buzzer is enabled by setting the BUen bit to 1 . Table 22 below shows how to select the frequency by writing to the BCF1 and BCF0 control flags in the BEEP register. After writing to the buzzer control register BEEP, the chosen frequency (or silence) is selected immediately. With the BUen bit set to 1, the selected frequency is output at PB0 when BuzzerPE0 is 0. When the BUen is set to 0 PB0 is used as a normal I/O terminal of PortB. The BUen bit has a higher priority over the I/O control bit CIOPB0 in the CIOPortB register. In case when BuzzerPE0 is 1 and BUen is set to 1 PE0 becomes output and PB0 is not influenced by buzzer function. Tone frequency silence 1024 Hz 2048 Hz 2667 Hz Table 2. BCF1 0 0 1 1 BCF0 0 1 0 1 Buzzer frequency selection 8.1 Buzzer Register Buzzer control register - BEEP Name TimEn BUen BCF1 BCF0 Reset 0 0 0 0 R/W R/W R/W R/W R/W Description Timer/counter enable Buzzer enable Buzzer Frequency control Buzzer Frequency control Table 27. Bit 3 2 1 0 Table 28. Buzzer output pad allocation BuzzerPE0 in register Option2 Buzzer on PB0 or PE0 Buzzer output on PE0 Buzzer output on PB0 1 0 Table 29. CIOPB0 PB0 & PE0 function used with BUen and BuzzerPE0 control bits CIOPE0 BUen BuzzerPE0 Function distributions on PB0 and PE0 pads 0 1 X 0 1 0 1 0 X X 0 0 1 1 1 X X 0 1 1 PB0 and PE0 are Inputs PB0 and PE0 are independent outputs PB0 is Buzzer output, PE0 is input PB0 is input, PE0 is Buzzer output PB0 is general output, PE0 is Buzzer output Copyright (c) 2005, EM Microelectronic-Marin SA 20 www.emmicroelectronic.com R EM6607 9 Timer/Event Counter The EM6607 has a built-in 8 bit countdown auto-reload Timer/Event counter that takes an input from either the prescaler or Port PA3. If the Timer/Event counter counts down to $00 the interrupt request flag IntTim is set to 1. If the Timer/Event counter interrupt is enabled by setting the mask flag MTimC set to 1, then an interrupt request is generated to the CPU. See also section 9. If used as an event counter, pulses from the PA3 terminal are input to the event counter. See figure 10 and tables 28 and 29 on the next page for PA3 source selection (debounced or not, Rising/Falling edge). By default rising and debounced PA3 input is selected. The timer control register TimCtr selects the auto-reload function and input clock source. At initial RESET this bit is cleared to 0 selecting no auto-reload. To enable auto-reload TimAuto must be set to 1. The Timer/Event counter can be enabled or disabled by writing to the TIMen control bit in the BEEP register. At initial RESET it is cleared to 0. When used as timer, it is initialised according to the data written into the timer load/status registers LTimLS (low 4 bits) and HTimLS (high four bits). The timer starts to count down as soon as the LTimLS value is written. When loading the Timer/Event counter registers the correct order must be respected: First, write either the control register TimCtr or the high data nibble HTimLS. The last register written should be the low data nibble LTimLS. During count down, the timer can always be reloaded with a new value, but the high four bits will only be accepted during the write of the low four bits. In the case of the auto-reload function, the timer is initialised with the value of the load registers LTimLS and HTimLS. Counting with the auto-reload function is only enabled during the write to the low four bits, (writing TimAuto to 1 does not start the timer counting down with the last value in the timer load registers but it waits until a new LTimLS load). The timer counting to $00 generates a timer interrupt event and reloads the registers before starting to count down again. To stop the timer at any time, a write of $00 can be made to the timer load registers, this sets the TimAuto flag to 0. If the timer is stopped by writing the TimEn bit to 0, the timer status can be read. The current timer status can be always obtained by reading the timer registers LTimLS and HTimLS. For proper operation read ordering should be respected such that the first read should be of the LTimLS register followed by the HTimLS register. Example: To have continous 1sec timer IRQ with 128Hz one has to write 128dec (80hex) in Timer registers with auto-reload. Using the Timer/Event Counter as the event counter allows several possibilities: 1.) Firstly, load the number of PA3 input edges expected into the load registers and then generate an interrupt request when counter reaches $00. 2.) The second is to write timer/counter to $FF, then select the event counter mode, and lastly enable the event counter by setting the TimEn bit to 1, which starts the count. Because the counter counts down, a binary complement has to be done in order to get the number of events at the PA3 input. 3) Another option is to use the Timer/Event counter in conjunction with the prescaler interrupt, such that it is possible to count the number of the events during two consecutive 32Hz, 8Hz or 1Hz prescaler interrupts. Figure 12. Timer / Event Counter Copyright (c) 2005, EM Microelectronic-Marin SA 21 www.emmicroelectronic.com R EM6607 Table below shows the selection of inputs to the Timer/Event counter. Table 30. TEC2 0 0 0 0 1 1 1 1 Timer Clock Selection TEC1 0 0 1 1 0 0 1 1 TEC0 0 1 0 1 0 1 0 1 Timer/Counter clock source not active 2048 Hz from prescaler 512 Hz from prescaler 128 Hz from prescaler 32 Hz from prescaler 8 Hz from prescaler 1 Hz from prescaler PA3 input terminal (see tables 28 and 29) 9.1 Timer/Counter registers Timer control register - TimCtr Name TimAuto TEC2 TEC1 TEC0 Reset 0 0 0 0 R/W R/W R/W R/W R/W Description Timer/Counter AUTO reload Timer/Counter mode 2 Timer/Counter mode 1 Timer/Counter mode 0 Table 31. Bit 3 2 1 0 Table 32. Bit 3 2 1 0 Table 33. Bit 3 2 1 0 Table 34. bit 3 2 1 0 Table 35. PA3cntin 0 1 1 1 1 LOW Timer Load/Status register - LTimLS (4 low bits) Name TL3/TS3 TL2/TS2 TL1/TS1 TL0/TS0 Reset 0 0 0 0 R/W R/W R/W R/W R/W Description Timer load/status bit 3 Timer load/status bit 2 Timer load/status bit 1 Timer load/status bit 0 HIGH Timer Load/Status register - HTimLS (4 high bits) Name TL7/TS7 TL6/TS6 TL5/TS5 TL4/TS4 Reset 0 0 0 0 R/W R/W R/W R/W R/W Description Timer load/status bit 7 Timer load/status bit 6 Timer load/status bit 5 Timer load/status bit 4 PA3 counter input selection register - PA3cnt Name WDanadis Fout PA3cntin Reset 0 0 0 0 R/W R/W R/W R/W Description empty Analogue WD disable System freq. output on STB/RST pad PA3 input status PA3 counter input selection debPAN X 0 0 1 1 IRQedgeR X 0 1 0 1 Counter source PA3 debounced rising edge PA3 debounced falling edge PA3 debounced rising edge PA3 not debounced falling edge PA3 not debounced rising edge X ( Don't care) Copyright (c) 2005, EM Microelectronic-Marin SA 22 www.emmicroelectronic.com R EM6607 10 Interrupt Controller The EM6607 has 12 different interrupt sources, each of which is maskable. These are: External (9) - PortA PA3..PA0 inputs - PortC PC3..PC0 inputs - Combined AND of PortA * PortC Internal (3) - Prescaler (32Hz / 8Hz / 1Hz) - Timer/Event counter - SWB in interactive mode For an interrupt to the CPU to be generated, the interrupt request flag must be set (INTxx), and the corresponding mask register bit must be set to 1 (Mxx), the general interrupt enable flag (INTEN) must also be set to 1. The interrupt request can be masked by the corresponding interrupt mask registers MPortx for each input interrupt and by PSF0 ,PSF1 and MTim for internal interrupts. At initial reset the interrupt mask bits are set to 0. INTEN bit is set automatically to 1 by Halt Instruction except when starting the Automatic SWB transfer (see Serial Write Buffer (SWB) chapter 11) The CPU is interrupted when one of the interrupt request flags is set to 1 in register IntRq and the INTEN bit is enabled in the control register CIRQD. INTTE and INTPR flags are cleared automatically after a read of the IntRq register. The other two interrupt flags INTPA (IRQ from PortA) and INTPC (IRQ from PortC) in the IntRq register are cleared only after reading the corresponding Port interrupt request registers IRQpA and IRQpC. At the Power on reset and in SLEEP mode the INTEN bit is also set to 0 therefore not allowing any interrupt requests to the CPU until it is set to 1 by software. Since the CPU has only one interrupt subroutine and because the IntRq register is cleared after reading, the CPU does not miss any of the interrupt requests which come during the interrupt service routine. If any occur during this time a new interrupt will be generated as soon as the CPU comes out of the current interrupt subroutine. Interrupt priority can be controlled through software by deciding which flag in the IntRq register should be serviced first. For SWB interactive mode interrupt see section 11.0 Serial Write Buffer. 10.1 Interrupt control registers Table 36. Bit 3 2 1 0 2 Main Interrupt request register - IntRq (Read Only)* Name INTPR INTTE INTPC INTPA SLEEP Reset 0 0 0 0 0 R/W R R R R W* Description Prescaler interrupt request Timer/counter interrupt request PortC Interrupt request PortA Interrupt request SLEEP mode flag * Write bit 2 only if SLmask=1 If the SLEEP flag is written with 1 then the EM6607 goes immediately into SLEEP mode (SLmask was at 1). Copyright (c) 2005, EM Microelectronic-Marin SA 23 www.emmicroelectronic.com R EM6607 Table 37. Bit 3 2 1 0 Register - CIRQD Name DebCK INTEN Reset 0 0 0 0 R/W R/W R/W* R/W R/W Description Reserved, must written to 0 Reserved, must written to 0 Debouncer clock select (0=2ms : 1=16ms) Enable interrupt to CPU (1=enabled) Figure 13. Interrupt Request generation IRQ mask bit which can be written to 0 or 1 (1 to enable an interrupt) interrupt request flag which is set on the input rising edge. Timer IRQ flag INTTE and prescaler IRQ flag INTPR arrive independent of their mask bits not to loose any timing information. But the processor will be interrupted only with mask set to 1. Copyright (c) 2005, EM Microelectronic-Marin SA 24 www.emmicroelectronic.com R EM6607 11 Supply Voltage Level Detector (SVLD) The EM6607 has a software configurable Supply Voltage Level detector. Three levels can be defined within the power supply range. During SLEEP mode this function is disabled. Voltage level detector can be used also for Power-Check on Start-up of the EM6607 micro-controller when VDD is applied (see Chapter 4.7 POR with Power-Check Reset). 135H 136H The required voltage compare level is selected by writing the bits VLC1 and VLC2 in the SVLD control register that also activates the compare measurement. Since the measurement is not immediate the busy flag remains high during the measurement and is automatically cleared low when the measurement is finished. Reading the VLDR flag indicates the result. If the result is 0 then the voltage level is higher than the selected compare level. And if 1 it is lower than the compare level. The result VLDR of the last measurement remains until the new one is finished. The new result overwrites the previous one. During the SVLD operation power consumption increases by approximately 3A for 3.9msec. The measurement internally starts with the rising 256Hz edge following the SVLD test command. The additional SVLD consumption stops after the falling edge of the 256Hz internal clock. Table below lists the voltage level selection Table 38. SVLD Level selection VLC1 0 0 1 1 VLC0 0 1 0 1 Possible levels implementations Voltage level SVLD disabled VL1 VL2 VL3 VL1 : possible levels are from 1.3V to 3V by step of 100mV. VL2 : possible levels are 2.3V ; 2.6V to 3.5V by step of 100mV ; 3.7V and 4V VL3 : possible levels are 2.6V to 3.5V by step of 100mV ; 3.7V and 4V 137H VL1 level is also the level used for Power check if activated (table 15.1.1). Table 39. Bit 3 2 1 0 SVLD control register - SVLD Name VLDR busy VLC1 VLC0 Reset 0 0 0 0 R/W R R R/W R/W Description SVLD result (0=higher 1=lower) measurement in progress SVLD level control 1 SVLD level control 0 Copyright (c) 2005, EM Microelectronic-Marin SA 25 www.emmicroelectronic.com R EM6607 12 Serial Write Buffer - SWB The EM6607 has a simple Serial Write Buffer (SWB) which outputs serial data and serial clock. The SWB is enabled by setting the bit V03 in the CLKSWB register as well as setting port D to output mode. The combination of the possible PortD mode is shown in Table 34. In SWB mode the serial clock is output on port D0 and the serial data is output on port D1. The signal TestVar[3], which is used by the processor to make conditional jumps, indicates "Transmission finished" in automatic send mode or "SWBbuffer empty" in interactive send mode. In interactive mode, TestVar[3] (see port A section) is equivalent to the interrupt request flags stored in IntRq register : it permits to recognise the interrupt source. (See also the interrupt handling section 9.Interrupt Controller for further information). To serve the "SWBbuffer empty " interrupt request, one only has to make a conditional jump on TestVar[3]. Bits ClkSWB0 and ClkSWB1 in the ClkSWB register select the Serial Write Buffer output clock frequency. The possible values are 1kHz (default), 2kHz, 8kHz or 16kHz and are shown in Table below: Table 40. SWB clock selection CkSWB1 0 0 1 1 CkSWB0 0 1 0 1 SWB clock output 1024 Hz 2048 Hz 8192 Hz 16384 Hz Table 41. Bit 3 2 1 0 Table 42. SWB clock selection register - ClkSWB Name V03 CkSWB1 CkSWB0 PortD status CIOPD 0 0 1 1 V03 0 1 0 1 PD0 input input output PD0 serial clock Out PD1 input input output PD1 SWB serial data PD2 input input output PD2 output PD2 PD3 input input output PD3 output PD3 Reset 0 0 0 0 R/W R/W R R/W R/W Description Serial Write buffer selection RESERVED - read 0 SWB clock selector 1 SWB clock selector 0 PortD status NORMAL NORMAL NORMAL SWB When the SWB is enabled by setting the bit V03 TestVar[3], which is used to make conditional jumps, is reassigned to the SWB and indicates either "SWBbuffer empty " interrupt or "Transmission finished" . After Power-on-RESET V03 is cleared at "0" and TestVar[3] is consequently assigned to PA2 input terminal. The SWB data is output on the rising edge of the clock. Consequently, on the receiver side the serial data can be evaluated on falling edge of the serial clock edge. Copyright (c) 2005, EM Microelectronic-Marin SA 26 www.emmicroelectronic.com R EM6607 Figure 14. Table 43. Bit 3 2 1 0 Serial write buffer SWB buffer register - SWbuff Name Buff3 Buff2 Buff1 Buff0 Reset 1 1 1 1 R/W R/W R/W R/W R/W Description SWB buffer D3 SWB buffer D2 SWB buffer D1 SWB buffer D0 Table 44. Bit 3 2 1 0 SWB Low size register - LowSWB Name Size[3] Size[2] Size[1] Size[0] Reset 0 0 0 0 R/W R/W R/W R/W R/W Description Auto mode buffer size bit3 Auto mode buffer size bit2 Auto mode buffer size bit1 Auto mode buffer size bit0 Table 45. Bit 3 2 1 0 SWB High size register - HighSWB Name AutoSWB StSWB Size[5] Size[4] Reset 0 0 0 0 R/W R/W R/W R/W R/W Description SWB Automatic mode select SWB start interactive mode Auto mode buffer size bit5 Auto mode buffer size bit4 The SWB has two operational modes, automatic mode and interactive mode. Copyright (c) 2005, EM Microelectronic-Marin SA 27 www.emmicroelectronic.com R EM6607 12.1 SWB Automatic send mode Automatic mode enables a buffer on a predefined length to be sent at high transmission speeds ( up to 16khz). In this mode user prepares all the data to be sent (minimum 8 bits, maximum 256 bits) in RAM. The user then selects the clock speed, sets the number of data nibbles to be sent, selects automatic transmission mode (AutoSWB bit set to 1) and enters STANDBY mode by executing a HALT instruction. Once the HALT instruction is activated the SWB peripheral module sends the data in register SWBuff followed by the data in the RAM starting at address 00 up to the address specified by the bits size[5:0] located in the LowSWB, HighSWB registers. During automatic transmission the general INTEN bit is disabled automatically to prevent other Interrupts to reset the standby mode. At the end of automatic transmission EM6607 leaves standby mode and sets TestVar[3] high. TestVar[3] = 1 is signaling SWB transmission is terminated. Once the transmission is finished, do not forget to enable the general INTEN bit if necessary. The data to be sent must be prepared in the following order: First nibble to be sent must be written in the SWBuff register . The other nibbles must be loaded in the RAM from address 0 (second nibble at adr.0, third at adr.1,...) up to the address with last nibble of data to be send = "size" address. Max. address space for SWB is 3E ("size" 3E hex) what gives with SWBuff up to 64 nibbles (256 bits) of possible data to be sent. The minimum possible data length we can send in Automatic SWB mode is 8 bits when the last RAM address to be sent is 00 ("size" = 00) Once data are ready in the RAM and in the SWBuff, user has to load the "size" (adr. of the last nibble to be send - bits size[5:0]) into the LowSWB and HighSWB register together with AutoSWB bit = 1. Now everything is ready for serial transmission. To start the transmission one has to put the EM6607 in standby mode with the HALT instruction. With this serial transmission starts. When transmission is finished the TESTvar[3] (can be used for conditional jumps) becomes active High, the AutoSWB bit is cleared, the processor is leaving the Standby mode and INTEN is switched on. Figure 15. Automatic Serial Write Buffer transmission The processor now starts to execute the first instruction placed after the HALT instruction (for instance write of SWBuff register to clear TESTvar[3]), except if there was a IRQ during the serial transmission. In this case the CPU will go directly in the interrupt routine to serve other interrupt sources. TestVar[3] stays high until SWBuff is rewritten. Before starting a second SWB action this bit must be cleared by performing a dummy write on SWBuff address. Because the data in the RAM are still present one can start transmitting the same data once again only by recharging the SWBuff , LowSWB and HighSWB register together with AutoSWB bit and putting the EM6607 in HALT mode will start new transmission. Copyright (c) 2005, EM Microelectronic-Marin SA 28 www.emmicroelectronic.com R EM6607 12.2 SWB Interactive send mode In interactive SWB mode the reloading of the data transmission register SWBbuff is performed by the application program. This means that it is possible to have an unlimited length transmission data stream. However, since the application program is responsible for reloading the data a continuous data stream can only be achieved at 1kHz or 2kHz transmission speeds. For the higher transmission speeds a series of writes must be programmed and the serial output clock will not be continuous. Serial transmission using the interactive mode is detailed in Figure 14. Programming of the SWB in interactive is achieved in the following manner: Select the transmission clock speed using the bits ClkSW0 and ClkSW1 in the ClkSWB register. Load the first nibble of data into the SWB data register SWBbuff Start serial transmission by selecting the bit StSWB in the register HighSWB register. Once the data has been transferred into the serial transmission register a non maskable interrupt (SWBEmpty) is generated and TESTvar[3] goes high. The CPU goes in the interrupt routine, with the JPV3 as first instruction in the routine one can immediately jump to the SWB update routine to load the next nibble to be transmitted into the SWBuff register. If this reload is performed before all the serial data is shifted out then the next nibble is automatically transmitted. This is only possible at the transmission speeds of 1KHz or 2KHz due to the number of instructions required to reload the register. At the higher transmission speeds of 8khz and 16khz the application must restart the serial transmission by writing the StSWB in the High SWBHigh register after writing the next nibble to the SWBbuff register. Each time the SWBuff register is written the "SWBbuffer empty interrupt" and TestVar[3] are cleared to "0". For proper operation the SWBuff register must be written before the serial clock drops to low during sending the last bit (MSB) of the previous data. Figure 16. Interactive Serial Write Buffer transmission After loading the last nibble in the SWBbuff register a new interrupt is generated when this data is transferred to an intermediate Shift Register. Precaution must be made in this case because the SWB will give repetitive interrupts until the last data is sent out completely and the STSWB bit goes low automatically. One possibility to overcome this is to check in the Interrupt subroutine that the STSWB bit went low before exiting interrupt. Be careful because if STSWB bit is cleared by software transmission is stopped immediately. At the end of transmission a dummy write of SWBuff must be done to clear TESTvar[3] and "SWBbuffer empty interrupt" or the next transmission will not work. Copyright (c) 2005, EM Microelectronic-Marin SA 29 www.emmicroelectronic.com R EM6607 13 STroBe / ReSeT Output The STB/RST output pin is used to indicate the EM6607 RESET condition as well as write operations to ports B, C and D. For a PortB, PortC and PortD write operation the STROBE signal goes high for half of the system clock period. Write is effected on falling edge of the strobe signal and it can this be used to indicate when data changes at the output port pins. In addition, any EM6607 internal RESET condition is indicated by a continuous high level on STB/RST for the period of the RESET. 14 Test at EM - Active Supply Current test For this purpose, five instructions at the end of the ROM will be added. Testloop: STI00H, 0AH LDR 1BH NXORX JPZ Testloop JMP 00H To stay in the testloop, these values must be written in the corresponding addresses before jumping in the loop: 1BH: 32H: 6EH: 6FH: 0101b 1010b 0010b 0011b Free space after last instruction: JMP 00H (0000) Remark: empty space within the program are filled with NOP (FOFF). Copyright (c) 2005, EM Microelectronic-Marin SA 30 www.emmicroelectronic.com R EM6607 15 Metal Mask Options The following options can be selected at the time of programming the metal mask ROM. Table 46. input/output Ports Pull-Down Yes / No Strong / Weak Pull-Up Yes / No Strong / Weak Nch-open drain Yes / No Input blocked when Output Yes / No Output Hi-Z in SLEEP mode Yes / No 0 1 (*1) 2 (*1) 3 (*2) 4 PE3 In/Out Put one letter (Y, N) in each BOX from proposed for the column. For Pull-Up/Down if "Y" add also one letter (S,W) to define type of resistor. (see 18.5 electrical parameters also) *1 When used as N-channel Open drain output not-controlled Pull-Up (Y-SOD) can be used. Pull Up active during Output also if Y-S is set in Pull-Up & Y for Nch-open drain an external resistor is needed to make output High !!!! because Pull Up is active during input only ! This is applicable only for Ports B,C,D and E which can be outputs also. *2 Port-wise for PortC and PortD (one possibility for the whole port); PortB bit-wise 138H A0 A1 A2 A3 B0 B1 B2 B3 C0 C1 C2 C3 D0 D1 D2 D3 E0 E1 E2 E3 PA0 input PA1 input PA2 input PA3 input PB0 In/Out PB1 In/Out PB2 In/Out PB3 In/Out PC0 In/Out PC1 In/Out PC2 In/Out PC3 In/Out PD0 In/Out PD1 In/Out PD2 In/Out PD3 In/Out PE0 In/Out PE1 In/Out PE2 In/Out OEBsleepRes Bit in Option2 register. Yes =1, No=0 OECsleepRes Bit in Option2 register. Yes =1, No=0 OEDsleepRes Bit in Option2 register. Yes =1, No=0 Table 47. PortB Hi Current Drive capability Driving to VSS (negative supply) Possible options are 4n (weak), 10n, 18n (strong) Driving to VDD (positive supply) Possible options are 6p (weak), 14p, 24p (strong) B0 B1 B2 B3 PB0 output PB1 output PB2 output PB3 output At higher VDD scaling of this buffer is needed not to overcome the Maximum VDD and VSS current for the IC. Put in each box one of 3 possibilities mentioned in the title of column like 18n, 24p (strongest configuration). Numbers above state for number of active N and P transistors in output buffer. See electrical parameters to know what to expect at different option. Important Note: Maximum VDD and VSScurrent MUST be limited to 90 mA !! Only 2 PortB High current terminals can switch at the same time in strongest configuration to limit the spikes generated by switching. Copyright (c) 2005, EM Microelectronic-Marin SA 31 www.emmicroelectronic.com R EM6607 15.1.1 Power-Check Level Option Option Name PwCheck Power-Check Yes / No Default Value A NO User Value B Power Check function can be enabled or disabled. For EM6603 compatibility the default selection is NO, but can be set to YES to be sure VDD on Power-Up came over SVLD level VL1 before internal Reset is released and circuit starts to execute instructions. 15.1.2 PortA reset Option, see paragraph 4.3 139H Option Name RA 15.1.3 Option Name VLX PortAreset Default Value A rstpa_no User Value B Refer to chapter 4.3 Input port (PA0..PA3) RESET to select the PortA reset option. Possible options are rstpa_no, rstpa_xh where x={3,5,6,7,9,a,b,c,d,e,f} 140H 14H SVLD levels Option, see paragraph 11 SVLD 142H typ. VL1 level [V] SVLD level in Volts 143H typ. VL2 level [V] typ. VL3 level [V] VL1 level is also the level used for Power check if activated (table 15.1.1). VL1 : possible levels are from 1.3V to 3V by step of 100mV. VL2 : possible levels are 2.3V ; 2.6V to 3.5V by step of 100mV ; 3.7V and 4V VL3 : possible levels are 2.6V to 3.5V by step of 100mV ; 3.7V and 4V Software name is : ______________.bin, dated ______________ The customer should specify the required options at the time of ordering. A copy of this sheet, as well as the Software ROM characteristic file generated by the assembler (*.STA) should be attached to the order. Copyright (c) 2005, EM Microelectronic-Marin SA 32 www.emmicroelectronic.com R EM6607 16 PERIPHERAL MEMORY MAP The following table shows the peripheral memory map of the EM6607. The address space is between $00 and $7F (Hex). Any addresses not shown can be considered to be reserved. power up value b'3210 xxxx Register name add hex 00- add dec write_bits read_bits Remarks RAM 5f LTimLS 60 0-95 96 0000 HTimLS 61 97 0000 TimCtr 62 98 0000 Option 63 99 0000 Option2 64 100 0000 PA3cnt 65 101 0000 PortE 66 102 xxxx CIOportE 67 103 0000 ClkSWB 68 104 0000 SWBuff 69 105 1111 LowSWB 6A 106 0000 HighSWB 6B 107 0000 power up value Read/Write_bits 0: D0 1: D1 2: D2 3: D3 0: TL0 0: TS0 1: TL1 1: TS1 2: TL2 2: TS2 3: TL3 3: TS3 0: TL4 0: TS4 1: TL5 1: TS5 2: TL6 2: TS6 3: TL7 3: TS7 0: TEC0 1: TEC1 2: TEC2 3: TimAuto 0: NoWD 1: debPAN 2: debPCN 3: IRQedgeR 0: BUZZERPE0 1: OEBsleepRes 2: OECsleepRes 3: OEDsleepRes 0: PA3cntin 1: Fout 2: WDdisana 3: 0 0: PE0 1: PE1 2: PE2 3: PE3 0: CIOPE0 1: CIOPE1 2: CIOPE2 3: CIOPE3 0: CkSWB0 1: CkSWB1 2: 0 3: V03 0: Buff0 1: Buff1 2: Buff2 3: Buff3 0: size[0] 1: size[1] 2: size[2] 3: size[3] 0: size[4] 1: size[5] 2: StSWB 3: AutoSWB write_bits read_bits direct addressing low nibble of 8bit timer load and status register high nibble of 8bit timer load and status register timer control register with frequency selector Watch dog timer off Debouncer on port A disabled Debouncer on port C disabled Rising edge interrupt Buzzer on PE0 enable PortB OE reset by Sleep PortC OE reset by Sleep PortD OE reset by Sleep PA3 counter input Frequency output on STRB Disable analogue WD Port E Input/Output Port E Input/Output individual control Clock selector for SWB SWB intermediate buffer low nibble to define the size of data to be send in Automatic mode the size of the data to be sent & SWB control Remarks Register name add hex add dec Copyright (c) 2005, EM Microelectronic-Marin SA 33 www.emmicroelectronic.com R EM6607 b'3210 SVLD 6C 108 0000 Read/Write_bits 0: VLC0 0: VLC0 1: VLC1 1: VLC1 2: 2: busy 3: 3: VLDR 0: INTEN 1: DebCK 2: 0 3: 0 voltage level detector control global interrupt enable debouncer clock IRQ Comp Bit IRQ Comp Mask internally used for INDEX register internally used for INDEX register interrupt requests sleep mode WatchDog timer control and SLEEP mask Port A status CIRQD Index LOW Index HIGH IntRq 6D 6E 6F 70 109 110 111 112 0000 xxxx xxxx 0000 WD 71 113 0000 0: 1: 2: SLEEP 3: 0: 1: 2: SLmask 3: WDrst PortA 72 114 xxxx IRQpA 73 115 0000 0: MPA0 1: MPA1 2: MPA2 3: MPA3 0: PB0 1: PB1 2: PB2 3: PB3 0: CIOPB0 1: CIOPB1 2: CIOPB2 3: CIOPB3 0: PC0 1: PC1 2: PC2 3: PC3 0: INTPA 1: INTPC 2: INTTE 3: INTPR 0: WD0 1: WD1 2: SLmask 3: 0 0: PA0 1: PA1 2: PA2 3: PA3 0: IRQpa0 1: IRQpa1 2: IRQpa2 3: IRQpa3 Port A interrupt request MPortA 74 116 0000 Port A mask PortB 75 117 xxxx Port B Input/Output CIOportB 76 118 0000 Port B Input/Output individual control PortC 77 119 xxxx Port C Input/Output 0: IRQpc0 1: IRQpc1 2: IRQpc2 3: IRQpc3 IRQpC 78 120 0000 0: MPC0 1: MPC1 2: MPC2 3: MPC3 0: PD0 1: PD1 2: PD2 3: PD3 Port C interrupt request MPortC 79 121 0000 Port C mask PortD 7A 122 xxxx Port D Input/Output Copyright (c) 2005, EM Microelectronic-Marin SA 34 www.emmicroelectronic.com R EM6607 Register name add hex add dec power up value b'3210 0000 write_bits read_bits Remarks Read/Write_bits 0: 0 0: 0 1: 0 1: 0 2: -2: -3: SOFTPOR 3: 0: PA&C 1: CIOPC 2: CIOPD 3: 0 0: PSF0 0: PSF0 1: PSF1 1: PSF1 2: PRST 2: 0 3: MTim 3: MTim 0: BCF0 1: BCF1 2: BUen 3: TimEn ------- RegSoftPOR 7B 123 Software POR PortAirq AND PortCirq PortC In/Out PortD In/Out Prescaler control timer mask Buzzer control Timer Enable reserved CPIOB 7C 124 x000 PRESC 7D 125 0000 BEEP 7E 7F 126 127 0000 ---- RegTestEM Copyright (c) 2005, EM Microelectronic-Marin SA 35 www.emmicroelectronic.com R EM6607 17 Temperature and Voltage Behaviours 17.1 IDD Current (Typical) Idd RUN @ 3V [uA] 2.50 2.00 1.50 1.00 0.50 0.00 -40 -20 0 20 40 60 80 [C] 100 Idd RUN @ 1.5V [uA] 2.50 2.00 1.50 1.00 0.50 0.00 -40 -20 0 20 40 60 80 [C] 100 Idd HALT @ 3.0V [nA] 1000.00 800.00 600.00 400.00 200.00 0.00 -40 -20 0 20 40 60 80 [C] 100 Idd HALT @ 1.5V [nA] 1000.00 800.00 600.00 400.00 200.00 0.00 -40 -20 0 20 40 60 80 [C] 100 Idd SLEEP @ 3.0V [nA] 250.00 200.00 150.00 100.00 50.00 0.00 -40 -20 0 20 40 60 80 [C] 100 Idd SLEEP @ 1.5V [nA] 250.00 200.00 150.00 100.00 50.00 0.00 -40 -20 0 20 40 60 80 [C] 100 Copyright (c) 2005, EM Microelectronic-Marin SA 36 www.emmicroelectronic.com R EM6607 17.2 Pull-down resistance (Typical) [kohm] 250.00 200.00 150.00 100.00 50.00 0.00 -40 -20 Weak Pull-Up @ 3V [kohm] 700.00 600.00 500.00 400.00 300.00 200.00 100.00 0.00 -40 -20 Weak Pull-Up @ 1.5V 0 20 40 60 80 [C] 100 0 20 40 60 80 [C] 100 [kohm] 400.00 350.00 300.00 250.00 200.00 150.00 100.00 50.00 0.00 -40 -20 Weak Pull-Down @ 3V [kohm] 200.00 150.00 100.00 50.00 0.00 -40 -20 Weak Pull-Down @ 1.5V 0 20 40 60 80 [C] 100 0 20 40 60 80 [C] 100 Strong Pull-Up @ 3V [kohm] 140.00 120.00 100.00 80.00 60.00 40.00 20.00 0.00 -40 -20 0 20 40 60 80 [C] 100 [kohm] 140.00 120.00 100.00 80.00 60.00 40.00 20.00 0.00 -40 -20 Strong Pull-Up @ 1.5V 0 20 40 60 80 [C] 100 Strong Pull-Down @ 3V [kohm] 120.00 100.00 80.00 60.00 40.00 20.00 0.00 -40 -20 0 20 40 60 80 [C] 100 [kohm] 120.00 100.00 80.00 60.00 40.00 20.00 0.00 -40 -20 Strong Pull-Down @ 1.5V 0 20 40 60 80 [C] 100 Copyright (c) 2005, EM Microelectronic-Marin SA 37 www.emmicroelectronic.com R EM6607 17.3 Output Currents (Typical) Port B: IOL current VDD=3.0V , VOL=0.4V [mA] 40 35 30 25 20 15 10 5 0 -40 -20 0 20 40 60 18 Tr 10 Tr 4 Tr 80 [C] 100 [mA] 20.00 15.00 10.00 5.00 0.00 -40 -20 0 20 40 60 18 Tr 10 Tr 4 Tr 80 [C] 100 Port B: IOL current VDD=1.5V , VOL=0.3V Port B: IOL current VDD=1.2V , VOL=0.15V [mA] 8 7 6 5 4 3 2 1 0 -40 -20 0 20 40 60 80 [C] 100 18 Tr Port IOL current VDD=3.0V , VOL=0.4V [mA] 10 8 6 4 2 0 -40 -20 0 20 40 60 80 [C] 100 [mA] 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 -40 Port IOL current VDD=1.5V , VOL=0.3V -20 0 20 40 60 80 [C] 100 Copyright (c) 2005, EM Microelectronic-Marin SA 38 www.emmicroelectronic.com R EM6607 Port B: IOH current VDD=3.0V , VOH=2.5V [mA] 0.00 -5.00 -10.00 -15.00 -20.00 -25.00 -30.00 -35.00 -40.00 -45.00 -40 -20 0 20 40 60 [mA] 0 -2 6 Tr 14 Tr 24 Tr -4 -6 -8 -10 -12 80 [C] 100 -40 -20 0 20 40 60 80 [C] 100 24 Tr 6 Tr 14 Tr Port B: IOH current VDD=1.5V , VOH=1.2V Port B: IOH current VDD=1.2V , VOH=1.05V [mA] 0 -0.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 -40 -20 0 20 40 60 24 Tr 80 [C] 100 Port IOH current VDD=3.0V , VOH=2.5V [mA] 0.00 -1.00 -2.00 -3.00 -4.00 -5.00 -6.00 -40 -20 0 20 40 60 80 [C] 100 [mA] 0.00 -0.40 -0.80 -1.20 -1.60 -40 Port IOH current VDD=1.5V , VOH=1.2V -20 0 20 40 60 80 [C] 100 Copyright (c) 2005, EM Microelectronic-Marin SA 39 www.emmicroelectronic.com R EM6607 18 Electrical specifications min. - 0.2 max. + 3.6 90 90 VDD+0.2 + 125 unit V mA mA V C 18.1 Absolute maximum ratings Parameter Supply voltage VDD-VSS VDD current (DC) VSS current (DC) Input voltage Storage temperature VSS - 0.2 - 40 Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified electrical characteristics may affect device reliability or cause malfunction. 18.2 Standard Operating Conditions Parameter Temperature VDD_range1 VDD_range2 (VREG = VDD) (note 1) VSS CVREG fq RQS CL df/f value -20C to +85C 1.4V to 3.3V 1.2V to 1.8V 0V (reference) min. 100nF 32768Hz 35k 8.2pF 30ppm Description With internal voltage regulator Without internal voltage regulator regulated voltage capacitor tow. VSS nominal frequency typical quartz serial resistor typical quartz load capacitance quartz frequency tolerance 18.3 Handling Procedures This device has built-in protection against high static voltages or electric fields; however, anti-static precautions should be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. 18.4 DC characteristics - Power Supply Pins Conditions: VDD=VREG=1.5V, T=25C (note 5) (unless otherwise specified) Parameter Conditions Symb. IVDDa IVDDa IVDDh IVDDh IVDDs IVDDs VPOR VRD VREG Min. Typ. (note1) 1.8 Max. Unit A A A A A A V V V ACTIVE Supply Current ACTIVE Supply Current (in active mode) STANDBY Supply Current STANDBY Supply Current (in Halt mode) SLEEP Supply Current SLEEP Supply Current (SLEEP =1) POR voltage RAM data retention Regulated Voltage +25C (note2) (note2) (note2) -20C to +85C +25C (note3) -20C to +85C +25C (note3) -20C to +85C 3.0 4.5 1.0 1.8 0.4 1.2 1.0 1.5 0.5 0.1 0.7 1.1 1.10 VREG not at VDD Copyright (c) 2005, EM Microelectronic-Marin SA 40 www.emmicroelectronic.com R EM6607 Conditions: VDD=3.0V, T=25C (note 5) (unless otherwise specified), VREG not shorted to VDD Parameter Conditions Symb. IVDDa IVDDa IVDDh IVDDh IVDDs IVDDs VPOR VRD VREG Min. ACTIVE Supply Current ACTIVE Supply Current (in active mode) STANDBY Supply Current STANDBY Supply Current (in Halt mode) SLEEP Supply Current SLEEP Supply Current (SLEEP =1) POR voltage RAM data retention Regulated Voltage +25C (note 3) (note 3) (note 4) -20C to +85C +25C (note 4) -20C to +85C +25C (note 4) -20C to +85C Typ. (note 2) 1.8 Max. Unit A A A A A A V V V 3.0 4.5 1.0 1.8 0.4 1.2 1.0 1.90 0.5 0.1 0.7 1.1 1.10 -20C to +85C Note 1 Because of the voltage regulator drop at low voltages VREG = VDD when VDD<1.8V Note 2: For current measurement typical quartz described in Operating Conditions is used. All I/O pins without internal Pull Up/Down are pulled to VDD externally. Note 3: Test loop with successive writing and reading of two different addresses with an inverted values (five instructions should be reserved for this measurement), Note 4: NOT tested if delivered in chip form. Note 5: Test conditions for ACTIVE and STANDBY Supply current mode are: QIN = external square wave, from rail to rail of VREG (regulated voltage) with 100nF capacitor on VREG. fQIN = 32kHz. Copyright (c) 2005, EM Microelectronic-Marin SA 41 www.emmicroelectronic.com R EM6607 18.5 DC characteristics - Input/Output Pins Conditions: VDD=1.5V / 3.0V, -20C Pin at hi-impedance VIL VSS VSS VSS 0.7VDD 0.7VDD 0.9VREG 3.0 9.5 5.0 1.5 1.0 23.0 13.0 5.4 5.4 6.0 15.0 8.0 3.5 2.5 33.0 20.5 8.8 7.8 -3.5 -9.4 -5.0 -2.5 -1.2 -33.0 -20.0 -9.0 -4.5 0.3VDD 0.3VDD 0.3VREG VDD VDD VREG V V V V V V mA mA mA mA mA mA mA mA mA Pin at hi-impedance VOL = 0.15V, VDD = 1.2V VOL = 0.3V, VDD = 1.5V VIH IOL IOL VOL = 0.4V, VDD = 3.0V IOL VOH = 1.05V, VDD = 1.2V VOH = 1.2V, VDD = 1.5V IOH IOH -2.5 -6.0 -3.0 -1.5 -0.6 -23.0 -15.0 -3.0 -3.0 50 mA mA mA mA mA mA mA mA mA nF k k k k k k k k k k k k VOH = 2.5V, VDD = 3.0V IOH Capacitor Resistor Input pull-down strong I/O ports A,B,C,D,E (option) Reset Test Input pull-down strong I/O ports A,B,C,D,E (option) Reset Test Input pull-down weak I/O ports A,B,C,D,E (option) Input pull-down weak I/O ports A,B,C,D,E (option) Input pull-up strong I/O ports A,B,C,D,E (option) Input pull-up strong I/O ports A,B,C,D,E (option) Input pull-up weak I/O ports A,B,C,D,E (option) Input pull-up weak I/O ports A,B,C,D,E (option) VDD = 3.0V,Port B 18/24 transistors option with 4 toggling ports. 150 Pin at VDD = 1.5V, 25C RIN 50 50 10 50 50 10 80 50 50 50 300 100 90 110 18 90 110 18 130 250 100 100 550 180 350 200 35 160 200 35 350 600 250 200 1000 400 Pin at VDD = 3.0V, 25C RIN Pin at VDD = 1.5V, 25C Pin at VDD = 3.0V, 25C Pin at VDD = 1.5V, 25C Pin at VDD = 3.0V, 25C Pin at VDD = 1.5V, 25C Pin at VDD = 3.0V, 25C RIN RIN RIN RIN RIN RIN Note 5: QOUT is used only with crystal. Copyright (c) 2005, EM Microelectronic-Marin SA 42 www.emmicroelectronic.com R EM6607 18.6 DC characteristics - Supply Voltage Detector Levels Conditions: T= +25C (unless otherwise specified) Parameter Conditions Symb. Min. Typ. Max. Unit Supply Voltage Detector SVLD lev3 SVLD lev2 SVLD lev1 Supply Voltage Detector SVLD lev3 SVLD lev2 SVLD lev1 VL3 VL2 VL1 0C to +65C VL3 VL2 VL1 0.88 x VL3 0.88 x VL2 0.88 x VL1 0.88 x VL3 0.88 x VL2 0.88 x VL1 VL3 VL2 VL1 VL3 VL2 VL1 1.12 x VL3 1.12 x VL2 1.12 x VL1 1.12 x VL3 1.12 x VL2 1.12 x VL1 V V V V V V SVLD typical level values must be selected with a precision of 100 mV. 18.7 Oscillator Conditions: T=25C (unless otherwise specified) Parameter Conditions Symbol Min. Typ. Max. Unit Temperature stability Voltage stability Input capacitor Output capacitor Transconductance Oscillator start voltage Oscillator start time System start time (oscillator + cold-start + reset) Oscillation detector frequency +15C to +35 C VDD=1,4V to 1,6 V Ref. on VSS Ref. on VSS 50mVpp,VDD min TSTART< 10 s VDD > VDD Min df/f x dT df/f x dU CIN CIN Gm USTART tDOSC tDSYS tDetFreq 5,6 12,1 2.5 VDD min 7 14 0,3 5 8,4 15,9 15.0 3 4 12 0.5 1.5 6 ppm /C ppm /V pF pF A/V V s s kHz VDD > VDD min 18.8 Input Timing characteristics Conditions: 1.5V RESET pulse length to exit SLEEP mode RESET pulse length (debounced) PortA , C pulse length (debounced) RESET pulse length (debounced) PortA , C pulse length (debounced) RESET from SLEEP DebCK = 0 DebCK = 0 DebCK = 1 DebCK = 1 tRESsl tdeb0 tdeb0 tdeb1 tdeb1 2 2 2 16 16 ms ms ms ms Copyright (c) 2005, EM Microelectronic-Marin SA 43 www.emmicroelectronic.com R EM6607 19 Pad Location Diagram PD[3] PD[2] PD[1] PD[0] PC[3] PE[2] PE[3] PC[2] PC[1] RESET PC[0] STRB VREG VDD VDD PA[0] EM6607 Chip size upon request Substrate of the die is at VSS VSS VSS QIN PA[1] PA[2] QOUT PA[3] TEST PE[0] PB[0] PB[1] PB[2] PB[3] Copyright (c) 2005, EM Microelectronic-Marin SA PE[1] 44 www.emmicroelectronic.com R EM6607 20 Package Dimensions SOP-24(1.27mm pitch, 300mils body width) Figure 17. Dimensions of SOP24 Package SOIC TSSOP24 (0.65mm pitch, 4.4mm body width) Figure 18. Dimensions of TSSOP24 Package Copyright (c) 2005, EM Microelectronic-Marin SA 45 www.emmicroelectronic.com R EM6607 SOP-28(1.27mm pitch, 300mils body width) Figure 19. Dimensions of SOP28 Package SOIC TSSOP28 (0.65mm pitch, 4.4mm body width) Figure 20. Dimensions of TSSOP28 Package Copyright (c) 2005, EM Microelectronic-Marin SA 46 www.emmicroelectronic.com R EM6607 21 Ordering Information Device in DIE Form: EM6607 WS 11 - %%% Die form: WW = Wafer WS = Sawn Wafer/Frame WP = Waffle Pack Thickness: 11 = 11 mils (280um), by default 27 = 27 mils (686um), not backlapped (for other thickness, contact EM) Packaged Device: EM6607 SO28 A - %%% Package: SO28 = 28 pin SOIC SO24 = 24 pin SOIC TP28 = 28 pin TSSOP TP24 = 24 pin TSSOP Delivery Form: A = Stick B = Tape&Reel Customer Version: customer-specific number given by EM Microelectronic Customer Version: customer-specific number given by EM Microelectronic Ordering Part Number (selected examples) Part Number EM6607SO28A-%%% EM6607SO28B-%%% EM6607SO24A-%%% EM6607SO24B-%%% EM6607TP28B-%%% EM6607TP24B-%%% EM6607WS11-%%% EM6607WP11-%%% Package/Die Form 28 pin SOIC 28 pin SOIC 24 pin SOIC 24 pin SOIC 28 pin TSSOP 24 pin TSSOP Sawn wafer Die in waffle pack Delivery Form/ Thickness Stick Tape&Reel Stick Tape&Reel Tape&Reel Tape&Reel 11 mils 11 mils Please make sure to give the complete Part Number when ordering, including the 3-digit customer version. The customer version is made of 3 numbers %%% (e.g. 008 , 012, 131, etc.) 21.1 Package Marking 24/28-pin SOIC marking: First line: Second line: Third line: EM6607 %%%Y PPPPPPPPPPP CCCCCCCCCCC 28-pin TSSOP marking: First line: Second line: Third line: EM660 7 %%%Y PPPPPPPPPPP CCCCCCCC 24-pin TSSOP marking: EM6 6 0 7%% PP PPPPPP CCCCYP Where: %%% or %% = customer version, specific number given by EM (e.g. 008, 012, 131, etc.) PP...P = Production identification (date & lot number) of EM Microelectronic Y = year of assembly CC...C = Customer specific package marking on third line, selected by customer 21.2 Customer Marking There are 11 digits available for customer marking on SO24/28, 4 for TSSOP24, and 8 for TSSOP14. EM Microelectronic-Marin SA (EM) makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in EM's General Terms of Sale located on the Company's web site. EM assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of EM are granted in connection with the sale of EM products, expressly or by implications. EM's products are not authorized for use as components in life support devices or systems. (c) EM Microelectronic-Marin SA, 01/06, Rev. D Copyright (c) 2005, EM Microelectronic-Marin SA 47 www.emmicroelectronic.com |
Price & Availability of EM6607WS11
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