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White Electronic Designs
WV3HG2128M72EEU-AD4
ADVANCED*
2GB - 2x128Mx72 DDR2 SDRAM UNBUFFERED, ECC w/PLL
FEATURES
200-pin, dual in-line memory module (SO-DIMM) Support ECC error detection and correction Fast data transfer rates: PC2-6400*, PC2-5300*, PC2-4200 and PC2-3200 VCC = VCCQ = 1.8V 0.1V 1.8V I/O (SSTL_18-compatible) Differential data strobe (DQS, DQS#) option Differential clock inputs (CK, CK#) Multiple internal device banks for concurrent operation Programmable CAS# latency (CL): 3, 4, 5 and 6 Adjustable data-output drive strength On-die termination (ODT) Posted CAS# latency: 0, 1, 2, 3 and 4 Serial Presence Detect (SPD) with EEPROM 64ms: 8,192 cycle refresh Gold edge contacts Dual Rank RoHS compliant Package option * 200 Pin SO-DIMM * PCB - 30.00mm (1.181") Max
* This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. NOTE: Consult factory for availability of: * Vendor source control options * Industrial temperature option
DESCRIPTION
The WV3HG2128M72EEU is a 2x128Mx72 Double Data Rate DDR2 SDRAM high density module. This memory module consists of eighteen 128Mx8 bit stacked BGA with 8 banks DDR2 Synchronous DRAMs in FBGA packages, mounted on a 200-pin SO-DIMM FR4 substrate.
OPERATING FREQUENCIES
PC2-6400* Clock Speed CL-tRCD-tRP 400MHz 6-6-6 PC2-5300* 333MHz 5-5-5 PC2-4200 266MHz 4-4-4 PC2-3200 200MHz 3-3-3
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PIN CONFIGURATION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Symbol VREF VSS DQ0 DQ4 VSS DQ5 DQ1 VSS DQS0# DM0 DQS0 VSS VSS DQ6 DQ2 DQ7 DQ3 VSS VSS DQ12 DQ8 DQ13 DQ9 VSS VSS DM1 DQS1# VSS DQS1 DQ14 VSS DQ15 DQ10 VSS DQ11 DQ20 VSS DQ21 DQ16 VSS DQ17 NC VSS DM2 DQS2# VSS DQS2 DQ22 VSS DQ23 Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol DQ18 VSS DQ19 DQ28 VSS DQ29 DQ24 VSS DQ25 DM3 VSS VSS DQS3# DQ30 DQS3 DQ31 VSS VSS DQ26 CB4 DQ27 CB5 VSS VSS CB0 DM8 CB1 VSS VSS CB6 DQS8# CB7 DQS8 VCC VSS CB2 CKE0 CB3 CKE1 VSS NC/CS2# BA2 VCC NC A12 A11 A9 VCC A7 A8 Pin No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Symbol VCC A6 A5 A4 A3 VCC A2 A1 VCC A0 A10/AP BA1 BA0 VCC RAS# WE# VCC CS0# CAS# ODT0 CS1# A13 VCC VCC ODT1 CK NC/CS3# CK# DQ32 Vss VSS DQ36 DQ33 DQ37 DQS4# VSS DQS4 DM4 VSS VSS DQ34 DQ38 DQ35 DQ39 VSS VSS DQ40 DQ44 DQ41 DQ45 Pin No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Symbol VSS VSS DQS5# DM5 DQS5 VSS VSS DQ46 DQ42 DQ47 DQ43 VSS VSS DQ52 DQ48 DQ53 DQ49 VSS VSS DM6 DQS6# VSS DQS6 DQ54 VSS DQ55 DQ50 VSS DQ51 DQ60 VSS DQ61 DQ56 VSS DQ57 DM7 VSS DQ62 DQS7# VSS DQS7 DQ63 DQ58 SDA VSS SCL DQ59 SA1 VCCSPD SA0
WV3HG2128M72EEU-AD4
ADVANCED
PIN NAMES
Pin Name A0-A13 A10/AP BA0 - BA2 DQ0-DQ63 CB0-CB7 DQS0-DQS8 DQS0#-DQS8# ODT0, ODT1 CK,CK# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# VCC VSS SA0-SA1 SDA VREF DM0-DM8 VCCSPD SCL NC Function Address Inputs Address Input/Auto Precharge SDRAM Bank Address Data Input/Output Check Bits Data strobes Data strobes negative On-die termination control Clock inputs, positive/negative Clock enable input Chip select input Row Address Strobe Column Address Strobe Write Enable Core Power (1.8V) Ground SPD address Serial Data Input/Output Input/Output Reference Data-in mask Serial EEPROM power supply Serial Presence Detect(SPD) Clock Input No Connect
NOTES: SA2 does NOT connect to memory connector and is shown ONLY on Block Diagram SA2 is tied LOW on memory module for all memory configurations
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WV3HG2128M72EEU-AD4
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
CS1# CS0# DQS0 DQS0# DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1# DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS2# DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3# DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DQS8# DM8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM# I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS#
DQS4 DQS4# DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQS5# DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQS6# DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7# DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS# DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS# DQS DQS#
Serial PD SCL WP A0 A1 A2 SA2 SDA
SA0 SA1
VCCSPD VCC
Serial PD DDR2 SDRAMs DDR2 SDRAMs DDR2 SDRAMs DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2 DDR2 SDRAM x 2
CS0# CS1# BA0 - BA2 A0 - A13 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1
CS0# : DDR2 SDRAMs CS1# : DDR2 SDRAMs BA0 - BA2 : DDR2 SDRAMs A0 - A13 : DDR2 SDRAMs RAS# : DDR2 SDRAMs CAS# : DDR2 SDRAMs WE# : DDR2 SDRAMs CKE0 : DDR2 SDRAMs CKE1 : DDR2 SDRAMs ODT0 : DDR2 SDRAMs ODT1 : DDR2 SDRAMs
VREF VSS
120 CK0 CK0#
PLL
CK CK#
NOTE: All resistor values are 22 ohms unless otherwise specified.
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WV3HG2128M72EEU-AD4
ADVANCED
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VIN, VOUT TSTG TCASE Parameter Voltage on VCC pin relative to VSS Voltage on any pin relative to VSS Storage Temperature Device operating Temperature Command/Address, RAS#, CAS#, WE# IL Input leakage current; Any input 0VDC OPERATING CONDITIONS
All voltages referenced to VSS Rating Parameter Supply Voltage I/O Reference Voltage I/O Termination Voltage Symbol VCC VREF VTT Min. 1.7 0.49 x VCC VREF-0.04 Type 1.8 0.50 x VCC VREF Max. 1.9 0.51 x VCC VREF+0.04 Units V V V 1 2 Notes
Notes: 1 VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor. 2. VTT in sot applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF.
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WV3HG2128M72EEU-AD4
ADVANCED
OPERATING TEMPERATURE CONDITION
Parameter Operating temperature Symbol TOPER Rating 0 to 85 Units C Notes 1, 2
Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDED JESD51.2 2. At 0C - 85C, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS Parameter Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Symbol VIH(DC) VIL(DC) Min VREF + 0.125 -0.300 Max VCC + 0.300 VREF - 0.125 Units V V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS Parameter Input High (Logic 1) Voltage DDR2-400 & DDR2-533 Input Low (Logic 1) Voltage DDR2-667 Input Low (Logic 0) Voltage DDR2-400 & DDR2-533 Input Low (Logic 0) Voltage DDR2-667 Symbol VIH(AC) VIH(AC) VIL(AC) VIL(AC) Min VREF + 0.250 VREF + 0.200 Max VREF - 0.250 VREF - 0.200 Units V V V V
INPUT/OUTPUT CAPACITANCE
TA = 25C, f = 100MHz Parameter Input Capacitance (A0~A13, BA0~BA2, RAS#, CAS#, WE#) Input Capacitance (CKE0, CKE1), (ODT0, ODT1) Input Capacitance (CS0# ~ CS1#) Input Capacitance (CK, CK#) Input Capacitance (DM0 ~ DM8), (DQS0 ~ DQS8) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 (665) CIN5 (534, 403) COUT1 (665) COUT1 (534, 403) Min 22 13 13 6 9 9 9 9 Max 40 22 22 7 11 12 11 12 Units pF pF pF pF pF pF pF pF
Input Capacitance (DQ0 ~ DQ63), (CB0 ~ CB7)
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WV3HG2128M72EEU-AD4
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only 0C TCASE < +70C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V Symbol ICC0* Proposed Conditions Operating one bank active-precharge current; tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current; IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W Precharge power-down current; All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge quiet standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Precharge standby current; All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Active power-down current; All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING Fast PDN Exit MRS(12) = 0 Slow PDN Exit MRS(12) = 1 806
TBD
665 1,218
534 1,173
403 1,128
Units mA
ICC1*
TBD
1,308
1,263
1,218
mA
ICC2P**
TBD
516
516
516
mA
ICC2Q**
TBD
1,020
930
930
mA
ICC2N**
TBD
1,110 840 516
1,020 750 516
1,020 750 516
mA mA mA
ICC3P**
TBD TBD
ICC3N**
Active standby current; All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as ICC4W Burst auto refresh current; tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self refresh current; CK and CK\ at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as ICC4R; Refer to the following page for detailed timing conditions
TBD
1,200
1,110
1,110
mA
ICC4W*
TBD
1,803
1,578
1,443
mA
ICC4R*
TBD
1,803
1,578
1,443
mA
ICC5**
TBD
4,260
4,170
4,080
mA
ICC6**
TBD
108
108
108
mA
ICC7*
TBD
3,108
2,928
2,748
mA
Note: ICC specification is based on SAMSUNG components. Other DRAM Manufacturers specification may be different. * Value calculated as one module rank in this operation condition, and all other module ranks in ICC2P (CKE LOW) mode. ** Value calculated reflects all module ranks in the operating condition.
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AC CHARACTERISTICS PARAMETER CL = 6 CL = 5 CL = 4 CL = 3 SYMBOL tCK (6) tCK (5) tCK (4) tCK (3) tCH tCL tHP tJIT tAC tHZ tLZ tDS tDH tDIPW tQHS tQH tDVW tDQSH tDQSL tDQSCK tDSS tDSH tDQSQ tRPRE tRPST tWPRES tWPRE tWPST tDQSS
tIPW tIS tIH tCCD
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
WV3HG2128M72EEU-AD4
ADVANCED
AC TIMING PARAMETERS & SPECIFICATIONS
806 MIN
TBD TBD TBD TBD TBD TBD TBD
665 MAX
TBD TBD TBD TBD TBD TBD TBD
534 MAX 8,000 8,000 8,000 0.55 0.55 MIN MAX MIN
403 MAX UNIT ps ps ps ps tCK tCK ps 125 +600 tAC MAX tAC MIN 150 275 0.35 400 450 tHP - tQHS tQH - tDQSQ 0.35 0.35 -500 0.2 0.2 300 350 0.9 0.4 0 0.25 0.4 WL - 0.25
0.6 350 475 2
MIN 3,000 3,750 5,000 0.45 0.45 MIN (tCH, tCL) -125 -450
Clock cycle time Clock
3,750 5,000 0.45 0.45 MIN (tCH, tCL) -125 -500
8,000 8,000 0.55 0.55
5,000 5,000 0.45 0.45 MIN (tCH, tCL) -125 -600
8,000 8,000 0.55 0.55
CK high-level width CK low-level width Half clock period Clock jitter DQ output access time from CK/CK# Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# DQ and DM input setup time relative to DQS DQ and DM input hold time relative to DQS DQ and DM input pulse width (for each input) Data hold skew factor DQ...DQS hold, DQS to first DQ to go nonvalid, per access Data valid output window (DVW) DQS input high pulse width DQS input low pulse width DQS output access time from CK/CK# DQS falling edge to CK rising ... setup time DQS falling edge from CK rising ... hold time DQS...DQ skew, DQS to last DQ valid, per group, per access DQS read preamble DQS read postamble DQS write preamble setup time DQS write preamble DQS write postamble Write command to first DQS latching transition
Address and control input pulse width for each input Address and control input setup time Address and control input hold time Address and control input hold time
TBD TBD TBD
TBD TBD TBD
125 +450 tAC MAX
125 +500 tAC MAX
ps ps ps ps ps ps tCK ps ps ns tCK tCK ps tCK tCK ps tCK tCK ps tCK tCK tCK
tCK ps ps tCK
TBD
TBD
tAC MIN 100 175 0.35
tAC MAX
tAC MIN 100 225 0.35
tAC MAX
tAC MAX
TBD
TBD
Data
TBD TBD
TBD TBD
TBD TBD
TBD TBD
340 tHP - tQHS tQH - tDQSQ 0.35 0.35 -400 0.2 0.2 240 0.9 0.4 0 0.25 0.4 WL - 0.25
0.6 200 275 2
tHP - tQHS tQH - tDQSQ 0.35 0.35 -450 0.2 0.2
TBD TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD TBD
+400
+450
+500
Data Strobe
TBD
TBD
1.1 0.6
0.6 WL + 0.25
0.9 0.4 0 0.25 0.4 WL - 0.25
0.6 250 375 2
1.1 0.6
1.1 0.6
0.6 WL + 0.25
0.6 WL + 0.25
TBD
TBD
TBD TBD TBD
TBD TBD TBD
AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different. Continued on next page
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AC CHARACTERISTICS PARAMETER
ACTIVE to ACTIVE (same bank) command ACTIVE bank a to ACTIVE bank b command ACTIVE to READ or WRITE delay Four Bank Activate period ACTIVE to PRECHARGE command Internal READ to precharge command delay Write recovery time Auto precharge write recovery + precharge time Internal WRITE to READ command delay PRECHARGE command period PRECHARGE ALL command period LOAD MODE command cycle time CKE low to CK,CK# uncertainty REFRESH to Active of Refresh to Refresh command interval
WV3HG2128M72EEU-AD4
ADVANCED
AC TIMING PARAMETERS (cont'd)
806 SYMBOL
tRC tRRD tRCD tFAW tRAS tRTP tWR tDAL tWTR tRP tRPA tMRD tDELAY tRFC tREFI tXSNR tXSRD tISXR tAOND tAON tAOFD tAOF
TBD TBD TBD TBD TBD TBD
665 MAX
TBD TBD TBD TBD TBD TBD TBD TBD
534 MAX MIN
60 7.5 15 37.5 40 7.5 15 tWR + tRP 7.5 15 tRP+tCK 2 tIS+tCK
+tIH
403 MAX MIN
65 7.5 15 37.5 40 7.5 15 tWR + tRP 10 15 tRP+tCK 2 tIS+tCK
+tIH
MIN
TBD TBD TBD TBD TBD TBD TBD TBD
MIN
55 7.5 15 37.5 40 7.5 15 tWR + tRP 7.5 15 tRP+tCK 2 tIS+tCK
+tIH
MAX
UNIT
ns ns ns ns ns ns ns ns ns ns ns tCK ns
Command and Address
37.5 70,000
37.5 70,000
37.5 70,000
TBD TBD TBD TBD TBD
TBD TBD TBD TBD TBD
TBD
TBD
127.5
70,000 7.8
127.5
70,000 7.8
127.5
70,000 7.8
ns s ns tCK ps
Self Refresh
Average periodic refresh interval Exit self refresh to non-READ command Exit self refresh to READ command Exit self refresh timing reference ODT turn-on delay ODT turn-on ODT turn-off delay ODT turn-off
TBD TBD
TBD TBD
TBD TBD TBD TBD
TBD TBD TBD TBD
tRFC (MIN) + 10 200 tIS 2 tAC (MIN) 2.5 tAC (MIN) tAC (MIN) + 2000 tAC (MIN) + 2000 3 8 2 6 - AL 2 3 2 tAC (MAX) + 1000 2.5 tAC (MAX) + 600 2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1000
tRFC (MIN) + 10 200 tIS 2 tAC (MIN) 2.5 tAC (MIN) tAC (MIN) + 2000 tAC (MIN) + 2000 3 8 2 6 - AL 2 3 2 tAC (MAX) + 1000 2.5 tAC (MAX) + 600 2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1000
tRFC (MIN) + 10 200 tIS 2 tAC (MIN) 2.5 tAC (MIN) tAC (MIN) + 2000 tAC (MIN) + 2000 3 8 2 6 - AL 2 3 2 tAC (MAX) + 1000 2.5 tAC (MAX) + 600 2 x tCK + tAC (MAX) + 1000 2.5 x tCK + tAC (MAX) + 1000
tCK ps tCK ps
ODT
ODT turn-on (power-down mode)
tAONPD
TBD TBD
ps
ODT turn-off (power-down mode) ODT to power-down entry latency ODT power-down exit latency Exit active power-down to READ command, MR[bit12=0] Exit active power-down to READ command, MR[bit12=1] A Exit precharge power-down to any nonREAD command. CKE minimum high/low time
tAOFPD tANPD tAXPD tXARD tXARDS tXP tCKE
TBD TBD TBD TBD TBD TBD
ps tCK tCK tCK tCK tCK tCK
Power-Down
TBD
TBD
TBD
TBD
TBD
TBD
AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
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WV3HG2128M72EEU-AD4
ADVANCED
ORDERING INFORMATION FOR D4
Part Number WV3HG2128M72EEU806AD4-xG WV3HG2128M72EEU665AD4-xG WV3HG2128M72EEU534AD4-xG WV3HG2128M72EEU403AD4-xG Clock/Data Rate Speed 400MHz/800Mb/s 333MHz/667Mb/s 266MHz/533Mb/s 200MHz/400Mb/s CAS Latency 6 5 4 3 tRCD 6 5 4 3 tRP 6 5 4 3 Height* 30.00mm (1.181") 30.00mm (1.181") 30.00mm (1.181") 30.00mm (1.181")
NOTES: * RoHS product. ("G" = RoHS Compliant) * Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "-x" in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS FOR AD4
FRONT VIEW
67.75 (2.667) 67.45 (2.656) 6.35 (0.250) MAX
4.10 (0.161) (2X) 3.90 (0.154)
1.80 (0.071) (2X)
30.15 (1.187) 29.85 (1.175) 20.00 (0.787) TYP
6.00 (0.236) 2.55 (0.100) 1.10 (0.043) 0.90 (0.035) 1.00 (0.039) TYP 0.45 (0.018) TYP 2.504 (63.60) TYP 0.60 (0.024) TYP
2.15 (0.085)
PIN 199
PIN 1
BACK VIEW
PIN 200
47.40 (1.866) TYP
4.2 (0.165) TYP 11.40 (0.449) TYP
PIN 2
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) Tolerances: 0.13 (0.005) unless otherwise specified
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WV3HG2128M72EEU-AD4
ADVANCED
PART NUMBERING GUIDE
WV 3 H G 2 128M 72 E E U xxx AD4 x G
WEDC MEMORY (SDRAM) DDR 2 GOLD DUAL RANK DEPTH BUS WIDTH COMPONENT WIDTH x8 1.8V UNBUFFERED SPEED (Mb/s) PACKAGE 200 PIN SO-DIMM COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = RoHS COMPLIANT
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White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Document Title
WV3HG2128M72EEU-AD4
ADVANCED
2GB - 2x128Mx72 DDR2 SDRAM UNBUFFERED, ECC w/PLL
Revision History Rev #
Rev 0
History
Created
Release Date
February 2006
Status
Advanced
February 2006 Rev. 0
11
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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