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3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 256 x 256
FEATURES:
* * * * * * * *
IDT72V8980
* *
256 x 256 channel non-blocking switch Serial Telecom Bus Compatible (ST-BUS(R)) 8 RX inputs--32 channels at 64 Kbit/s per serial line 8 TX output--32 channels at 64 Kbit/s per serial line Three-state serial outputs Microprocessor Interface (8-bit data bus) 3.3V Power Supply Available in 44-pin Plastic Leaded Chip Carrier (PLCC), 48-pin Small Shrink Outline Package (SSOP), and 44-pin Plastic Quad Flatpack (PQFP) Operating Temperature Range -40C to +85C 3.3V I/O with 5V Tolerant Inputs
and output channels. Those 256 channels are divided into 8 serial inputs and outputs, each of which consists of 32 channels (64 Kbit/s per channel) to form a multiplexed 2.048 Mb/s stream.
FUNCTIONAL DESCRIPTION
A functional block diagram of the IDT72V8980 device is shown on below. The serial ST-BUS(R) streams operate continuously at 2.048 Mb/s and are arranged in 125s wide frames each containing 32, 8-bit channels. Eight input (RX0-7) and eight output (TX0-7) serial streams are provided in the IDT72V8980 device allowing a complete 256 x 256 channel non-blocking switch matrix to be constructed. The serial interface clock (C4i) for the device is 4.096 MHz. The received serial data is internally converted to a parallel format by the on chip serial-to-parallel converters and stored sequentially in a 256-position Data Memory. By using an internal counter that is reset by the input 8 KHz frame pulse, F0i, the incoming serial data streams can be framed and sequentially addressed.
DESCRIPTION:
The IDT72V8980 is a ST-BUS(R) compatible digital switch controlled by a microprocessor. The IDT72V8980 can handle as many as 256, 64 Kbit/s input
FUNCTIONAL BLOCK DIAGRAM
C4i
F0i
VCC
GND
RESET(1)
ODE
RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7
Timing Unit
TX0
Output MUX
Transmit Serial Data Streams
TX1 TX2
Receive Serial Data Streams
Data Memory Control Register Connection Memory
TX3 TX4 TX5 TX6 TX7
Microprocessor Interface
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DS CS R/W A0 DTA D0/ A5/ D5
CCO
NOTE: 1. The RESET Input is only provided on the SSOP package.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS is a trademark of Mitel Corp.
AUGUST 2003
DSC-5705/5
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT72V8980 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
PIN CONFIGURATION
DNC(1)
DNC(1)
DNC(1)
DTA CCO
DTA
CCO
RX2
RX1
RX0
ODE
TX0
TX1
INDEX
TX2
INDEX
44
43
42
41
40
39
38
37
36
35
44
43
42
RX3 RX4 RX5 RX6 RX7 VCC F0i C4i A0 A1 A2
1
41
40
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
TX3 TX4 TX5 TX6 TX7 GND D0 D1 D2 D3 D4
RX3 RX4 RX5 RX6 RX7 VCC F0i C4i A0 A1 A2
34
6
5
4
3
2
DNC(1)
ODE TX0
RX2
RX1
RX0
TX1
TX2
1 2 3 4 5 6 7 8 9 10 11
12 13 14 15 16 17 18 19 20 21 22
33 32 31 30 29 28 27 26 25 24 23
TX3 TX4 TX5 TX6 TX7 GND D0 D1 D2 D3 D4
18
19
20
21
22
23
24
25
26
27
DNC(1)
28
DNC(1)
D7
D6
R/W
DS
CS
D5
A3
A4
A5
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DNC(1)
A5 DS R/W
CS D7
D6
D5
PLCC: 0.05in. pitch, 0.65in. x 0.65in. (J44-1, order code: J) TOP VIEW
PQFP: 0.80mm pitch, 10mm x 10mm (DB44-1, order code: DB) TOP VIEW
GND DTA RX0 RX1 RX2 DNC(1) RX3 RX4 RX5 RX6 RX7 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
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CCO ODE TX0 TX1 TX2 DNC(1) TX3 TX4 TX5 TX6 TX7 GND VCC D0 D1 D2 D3 D4 DNC(1) D5 D6 D7 CS GND
RESET(2)
F0i C4i A0 A1 A2 DNC(1) A3 A4 A5 DS R/W
2 4
TOP VIEW
Package Type SSOP: 0.025in. pitch, 0.625in. x 0.295in.
NOTES: 1. DNC - Do Not Connect 2. The RESET Input is only provided on the SSOP package.
Reference Identifier SO48-1
Order Code PV
2
DNC(1)
A3
A4
IDT72V8980 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
PIN DESCRIPTIONS
SYMBOL
GND VCC
NAME
Ground. VCC Data Acknowledgment (Open Drain) RX Input 0 to 7 Frame Pulse Clock Address 0 to 5 Data Strobe Read/Write Chip Select Data Bus 0 to 7 TX Outputs 0 to 7 Output Drive Enable Control Channel Output Device Reset (Schmitt Trigger Input)
I/O
DESCRIPTION
Ground Rail. +3.3 Volt Power Supply. This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this output. Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s. This input identifies frame synchronization signals formatted to ST-BUS(R) specifications. 4.096 MHz serial clock for shifting data in and out of the data streams. These lines provide the address to IDT72V8980 internal registers. This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with CS to enable the internal read and write generation. This input controls the direction of the data bus lines (D0-D7) during a microprocessor access. Active LOW input enabling a microprocessor read or write of control register or internal memories. These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH, Connection Memory LOW and data memory. Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s. This is an output enable for the TX0-7 serial outputs. If this input is LOW, TX0-7 are high-impedance. If this is HIGH, each channel may still be put into high-impedance by software control. This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the contents of the CCO bit in the Connection Memory HIGH locations. This input (active LOW) puts the IDT72V8980 in its reset state that clears the device internal counters, registers and brings TX0-7 and microport data outputs to a high-impedance state. The time constant for a power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RESET pin must be held LOW for a minimum of 100ns to reset the device.
DTA
RX0-7
O I I I I I I I I/O O I O I
F0i C4i
A0-A5 DS R/W
CS
D0-D7 TX0-7 ODE CCO
RESET
3
IDT72V8980 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
FUNCTIONAL DESCRIPTION (Cont'd)
Data to be output on the serial streams may come from two sources: Data Memory or Connection Memory. The Connection Memory is 16 bits wide and is split into two 8-bit blocks--Connection Memory HIGH and Connection Memory LOW. Each location in Connection Memory is associated with a particular channel in the output stream so as to provide a one-to-one correspondence between the two memories. This correspondence allows for per channel control for each TX output stream. In Processor Mode, data output on the TX stream is taken from the Connect Memory Low and originates from the microprocessor (Figure 2). Where as in Connection Mode (Figure 1), data is read from Data Memory using the address in Connection Memory. Data destined for a particular channel on the serial output stream is read during the previous channel time slot to allow time for memory access and internal parallelto-serial conversion. CONNECTION MODE In Connection Mode, the addresses of input source for all output channels are stored in the Connect Memory Low. The Connect Memory Low locations are mapped to corresponding 8-bit x 32-channel output. The contents of the Data Memory at the selected address are then transferred to the parallel-toserial converters. By having the output channel to specify the input channel through the connect memory, input channels can be broadcast to several output channels. PROCESSOR MODE In Processor Mode the CPU writes data to specific Connect Memory Low locations which are to be output on the TX streams. The contents of the Connect Memory Low are transferred to the parallel-to-serial converter one channel before it is to be output and are transmitted each frame to the output until it is changed by the CPU. CONTROL The Connect Memory High bits (Table 4) control the per-channel functions available in the IDT72V8980. Output channels are selected into specific modes such as: Processor Mode or Connection mode and Output Drivers Enabled or in three-state condition. There is also one bit to control the state of the CCO output pin. OUTPUT DRIVE ENABLE (ODE) The ODE pin is the master output control pin. If the ODE input is held LOW all TDM outputs will be placed in high impedance regardless Connect Memory High programming. However, if ODE is HIGH, the contents of Connect Memory High control the output state on a per-channel basis. DELAY THROUGH THE IDT72V8980 The transfer of information from the input serial streams to the output serial streams results in a delay through the device. The delay through the IDT72V8980
device varies according to the combination of input and output streams and the movement within the stream from channel to channel. Data received on an input stream must first be stored in Data Memory before it is sent out. As information enters the IDT72V8980 it must first pass through an internal serial-to-parallel converter. Likewise, before data leaves the device, it must pass through the internal parallel-to-serial converter. This data preparation has an effect on the channel positioning in the frame immediately following the incoming frame--mainly, data cannot leave in the same time slot, on in the time slot immediately following. Therefore, information that is to be output in the same channel position as the information is input, relative to the frame pulse, will be output in the following frame. As well, information switched to the channel immediately following the input channel will not be output in the time slot immediately following but in the next timeslot allocated to the output channel, one frame later. Whether information can be output during a following timeslot after the information entered the IDT72V8980 depends on which RX stream the channel information enters on and which TX stream the information leaves on. This situation is caused by the order in which input stream information is placed into Data Memory and the order in which stream information is queued for output. Table 1 shows the allowable input/output stream combinations for the minimum 2 channel delay.
SOFTWARE CONTROL
If the A5 address line input is LOW then the IDT72V8980 Internal Control Register is addressed. If A5 input line is high, then the remaining address input lines are used to select the 32 possible channels per input or output stream. The address input lines and the Stream Address bits (STA) of the Control register give the user the capability of selecting all positions of IDT72V8980 Data and Connection memories. The IDT72V8980 memory mapping is illustrated in Table 2 and Figure 3. The data in the control register consists of Memory Select and Stream Address bits, Split Memory and Processor Mode bits. In Split Memory mode (Bit 7 of the Control register) reads are from the Data Memory and writes are to the Connect Memory as specified by the Memory Select Bits (Bits 4 and 3 of the Control Register). The Memory Select bits allow the Connect Memory High or LOW or the Data Memory to be chosen, and the Stream Address bits define internal memory subsections corresponding to input or output streams. The Processor Enable bit (bit 6) places EVERY output channel on every output stream in Processor Mode; i.e., the contents of the Connect Memory LOW (CML, see Table 5) are output on the TX output streams once every frame unless the ODE input pin is LOW. If PE bit is HIGH, then the IDT72V8980 behaves as if bits 2 (Channel Source) and 0 (Output Enable) of every Connect Memory High (CMH) locations were set to HIGH, regardless of the actual value. If PE is LOW, then bit 2 and 0 of each Connect Memory High location operates normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output channel is in Processor Mode. If bit 2 of the CMH is LOW, then the contents of the CML define the source information (stream and channel) of the time slot that is to be switched to an output.
RX
Receive Serial Data Streams
Data Memory Connection Memory
Transmit Serial Data Streams
TX
Receive Serial Data Streams
Data Memory Connection Memory
Transmit Serial Data Streams
TX
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Microprocessor
Figure 1. Connection Mode
4
Figure 2. Processor Mode
IDT72V8980 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
If the ODE input pin is LOW, then all the serial outputs are high-impedance. If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH) or disables (if LOW) the output stream and channel. The contents of bit 1 (CCO) of each Connection Memory High Location (see Table 4) is output on CCO pin once every frame. The CCO pin is a 2.048 Mb/s output, which carries 256 bits. If CCO bit is set HIGH, the corresponding bit on CCO output is transmitted HIGH. If CCO is LOW, the corresponding bit on the CCO output is transmitted in LOW. The contents of the 256 CCO bits of the CMH are transmitted sequentially on to the CCO output pin and are synchronous to the TX streams. To allow for delay in any external control circuitry the contents of the CCO bit is output one channel before the corresponding channel on the TX streams. For example, the contents of CCO bit in position 0 (corresponding to TX0, CH0) is transmitted synchronously with the TX channel 31, bit 7. Bit 1's of CMH for channel 1 of streams 0-7 are output synchronously with TX channel 0 bits 7-0. INITIALIZATION OF THE IDT72V8980 On initialization or power up, the contents of the Connection Memory High can be in any state. This is a potentially hazardous condition when multiple TX
outputs are tied together to form matrices. The ODE pin should be held low on power up to keep all outputs in the high impedance condition until the contents of the CMH are programmed. During the microprocessor initialization routine, the microprocessor should program the desired active paths through the matrices, and put all other channels into the high impedance state. Care should be taken that no two connected TX outputs drive the bus simultaneously. With the CMH setup, the microprocessor controlling the matrices can bring the ODE signal high to relinquish high impedance state control to the Connection Memory High bits outputs. RESET The reset pin is designed to be used with board reset circuitry. During reset the TX serial streams will be put into high-impedance and the state of internal registers and counters will be reset. As the connection memory can be in any state after a power up, the ODE pin should be used to hold the TX streams in high-impedance until the per-channel output enable control in the connection memory high is appropriately programmed. The main difference between ODE and reset is, reset alters the state of the registers and counters where as ODE controls only the high-impedance state of the TX streams. RESET input is only provided on the SSOP package.
TABLE 1 -- INPUT STREAM TO OUTPUT TABLE 2 -- ADDRESS MAPPING STREAM COMBINATIONS THAT CAN A5 A4 A3 A2 A1 A0 HEX ADDRESS LOCATION PROVIDE THE MINIMUM 2-CHANNEL 0XXXXX 00-1F Control Register(1) DELAY 100000 20 Channel 0(2)
Input 0 1 2 3 4 5 6 7 Output Stream 1,2,3,4,5,6,7 3,4,5,6,7 5,6,7 7 1,2,3,4,5,6,7 3,4,5,6,7 5,6,7 7
Control Register CRb7 CRb6 CRb5
1
* * *
0
* * *
0
* * *
0
* * *
0
* * *
1
* * *
21
* * *
Channel 1(2)
* * *
1
1
1
1
1
1
3F
Channel 31(2)
NOTES: 1. Writing to the Control Register is the only fast transaction. 2. Memory and stream are specified by the contents of the Control Register.
CRb4
CRb3
CRb2
CRb1
CRb0
The Control Register is only accessed when A5=0. All other address bits have no effect when A5=0. When A5 =1, only 32 bytes are randomly accessable via A0-A4 at any one instant. Which 32 bytes are accessed is determined by the state of CRb0 -CRb4. The 32 bytes correlate to 32 channel of one ST-BUS stream.
CRb4 0 1 1
CRb3 1 0 1
Connection Memory High
Connection Memory Low
Data Memory Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 31 Channel 31 Channel 31 Channel 31 Channel 31 Channel 31 Channel 31 Channel 31
CRb2 0 0 0 0 1 1 1 1
CRb1 0 0 1 1 0 0 1 1
CRb0 Stream 0 0 1 1 2 0 1 3 0 4 1 5 0 6 7 1
100000
100001
100010
111111
External Address Bits
A5-A0
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Figure 3. Address Mapping
5
IDT72V8980 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
TABLE 3 -- CONTROL REGISTER CONFIGURATION
Mode Control Bits (unused) Memory Select Bits Stream Address Bits
7
6
5
4
3
2
1
0
Bit
7
Name
SM (Split Memory)
Description
When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory LOW, except when the Control Register is accessed again. When 0, the Memory Select bits specify the memory for the operations. In either case, the Stream Address Bits select the subsection of the memory which is made available. When 1, the contents of the Connection Memory LOW are output on the Serial Output streams except when the ODE pin is LOW. When 0, the Connection Memory bits for each channel determine what is output. unused 0-0 - Not to be used. 0-1 - Data Memory (read only from the microprocessor port) 1-0 - Connection Memory LOW 1-1 - Connection Memory is HIGH The number expressed in binary notation on these bits refers to the input or output stream which corresponds to the subsection of memory made accessible for subsequent operations.
6 5 4-3
PE (Processor Mode)
MS1-MS0 (Memory Select Bits)
2-0
STA2-0 (Stream Address Bits)
TABLE 4 -- CONNECTION MEMORY HIGH REGISTER
No Corresponding Memory - These bits give 0s if read Per Channel Control Bits
7
6
5
4
3
2
1
0
Bit
2
Name
CS (Channel Source)
Description
When 1, the contents of the corresponding location in Connection Memory LOW are output on the location's channel and stream. When 0, the contents of the corresponding location in Connection Memory LOW act as an address for the Data Memory and determine the source of the connection to the location's channel and stream. This bit is output on the CCO pin one channel early. The CCO bit for stream 0 is output first. If the ODE pin is HIGH and bit 6 of the Control Register is 0, then this bit enables the output drive for the location's channel and stream. This allows individuals channels on individuals streams to be made high-impedance, allowing switching matrices to be constructed. A 1 enables the driver and a 0 disables it.
1 0
CCO (CCO Bit) OE (Output Enable)
TABLE 5 -- CONNECTION MEMORY LOW REGISTER
Stream Address Bits Channel Address Bits
7
6
5
4
3
2
1
0
Bit
7-5
(1)
Name
Stream Address Bits*
Description
The number expressed in binary notation on these 3 bits are the number of the stream for the source of the connection. Bit 7 is the most significant bit, e.g., If bit 7 is 1, bit 6 is 0 and bit 5 is 0 then the source of the connection is a channel on RX4. The number expressed in binary notation on these 5 bits is the number of the channel which is the source of the connection (the stream where the channel lies is defined by bits 7, 6 and 5). Bit 4 is the most significant bit, e.g., if bit 4 is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.
4-0(1) Channel Address Bits*
NOTE: 1. If bit 2 of the corresponding Connection HIGH location is 1 or bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with this location. Otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location.
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IDT72V8980 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
(1)
ABSOLUTE MAXIMUM RATINGS
Symbol Vcc Vi VO IO TS PD Parameter Symbol Voltage Voltage on Digital Inputs Voltage on Digital Outputs Current at Digital Outputs Storage Temperature Package Power Dissapation -55 Min. -0.3 GND - 0.3 GND - 0.3 Max. 5
Unit V V V mA C W
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI TOP Parameter Positive Supply Input Voltage Operating Temperature Commercial Min. 3.0 0 -40 Typ.(1) 25 Max. 3.6 5.25 +85 Unit V V C
VCC +0.5 VCC +0.3 20 +125 1
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
NOTE: 1. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
DC ELECTRICAL CHARACTERISTICS
Symbol ICC VIH VIL IIL CI VOH IOH VOL IOL IOZ CO Parameter Supply Current Input High Voltage Input Low Voltage Input Leakage Input Capacitance Output High Voltage Output High Current Output Low Voltage Output Low Current High Impedance Leakage Output Pin Capacitance Min. 2.0 2.4 10 5 Typ.(1) 3 Max. 5 0.8 15 10 0.4 5 10 Units mA V V A pF V mA V mA A pF IOH = 10mA Sourcing. VOH = 2.4V IOL = 5mA Sinking. VOL = 0.4V VO between GND and VCC VI between GND and VCC Test Conditions Outputs Unloaded
NOTE: 1. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Test Point
VCC
Output Pin S1 CL GND
RL S2 GND
S1 is open circuit except when testing output levels or high impedance states. S2 is switched to VCC or GND when testing output levels or high impedance states.
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Figure 4. Output Load
7
IDT72V8980 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
(1)
AC ELECTRICAL CHARACTERISTICS
Symbol tCLK tCH tCL tCTT tFPS tFPH tFPW Characteristics Clock Period(3) Clock Width High Clock Width Low Clock Transition Time Frame Pulse Setup Time Frame Pulse Hold Time Frame Pulse Width Min. 110 5 5
CLOCK TIMING
Typ.(2) 244 122 122 20 20 20 244 Max. 150 190 190 Unit ns ns ns ns ns ns ns
NOTE: 1. Timing is over recommended temperature and power supply voltages. 2. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. 3. Contents of Connection Memory are not lost if the clock stops, however, TX output go into the high impedance state.
C4i
F0i
Bit Cells
Channel 31 Bit 0
Channel 0 Bit 7
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Figure 5. Frame Alignment
tCLK tCTT tCL
C4i
tCTT tCHL tCH
tFPH
F0i
tFPS tFPW
tFPH
tFPS
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Figure 6. Clock Timing
8
IDT72V8980 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
(1)
AC ELECTRICAL CHARACTERISTICS
Symbol tTAZ tTZA tTAA tTOH tOED tXCH tXCD tSIS tSIH tRSZ tZRS tZDO tRPW Characteristics TX0-7 Delay - Active to High Z TX0-7 Delay - High Z to Active TX0-7 Delay - Active to Active TX0-7 Hold Time Output Driver Enable Delay External Control Hold Time External Control Delay Serial Input Setup Time Serial Input Hold Time Reset to High Z High Z to Reset High Z to Valid Data Reset Pulse Width Min. 20 5 10 10 5 0 100
SERIAL STREAM TIMING
Typ.(2) 30 45 40 45 45 50 15 20 20 30 32 Max. 45 60 60 60 30 Unit ns ns ns ns ns ns ns ns ns ns ns cycles ns C4i cycles RL = 1K(3), CL = 150pF Test Conditions RL = 1K(3), CL = 150pF CL = 150pF CL = 150pF CL = 150pF RL = 1K(3), CL = 150pF CL = 150pF CL = 150pF
NOTE: 1. Timing is over recommended temperature and power supply voltages. 2. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. 3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
ODE
tOED
tOED
Bit Cell Boundary
TX0-7
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C4i tTAZ tTOH
C4i
Figure 8. Output Driver Enable
Bit Cell Boundaries
TX0-7
tSIS tSIH
tTZA
RX0-7
TX0-7
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tTAA tTOH TX0-7
RS
Figure 9. Serial Inputs
tXCD tXCH CCO
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tRPW TX tZDO tRSZ tZRS
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Figure 7. Serial Outputs and External Control
9
Figure 10. Reset
IDT72V8980 3.3V Time Slot Interchange Digital Switch 256 x 256
Commercial Temperature Range
(1)
AC ELECTRICAL CHARACTERISTICS
Symbol tCSS tRWS tADS tAKD tAKD tFWS tSWD tRDS tDHT tDHT tRDZ tCSH tRWH tADH tAKH Characteristics Chip Select Setup Time Read/Write Setup Time Address Setup Time Acknowledgment Delay Fast Acknowledgment Delay Slow Fast Write Data Setup Time Slow Write Data Delay Read Data Setup Time Data Hold Time Read Data Hold Time Write Read Data to High Impedance Chip Select Hold Time Read/Write Hold Time Address Hold Time Acknowledgment Hold Time Min. 0 5 5 10 20 10 10 0 0 0
PROCESSOR BUS
Typ.(2) 40 2.0 50 50 5 5 5 20 Max. 60 4.5 1.7 0.5 75 40 Unit ns ns ns ns cycles ns cycles cycles ns ns ns ns ns ns ns RL = 1K(3), CL = 150pF RL = 1K(3), CL = 150pF C4i cycles C4i cycles, CL = 150pF RL = 1K(3), CL = 150pF CL = 150pF C4i cycles(4) Test Conditions
NOTE: 1. Timing is over recommended temperature and power supply voltages. 2. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. 3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. 4. Processor accesses are dependent on the C4i clock, and so some things are expressed as multiples of the C4i.
DS tCSS CS tRWS R/W tRWH tCSH
tADS A5-A0 tAKD DTA tRDS tSWD D7-D0 tFWS
tADH
tAKH
tRDZ tDHT
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Figure 11. Processor Bus
10
ORDERING INFORMATION
IDT XXXXXX Device Type XX Package X Process/ Temperature Range BLANK Commercial (-40C to +85C)
J PV DB
Plastic Leaded Chip Carrier (PLCC, J44-1) Small Shrink Outline Package (SSOP,SO48-1) Plastic Quad Flatpack (PQFP, DB44-1)
72V8980
256 x 256 3.3V Time Slot Interchange Digital Switch
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DATASHEET DOCUMENT HISTORY
05/23/2000 08/18/2000 01/24/2001 03/10/2003 05/09/2003 08/20/2003 pgs. pgs. pgs. pg. pgs. pg. 1, 2, and 11. 1, 2 and 11. 1 and 7. 1. 1, 2 and 11. 7. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
11
for Tech Support: 408-330-1753 email: TELECOMhelp@idt.com

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