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S72WS-P based MCP/PoP Products
1.8 Volt-only x16 Flash Memory and SDRAM on Split Bus Simultaneous Read/Write, Burst Mode NOR Flash NAND Flash or NAND Interface ORNANDTM Flash on Bus 1 Mobile SDRAM on Bus 2
Data Sheet (Advance Information)
S72WS-P based MCP/PoP Products Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S72WS-P_00
Revision A
Amendment 4
Issue Date May 29, 2006
Data
Sheet
(Advance
Information)
Notice On Data Sheet Designations
Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion LLC is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion LLC therefore places the following conditions upon Advance Information content:
"This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice."
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content:
"This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications."
Combination
Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion LLC applies the following conditions to documents in this category:
"This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion LLC deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur."
Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.
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S72WS-P based MCP/PoP Products
S72WS-P_00_A4 May 29, 2006
S72WS-P based MCP/PoP Products
1.8 Volt-only x16 Flash Memory and SDRAM on Split Bus Simultaneous Read/Write, Burst Mode NOR Flash NAND Flash or NAND Interface ORNANDTM Flash on Bus 1 Mobile SDRAM on Bus 2
Data Sheet (Advance Information)
Features
Power supply voltage of 1.7 to 1.95V Flash access time: 80 ns for NOR Flash, 25 ns for ORNAND Flash Flash burst frequencies: 66 MHz, 80 MHz, 108 MHz Mobile SDRAM burst frequency: 104 MHz (SDR), 133 MHz (DDR) Package: 9.0 x 12.0 mm MCP 11.0 x 13.0 mm MCP 15.0 x 15.0 mm Package-on-Package (PoP) Operating Temperature -25C to +85C (wireless)
The S72WS series is a product line of stacked packages and consists of:
One or two NOR flash memory die One NAND Interface ORNAND die Separate bus for one or more Mobile SDRAM die
The products covered by this document are listed in the table below.
ORNANDTM Flash Density 1024Mb 512Mb
NOR Flash Density Device S72WS256PD0 (MCP) S72WS256PD0 (POP) S72WS512PE0 (MCP) S72WS512PEF (POP) S72WS512PEF (POP) S72WS512PFF (MCP) S72WS512PFF (POP) S72WS512PFF (MCP) S72WS512PFF (POP) S72WS512PFG (MCP) S72WS512PFG (POP) X X X X X X X X X 512Mb 256Mb X X 128Mb
NAND Flash Density 512Mb 512Mb
DRAM Density 256Mb 128Mb X (DDR) X (DDR) X (SDR)
X X X X X X X X X (DDR) X (DDR) X (DDR) X (DDR) X (DDR) X (DDR)
X (SDR) X (SDR)
Note: For a full list of OPNs, please contact the local sales representative or refer to the Ordering Information valid combinations tables.
For detailed specifications, please refer to the individual data sheets.
Document S29WS-P S30MS-P 128 Mb Mobile DDR-DRAM Type 5 256 Mb Mobile SDR-DRAM Type 2 512 Mb Mobile DDR-DRAM Type 1 512 Mb Mobile SDR-DRAM Type 4 512 Mb NAND Type 1 512 Mb Mobile DDR-DRAM Type 5 Publication Identification Number (PID) S29WS-P_00 S30MS-P_00 SDRAM_07 SDRAM_05 SDRAM_09 SDRAM_06 NAND_01 DRAM_04
Publication Number S72WS-P_00
Revision A
Amendment 4
Issue Date May 29, 2006
This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.
Data
Sheet
(Advance
Information)
1.
1.1
Product Selector Guide
NOR Flash + DRAM Products
Device S72WS256PD0KFKLG 256 Mb S72WS256PD0HF6LG S72WS512PE0HF61R 512 Mb 80 MHz 256 Mb 104 MHz (SDR) Type 2 66 MHz 128 Mb 133 MHz (DDR) Type 5 MCP 9 x 12 mm MCP 9 x 12 mm NOR Flash Density NOR Flash Speed DRAM Density DRAM Speed DRAM Supplier Package PoP 15 x 15 mm
1.2
NOR Flash + ORNAND Flash + DRAM Products
Device-Model# S72WS512PEFKFKHH NOR Flash Density NOR Flash Speed ORNAND Flash Density ORNAND Bus Width ECC Required DRAM Density 256 Mb DRAM Speed DRAM Supplier Type 2 Package PoP 15 x 15 mm 160-ball PoP 15 x 15 mm 160-ball x16 Yes Type 1 S72WS512PFGJF9GH 512 Mb 1024 Mb S72WS512PFGKFKGH 512 Mb PoP 15 x 15 mm 160-ball MCP 11 x 13 mm 137-ball 80 MHz S72WS512PFFKFKLD 512 Mb x16 Yes Type 5 PoP 15 x 15 mm 160-ball 133 MHz (DDR) MCP 11 x 13 mm 137-ball MCP 11 x 13 mm 137-ball
S72WS512PFFKFKGH
512Mb
S72WS512PFFJF9GH
66 MHz
S72WS512PFFJF9LD
1.3
NOR Flash + NAND Flash + DRAM Products
Device-Model# S72WS512PEFKFKHJ NOR Flash Density NOR Flash Speed NAND Flash Density NAND Bus Width ECC Required DRAM Density 256 Mb DRAM Speed DRAM Supplier Type 2 Package PoP 15 x 15 mm 160-ball PoP 15 x 15 mm 160-ball Type 1 S72WS512PFFJF9GJ 512Mb 512Mb x16 Yes 512 Mb S72WS512PFFKFKLE 80 MHz S72WS512PFFJF9LE Type 5 MCP 11 x 13 mm 137-ball PoP 15 x 15 mm 160-ball 133 MHz (DDR) MCP 11 x 13 mm 137ball
S72WS512PFFKFKGJ
66 MHz
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S72WS-P based MCP/PoP Products
S72WS-P_00_A4 May 29, 2006
Data
Sheet
(Advance
Information)
2. MCP Block Diagram
2.1 NOR Flash + DRAM Products
A0-Amax A0-Amax
F-RDY
RDY
DQ0-DQ15
F-DQ15 - F-DQ0
F-CLK F-ADV# F-CE# F-OE# F-RST# F-ACC F-WP# F-WE#
CLK ADV# CE# OE# RESET# ACC WP# WE#
WS-P NOR Flash Memory
VSS VSSQ
F-VSS F-VSS Q
VCC VCCQ
F-VCC F-VCC Q
D-RAS# D-CAS# D-BA0 D-BA1 D-CKE D-WE# D-CE# D-A0 - D-Amax D-VCC D-VCCQ
RAS# CAS# BA0 BA1 CKE WE# CE# A0-Amax VCC VCCQ
DDR DRAM MEMORY
CLK CLK# DQS0 DQS1 LDQM UDQM DQ15-DQ0 VSS VSSQ
D-CLK D-CLK# D-D QS0 D-D QS1 D-DM0 D-DM1 D-DQ15 - D-DQ0 D-VSS D-VSSQ
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Data
Sheet
(Advance
Information)
2.2
NOR Flash + (OR)NAND Flash + DRAM Products
A0-A24 A0-A24
F-RDY
RDY CLK AVD# CE# OE# RESET# ACC WP# WE#
DQ0-DQ15
DQ0-DQ15
F-CLK F-AVD# F-CE# F-OE# F-RST# F-ACC F-WP# F-WE#
WS512P NOR Flash Memory
VSS VSSQ
F-VSS F-VSSQ
VCC VCCQ
F-VCC F-VCCQ
I/O0-I/O15
N-RY/BY#
RB#
N-CLE N-CE# N-ALE N-PRE N-RE# N-WP# N-WE#
CLE CE# ALE PRE RE# WP# WE#
MS512P x16 ORNAND Flash Memory
VSS
N-VSS
VCC
N-VCC
D-RAS# D-CAS# D-BA0 D-BA1 D-CKE D-WE# D-CE# D-A0 - D-A12 D-VCC D-VCCQ
RAS# CAS# BA0 BA1 CKE WE# CE# A0-A12 VCC VCCQ
512Mb DDR DRAM MEMORY
CLK CLK# DQS0 DQS1 LDQM UDQM DQ15-DQ0 VSS VSSQ
D-CLK D-CLK# D-D QS0 D-D QS1 D-DM0 D-DM1 D-DQ15 - D-DQ0 D-VSS D-VSSQ
Note 1. For MCPs, VSS is shared between all Flash (NOR and ORNAND). Also, VSSQ is tied to VSS internally within the MCP.
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S72WS-P based MCP/PoP Products
S72WS-P_00_A4 May 29, 2006
Data
Sheet
(Advance
Information)
3. Connection Diagrams
3.1 256Mb NOR Flash with 128Mb SDR/DDR-DRAM
137-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)
A1
D-CKE
A2 D-CLK
A3
D-CLK#
A4
RFU
A5
D-VSS
A6
D-VCC
A7
RFU
A8
D-A11
A9
D-VSS
A10
D-CE#
B1
B2
B3
D-A9
B4
D-A8
B5
D-VSSQ
B6
D-VCCQ
B7
D-A7
B8
D-A6
B9
RFU
B10
D-CAS#
D-RAS# D-WE#
C1
D-A10
C2
AVD#
C3
VSS
C4
CLK
C5
RFU
C6
RFU
C7
RFU
C8
RFU
C9
RFU
C10
RFU
D1
D-A0
D2
F-WP#
D3
A7
D4
D-DM0
D5
F-ACC
D6
WE#
D7
A8
D8
A11
D9
RFU
D10
D-A5
Legend
E1
D-VCCQ
E2
A3
E3
A6
E4
D-DM1
E5
F-RST#
E6
RFU
E7
A19
E8
A12
E9
A15
E10
D-VCCQ
NOR Flash only
F1
D-VSSQ
F2
A2
F3
A5
F4
A18
F5
F-RDY
F6
A20
F7
A9
F8
A13
F9
A21
F10
D-VSSQ
DRAM only
G1
D-DQ0
G2
A1
G3
A4
G4
A17
G6
A23
G7
A10
G8
A14
G9
A22
G10
D-DQ15
H1
D-DQ1
H2
A0
H3
VSS
H4
DQ1
H7
DQ6
H8
RFU
H9
A16
H10
D-DQ14
Reserved for Future Use
J1
J2
J3
OE#
J4
DQ9
J5
DQ3
J6
DQ4
J7
DQ13
J8
DQ15
J9
RFU
J10
D-DQ13
DDR DRAM only
D-DQ2 F1-CE#
K1
D-DQ3
K2
RFU
K3
DQ0
K4
DQ10
K5
F-VCC
K6
RFU
K7
DQ12
K8
DQ7
K9
VSS
K10
D-DQ12
L1
D-DQ4
L2
RFU
L3
DQ8
L4
DQ2
L5
DQ11
L6
RFU
L7
DQ5
L8
DQ14
L9
RFU
L10
D-DQ11
M1
D-DQ5
M2
RFU
M3
RFU
M4
VSS
M5
F-VCC
M6
RFU
M7
RFU
M8
F-VCCQ
M9
RFU
M10
D-DQ10
N1
RFU
N2
D-BA0
N3
D-DQ6
N4
D-DQ7
N5
D-VSSQ
N6
D-VCCQ
N7
D-DQ8
N8
D-DQ9
N9
D-BA1
N10
RFU
P1
P2
P3
D-A1
P4
D-A2
P5
D-VSS
P6
D-VCC
P7
D-A3
P8
D-A4
P9
RFU
P10
D-DQS1
D-DQS0 D-VSS
Note: DDR-only signals are RFUs in the case of the SDR DRAM-based solutions.
S72WS-P_00_A4 May 29, 2006
S72WS-P based MCP/PoP Products
5
Data
Sheet
(Advance
Information)
3.2
512Mb NOR Flash with 512-Mb (OR)NAND on Bus 1 and 512-Mb DRAM on Bus 2
137-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)
A1 D-CKE
A2 D-CLK
A3 D-CLK# B3 D-A9 C3 VSS D3 A7 E3 A6
A4 RFU
A5 D-VSS B5 D-VSSQ C5 RFU
A6 D-VCC B6 D-VCCQ C6 F-VCC D6 F-WE# E6 DNU
A7 D-A12
A8 D-A11
A9 D-VSS B9 RFU C9 N-CLE
A10 D-CE#
B1 D-RAS# C1 D-A10
B2 D-WE# C2 F-AVD#
B4 D-A8 C4 F-CLK
B7 D-A7 C7 N-PRE
B8 D-A6 C8 N-ALE
B10 D-CAS# C10 RFU
Legend
Reserved for Future Use
D1 D-A0 E1 D-VCCQ F1 D-VSSQ G1 D-DQ0
D2 F-WP# E2 A3
D4 D-DM0 E4 D-DM1
D5 F-ACC E5 F-RST#
D7 A8 E7 A19
D8 A11 E8 A12
D9 N-CE# E9 A15
D10 D-A5 E10 D-VCCQ F10 D-VSSQ ORNAND Flash Only G10 D-DQ15 DRAM Only NOR Flash Only Do Not Use
F2 A2
F3 A5
F4 A18
F5 F-RDY
F6 A20
F7 A9
F8 A13
F9 A21
G2 A1
G3 A4
G4 A17
G6 A23
G7 A10
G8 A14
G9 A22
H1 D-DQ1 J1 D-DQ2 K1 D-DQ3 L1 D-DQ4 M1 D-DQ5 N1 N-WE# P1 D-DQS0
H2 A0 J2 F1-CE# K2 DNU L2 N-VCC M2 RFU N2 D-BA0 P2 D-VSS
H3 VSS J3 F-OE# K3 DQ0 L3 DQ8 M3 RFU N3 D-DQ6 P3 D-A1
H4 DQ1 J4 DQ9 K4 DQ10 L4 DQ2 M4 VSS N4 D-DQ7 P4 D-A2 J5 DQ3 K5 F-VCC L5 DQ11 M5 F-VCC N5 J6 DQ4 K6 N-VCC L6 RFU M6 RFU N6
H7 DQ6 J7 DQ13 K7 DQ12 L7 DQ5 M7 DNU N7 D-DQ8 P7 D-A3
H8 A24 J8 DQ15 K8 DQ7 L8 DQ14 M8 F-VCCQ N8 D-DQ9 P8 D-A4
H9 A16 J9 DNU K9 VSS L9 N-WP# M9 DNU N9 D-BA1 P9 P9
H10 D-DQ14 J10 D-DQ13 K10 D-DQ12 L10 D-DQ11 M10 D-DQ10 N10 N-RE# P10
All Flash Shared
D-VSSQ D-VCCQ P5 D-VSS P6 D-VCC
N-RY/BY# D-DQS1
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S72WS-P based MCP/PoP Products
S72WS-P_00_A4 May 29, 2006
Data
Sheet
(Advance
Information)
3.2.0.1
Special Handling Instructions For FBGA Package
Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150xC for prolonged periods of time.
3.2.1
Package-on-Package Connection Diagram
160-ball Fine Pitch Ball Grid Array (Top View, Balls Facing Down)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Legend
A
NC
D-V SS
F-A1
F-V SS
F-A3
F-A5
F-A7
F-A9
F-V SSQ
N-CLE
F-A11
F-A13
F-A15
F-A17
F-V SSQ
F-A19
F-A21
F-A23
RFU
RFU
N-V SS
NC
B
D-V SS
D-V DD
F-A0
F-V CC
F-A2
F-A4
F-A6
F-A8
F-V CCQ
N-ALE
F-A10
F-A12
F-A14
F-A16
F-V CCQ
F-A18
F-A20
F-A22
F-A24
N-V CC
F-V CCQ
F-V SSQ
C
N-WE#
N-RY/ BY#
NOR Flash Only
F-RST#
RFU
D E F
D-DQ1
D-DQ0
F1-CE#
F2-CE#
D-V SSQ
D-V DDQ
N1-CE#
RFU
Reserved for Future Use
D-DQ3
D-DQ2
N-RE#
N-WP#
DDR DRAM Only G
D-DQ5 D-DQ4
F-WE#
F-WP#
H J K
D-V SSQ
D-V DDQ
D-WE#
F-OE#
ORNAND Flash Only
D-DQ7
D-DQ6
D-V DD
D-V SS
D-DM0
D-DQS0
D-A0
D-A1
Flash Shared Only
L
D-DM1
D-DQS1
D-A2
D-A3
M
D-V SSQ
D-V DDQ
D-A4
D-A5
No Connect
N
D-DQ9
D-DQ8
D-A6
D-A7
P
D-V SS
D-V DD
D-BA0
D-BA1
R
D-DQ11
D-DQ10
D1-CS#
RFU
T
D-DQ13
D-DQ12
D-RAS# D-CAS#
U
D-V SSQ
D-V DDQ
D-A8
D-A9
V
D-DQ15
D-DQ14
D-A10
D-A11
W
D-CKE
D-CLK
D-A12
RFU
Y AA
RFU
D-CLK#
F-ACC
D-V SS
RFU
F-V SS
F-V CC
F-DQ0/ N-ADQ0
F-V CCQ
F-DQ2/ N-ADQ2
F-DQ4/ N-ADQ4
F-V CCQ
F-DQ6/ N-ADQ6
RFU
F-CLK
N-V CC
RFU
F-DQ8/ N-ADQ8
F-V CCQ
F-DQ10/ N-ADQ10
F-DQ12/ N-ADQ12
F-V CCQ
F-DQ14/ N-ADQ14
F-ADV#
D-V DD
RFU
AB
NC
D-V DD
N-PRE
F-DQ1/ N-ADQ1
F-V SSQ
F-DQ3/ N-ADQ3
F-DQ5/ N-ADQ5
F-V SSQ
F-DQ7/ N-ADQ7
RFU
RFU
N-V SS
RFU
F-DQ9/ N-ADQ9
F-V SSQ
F-DQ11/ N-ADQ11
F-DQ13/ N-ADQ13
F-V SSQ
F-DQ15/ N-ADQ15
F-WAIT
F-V CCQ
NC
3.2.2
Look-ahead Ballout for Future Designs
Please refer to the Design-in Scalable Wireless Solutions with Spansion Products application note (publication number: Design_Scalable_Wireless_A0_E). Contact your local Spansion sales representative for more details.
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7
Data
Sheet
(Advance
Information)
3.3
NOR Flash and DRAM Input/Output Descriptions
Amax-A0 DQ15-DQ0 F-CE# F-OE# F-WE# F-VCC F-VCCQ VSS RFU F-RDY F-CLK = = = = = = = = = = = NOR Flash Address inputs Flash Data input/output, shared between NOR and ORNAND Flash. DQ0-DQ7 shared for x8 ORNAND NOR Flash Chip-enable input #1. Asynchronous relative to CLK for Burst Mode. NOR Flash Output Enable input. Asynchronous relative to CLK for Burst mode. NOR Flash Write Enable input. NOR Flash device power supply (1.7 V - 1.95V). Input/Output Buffer power supply. Ground Reserved for Future Use Flash ready output. Indicates the status of the Burst read. VOL = data valid. NOR Flash Clock. The first rising edge of CLK in conjunction with AVD# low latches the address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low during asynchronous access. NOR Flash Address Valid input. Indicates to device that the valid address is present on the address inputs. VIL = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge of CLK. VIH= device ignores address inputs NOR Flash hardware reset input. VIL= device resets and returns to reading array data NOR Flash hardware write protect input. VIL = disables program and erase functions in the four outermost sectors. NOR Flash accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. SDRAM Address inputs SDRAM Data input/output SDRAM System Clock SDRAM Chip Select SDRAM Clock Enable SDRAM Bank Select SDRAM Row Address Strobe SDRAM Column Address Strobe SDRAM Data Input/Output Mask SDRAM Write Enable input SDRAM Ground DDR SDRAM Clock - in addition to D-CLK, this signal is available for DDRAMs that need CLK# for normal operations SDRAM Input/Output Buffer ground SDRAM Input/Output Buffer power supply SDRAM device power supply DDR SDRAM Data Strobe pins. DQS provides the read data strobes (as output) and the write data strobes (as input). Each DQS pin corresponds to eight DQ pins, respectively.
F-AVD#
=
F-RST# F-WP# F-ACC D-Amax-D-A0 D-DQ15-D-DQ0 D-CLK D-CE# D-CKE D-BA1-BA0 D-RAS# D-CAS# D-DM1-D-DM0 D-WE# D-VSS D-CLK# D-VSSQ D-VCCQ D-VCC D-DQS0 - DDQS1
= = = = = = = = = = = = = = = = = = =
3.3.1
ORNAND Signal Descriptions
N-PRE N-ALE N-CLE N-CE# N-WP# N-WE# N-RE# N-RY/BY# N-I/O0-N-I/O15 N-VCC = = = = = = = = = = ORNAND Power-On Read Enable. Tie to VSS on customer board if not used ORNAND Address Latch Enable ORNAND Command Latch Enable ORNAND Chip-enablE ORNAND Write-protect ORNAND Write-enable ORNAND Read-enable ORNAND Ready-Busy ORNAND I/O Signals (I/O0-I/O7 for x8 bus width) ORNAND Power Supply
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Data
Sheet
(Advance
Information)
4. Ordering Information
The order number is formed by a valid combinations of the following:
S72WS
512
P
D0
HF
0
L
G
0 PACKING TYPE 0 = Tray 2 = 7" Tape and Reel 3 = 13" Tape and Reel MODEL NUMBER 2 G = 66MHz/133MHz Speed, No Data Flash H = 66MHz/133MHz Speed, Spansion MS-P as Data Flash J = 66MHz/133MHz Speed, NAND Type 1 as Data Flash R = 80MHz/104MHz Speed, No Data Flash D = 80MHz/133MHz Speed, Spansion MS-P as Data Flash E = 80MHz/133MHz Speed, NAND Type 1 as Data Flash MODEL NUMBER 1 L = x16 DDR DRAM Type 5 G = x16 DDR DRAM Type 1 H = x16 DDR DRAM Type 2 1 = x16 SDR DRAM Type 2 PACKAGE DESCRIPTOR Depends on Character 12. For a more detailed description see Table 4.1. PACKAGE TYPE & MATERIAL SET HF = 1.2mm MCP FBGA, Pb-free KF = 1.2mm POP FBGA, Pb-free JF = 1.4mm MCP FBGA, Pb-free DRAM & ORNAND FLASH DENSITY D0 = 128 Mb DRAM, No Data Flash EF = 256Mb DRAM, 512Mb NAND Flash FF = 512Mb DRAM, 512Mb NAND Flash E0 = 256Mb DRAM, No Data Flash PROCESS TECHNOLOGY P = 90 nm, MirrorBitTM Technology CODE FLASH DENSITY 256 = 256Mb 512 = 512Mb PRODUCT FAMILY S72WS Stacked Products (MCP/PoP) 1.8 V NOR Flash and ORNAND Flash on Bus 1 with Mobile DRAM on Bus 2
Table 4.1 Character Position Descriptions (Sheet 1 of 2)
Character 14 Description Character 12 Character 13 0 1 2 3 4 H, J, or G 5 6 7 8 9 9x12 mm 9x12 mm 11x13 mm 11x13 mm 11x13 mm 115 137 84 115 137 Package Area 7x9 mm 7x9 mm 8x11.6 mm 8x11.6 mm 9x12 mm Package Ball Count 56 80 64 84 84 0.35 mm Raw Ball Size
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Table 4.1 Character Position Descriptions (Sheet 2 of 2)
Character 14 Description Character 12 Character 13 A B D F G K H J K L M 14x14 mm 15x15 mm 15x15 mm 17x17 mm 17x17 mm 152 160 160 192 192 0.50 mm 0.45 mm 0.50 mm 0.45 mm 0.50 mm Package Area 11x11 mm 11x11 mm 12x12 mm 12x12 mm 14x14 mm Package Ball Count 112 112 128 128 152 Raw Ball Size 0.45 mm 0.50 mm 0.45 mm 0.50 mm 0.45 mm
4.1
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
S72WS-P Valid Combinations
Base Ordering Number
Package & Material Set KF
Package Descriptor K
Packing Type
NOR Flash Speed
DRAM Supplier
DRAM Speed
Package Type 15x15 mm (PoP)
Package Markings
S72WS256PD0 HF S72WS512PE0 S72WS512PEF HF KF HF JF 6 6 K 6 9
66 MHz
Type 5
133 MHz 9x12 mm (MCP)
80 MHz 66 MHz 66 MHz 66 MHz
Type 2 Type 2 Type 1 Type 1 Type 5 Type 1 Type 5
104 MHz 133 MHz
9x12 mm (MCP) 15x15 mm (PoP) 15x15 mm (PoP) (Note 2)
0, 2, 3 (Note 1)
S72WS512PFF
80 MHz 66 MHz KF JF K 80 MHz 9 66 MHz KF K
133 MHz
11x13 mm (MCP) 15x15 mm (PoP) 11x13 mm (MCP)
S72WS512PFG
Type 1
133 MHz 15x15 mm (PoP)
Notes: 1. Packing Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading S and packing type designator from ordering part number.
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5. Physical Dimensions
5.1 TLD137--137-ball Fine-Pitch Ball Grid Array (FBGA) 12 x 9 mm Package
D
0.15 C (2X)
10 9 8 7 6 5 4
A
D1 eD
SE 7 E1
E eE
3 2 1
INDEX MARK PIN A1 CORNER 10
P NML K J
HG F
EDC
BA
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW A A2 A1
6
0.20 C
C
0.08 C
SIDE VIEW b
137X
0.15 M C A B 0.08 M C
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n b eE eD SD / SE 0.35 TLD 137 N/A 12.00 mm x 9.00 mm PACKAGE MIN --0.17 0.81 NOM ------12.00 BSC. 9.00 BSC. 10.40 BSC. 7.20 BSC. 14 10 137 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. G5,H5,H6 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3393\ 16-038.22a
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5.2
FVD137--137-ball Fine-Pitch Ball Grid Array (FBGA) 13 x 11 mm Package
D
0.15 C (2X)
10 9 8 7 6 5 4 3 2 1
A
eD
D1
SE
7
E eE
E1
P
NM
LK
J
HGF
E
DCB
A
PIN A1 CORNER
9 INDEX MARK
B
7
PIN A1 CORNER
TOP VIEW A A2 A1
6
0.15 C (2X) 0.20 C
SD
BOTTOM VIEW
SIDE VIEW b
C
0.08 C
137X
0.15 M C A B 0.08 M C
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n Ob eE eD SD SE 0.35 FVD 137 N/A 13.00 mm x 11.00 mm PACKAGE MIN --0.10 1.09 NOM ------13.00 BSC. 11.00 BSC. 10.40 BSC. 7.20 BSC. 14 10 137 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. G5,H5,H6 0.45 MAX 1.40 --1.24 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9 8. 6 7 4. 5. NOTE 2. 3. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3522 \ 16-038.21 \ 09.29.05
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5.3
BWB160--160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package
PIN A1 CORNER
D
9 INDEX MARK
A
D1 eD
A B C D E F G H J K L M N P R T U V W Y AA AB
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
PIN A1 CORNER
SE 7 E1
E eE
0.10 C (2X)
B
SD BOTTOM VIEW
7
TOP VIEW
0.10 C (2X)
A A2 A1
6
0.20 C
C
0.10 C
SIDE VIEW b
M C AB MC
160X
0.15 0.08
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n N R Ob eE eD SD / SE ? 0.45 BWB 160 N/A 15.00 mm x 15.00 mm PACKAGE MIN --0.40 0.74 NOM ------15.00 BSC. 15.00 BSC. 13.65 BSC. 13.65 BSC. 22 22 160 160 2 0.50 0.65 BSC. 0.65 BSC. 0.325 BSC. C3~C20,D3~D20,E3~E20,F3~F20 G3~G20,H3~H20,J3~J20,K3~K20 L3~L20,M3~M20,N3~N20,P3~P20 R3~R20,T3~T20,U3~U20,V3~V20 W3~W20,Y3~Y20 0.55 MAX 1.30 --0.84 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT MAXIMUM NUMBER OF BALLS NUMBER OF LAND PARAMETERS BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9 8. 7 6 NOTE 1. 2. 3. 4. 5. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3523 \ 16-038.46 \ 02.23.06
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5.4
BTA160--160-ball Fine-Pitch Ball Grid Array (FBGA) 15 x 15 mm Package
PIN A1 CORNER
D
9 INDEX MARK
A
D1 eD
A B C D E F G H J K L M N P R T U V W Y AA AB
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
PIN A1 CORNER
SE 7 E1
E eE
0.10 C (2X)
B
SD
7
TOP VIEW A A2 A1
6
0.10 C (2X) 0.20 C
BOTTOM VIEW
C
0.10 C
SIDE VIEW b
C AB C
160X
0.15 M 0.08 M
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n N R Ob eE eD SD SE 0.45 BTA 160 N/A 15.00 mm x 15.00 mm PACKAGE MIN --0.40 0.74 NOM ------15.00 BSC. 15.00 BSC. 13.65 BSC. 13.65 BSC. 22 22 160 160 2 0.50 0.65 BSC. 0.65 BSC. 0.325 BSC. C3~C20,D3~D20,E3~E20,F3~F20 G3~G20,H3~H20,J3~J20,K3~K20 L3~L20,M3~M20,N3~N20,P3~P20 R3~R20,T3~T20,U3~U20,V3~V20 W3~W20,Y3~Y20 0.55 MAX 1.30 --0.84 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT MAXIMUM NUMBER OF BALLS NUMBER OF LAND PARAMETERS BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9 8. 7 6 NOTE 1. 2. 3. 4. 5. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JEP95, SECTION 4.3, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
10. OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT.
3550 \ 16-038.55 \ 02.23.06
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6.
6.1
Revision History
Revision A1 (February 23, 2006)
Initial release.
6.2
Revision A2 (March 29, 2006)
Modified Block Diagram for Section 2.1 and Section 2.2 2. Updated PoP Connection Diagram in Section 3.2.2 3. Updated Section 3.3 to append F-RDY and N-RY/BY# as separate signals
6.3
Revision A3 (April 11, 2006)
Added a note to the NOR Flash + (OR)NAND Flash + DRAM Products block diagram Updated pin M8 on the 256Mb NOR Flash with 128Mb SDR/DDR-DRAM connection diagram
6.4
Revision A4 (May 29, 2006)
Added OPNs for products based on DRAM Type 5 Updated Product Selector Guide Updated Ordering Information Updated Valid Combinations
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2006 Spansion LLC. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion LLC. Other names are for informational purposes only and may be trademarks of their respective owners.
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