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Freescale Semiconductor
Technical Data
MPC8347EAEC Rev. 3, 11/2006
MPC8347EA PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications
The MPC8347EA contains a PowerPCTM processor core (built on Power ArchitectureTM technology) with system logic for networking, storage, and general-purpose embedded applications. For functional characteristics of the processor, refer to the MPC8349EA PowerQUICCTM II Pro Integrated Host Processor Reference Manual, Rev. 0. To locate published errata or updates for this document, contact your Freescale sales office. NOTE The information in this document is accurate for revision 3.x silicon and later (in other words, for devices with part numbers ending in A or B, such as the MPC8347EA or MPC8347EB). For information on revision 1.1 silicon and earlier versions (MPC8347E/MPC8347), see the PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications. See Section 23.1, "Part Numbers Fully Addressed by this Document," for silicon revision level determination.
Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11 Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13 RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 14 DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 16 DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Ethernet: Three-Speed Ethernet, MII Management . 24 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 59 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 System Design Information . . . . . . . . . . . . . . . . . . . 99 Document Revision History . . . . . . . . . . . . . . . . . . 104 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 104
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 17. 18. 19. 20. 21. 22. 23.
(c) Freescale Semiconductor, Inc., 2005, 2006. All rights reserved.
Overview
1
Overview
This section provides a high-level overview of the MPC8347EA features. Figure 1 shows the major functional units within the MPC8347EA.
Security
DUART Dual I2C Timers GPIO
e300 Core Interrupt Controller 32KB D-Cache 32KB I-Cache DDR SDRAM Controller
Local Bus
High-Speed USB 2.0 Dual Role Host
10/100/1000 Ethernet
10/100/1000 Ethernet
PCI
SEQ
DMA
Figure 1. MPC8347EA Block Diagram
Major features of the MPC8347EA are as follows: * Embedded PowerPC e300 processor core; operates at up to 667 MHz -- High-performance, superscalar processor core -- Floating-point, integer, load/store, system register, and branch processing units -- 32-Kbyte instruction cache, 32-Kbyte data cache -- Lockable portion of L1 cache -- Dynamic power management -- Software-compatible with the other Freescale processor families that implement the PowerPC architecture * Double data rate, DDR1/DDR2 SDRAM memory controller -- Programmable timing supporting DDR1 and DDR2 SDRAM -- 32- or 64-bit data interface, up to 400 MHz data rate for TBGA, 266 MHz for PBGA -- Up to four physical banks (chip selects), each bank up to 1 Gbyte independently addressable -- DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports -- Full error checking and correction (ECC) support -- Support for up to 16 simultaneous open pages (up to 32 pages for DDR2) -- Contiguous or discontiguous memory mapping -- Read-modify-write support -- Sleep-mode support for SDRAM self refresh -- Auto refresh
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Overview
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-- On-the-fly power management using CKE -- Registered DIMM support -- 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2 Dual three-speed (10/100/1000) Ethernet controllers (TSECs) -- Dual controllers designed to comply with IEEE Std. 802.3TM, 802.3u, 820.3x, 802.3z, 802.3ac -- Ethernet physical interfaces: - 1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex - 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex -- Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100 programming models -- 9.6-Kbyte jumbo frame support -- RMON statistics support -- Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module -- MII management interface for control and status -- Programmable CRC generation and checking PCI interface -- Designed to comply with PCI specification revision 2.3 -- Data bus width: - 32-bit data PCI interface operating at up to 66 MHz -- PCI 3.3-V compatible -- PCI host bridge capabilities -- PCI agent mode on PCI interface -- PCI-to-memory and memory-to-PCI streaming -- Memory prefetching of PCI read accesses and support for delayed read transactions -- Posting of processor-to-PCI and PCI-to-memory writes -- On-chip arbitration supporting five masters on PCI -- Accesses to all PCI address spaces -- Parity supported -- Selectable hardware-enforced coherency -- Address translation units for address mapping between host and peripheral -- Dual address cycle for target -- Internal configuration registers accessible from PCI Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, IEEE Std. 802.11iTM, iSCSI, and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units (EUs): -- Public key execution unit (PKEU) : - RSA and Diffie-Hellman algorithms - Programmable field size up to 2048 bits
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Overview
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- Elliptic curve cryptography - F2m and F(p) modes - Programmable field size up to 511 bits -- Data encryption standard (DES) execution unit (DEU) - DES and 3DES algorithms - Two key (K1, K2) or three key (K1, K2, K3) for 3DES - ECB and CBC modes for both DES and 3DES -- Advanced encryption standard unit (AESU) - Implements the Rijndael symmetric-key cipher - Key lengths of 128, 192, and 256 bits - ECB, CBC, CCM, and counter (CTR) modes -- XOR parity generation accelerator for RAID applications -- ARC four execution unit (AFEU) - Stream cipher compatible with the RC4 algorithm - 40- to 128-bit programmable key -- Message digest execution unit (MDEU) - SHA with 160-, 224-, or 256-bit message digest - MD5 with 128-bit message digest - HMAC with either algorithm -- Random number generator (RNG) -- Four crypto-channels, each supporting multi-command descriptor chains - Static and/or dynamic assignment of crypto-execution units through an integrated controller - Buffer size of 256 bytes for each execution unit, with flow control for large data sizes Universal serial bus (USB) dual role controller -- USB on-the-go mode with both device and host functionality -- Complies with USB specification Rev. 2.0 -- Can operate as a stand-alone USB device - One upstream facing port - Six programmable USB endpoints -- Can operate as a stand-alone USB host controller - USB root hub with one downstream-facing port - Enhanced host controller interface (EHCI) compatible - High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations -- External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI) Universal serial bus (USB) multi-port host controller -- Can operate as a stand-alone USB host controller - USB root hub with one or two downstream-facing ports
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Overview
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- Enhanced host controller interface (EHCI) compatible - Complies with USB specification Rev. 2.0 -- High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations -- Direct connection to a high-speed device without an external hub -- External PHY with serial and low-pin count (ULPI) interfaces Local bus controller (LBC) -- Multiplexed 32-bit address and data operating at up to 133 MHz -- Eight chip selects for eight external slaves -- Up to eight-beat burst transfers -- 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller -- Three protocol engines on a per chip select basis: - General-purpose chip select machine (GPCM) - Three user-programmable machines (UPMs) - Dedicated single data rate SDRAM controller -- Parity support -- Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit) Programmable interrupt controller (PIC) -- Functional and programming compatibility with the MPC8260 interrupt controller -- Support for 8 external and 35 internal discrete interrupt sources -- Support for 1 external (optional) and 7 internal machine checkstop interrupt sources -- Programmable highest priority request -- Four groups of interrupts with programmable priority -- External and internal interrupts directed to host processor -- Redirects interrupts to external INTA pin in core disable mode. -- Unique vector number for each interrupt source Dual industry-standard I2C interfaces -- Two-wire interface -- Multiple master support -- Master or slave I2C mode support -- On-chip digital filtering rejects spikes on the bus -- System initialization data optionally loaded from I2C-1 EPROM by boot sequencer embedded hardware DMA controller -- Four independent virtual channels -- Concurrent execution across multiple channels with programmable bandwidth control -- Handshaking (external control) signals for all channels: DMA_DREQ[0:3], DMA_DACK[0:3], DMA_DDONE[0:3] -- All channels accessible to local core and remote PCI masters
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Overview
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-- Misaligned transfer capability -- Data chaining and direct mode -- Interrupt on completed segment and chain DUART -- Two 4-wire interfaces (RxD, TxD, RTS, CTS) -- Programming model compatible with the original 16450 UART and the PC16550D Serial peripheral interface (SPI) for master or slave General-purpose parallel I/O (GPIO) -- 52 parallel I/O pins multiplexed on various chip interfaces System timers -- Periodic interrupt timer -- Real-time clock -- Software watchdog timer -- Eight general-purpose timers Designed to comply with IEEE Std. 1149.1TM, JTAG boundary scan Integrated PCI bus and SDRAM clock generation
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Electrical Characteristics
2
Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal charaistics for the MPC8347EA. The MPC8347EA is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications.
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings 1
Characteristic Symbol VDD AVDD GVDD LVDD OVDD MVIN MVREF LVIN OVIN OVIN TSTG Max Value -0.3 to 1.32 -0.3 to 1.32 -0.3 to 2.75 -0.3 to 1.98 -0.3 to 3.63 -0.3 to 3.63 -0.3 to (GVDD + 0.3) -0.3 to (GVDD + 0.3) -0.3 to (LVDD + 0.3) -0.3 to (OVDD + 0.3) -0.3 to (OVDD + 0.3) -55 to 150 Unit V V V V V V V V V V *C 2, 5 2, 5 4, 5 3, 5 6 Notes
Table 1 provides the absolute maximum ratings.
Core supply voltage PLL supply voltage DDR and DDR2 DRAM I/O voltage Three-speed Ethernet I/O, MII management voltage PCI, local bus, DUART, system control and power management, I2C, and JTAG I/O voltage Input voltage DDR DRAM signals DDR DRAM reference Three-speed Ethernet signals Local bus, DUART, CLKIN, system control and power management, I2C, and JTAG signals PCI Storage temperature range
Notes: 1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 4. Caution: LVIN must not exceed LVDD by more than 0.3 V. This limit can be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. (M,L,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2. 6. OVIN on the PCI interface can overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as shown in Figure 3.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 7
Electrical Characteristics
2.1.2
Power Supply Voltage Specification
Table 2 provides the recommended operating conditions for the MPC8347EA. Note that the values in Table 2 are the recommended and tested operating conditions. Proper device operation outside these conditions is not guaranteed.
Table 2. Recommended Operating Conditions
Characteristic Core supply voltage PLL supply voltage DDR and DDR2 DRAM I/O voltage Three-speed Ethernet I/O supply voltage Three-speed Ethernet I/O supply voltage PCI, local bus, DUART, system control and power management, I2C, and JTAG I/O voltage Symbol VDD AVDD GVDD LVDD1 LVDD2 OVDD Recommended Value 1.2 V 60 mV 1.2 V 60 mV 2.5 V 125 mV 1.8 V 90 mV 3.3 V 330 mV 2.5 V 125 mV 3.3 V 330 mV 2.5 V 125 mV 3.3 V 330 mV Unit V V V V V V Notes 1 1
Notes: 1. GVDD, LVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction--either in the positive or negative direction.
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8347EA.
G/L/OVDD + 20% G/L/OVDD + 5% VIH G/L/OVDD
GND GND - 0.3 V VIL GND - 0.7 V Not to Exceed 10% of tinterface1
Note: 1. tinterface refers to the clock period associated with the bus clock interface.
Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD
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Electrical Characteristics
Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8347EA for the 3.3-V signals, respectively.
11 ns (Min) +7.1 V Overvoltage Waveform 0V 4 ns (Max) 62.5 ns +3.6 V Undervoltage Waveform -3.5 V 7.1 V p-to-p (Min) 7.1 V p-to-p (Min)
4 ns (Max)
Figure 3. Maximum AC Waveforms on PCI interface for 3.3-V Signaling
2.1.3
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates.
Table 3. Output Drive Capability
Driver Type Local bus interface utilities signals PCI signals (not including PCI output clocks) PCI output clocks (including PCI_SYNC_OUT) DDR signal DDR2 signal TSEC/10/100 signals DUART, system control, I2C, JTAG GPIO signals Output Impedance () 42 25 42 20 16 32 (half strength mode) 42 42 42 GVDD = 2.5 V GVDD = 1.8 V LVDD = 2.5/3.3 V OVDD = 3.3 V OVDD = 3.3 V, LVDD = 2.5/3.3 V Supply Voltage OVDD = 3.3 V
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 9
Electrical Characteristics
2.2
Power Sequencing
MPC8347EA does not require the core supply voltage and I/O supply voltages to be applied in any particular order. Note that during the power ramp up, before the power supplies are stable, there may be a period of time that I/O pins are actively driven. After the power is stable, as long as PORESET is asserted, most I/O pins are tri-stated. To minimize the time that I/O pins are actively driven, it is recommended to apply core voltage before I/O voltage and assert PORESET before the power supplies fully ramp up.
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Power Characteristics
3
Power Characteristics
Table 4. MPC8347EA Power Dissipation 1
Core Frequency (MHz) 266 CSB Frequency (MHz) 266 133 400 PBGA 133 400 200 100 333 333 166 400 266 133 450 TBGA 150 500 333 166 533 266 133 667 333 2.1 2.4 2.2 2.4 2.2 3.5 3.0 3.3 3.1 3.3 3.1 4.6 3.2 3.6 3.4 3.6 3.4 5 W W W W W W 300 1.4 1.5 1.3 2.0 1.8 2.1 1.9 2.3 1.7 1.8 1.7 3.0 2.8 3.0 2.9 3.2 1.9 2.0 1.9 3.2 2.9 3.3 3.1 3.5 W W W W W W W W 266 Typical at TJ = 65 1.3 1.1 1.5 Typical 2, 3 Maximum 4 Unit
The estimated typical power dissipation for the MPC8347EA device is shown in Table 4.
1.6 1.4 1.9
1.8 1.6 2.1
W W W
1
The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD. For I/O power values, see Table 5. Typical power is based on a voltage of Vdd = 1.2 V, a junction temperature of TJ = 105C, and a Dhrystone benchmark application. 3 Thermal solutions may need to design to a value higher than typical power based on the end application, T target, and I/O A power. 4 Maximum Power is based on a voltage of Vdd = 1.2 V, worst case process, a junction temperature of T = 105C, and an J artificial smoke test.
2
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 11
Power Characteristics
Table 5 shows the estimated typical I/O power dissipation for MPC8347EA.
Table 5. MPC8347EA Typical I/O Power Dissipation
Interface Parameter DDR2 GVDD (1.8 V) 0.31 0.42 0.35 0.47 0.37 0.50 0.39 0.53 0.44 0.59 -- -- -- -- -- -- -- -- -- -- -- -- -- DDR1 GVDD (2.5 V) 0.42 0.55 0.5 0.66 0.54 0.7 0.58 0.76 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- OVDD (3.3 V) -- -- -- -- -- -- -- -- -- -- 0.04 0.07 0.34 0.27 0.17 0.14 0.11 -- -- -- 0.01 0.2 0.01 LVDD (3.3 V) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.01 0.06 -- -- -- -- LVDD (2.5 V) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.04 -- -- -- Unit Comments
200 MHz, 32 bits 200 MHz, 64 bits 266 MHz, 32 bits DDR I/O 65% utilization 2.5 V Rs = 20 Rt = 50 2 pair of clocks 266 MHz, 64 bits 300 MHz 1, 32 bits 300 MHz1, 64 bits 333 MHz1, 32 bits 333 MHz1, 64 bits 400MHz1, 32b 400MHz1, 64b 33 MHz, 32 bits PCI I/O load = 30 pf 66 MHz, 32 bits 167 Mhz, 32 bits 133 MHz, 32 bits Local Bus I/O Load = 25 pf 83 MHz, 32 bits 66 MHz, 32 bits 50 Mhz, 32 bits MII TSEC I/O Load = 25 pf GMII or TBI RGMII or RTBI 12 MHz USB 480 MHz Other I/O
1
W W W W W W W W
-- -- -- -- -- -- -- -- -- --
W W W W W W W W W W W W W
-- -- -- -- -- -- -- Multiply by number of interfaces used.
Multiply by 2 if using 2 ports. --
TBGA package only.
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Clock Input Timing
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4.1
Clock Input Timing
DC Electrical Characteristics
Table 6. CLKIN DC Electrical Characteristics
Parameter Condition -- -- 0V VIN OVDD 0V VIN 0.5 V or OVDD - 0.5 V VIN OVDD 0.5 V VIN OVDD - 0.5 V Symbol VIH VIL IIN IIN IIN Min 2.7 -0.3 -- -- -- Max OVDD+0.3 0.4 10 10 50 Unit V V A A A
This section provides the clock input DC and AC electrical characteristics for the MPC8347EA.
Table 7 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the MPC8347EA.
Input high voltage Input low voltage CLKIN Input current PCI_SYNC_IN Input current PCI_SYNC_IN Input current
4.2
AC Electrical Characteristics
The primary clock source for the MPC8347EA can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. Table 7 provides the clock input (CLKIN/PCI_CLK) AC timing specifications for the MPC8347EA.
Table 7. CLKIN AC Timing Specifications
Parameter/Condition CLKIN/PCI_CLK frequency CLKIN/PCI_CLK cycle time CLKIN/PCI_CLK rise and fall time CLKIN/PCI_CLK duty cycle CLKIN/PCI_CLK jitter Symbol fCLKIN tCLKIN tKH, tKL tKHK/tCLKIN -- Min -- 15 0.6 40 -- Typical -- -- 1.0 -- -- Max 66 -- 2.3 60 +/- 150 Unit MHz ns ns % ps Notes 1 -- 2 3 4, 5
Notes: 1. Caution: The system, core, USB, security, and TSEC must not exceed their respective maximum or minimum operating frequencies. 2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V. 3. Timing is guaranteed by design and characterization. 4. This represents the total input jitter--short term and long term--and is guaranteed by design. 5. The CLKIN/PCI_CLK driver's closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
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RESET Initialization
5
RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and electrical requirements of the MPC8347EA.
5.1
RESET DC Electrical Characteristics
Table 8. RESET Pins DC Electrical Characteristics
Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage Symbol VIH VIL IIN VOH VOL VOL IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2 mA 2.4 -- -- Condition Min 2.0 -0.3 Max OVDD+0.3 0.8 5 -- 0.5 0.4 Unit V V A V V V
Table 8 provides the DC electrical characteristics for the RESET pins of the MPC8347EA.
Notes: 1. This table applies for pins PORESET, HRESET, SRESET and QUIESCE. 2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins.
5.2
RESET AC Electrical Characteristics
Table 9. RESET Initialization Timing Specifications
Parameter/Condition Min 32 32 32 512 16 4 Max -- -- -- -- -- -- Unit tPCI_SYNC_IN tCLKIN tPCI_SYNC_IN tPCI_SYNC_IN tPCI_SYNC_IN tCLKIN Notes 1 2 1 1 1 2
Table 9 provides the reset initialization AC timing specifications of the MPC8347EA.
Required assertion time of HRESET or SRESET (input) to activate reset flow Required assertion time of PORESET with stable clock applied to CLKIN when the MPC8347EA is in PCI host mode Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN when the MPC8347EA is in PCI agent mode HRESET/SRESET assertion (output) HRESET negation to SRESET negation (output) Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8347EA is in PCI host mode Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8347EA is in PCI agent mode
4
--
tPCI_SYNC_IN
1
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RESET Initialization
Table 9. RESET Initialization Timing Specifications (continued)
Input hold time for POR configuration signals with respect to negation of HRESET Time for the MPC8347EA to turn off POR configuration signals with respect to the assertion of HRESET Time for the MPC8347EA to turn on POR configuration signals with respect to the negation of HRESET 0 -- 1 -- 4 -- ns ns tPCI_SYNC_IN 3 1, 3
Notes: 1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8349EA Integrated Host Processor Reference Manual. 2. tCLKIN is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349EA Integrated Host Processor Reference Manual. 3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
Table 10 lists the PLL and DLL lock times.
Table 10. PLL and DLL Lock Times
Parameter/Condition PLL lock times DLL lock times Min -- 7680 Max 100 122,880 Unit s csb_clk cycles 1, 2 Notes
Notes: 1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum. 2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 19, "Clocking."
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DDR and DDR2 SDRAM
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DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the MPC8347EA. Note that DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V. The AC electrical specifications are the same for DDR and DRR2 SDRAM. NOTE The information in this document is accurate for revision 3.0 silicon and later. For information on revision 1.1 silicon and earlier versions see the MPC8347E PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications. See Section 23.1, "Part Numbers Fully Addressed by this Document," for silicon revision level determination.
6.1
DDR and DDR2 SDRAM DC Electrical Characteristics
Table 11 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MPC8347EA when GVDD(typ) = 1.8 V.
Table 11. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (VOUT = 1.420 V) Output low current (VOUT = 0.280 V) Symbol GVDD MVREF VTT VIH VIL IOZ IOH IOL Min 1.71 0.49 x GVDD MVREF - 0.04 MVREF+ 0.125 -0.3 -9.9 -13.4 13.4 Max 1.89 0.51 x GVDD MVREF + 0.04 GVDD + 0.3 MVREF - 0.125 9.9 -- -- Unit V V V V V A mA mA 4 Notes 1 2 3
Notes: 1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times. 2. MVREF is expected to equal 0.5 x GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREF cannot exceed 2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to equal MVREF. This rail should track variations in the DC level of MVREF. 4. Output leakage is measured with all outputs disabled, 0 V VOUT GVDD.
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DDR and DDR2 SDRAM
Table 12 provides the DDR2 capacitance when GVDD(typ) = 1.8 V.
Table 12. DDR2 SDRAM Capacitance for GVDD(typ)=1.8 V
Parameter/Condition Input/output capacitance: DQ, DQS, DQS Delta input/output capacitance: DQ, DQS, DQS Symbol CIO CDIO Min 6 -- Max 8 0.5 Unit pF pF Notes 1 1
Note: 1. This parameter is sampled. GVDD = 1.8 V 0.090 V, f = 1 MHz, TA = 25C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
Table 13 provides the recommended operating conditions for the DDR SDRAM component(s) when GVDD(typ) = 2.5 V.
Table 13. DDR SDRAM DC Electrical Characteristics for GVDD (typ) = 2.5 V
Parameter/Condition I/O supply voltage I/O reference voltage I/O termination voltage Input high voltage Input low voltage Output leakage current Output high current (VOUT = 1.95 V) Output low current (VOUT = 0.35 V) Symbol GVDD MVREF VTT VIH VIL IOZ IOH IOL Min 2.375 0.49 x GVDD MVREF - 0.04 MVREF + 0.18 -0.3 -9.9 -15.2 15.2 Max 2.625 0.51 x GVDD MVREF + 0.04 GVDD + 0.3 MVREF- 0.18 -9.9 -- -- Unit V V V V V A mA mA 4 Notes 1 2 3
Notes: 1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times. 2. MVREF is expected to be equal to 0.5 x GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise on MVREF may not exceed 2% of the DC value. 3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MVREF. This rail should track variations in the DC level of MVREF. 4. Output leakage is measured with all outputs disabled, 0 V VOUT GVDD.
Table 14 provides the DDR capacitance when GVDD (typ)=2.5 V.
Table 14. DDR SDRAM Capacitance for GVDD (typ) = 2.5 V
Parameter/Condition Input/output capacitance: DQ, DQS Delta input/output capacitance: DQ, DQS Symbol CIO CDIO Min 6 -- Max 8 0.5 Unit pF pF Notes 1 1
Note: 1. This parameter is sampled. GVDD = 2.5 V 0.125 V, f = 1 MHz, TA = 25C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
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DDR and DDR2 SDRAM
Table 15 provides the current draw characteristics for MVREF.
Table 15. Current Draw Characteristics for MVREF
Parameter / Condition Current draw for MVREF Symbol IMVREF Min -- Max 500 Unit A Note 1
1. The voltage regulator for MVREF must supply up to 500 A current.
6.2
DDR and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR and DDR2 SDRAM interface.
6.2.1
DDR and DDR2 SDRAM Input AC Timing Specifications
Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
Table 16 provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ)=1.8 V.
At recommended operating conditions with GVDD of 1.8 5%.
Parameter AC input low voltage AC input high voltage
Symbol VIL VIH
Min -- MVREF + 0.25
Max MVREF - 0.25 --
Unit V V
Notes
Table 17 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ)=2.5 V.
Table 17. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
At recommended operating conditions with GVDD of 2.5 5%.
Parameter AC input low voltage AC input high voltage
Symbol VIL VIH
Min -- MVREF + 0.31
Max MVREF - 0.31 --
Unit V V
Notes
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DDR and DDR2 SDRAM
Table 18 provides the input AC timing specifications for the DDR SDRAM interface.
Table 18. DDR and DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of (1.8 V or 2.5 V) 5%.
Parameter Controller Skew for MDQS--MDQ/MECC/MDM 400 MHz 333 MHz 266 MHz 200 MHz
Symbol tCISKEW
Min
Max
Unit ps
Notes 1 2 3 3 3
-600 -750 -750 -750
600 750 750 750
Note: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that will be captured with MDQS[n]. This should be subtracted from the total timing budget. 2. This specification applies only to the DDR2 interface. 3. This specification applies only to the DDR interface.
6.2.2
DDR and DDR2 SDRAM Output AC Timing Specifications
Table 19. DDR and DDR2 SDRAM Output AC Timing Specifications
Table 19 shows the DDR and DDR2 output AC timing specifications.
At recommended operating conditions with GVDD of (1.8 V or 2.5 V) 5%.
Parameter MCK[n] cycle time, (MCK[n]/MCK[n] crossing) ADDR/CMD/MODT output setup with respect to MCK 400 MHz 333 MHz 266 MHz 200 MHz ADDR/CMD/MODT output hold with respect to MCK 400 MHz 333 MHz 266 MHz 200 MHz MCS(n) output setup with respect to MCK 400 MHz 333 MHz 266 MHz 200 MHz
Symbol 1 tMCK tDDKHAS
Min 5
Max 10
Unit ns ns
Notes 2 3
1.95 2.40 3.15 4.20 tDDKHAX 1.95 2.40 3.15 4.20 tDDKHCS 1.95 2.40 3.15 4.20
-- -- -- -- ns -- -- -- -- ns -- -- -- -- 3 3
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DDR and DDR2 SDRAM
Table 19. DDR and DDR2 SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions with GVDD of (1.8 V or 2.5 V) 5%.
Parameter MCS(n) output hold with respect to MCK 400 MHz 333 MHz 266 MHz 200 MHz MCK to MDQS Skew MDQ/MECC/MDM output setup with respect to MDQS 400 MHz 333 MHz 266 MHz 200 MHz MDQ/MECC/MDM output hold with respect to MDQS 400 MHz 333 MHz 266 MHz 200 MHz MDQS preamble start
Symbol 1 tDDKHCX
Min
Max
Unit ns
Notes 3
1.95 2.40 3.15 4.20 tDDKHMH tDDKHDS, tDDKLDS 700 900 1100 1200 tDDKHDX, tDDKLDX 700 900 1100 1200 tDDKHMP -0.5 x tMCK - 0.6 -0.6
-- -- -- -- 0.6 ns ps -- -- -- -- ps -- -- -- -- -0.5 x tMCK +0.6 ns 6 5 4 5
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DDR and DDR2 SDRAM
Table 19. DDR and DDR2 SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions with GVDD of (1.8 V or 2.5 V) 5%.
Parameter MDQS epilogue end
Symbol 1 tDDKHME
Min -0.6
Max 0.6
Unit ns
Notes 6
Note: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output goes invalid (AX or DX). For example, tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are set up (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time. 2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V. 3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the ADDR/CMD setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks by 1/2 applied cycle. 4. tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of the DQSS override bits in the TIMING_CFG_2 registerand is typically set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these two parameters are set to the same adjustment value. See the MPC8349EA PowerQUICC II Pro Integrated Processor Reference Manual for the timing modifications enabled by use of these bits. 5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC (MECC), or data mask (MDM). The data strobe should be centered inside the data eye at the pins of the microprocessor. 6. All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that tDDKHMP follows the symbol conventions described in note 1.
Figure 4 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).
MCK[n] MCK[n] tMCK tDDKHMHmax) = 0.6 ns
MDQS tDDKHMH(min) = -0.6 ns
MDQS
Figure 4. Timing Diagram for tDDKHMH
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 21
DDR and DDR2 SDRAM
Figure 5 shows the DDR SDRAM output timing diagram.
MCK[n] MCK[n] tMCK tDDKHAS ,tDDKHCS tDDKHAX ,tDDKHCX ADDR/CMD/MODT Write A0 tDDKHMP tDDKHMH MDQS[n] tDDKHDS tDDKLDS MDQ[x] tDDKHDX D0 D1 tDDKLDX tDDKHME NOOP
Figure 5. DDR SDRAM Output Timing Diagram
Figure 6 provides the AC test load for the DDR bus.
Output Z0 = 50 GVDD/2
RL = 50
Figure 6. DDR AC Test Load
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DUART
7
DUART
This section describes the DC and AC electrical specifications for the DUART interface of the MPC8347EA.
7.1
DUART DC Electrical Characteristics
Table 20. DUART DC Electrical Characteristics
Parameter High-level input voltage Low-level input voltage Input current (0.8 V VIN 2 V) High-level output voltage, IOH = -100 A Low-level output voltage, IOL = 100 A Symbol VIH VIL IIN VOH VOL Min 2 -0.3 -- Max OVDD + 0.3 0.8 +/- 5 Unit V V A
Table 20 provides the DC electrical characteristics for the DUART interface of the MPC8347EA.
OVDD - 0.2 --
-- 0.2
V V
Note: 1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
7.2
DUART AC Electrical Specifications
Table 21. DUART AC Timing Specifications
Parameter Value 256 > 1,000,000 16 Unit baud baud -- 1 2 Notes
Table 21 provides the AC timing parameters for the DUART interface of the MPC8347EA.
Minimum baud rate Maximum baud rate Oversample rate
Notes: 1. Actual attainable baud rate will be limited by the latency of interrupt processing. 2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each 16th sample.
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Ethernet: Three-Speed Ethernet, MII Management
8
Ethernet: Three-Speed Ethernet, MII Management
This section provides the AC and DC electrical characteristics for three-speeds (10/100/1000 Mbps) and MII management.
8.1
Three-Speed Ethernet Controller (TSEC) --GMII/MII/TBI/RGMII/RTBI Electrical Characteristics
The electrical characteristics specified here apply to the gigabit media independent interface (GMII), the media independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface (RGMII), and reduced ten-bit interface (RTBI) signals except management data input/output (MDIO) and management data clock (MDC). The MII, GMII, and TBI interfaces are defined for 3.3 V, and the RGMII and RTBI interfaces can operate at 3.3 or 2.5 V. The RGMII and RTBI interfaces follow the Hewlett-Packard Reduced Pin-Count Interface for Gigabit Ethernet Physical Layer Device Specification, Version 1.2a (9/22/2000). The electrical characteristics for MDIO and MDC are specified in Section 8.3, "Ethernet Management Interface Electrical Characteristics."
8.1.1
TSEC DC Electrical Characteristics
All GMII, MII, TBI, RGMII, and RTBI drivers and receivers comply with the DC parametric attributes specified in Table 22 and Table 23. The potential applied to the input of a GMII, MII, TBI, RGMII, or RTBI receiver may exceed the potential of the receiver power supply (that is, a RGMII driver powered from a 3.6 V supply driving VOH into a RGMII receiver powered from a 2.5-V supply). Tolerance for dissimilar RGMII driver and receiver supply potentials is implicit in these specifications.The RGMII and RTBI signals are based on a 2.5 V CMOS interface voltage as defined by JEDEC EIA/JESD8-5.
Table 22. GMII/TBI and MII DC Electrical Characteristics
Parameter Supply voltage 3.3 V Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Symbol LVDD 2 VOH VOL VIH VIL IIH IIL IOH = -4.0 mA IOL = 4.0 mA -- -- VIN 1 = LVDD VIN = GND
1
Conditions -- LVDD = Min LVDD = Min -- --
Min 2.97 2.40 GND 2.0 -0.3 -- -600
Max 3.63 LVDD + 0.3 0.50 LVDD + 0.3 0.90 40 --
Unit V V V V V A A
Note: 1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2. 2. GMII/MII pins not needed for RGMII or RTBI operation are powered by the OVDD supply.
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Ethernet: Three-Speed Ethernet, MII Management
Table 23. RGMII/RTBI (When Operating at 2.5 V), DC Electrical Characteristics
Parameters Supply voltage 2.5 V Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Symbol LVDD VOH VOL VIH VIL IIH IIL IOH = -1.0 mA IOL = 1.0 mA -- -- Conditions -- LVDD = Min LVDD = Min LVDD = Min LVDD =Min VIN 1 = LVDD VIN 1 = GND Min 2.37 2.00 GND - 0.3 1.7 -0.3 -- -15 Max 2.63 LVDD + 0.3 0.40 LVDD + 0.3 0.70 10 -- Unit V V V V V A A
Note: 1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
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Ethernet: Three-Speed Ethernet, MII Management
8.2
GMII, MII, TBI, RGMII, and RTBI AC Timing Specifications
The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section.
8.2.1
GMII Timing Specifications
This section describes the GMII transmit and receive AC timing specifications.
8.2.1.1
GMII Transmit AC Timing Specifications
Table 24. GMII Transmit AC Timing Specifications
Table 24 provides the GMII transmit AC timing specifications.
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
Parameter/Condition GTX_CLK clock period GTX_CLK duty cycle GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay GTX_CLK clock rise time, VIL(min) to VIH(max) GTX_CLK clock fall time, VIH(max) to VIL(min) GTX_CLK125 clock period GTX_CLK125 reference clock duty cycle measured at LVDD/ 2
Symbol 1 tGTX tGTXH/tGTX tGTKHDX tGTXR tGTXF tG125
2
Min -- 43.75 0.5 -- -- -- 45
Typ 8.0 -- -- -- -- 8.0 --
Max -- 56.25 5.0 1.0 1.0 -- 55
Unit ns % ns ns ns ns %
tG125H/tG125
Notes: 1. The symbols for timing specifications follow the pattern t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This symbol represents the external GTX_CLK125 signal and does not follow the original symbol naming convention.
Figure 7 shows the GMII transmit AC timing diagram.
tGTX GTX_CLK tGTXH TXD[7:0] TX_EN TX_ER tGTKHDX tGTXF tGTXR
Figure 7. GMII Transmit AC Timing Diagram
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Ethernet: Three-Speed Ethernet, MII Management
8.2.1.2
GMII Receive AC Timing Specifications
Table 25. GMII Receive AC Timing Specifications
Table 25 provides the GMII receive AC timing specifications.
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
Parameter/Condition RX_CLK clock period RX_CLK duty cycle RXD[7:0], RX_DV, RX_ER setup time to RX_CLK RXD[7:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise, VIL(min) to VIH(max) RX_CLK clock fall time, VIH(max) to VIL(min)
Symbol 1 tGRX tGRXH/tGRX tGRDVKH tGRDXKH tGRXR tGRXF
Min -- 40 2.0 0.5 -- --
Typ 8.0 -- -- -- -- --
Max -- 60 -- -- 1.0 1.0
Unit ns % ns ns ns ns
Note: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 8 shows the GMII receive AC timing diagram.
G
tGRX RX_CLK tGRXH RXD[7:0] RX_DV RX_ER tGRDXKH tGRDVKH tGRXF
tGRXR
Figure 8. GMII Receive AC Timing Diagram
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Ethernet: Three-Speed Ethernet, MII Management
8.2.2
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.2.1
MII Transmit AC Timing Specifications
Table 26. MII Transmit AC Timing Specifications
Table 26 provides the MII transmit AC timing specifications.
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
Parameter/Condition TX_CLK clock period 10 Mbps TX_CLK clock period 100 Mbps TX_CLK duty cycle TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay TX_CLK data clock rise VIL(min) to VIH(max) TX_CLK data clock fall VIH(max) to VIL(min)
Symbol 1 tMTX tMTX tMTXH/tMTX tMTKHDX tMTXR tMTXF
Min -- -- 35 1 1.0 1.0
Typ 400 40 -- 5 -- --
Max -- -- 65 15 4.0 4.0
Unit ns ns % ns ns ns
Note: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). In general, the clock reference symbol is based on two to three letters representing the clock of a particular function. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 9 shows the MII transmit AC timing diagram.
tMTX TX_CLK tMTXH TXD[3:0] TX_EN TX_ER tMTKHDX tMTXF tMTXR
Figure 9. MII Transmit AC Timing Diagram
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Ethernet: Three-Speed Ethernet, MII Management
8.2.2.2
MII Receive AC Timing Specifications
Table 27. MII Receive AC Timing Specifications
Table 27 provides the MII receive AC timing specifications.
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
Parameter/Condition RX_CLK clock period 10 Mbps RX_CLK clock period 100 Mbps RX_CLK duty cycle RXD[3:0], RX_DV, RX_ER setup time to RX_CLK RXD[3:0], RX_DV, RX_ER hold time to RX_CLK RX_CLK clock rise VIL(min) to VIH(max) RX_CLK clock fall time VIH(max) to VIL(min)
Symbol 1 tMRX tMRX tMRXH/tMRX tMRDVKH tMRDXKH tMRXR tMRXF
Min -- -- 35 10.0 10.0 1.0 1.0
Typ 400 40 -- -- -- -- --
Max -- -- 65 -- -- 4.0 4.0
Unit ns ns % ns ns ns ns
Note: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. In general, the clock reference symbol is based on three letters representing the clock of a particular functionl. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
Figure 10 provides the AC test load for TSEC.
Output Z0 = 50 RL = 50 LVDD/2
Figure 10. TSEC AC Test Load
Figure 11 shows the MII receive AC timing diagram.
tMRX RX_CLK tMRXH RXD[3:0] RX_DV RX_ER tMRDVKH tMRDXKH tMRXF Valid Data tMRXR
Figure 11. MII Receive AC Timing Diagram
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Ethernet: Three-Speed Ethernet, MII Management
8.2.3
TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
8.2.3.1
TBI Transmit AC Timing Specifications
Table 28. TBI Transmit AC Timing Specifications
Table 28 provides the TBI transmit AC timing specifications.
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
Parameter/Condition GTX_CLK clock period GTX_CLK duty cycle GTX_CLK to TBI data TXD[7:0], TX_ER, TX_EN delay GTX_CLK clock rise, VIL(min) to VIH(max) GTX_CLK clock fall time, VIH(max) to VIL(min) GTX_CLK125 reference clock period GTX_CLK125 reference clock duty cycle
Symbol 1 tTTX tTTXH/tTTX tTTKHDX tTTXR tTTXF tG125
2
Min -- 40 1.0 -- -- -- 45
Typ 8.0 -- -- -- -- 8.0 --
Max -- 60 5.0 1.0 1.0 -- 55
Unit ns % ns ns ns ns ns
tG125H/tG125
Notes: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state )(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTTKHDV symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the valid state (V) or setup time. Also, tTTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from tTTX (K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of tTTX represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This symbol represents the external GTX_CLK125 and does not follow the original symbol naming convention
Figure 12 shows the TBI transmit AC timing diagram.
tTTX GTX_CLK tTTXH TXD[7:0] TX_EN TX_ER tTTKHDX tTTXF tTTXR
Figure 12. TBI Transmit AC Timing Diagram
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Ethernet: Three-Speed Ethernet, MII Management
8.2.3.2
TBI Receive AC Timing Specifications
Table 29. TBI Receive AC Timing Specifications
Table 29 provides the TBI receive AC timing specifications.
At recommended operating conditions with LVDD / OVDD of 3.3 V 10%.
Parameter/Condition PMA_RX_CLK clock period PMA_RX_CLK skew RX_CLK duty cycle RXD[7:0], RX_DV, RX_ER (RCG[9:0]) setup time to rising PMA_RX_CLK RXD[7:0], RX_DV, RX_ER (RCG[9:0]) hold time to rising PMA_RX_CLK RX_CLK clock rise time VIL(min) to VIH(max) RX_CLK clock fall time VIH(max) to VIL(min)
Symbol 1 tTRX tSKTRX tTRXH/tTRX tTRDVKH 2 tTRDXKH 2 tTRXR tTRXF
Min
Typ 16.0
Max
Unit ns
7.5 40 2.5 1.5 0.7 0.7
-- -- -- -- -- --
8.5 60 -- -- 2.4 2.4
ns % ns ns ns ns
Note: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tTRDVKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the tTRX clock reference (K) going to the high (H) state or setup time. Also, tTRDXKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) went invalid (X) relative to the tTRX clock reference (K) going to the high (H) state. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of tTRX represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript SK followed by the clock that is being skewed (TRX). 2. Setup and hold time of even numbered RCG are measured from the riding edge of PMA_RX_CLK1. Setup and hold times of odd-numbered RCG are measured from the riding edge of PMA_RX_CLK0.
Figure 13 shows the TBI receive AC timing diagram.
tTRX PMA_RX_CLK1 tTRXH RCG[9:0] tTRDVKH tSKTRX PMA_RX_CLK0 tTRXH tTRDVKH tTRDXKH tTRDXKH tTRXF Even RCG Odd RCG tTRXR
Figure 13. TBI Receive AC Timing Diagram
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Ethernet: Three-Speed Ethernet, MII Management
8.2.4
RGMII and RTBI AC Timing Specifications
Table 30. RGMII and RTBI AC Timing Specifications
Table 30 presents the RGMII and RTBI AC timing specifications.
At recommended operating conditions with LVDD of 2.5 V 5%.
Parameter/Condition Data to clock output skew (at transmitter) Data to clock input skew (at receiver) Clock cycle duration
3 4, 5 3, 5 2
Symbol 1 tSKRGT tSKRGT tRGT tRGTH/tRGT tRGTH/tRGT tRGTR tRGTF tG12
6
Min -0.5 1.0 7.2 45 40 -- -- -- 47
Typ -- -- 8.0 50 50 -- -- 8.0 --
Max 0.5 2.8 8.8 55 60 0.75 0.75 -- 53
Unit ns ns ns % % ns ns ns %
Duty cycle for 1000Base-T
Duty cycle for 10BASE-T and 100BASE-TX Rise time (20%-80%) Fall time (20%-80%) GTX_CLK125 reference clock period GTX_CLK125 reference clock duty cycle
tG125H/tG125
Notes: 1. In general, the clock reference symbol for this section is based on the symbols RGT to represent RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Also, the notation for rise (R) and fall (F) times follows the clock symbol. For symbols representing skews, the subscript is SK followed by the clock being skewed (RGT). 2. This implies that PC board design requires clocks to be routed so that an additional trace delay of greater than 1.5 ns is added to the associated clock signal. 3. For 10 and 100 Mbps, tRGT scales to 400 ns 40 ns and 40 ns 4 ns, respectively. 4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned. 5. Duty cycle reference is LVdd/2. 6. This symbol represents the external GTX_CLK125 and does not follow the original symbol naming convention.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 32 Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
Figure 14 shows the RBMII and RTBI AC timing and multiplexing diagrams.
tRGT tRGTH GTX_CLK (At Transmitter) tSKRGT TXD[8:5][3:0] TXD[7:4][3:0] TXD[3:0] TXD[8:5] TXD[7:4] TXD[9] TXERR tSKRGT TX_CLK (At PHY)
TX_CTL
TXD[4] TXEN
RXD[8:5][3:0] RXD[7:4][3:0]
RXD[8:5] RXD[3:0] RXD[7:4] tSKRGT RXD[4] RXDV RXD[9] RXERR tSKRGT
RX_CTL
RX_CLK (At PHY)
Figure 14. RGMII and RTBI AC Timing and Multiplexing Diagrams
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 33
8.3
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to the MII management interface signals management data input/output (MDIO) and management data clock (MDC). The electrical characteristics for GMII, RGMII, TBI and RTBI are specified in Section 8.1, "Three-Speed Ethernet Controller (TSEC) --GMII/MII/TBI/RGMII/RTBI Electrical Characteristics."
8.3.1
MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 2.5 V or 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in Table 31 and Table 32.
Table 31. MII Management DC Electrical Characteristics Powered at 2.5 V
Parameter Supply voltage (2.5 V) Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Symbol LVDD VOH VOL VIH VIL IIH IIL IOH = -1.0 mA IOL = 1.0 mA -- --
1
Conditions -- LVDD = Min LVDD = Min LVDD = Min LVDD = Min VIN = LVDD VIN = LVDD
Min 2.37 2.00 GND - 0.3 1.7 -0.3 -- -15
Max 2.63 LVDD + 0.3 0.40 -- 0.70 10 --
Unit V V V V V A A
Note: 1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
Table 32. MII Management DC Electrical Characteristics Powered at 3.3 V
Parameter Supply voltage (3.3 V) Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Symbol LVDD VOH VOL VIH VIL IIH IIL LVDD = Max LVDD = Max IOH = -1.0 mA IOL = 1.0 mA -- -- VIN 1 = 2.1 V VIN = 0.5 V Conditions -- LVDD = Min LVDD = Min Min 2.97 2.10 GND 2.00 -- -- -600 Max 3.63 LVDD + 0.3 0.50 -- 0.80 40 -- Unit V V V V V A A
Note: 1. The symbol VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 34 Freescale Semiconductor
8.3.2
MII Management AC Electrical Specifications
Table 33. MII Management AC Timing Specifications
Table 33 provides the MII management AC timing specifications.
At recommended operating conditions with LVDD is 3.3 V 10% or 2.5 V 5%
Parameter/Condition MDC frequency MDC period MDC clock pulse width high MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time MDC fall time
Symbol 1 fMDC tMDC tMDCH tMDKHDX tMDDVKH tMDDXKH tMDCR tMDHF
Min -- -- 32 10 5 0 -- --
Typ 2.5 400 -- -- -- -- -- --
Max -- -- -- 170 -- -- 10 10
Unit MHz ns ns ns ns ns ns ns
Notes 2
3
Notes: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is 8.3 MHz and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum frequency is 1.7 MHz). 3. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the delay is 70 ns and for a csb_clk of 333 MHz, the delay is 58 ns).
Figure 15 shows the MII management AC timing diagram.
tMDC MDC tMDCH MDIO (Input) tMDDVKH tMDDXKH MDIO (Output) tMDKHDX tMDCF tMDCR
Figure 15. MII Management Interface Timing Diagram
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 35
USB
9
9.1
USB
USB DC Electrical Characteristics
Table 34. USB DC Electrical Characteristics
Parameter High-level input voltage Low-level input voltage Input current High-level output voltage, IOH = -100 A Low-level output voltage, IOL = 100 A Symbol VIH VIL IIN VOH VOL Min 2 -0.3 -- OVDD - 0.2 -- Max OVDD + 0.3 0.8 5 -- 0.2 Unit V V A V V
This section provides the AC and DC electrical specifications for the USB interface of the MPC8347EA.
Table 34 provides the DC electrical characteristics for the USB interface.
Note: 1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
9.2
USB AC Electrical Specifications
Table 35. USB General Timing Parameters
Parameter Symbol 1 tUSCK tUSIVKH tUSIXKH tUSKHOV tUSKHOX Min 15 4 1 -- 2 Max -- -- -- 7 -- Unit ns ns ns ns ns Notes
Table 35 describes the general timing parameters of the USB interface of the MPC8347EA.
usb clock cycle time Input setup to usb clock - all inputs input hold to usb clock - all inputs usb clock to output valid - all outputs Output hold from usb clock - all outputs
Notes: 1. The symbols for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes usb timing (US) for the input (I) to go invalid (X) with respect to the time the usb clock reference (K) goes high (H). Also, tUSKHOX symbolizes USB timing (US) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to USB clock. 3. All signals are measured from OVDD/2 of the rising edge of the USB clock to 0.4 x OVDD of the signal in question for 3.3 V signaling levels. 4. Input timings are measured at the pin. 5. For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 36 Freescale Semiconductor
USB
Figure 16 and Figure 17 provide the AC test load and signals for the USB, respectively.
Output Z0 = 50 RL = 50 OVDD/2
Figure 16. USB AC Test Load
USB0_CLK/USB1_CLK/DR_CLK tUSIVKH Input Signals tUSIXKH
tUSKHOV Output Signals:
tUSKHOX
Figure 17. USB Signals
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 37
Local Bus
10 Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the MPC8347EA.
10.1
Local Bus DC Electrical Characteristics
Table 36. Local Bus DC Electrical Characteristics
Parameter High-level input voltage Low-level input voltage Input current High-level output voltage, IOH = -100 A Low-level output voltage, IOL = 100 A Symbol VIH VIL IIN VOH VOL Min 2 -0.3 -- OVDD - 0.2 -- Max OVDD + 0.3 0.8 5 -- 0.2 Unit V V A V V
Table 36 provides the DC electrical characteristics for the local bus interface.
10.2
Local Bus AC Electrical Specification
Table 37 and Table 38 describe the general timing parameters of the local bus interface of the MPC8347EA.
Table 37. Local Bus General Timing Parameters--DLL on
Parameter Local bus cycle time Input setup to local bus clock (except LUPWAIT) LUPWAIT input setup to local bus clock Input hold from local bus clock (except LUPWAIT) LUPWAIT Input hold from local bus clock LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) Local bus clock to LALE rise Local bus clock to output valid (except LAD/LDP and LALE) Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Output hold from local bus clock (except LAD/LDP and LALE) Output hold from local bus clock for LAD/LDP Symbol 1 tLBK tLBIVKH1 tLBIVKH2 tLBIXKH1 tLBIXKH2 tLBOTOT1 tLBOTOT2 tLBOTOT3 tLBKHLR tLBKHOV1 tLBKHOV2 tLBKHOV3 tLBKHOX1 tLBKHOX2 Min 7.5 1.5 2.2 1.0 1.0 1.5 3 2.5 -- -- -- -- 1 1 Max -- -- -- -- -- -- -- -- 4.5 4.5 4.5 4.5 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 3 3 3 3 Notes 2 3, 4 3, 4 3, 4 3, 4 5 6 7
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 38 Freescale Semiconductor
Local Bus
Table 37. Local Bus General Timing Parameters--DLL on (continued)
Parameter Local bus clock to output high impedance for LAD/LDP Symbol 1 tLBKHOZ Min -- Max 3.8 Unit ns Notes
Notes: 1. The symbols for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to the rising edge of LSYNC_IN. 3. All signals are measured from OVDD/2 of the rising edge of LSYNC_IN to 0.4 x OVDD of the signal in question for 3.3 V signaling levels. 4. Input timings are measured at the pin. 5.tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on the LALE output pin is at least 10 pF less than the load on the LAD output pins. 6.tLBOTOT2 should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the load on the LAD output pins. 7.tLBOTOT3 should be used when RCWH[LALE] is set and when the load on the LALE output pin equals the load on the LAD output pins. 8. For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 39
Local Bus
Table 38. Local Bus General Timing Parameters--DLL Bypass
Parameter Local bus cycle time Input setup to local bus clock Input hold from local bus clock LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) LALE output fall to LAD output transition (LATCH hold time) Local bus clock to output valid Local bus clock to output high impedance for LAD/LDP Symbol 1 tLBK tLBIVKH tLBIXKH tLBOTOT1 tLBOTOT2 tLBOTOT3 tLBKHOV tLBKHOZ Min 15 7 1.0 1.5 3 2.5 -- -- Max -- -- -- -- -- -- 3 4 Unit ns ns ns ns ns ns ns ns Notes 2 3, 4 3, 4 5 6 7 3
Notes: 1. The symbols for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time. 2. All timings are in reference to the falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or the rising edge of LCLK0 (for all other inputs). 3. All signals are measured from OVDD/2 of the rising/falling edge of LCLK0 to 0.4 x OVDD of the signal in question for 3.3 V signaling levels. 4. Input timings are measured at the pin. 5.tLBOTOT1 should be used when RCWH[LALE] is not set and when the load on the LALE output pin is at least 10 pF less than the load on the LAD output pins. 6.tLBOTOT2 should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the load on the LAD output pins.the 7.tLBOTOT3 should be used when RCWH[LALE] is set and when the load on the LALE output pin equals to the load on the LAD output pins. 8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 9. DLL bypass mode is not recommended for use at frequencies above 66 MHz.
Figure 18 provides the AC test load for the local bus.
Output Z0 = 50 RL = 50 OVDD/2
Figure 18. Local Bus C Test Load
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 40 Freescale Semiconductor
Local Bus
Figure 19 through Figure 24 show the local bus signals.
LSYNC_IN tLBIVKH Input Signals: LAD[0:31]/LDP[0:3] tLBIXKH Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE/ Output (Data) Signals: LAD[0:31]/LDP[0:3] tLBKHOV Output (Address) Signal: LAD[0:31] tLBKHLR LALE tLBOTOT tLBKHOZ tLBKHOX tLBKHOV tLBKHOX tLBIXKH
tLBKHOV
tLBKHOZ tLBKHOX
Figure 19. Local Bus Signals, Nonspecial Signals Only (DLL Enabled)
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 41
Local Bus
LCLK[n] tLBIVKH Input Signals: LAD[0:31]/LDP[0:3] tLBIVKH Input Signal: LGTA tLBIXKH Output Signals: LSDA10/LSDWE/LSDRAS/ LSDCAS/LSDDQM[0:3] LA[27:31]/LBCTL/LBCKE/LOE/ Output Signals: LAD[0:31]/LDP[0:3] tLBOTOT LALE tLBKHOV tLBIXKH tLBIXKH
tLBKHOV
tLBKHOZ
Figure 20. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode)
LSYNC_IN
T1 T3 tLBKHOV1 GPCM Mode Output Signals: LCS[0:7]/LWE tLBIVKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBKHOV1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] tLBKHOZ1 tLBIXKH1 tLBIXKH2 tLBKHOZ1
Figure 21. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Enabled)
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 42 Freescale Semiconductor
Local Bus
LCLK
T1 T3 tLBKHOV GPCM Mode Output Signals: LCS[0:7]/LWE tLBIVKH UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) tLBKHOV UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] tLBIVKH tLBIXKH tLBIXKH tLBKHOZ
tLBKHOZ
Figure 22. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Bypass Mode)
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 43
Local Bus
LCLK
T1 T2 T3 T4 tLBKHOV GPCM Mode Output Signals: LCS[0:7]/LWE tLBIVKH UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] (DLL Bypass Mode) tLBKHOV UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] tLBIVKH tLBIXKH tLBIXKH tLBKHOZ
tLBKHOZ
Figure 23. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Bypass Mode)
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 44 Freescale Semiconductor
Local Bus
LSYNC_IN
T1 T2 T3 T4 tLBKHOV1 GPCM Mode Output Signals: LCS[0:7]/LWE tLBIVKH2 UPM Mode Input Signal: LUPWAIT tLBIVKH1 Input Signals: LAD[0:31]/LDP[0:3] tLBKHOV1 UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] tLBKHOZ1 tLBIXKH1 tLBIXKH2 tLBKHOZ1
Figure 24. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (DLL Enabled)
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 45
JTAG
11 JTAG
This section describes the DC and AC electrical specifications for the IEEE Std. 1149.1 (JTAG) interface of the MPC8347EA
11.1
JTAG DC Electrical Characteristics
Table 39 provides the DC electrical characteristics for the IEEE Std. 1149.1 (JTAG) interface of the MPC8347EA.
Table 39. JTAG interface DC Electrical Characteristics
Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage Symbol VIH VIL IIN VOH VOL VOL IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2 mA 2.4 -- -- Condition Min Max Unit V V A V V V
OVDD - 0.3 OVDD + 0.3 -0.3 0.8 5 -- 0.5 0.4
11.2
JTAG AC Timing Specifications
This section describes the AC electrical specifications for the IEEE Std. 1149.1TM (JTAG) interface of the MPC8347EA. Table 40 provides the JTAG AC timing specifications as defined in Figure 26 through Figure 29.
Table 40. JTAG AC Timing Specifications (Independent of CLKIN) 1
At recommended operating conditions (see Table 2).
Parameter JTAG external clock frequency of operation JTAG external clock cycle time JTAG external clock pulse width measured at 1.4 V JTAG external clock rise and fall times TRST assert time Input setup times: Boundary-scan data TMS, TDI Input hold times: Boundary-scan data TMS, TDI Valid times: Boundary-scan data TDO
Symbol 2 fJTG t JTG tJTKHKL tJTGR & tJTGF tTRST tJTDVKH tJTIVKH tJTDXKH tJTIXKH tJTKLDV tJTKLOV
Min 0 30 15 0 25 4 4
Max 33.3 -- -- 2 -- -- --
Unit MHz ns ns ns ns ns
Notes
3 4
ns 10 10 -- -- ns 2 2 11 11 5 4
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 46 Freescale Semiconductor
JTAG
Table 40. JTAG AC Timing Specifications (Independent of CLKIN) 1 (continued)
At recommended operating conditions (see Table 2).
Parameter Output hold times: Boundary-scan data TDO JTAG external clock to output high impedance: Boundary-scan data TDO
Symbol 2
Min
Max
Unit ns
Notes
tJTKLDX tJTKLOX tJTKLDZ tJTKLOZ
2 2
-- -- ns
5
2 2
19 9
5, 6
Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50 load (see Figure 25). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. In general, the clock reference symbol is based on three letters representing the clock of a particular function. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only. 4. Non-JTAG signal input timing with respect to tTCLK. 5. Non-JTAG signal output timing with respect to tTCLK. 6. Guaranteed by design and characterization.
Figure 25 provides the AC test load for TDO and the boundary-scan outputs of the MPC8347EA.
Output Z0 = 50 RL = 50 OVDD/2
Figure 25. AC Test Load for the JTAG Interface
Figure 26 provides the JTAG clock input timing diagram.
JTAG External Clock VM tJTKHKL tJTG VM = Midpoint Voltage (OVDD/2) VM VM tJTGR tJTGF
Figure 26. JTAG Clock Input Timing Diagram
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 47
JTAG
Figure 27 provides the TRST timing diagram.
TRST VM tTRST VM = Midpoint Voltage (OVDD/2) VM
Figure 27. TRST Timing Diagram
Figure 28 provides the boundary-scan timing diagram.
JTAG External Clock VM tJTDVKH tJTDXKH Boundary Data Inputs tJTKLDV tJTKLDX Boundary Data Outputs tJTKLDZ Boundary Data Outputs Output Data Valid VM = Midpoint Voltage (OVDD/2) Output Data Valid Input Data Valid VM
Figure 28. Boundary-Scan Timing Diagram
Figure 29 provides the test access port timing diagram.
JTAG External Clock VM tJTIVKH tJTIXKH TDI, TMS tJTKLOV tJTKLOX TDO tJTKLOZ TDO Output Data Valid VM = Midpoint Voltage (OVDD/2) Output Data Valid Input Data Valid VM
Figure 29. Test Access Port Timing Diagram
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 48 Freescale Semiconductor
I2 C
12 I2C
This section describes the DC and AC electrical characteristics for the I2C interface of the MPC8347EA.
12.1
I2C DC Electrical Characteristics
Table 41. I2C DC Electrical Characteristics
Table 41 provides the DC electrical characteristics for the I2C interface of the MPC8347EA.
At recommended operating conditions with OVDD of 3.3 V 10%.
Parameter Input high voltage level Input low voltage level Low level output voltage Output fall time from VIH(min) to VIL(max) with a bus capacitance from 10 to 400 pF Input current each I/O pin (input voltage is between 0.1 x OVDD and 0.9 x OVDD(max) Capacitance for each I/O pin
Symbol VIH VIL VOL tI2KLKV
Min 0.7 x OVDD -0.3 0 20 + 0.1 x CB 0 -10 --
Max OVDD+ 0.3 0.3 x OVDD 0.2 x OVDD 250 50 10 10
Unit Notes V V V ns ns A pF 1 2 3 4
Pulse width of spikes which must be suppressed by the input filter tI2KHKL II CI
Notes: 1. Output voltage (open drain or open collector) condition = 3 mA sink current. 2. CB = capacitance of one bus line in pF. 3. Refer to the MPC8349E Integrated Host Processor Reference Manual for information on the digital filter used. 4. I/O pins obstruct the SDA and SCL lines if OVDD is switched off.
12.2
I2C AC Electrical Specifications
Table 42 provides the AC timing parameters for the I2C interface of the MPC8347EA. Note that all values refer to VIH (min) and VIL (max) levels (see Table 41).
Table 42. I2C AC Electrical Specifications
Parameter SCL clock frequency Low period of the SCL clock High period of the SCL clock Setup time for a repeated START condition Hold time (repeated) START condition (after this period, the first clock pulse is generated) Data setup time Data hold time: CBUS compatible masters I2C bus devices Symbol 1 fI2C tI2CL tI2CH tI2SVKH tI2SXKL tI2DVKH tI2DXKL -- 02 -- 0.9 3 Min 0 1.3 0.6 0.6 0.6 100 Max 400 -- -- -- -- -- Unit kHz s s s s ns s
MPC8347EA MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 49
I2 C
Table 42. I2C AC Electrical Specifications (continued)
Parameter Rise time of both SDA and SCL signals Fall time of both SDA and SCL signals Set-up time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) Noise margin at the HIGH level for each connected device (including hysteresis) Symbol 1 tI2CR Min 20 + 0.1 Cb 4 20 + 0.1 Cb 4 0.6 1.3 0.1 x OVDD 0.2 x OVDD Max 300 300 -- -- -- -- Unit ns ns s s V V
tI2CF
tI2PVKH tI2KHDX VNL VNH
Notes: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the start condition (S) goes invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaches the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). 2. MPC8347EA provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3. The maximum tI2DVKH must be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal. 4. CB = capacitance of one bus line in pF.
Figure 30 provides the AC test load for the I2C.
Output Z0 = 50 RL = 50 OVDD/2
Figure 30. I2C AC Test Load
Figure 31 shows the AC timing diagram for the I2C bus.
SDA tI2CF tI2CL SCL tI2SXKL S tI2DXKL tI2CH Sr tI2SVKH tI2PVKH P S tI2DVKH tI2SXKL tI2KHKL tI2CR tI2CF
Figure 31. I2C Bus AC Timing Diagram
MPC8347EA MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 50 Freescale Semiconductor
PCI
13 PCI
This section describes the DC and AC electrical specifications for the PCI bus of the MPC8347EA.
13.1
PCI DC Electrical Characteristics
Table 43. PCI DC Electrical Characteristics
Parameter Symbol VIH VIL IIN VOH VOL Test Condition VOUT VOH (min) or VOUT VOL (max) VIN = 0 V or VIN = OVDD OVDD = min, IOH = -100 A OVDD = min, IOL = 100 A
1
Table 43 provides the DC electrical characteristics for the PCI interface of the MPC8347EA.
Min 2 -0.3 -- OVDD - 0.2 --
Max OVDD + 0.3 0.8 5 -- 0.2
Unit V V A V V
High-level input voltage Low-level input voltage Input current High-level output voltage Low-level output voltage
Notes: 1. The symbol VIN, in this case, represents the OVIN symbol referenced in Table 1.
13.2
PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus of the MPC8347EA. Note that the PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8347EA is configured as a host or agent device. Table 44 provides the PCI AC timing specifications at 66 MHz.
Table 44. PCI AC Timing Specifications at 66 MHz6
Parameter Clock to output valid Output hold from Clock Clock to output high impedance Input setup to Clock Input hold from Clock Symbol 1 tPCKHOV Min -- 1 -- 3.0 0 Max 6.0 -- 14 -- -- Unit ns ns ns ns ns Notes 2 2 2, 3 2, 4 2, 4
tPCKHOX
tPCKHOZ tPCIVKH tPCIXKH
Notes: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications. 3. For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. 6. PCI timing depends on M66EN and the ratio between PCI1/PCI2. Refer to the PCI chapter of the reference manual for a description of M66EN.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 51
PCI
Table 45 provides the PCI AC timing specifications at 33 MHz.
Table 45. PCI AC Timing Specifications at 33 MHz
Parameter Clock to output valid Output hold from Clock Clock to output high impedance Input setup to Clock Input hold from Clock Symbol 1 tPCKHOV Min -- 2 -- 3.0 0 Max 11 -- 14 -- -- Unit ns ns ns ns ns Notes 2 2 2, 3 2, 4 2, 4
tPCKHOX
tPCKHOZ tPCIVKH tPCIXKH
Notes: 1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state. 2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications. 3. For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin.
Figure 32 provides the AC test load for PCI.
Output Z0 = 50 RL = 50 OVDD/2
Figure 32. PCI AC Test Load
Figure 33 shows the PCI input AC timing diagram.
CLK tPCIVKH tPCIXKH Input
Figure 33. PCI Input AC Timing Diagram
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 52 Freescale Semiconductor
PCI
Figure 34 shows the PCI output AC timing diagram.
CLK tPCKHOV Output Delay tPCKHOZ High-Impedance Output tPCKHOX
Figure 34. PCI Output AC Timing Diagram
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 53
Timers
14 Timers
This section describes the DC and AC electrical specifications for the timers.
14.1
Timer DC Electrical Characteristics
Table 46 provides the DC electrical characteristics for the MPC8347EA timer pins, including TIN, TOUT, TGATE, and RTC_CLK.
Table 46. Timer DC Electrical Characteristics
Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage Symbol VIH VIL IIN VOH VOL VOL IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2 mA 2.4 -- -- Condition Min 2.0 -0.3 Max OVDD+0.3 0.8 5 -- 0.5 0.4 Unit V V A V V V
14.2
Timer AC Timing Specifications
Table 47. Timers Input AC Timing Specifications 1
Characteristic Symbol 2 tTIWID Min 20 Unit ns
Table 47 provides the timer input and output AC timing specifications.
Timers inputs--minimum pulse width
Notes: 1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN. Timings are measured at the pin. 2. Timer inputs and outputs are asynchronous to any visible clock. Timer outputs should be synchronized before use by external synchronous logic. Timer inputs are required to be valid for at least tTIWID ns to ensure proper operation.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 54 Freescale Semiconductor
GPIO
15 GPIO
This section describes the DC and AC electrical specifications for the GPIO.
15.1
GPIO DC Electrical Characteristics
Table 48. GPIO DC Electrical Characteristics
Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage Symbol VIH VIL IIN VOH VOL VOL IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2 mA 2.4 -- -- Condition Min 2.0 -0.3 Max OVDD+0.3 0.8 5 -- 0.5 0.4 Unit V V A V V V
Table 48 provides the DC electrical characteristics for the MPC8347EA GPIO.
15.2
GPIO AC Timing Specifications
Table 49. GPIO Input AC Timing Specifications 1
Characteristic Symbol 2 tPIWID Min 20 Unit ns
Table 49 provides the GPIO input and output AC timing specifications.
GPIO inputs--minimum pulse width
Notes: 1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN. Timings are measured at the pin. 2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by external synchronous logic. GPIO inputs must be valid for at least tPIWID ns to ensure proper operation.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 55
IPIC
16 IPIC
This section describes the DC and AC electrical specifications for the external interrupt pins.
16.1
IPIC DC Electrical Characteristics
Table 50. IPIC DC Electrical Characteristics
Characteristic Input high voltage Input low voltage Input current Output low voltage Output low voltage Symbol VIH VIL IIN VOL VOL IOL = 8.0 mA IOL = 3.2 mA -- -- Condition Min 2.0 -0.3 Max OVDD+0.3 0.8 5 0.5 0.4 Unit V V A V V
Table 50 provides the DC electrical characteristics for the external interrupt pins.
Notes: 1. This table applies for pins IRQ[0:7], IRQ_OUT and MCP_OUT. 2. IRQ_OUT and MCP_OUT are open-drain pins; thus VOH is not relevant for those pins.
16.2
IPIC AC Timing Specifications
Table 51. IPIC Input AC Timing Specifications 1
Characteristic Symbol 2 tPICWID Min 20 Unit ns
Table 51 provides the IPIC input and output AC timing specifications.
IPIC inputs--minimum pulse width
Notes: 1. Input specifications are measured from the 50 percent level of the signal to the 50 percent level of the rising edge of CLKIN. Timings are measured at the pin. 2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by external synchronous logic. IPIC inputs must be valid for at least tPICWID ns to ensure proper operation in edge triggered mode.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 56 Freescale Semiconductor
SPI
17 SPI
This section describes the SPI DC and AC electrical specifications.
17.1
SPI DC Electrical Characteristics
Table 52. SPI DC Electrical Characteristics
Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage Symbol VIH VIL IIN VOH VOL VOL IOH = -8.0 mA IOL = 8.0 mA IOL = 3.2 mA 2.4 -- -- Condition Min 2.0 -0.3 Max OVDD+0.3 0.8 5 -- 0.5 0.4 Unit V V A V V V
Table 52 provides the SPI DC electrical characteristics.
17.2
SPI AC Timing Specifications
Table 53. SPI AC Timing Specifications 1
Characteristic Symbol 2 tNIKHOV tNIKHOX tNEKHOV tNEKHOX tNIIVKH tNIIXKH tNEIVKH tNEIXKH 2 4 0 4 2 0.5 8 Min Max 6 Unit ns ns ns ns ns ns ns ns
Table 53 provides the SPI input and output AC timing specifications.
SPI outputs valid--Master mode (internal clock) delay SPI outputs hold--Master mode (internal clock) delay SPI outputs valid--Slave mode (external clock) delay SPI outputs hold--Slave mode (external clock) delay SPI inputs--Master mode (internal clock input setup time SPI inputs--Master mode (internal clock input hold time SPI inputs--Slave mode (external clock) input setup time SPI inputs--Slave mode (external clock) input hold time
Notes: 1. Output specifications are measured from the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal. Timings are measured at the pin. 2. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOX symbolizes the internal timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 57
SPI
Figure 35 provides the AC test load for the SPI.
Output Z0 = 50 RL = 50 OVDD/2
Figure 35. SPI AC Test Load
Figure 36 through Figure 37 represent the AC timings from Table 53. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge. Figure 36 shows the SPI timings in slave mode (external clock).
SPICLK (input) tNEIVKH tNEIXKH
Input Signals: SPIMOSI (See Note) Output Signals: SPIMISO (See Note)
tNEKHOX
Note: The clock edge is selectable on SPI.
Figure 36. SPI AC Timing in Slave Mode (External Clock) Diagram
Figure 37 shows the SPI timings in master mode (internal clock).
SPICLK (output) tNIIVKH tNIIXKH
Input Signals: SPIMISO (See Note) Output Signals: SPIMOSI (See Note)
tNIKHOX
Note: The clock edge is selectable on SPI.
Figure 37. SPI AC Timing in Master Mode (Internal Clock) Diagram
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 58 Freescale Semiconductor
Package and Pin Listings
18 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8347EA is available in two packages a tape ball grid array (TBGA) and a plastic ball grid array (PBGA). See Section 18.1, "Package Parameters for the MPC8347EA TBGA," and Section 18.2, "Mechanical Dimensions of the MPC8347EA TBGA," and Section 18.3, "Package Parameters for the MPC8347EA PBGA" and Section 18.4, "Mechanical Dimensions of the MPC8347EA PBGA."
18.1
Package Parameters for the MPC8347EA TBGA
The package parameters are provided in the following list. The package type is 35 mm x 35 mm, 672 tape ball grid array (TBGA). Package outline 35 mm x 35 mm Interconnects 672 Pitch 1.00 mm Module height (typical) 1.46 mm Solder Balls 62 Sn/36 Pb/2 Ag (ZU package) 95.5 Sn/0.5 Cu/4Ag (VV package) Ball diameter (typical) 0.64 mm
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 59
Package and Pin Listings
18.2
Mechanical Dimensions of the MPC8347EA TBGA
Figure 38 shows the mechanical dimensions and bottom surface nomenclature of the MPC8347EA, 672-TBGA package.
Figure 38. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8347EA TBGA NOTES
1. 2. 3. 4. 5.
All dimensions are in millimeters. Dimensions and tolerances per ASME Y14.5M-1994. Maximum solder ball diameter measured parallel to datum A. Datum A, the seating plane, is determined by the spherical crowns of the solder balls. Parallelism measurement must exclude any effect of mark on top surface of package.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 60 Freescale Semiconductor
Package and Pin Listings
18.3
Package Parameters for the MPC8347EA PBGA
The package parameters are as provided in the following list. The package type is 29 mm x 29 mm, 620 Plastic ball grid array (PBGA). Package outline 29 mm x 29 mm Interconnects 620 Pitch 1.00 mm Module height (maximum) 2.46 mm Module height (typical) 2.23 mm Module height (minimum) 2.00 mm Solder Balls 62 Sn/36 Pb/2 Ag (ZQ package) 95.5 Sn/0.5 Cu/4Ag (VR package) Ball diameter (typical) 0.60 mm
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 61
Package and Pin Listings
18.4
Mechanical Dimensions of the MPC8347EA PBGA
Figure 39 shows the mechanical dimensions and bottom surface nomenclature of theMPC8347EA , 620-PBGA package.
Figure 39. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8347EA PBGA
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 62 Freescale Semiconductor
Package and Pin Listings
NOTE
1. 2. 3. 4.
All dimensions in millimeters Dimensioning and tolerancing per ASME Y14. 5M-1994 Maximum solder ball diameter measured parallel to datum A Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 63
18.5
Pinout Listings
Table 54. MPC8347EA (TBGA) Pinout Listing
Signal Package Pin Number PCI Pin Type Power Supply Notes
Table 51 provides the pin-out listing for the MPC8347EA, 672 TBGA package.
PCI_INTA/IRQ_OUT PCI_RESET_OUT PCI_AD[31:0]
B34 C33 G30, G32, G34, H31, H32, H33, H34, J29, J32, J33, L30, K31, K33, K34, L33, L34, P34, R29, R30, R33, R34, T31, T32, T33, U31, U34, V31, V32, V33, V34, W33, W34 J30, M31, P33, T34 P32 M32 N29 M34 N31 N30 J31 N34 N33 D32 D34 E34, F32, G29 C34 D33 E33 F31, F33 A19
O O I/O
OVDD OVDD OVDD
2
PCI_C/BE[3:0] PCI_PAR PCI_FRAME PCI_TRDY PCI_IRDY PCI_STOP PCI_DEVSEL PCI_IDSEL PCI_SERR PCI_PERR PCI_REQ[0] PCI_REQ[1]/CPCI1_HS_ES PCI_REQ[2:4] PCI_GNT0 PCI_GNT1/CPCI1_HS_LED PCI_GNT2/CPCI1_HS_ENUM PCI_GNT[3:4] M66EN
I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I I I/O O O O I
OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD 5 5 5 5 5 5 5
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 64 Freescale Semiconductor
Table 54. MPC8347EA (TBGA) Pinout Listing (continued)
Signal Package Pin Number DDR SDRAM Memory Interface MDQ[0:63] D5, A3, C3, D3, C4, B3, C2, D4, D2, E5, G2, H6, E4, F3, G4, G3, H1, J2, L6, M6, H2, K6, L2, M4, N2, P4, R2, T4, P6, P3, R1, T2, AB5, AA3, AD6, AE4, AB4, AC2, AD3, AE6, AE3, AG4, AK5, AK4, AE2, AG6, AK3, AK2, AL2, AL1, AM5, AP5, AM2, AN1, AP4, AN5, AJ7, AN7, AM8, AJ9, AP6, AL7, AL9, AN8 W4, W3, Y3, AA6, T1 U1 Y1, Y6 B1, F1, K1, R4, AD4, AJ1, AP3, AP7, Y4 B2, F5, J1, P2, AC1, AJ2, AN4, AL8, W2 AD1, AA5 W1, U4, T3, R3, P1, M1, N1, L3, L1, K2, Y2, K3, J3, AP2, AN6 AF1 AF4 AG3 AG2, AG1, AK1, AL4 H3, G1 U2, F4, AM3, V3, F2, AN3 U3, E3, AN2, V4, E1, AM4 AH3, AJ5, AH1, AJ4 H4 AB1 AA1 Local Bus Controller Interface LAD[0:31] AM13, AP13, AL14, AM14, AN14, AP14, AK15, AJ15, AM15, AN15, AP15, AM16, AL16, AN16, AP16, AL17, AM17, AP17, AK17, AP18, AL18, AM18, AN18, AP19, AN19, AM19, AP20, AK19, AN20, AL20, AP21, AN21 AM21 AP22 I/O OVDD I/O GVDD Pin Type Power Supply Notes
MECC[0:4]/MSRCID[0:4] MECC[5]/MDVAL MECC[6:7] MDM[0:8] MDQS[0:8] MBA[0:1] MA[0:14] MWE MRAS MCAS MCS[0:3] MCKE[0:1] MCK[0:5] MCK[0:5] MODT[0:3] MBA[2] MDIC0 MDIC1
I/O I/O I/O O I/O O O O O O O O O O O O I/O I/O
GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD -- -- 10 10 3
LDP[0]/CKSTOP_OUT LDP[1]/CKSTOP_IN
I/O I/O
OVDD OVDD
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 65
Table 54. MPC8347EA (TBGA) Pinout Listing (continued)
Signal LDP[2]/LCS[4] LDP[3]/LCS[5] LA[27:31] LCS[0:3] LWE[0:3]/LSDDQM[0:3]/ LBS[0:3] LBCTL LALE LGPL0/LSDA10/ cfg_reset_source0 LGPL1/LSDWE/ cfg_reset_source1 LGPL2/ LSDRAS/LOE LGPL3/LSDCAS/ cfg_reset_source2 LGPL4/LGTA/LUPWAIT/LPBSE LGPL5/cfg_clkin_div LCKE LCLK[0:2] LSYNC_OUT LSYNC_IN AN22 AM22 AK21, AP23, AN23, AP24, AK22 AN24, AL23, AP25, AN25 AK23, AP26, AL24, AM25 AN26 AK24 AP27 AL25 AJ24 Package Pin Number Pin Type I/O I/O O O O O O I/O I/O O Power Supply OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Notes
AN27 AP28 AL26 AM27 AN28, AK26, AP29 AM12 AJ10 General Purpose I/O Timers
I/O I/O I/O O O O I
GPIO1[0]/DMA_DREQ0/ GTM1_TIN1/ GTM2_TIN2 GPIO1[1]/DMA_DACK0/ GTM1_TGATE1/ GTM2_TGATE2 GPIO1[2]/DMA_DDONE0/ GTM1_TOUT1 GPIO1[3]/DMA_DREQ1/ GTM1_TIN2/ GTM2_TIN1 GPIO1[4]/DMA_DACK1/ GTM1_TGATE2/ GTM2_TGATE1
F24
I/O
OVDD
E24
I/O
OVDD
B25 D24
I/O I/O
OVDD OVDD
A25
I/O
OVDD
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 66 Freescale Semiconductor
Table 54. MPC8347EA (TBGA) Pinout Listing (continued)
Signal GPIO1[5]/DMA_DDONE1/ GTM1_TOUT2/ GTM2_TOUT1 GPIO1[6]/DMA_DREQ2/ GTM1_TIN3/ GTM2_TIN4 GPIO1[7]/DMA_DACK2/ GTM1_TGATE3/ GTM2_TGATE4 GPIO1[8]/DMA_DDONE2/ GTM1_TOUT3 GPIO1[9]/DMA_DREQ3/ GTM1_TIN4/ GTM2_TIN3 GPIO1[10]/DMA_DACK3/ GTM1_TGATE4/ GTM2_TGATE3 GPIO1[11]/DMA_DDONE3/ GTM1_TOUT4/ GTM2_TOUT3 B24 Package Pin Number Pin Type I/O Power Supply OVDD Notes
A24
I/O
OVDD
D23
I/O
OVDD
B23 A23
I/O I/O
OVDD OVDD
F22
I/O
OVDD
E22
I/O
OVDD
USB Port 1 MPH1_D0_ENABLEN/DR_D0_ENABLEN A26 MPH1_D1_SER_TXD/DR_D1_SER_TXD B26 I/O I/O I/O I/O I/O I/O I/O I/O I I/O O I O O OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD
MPH1_D2_VMO_SE0/DR_D2_VMO_SE0 D25 MPH1_D3_SPEED/DR_D3_SPEED MPH1_D4_DP/DR_D4_DP MPH1_D5_DM/DR_D5_DM A27 B27 C27
MPH1_D6_SER_RCV/DR_D6_SER_RCV D26 MPH1_D7_DRVVBUS/DR_D7_DRVVBUS E26 MPH1_NXT/DR_SESS_VLD_NXT MPH1_DIR_DPPULLUP/ DR_XCVR_SEL_DPPULLUP MPH1_STP_SUSPEND/ DR_STP_SUSPEND MPH1_PWRFAULT/ DR_RX_ERROR_PWRFAULT MPH1_PCTL0/DR_TX_VALID_PCTL0 MPH1_PCTL1/DR_TX_VALIDH_PCTL1 D27 A28 F26 E27 A29 D28
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 67
Table 54. MPC8347EA (TBGA) Pinout Listing (continued)
Signal MPH1_CLK/DR_CLK B29 USB Port 0 MPH0_D0_ENABLEN/ DR_D8_CHGVBUS MPH0_D1_SER_TXD/ DR_D9_DCHGVBUS MPH0_D2_VMO_SE0/ DR_D10_DPPD MPH0_D3_SPEED/ DR_D11_DMMD MPH0_D4_DP/ DR_D12_VBUS_VLD MPH0_D5_DM/ DR_D13_SESS_END MPH0_D6_SER_RCV/DR_D14 MPH0_D7_DRVVBUS/ DR_D15_IDPULLUP MPH0_NXT/ DR_RX_ACTIVE_ID MPH0_DIR_DPPULLUP/ DR_RESET MPH0_STP_SUSPEND/ DR_TX_READY MPH0_PWRFAULT/ DR_RX_VALIDH MPH0_PCTL0/ DR_LINE_STATE0 MPH0_PCTL1/ DR_LINE_STATE1 MPH0_CLK/DR_RX_VALID C29 A30 E28 B30 C30 A31 B31 C31 B32 A32 A33 C32 D31 E30 B33 Programmable Interrupt Controller MCP_OUT IRQ0/MCP_IN/GPIO2[12] IRQ[1:5]/GPIO2[13:17] IRQ[6]/GPIO2[18]/ CKSTOP_OUT AN33 C19 C22, A22, D21, C21, B21 A21 O I/O I/O I/O OVDD OVDD OVDD OVDD 2 I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I I/O I/O I OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Package Pin Number Pin Type I Power Supply OVDD Notes
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 68 Freescale Semiconductor
Table 54. MPC8347EA (TBGA) Pinout Listing (continued)
Signal IRQ[7]/GPIO2[19]/ CKSTOP_IN C20 Package Pin Number Pin Type I/O Power Supply OVDD Notes
Ethernet Management Interface EC_MDC EC_MDIO A7 E9 Gigabit Reference Clock EC_GTX_CLK125 C8 Three-Speed Ethernet Controller (Gigabit Ethernet 1) TSEC1_COL/GPIO2[20] TSEC1_CRS/GPIO2[21] TSEC1_GTX_CLK TSEC1_RX_CLK TSEC1_RX_DV TSEC1_RX_ER/GPIO2[26] TSEC1_RXD[7:4]/ GPIO2[22:25] TSEC1_RXD[3:0] TSEC1_TX_CLK TSEC1_TXD[7:4]/GPIO2[27:30] TSEC1_TXD[3:0] TSEC1_TX_EN TSEC1_TX_ER/GPIO2[31] A17 F12 D10 A11 B11 B17 B16, D16, E16, F16 E10, A8, F10, B8 D17 A15, B15, A14, B14 A10, E11, B10, A9 B9 A16 Three-Speed Ethernet Controller (Gigabit Ethernet 2) TSEC2_COL/GPIO1[21] TSEC2_CRS/GPIO1[22] TSEC2_GTX_CLK TSEC2_RX_CLK TSEC2_RX_DV/GPIO1[23] TSEC2_RXD[7:4]/GPIO1[26:29] TSEC2_RXD[3:0]/GPIO1[13:16] TSEC2_RX_ER/GPIO1[25] TSEC2_TXD[7]/GPIO1[31] C14 D6 A4 B4 E6 A13, B13, C13, A12 D7, A6, E8, B7 D14 B12 I/O I/O O I I/O I/O I/O I/O I/O OVDD LVDD2 LVDD2 LVDD2 LVDD2 OVDD LVDD2 OVDD OVDD I/O I/O O I I I/O I/O I I I/O O O I/O OVDD LVDD1 LVDD1 LVDD1 LVDD1 OVDD OVDD LVDD1 OVDD OVDD LVDD1 LVDD1 OVDD 3 I LVDD1 O I/O LVDD1 LVDD1 2
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 69
Table 54. MPC8347EA (TBGA) Pinout Listing (continued)
Signal TSEC2_TXD[6]/ DR_XCVR_TERM_SEL TSEC2_TXD[5]/ DR_UTMI_OPMODE1 TSEC2_TXD[4]/ DR_UTMI_OPMODE0 TSEC2_TXD[3:0]/GPIO1[17:20] TSEC2_TX_ER/GPIO1[24] TSEC2_TX_EN/GPIO1[12] TSEC2_TX_CLK/GPIO1[30] C12 D12 E12 B5, A5, F8, B6 F14 C5 E14 DUART UART_SOUT[1:2]/ MSRCID[0:1]/LSRCID[0:1] UART_SIN[1:2]/ MSRCID[2:3]/LSRCID[2:3] UART_CTS[1]/ MSRCID4/LSRCID4 UART_CTS[2]/ MDVAL/ LDVAL UART_RTS[1:2] AK27, AN29 AL28, AM29 AP30 AN30 AP31, AM30 I2C interface IIC1_SDA IIC1_SCL IIC2_SDA IIC2_SCL AK29 AP32 AN31 AM31 SPI SPIMOSI/LCS[6] SPIMISO/LCS[7] SPICLK SPISEL AN32 AP33 AK30 AL31 Clocks PCI_CLK_OUT[0:2] PCI_CLK_OUT[3]/LCS[6] PCI_CLK_OUT[4]/LCS[7] AN9, AP9, AM10 AN10 AJ11 O O O OVDD OVDD OVDD I/O I/O I/O I OVDD OVDD OVDD OVDD I/O I/O I/O I/O OVDD OVDD OVDD OVDD 2 2 2 2 O I/O I/O I/O O OVDD OVDD OVDD OVDD OVDD Package Pin Number Pin Type O O O I/O I/O I/O I/O Power Supply OVDD OVDD OVDD LVDD2 OVDD LVDD2 OVDD 3 Notes
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 70 Freescale Semiconductor
Table 54. MPC8347EA (TBGA) Pinout Listing (continued)
Signal PCI_SYNC_IN/PCI_CLOCK PCI_SYNC_OUT RTC/PIT_CLOCK CLKIN AK12 AP11 AM32 AM9 JTAG TCK TDI TDO TMS TRST E20 F20 B20 A20 B19 Test TEST TEST_SEL D22 AL13 PMC QUIESCE A18 System Control PORESET HRESET SRESET C18 B18 D18 Thermal Management THERM0 K32 Power and Ground Signals AVDD1 L31 Power for e300 PLL (1.2 V) Power for system PLL (1.2 V) Power for DDR DLL (1.2 V) Power for LBIU DLL (1.2 V) AVDD1 I -- 9 I I/O I/O OVDD OVDD OVDD 1 2 O OVDD I I OVDD OVDD 6 7 I I O I I OVDD OVDD OVDD OVDD OVDD 4 3 4 4 Package Pin Number Pin Type I O I I Power Supply OVDD OVDD OVDD OVDD 3 Notes
AVDD2
AP12
AVDD2
AVDD3
AE1
--
AVDD4
AJ13
AVDD4
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 71
Table 54. MPC8347EA (TBGA) Pinout Listing (continued)
Signal GND Package Pin Number A1, A34, C1, C7, C10, C11, C15, C23, C25, C28, D1, D8, D20, D30, E7, E13, E15, E17, E18, E21, E23, E25, E32, F6, F19, F27, F30, F34, G31, H5, J4, J34, K30, L5, M2, M5, M30, M33, N3, N5, P30, R5, R32, T5, T30, U6, U29, U33, V2, V5, V30, W6, W30, Y30, AA2, AA30, AB2, AB6, AB30, AC3, AC6, AD31, AE5, AF2, AF5, AF31, AG30, AG31, AH4, AJ3, AJ19, AJ22, AK7, AK13, AK14, AK16, AK18, AK20, AK25, AK28, AL3, AL5, AL10, AL12, AL22, AL27, AM1, AM6, AM7, AN12, AN17, AN34, AP1, AP8, AP34 A2, E2, G5, G6, J5, K4, K5, L4, N4, P5, R6, T6, U5, V1, W5, Y5, AA4, AB3, AC4, AD5, AF3, AG5, AH2, AH5, AH6, AJ6, AK6, AK8, AK9, AL6 C9, D11 Pin Type -- Power Supply -- Notes
GVDD
Power for DDR DRAM I/O Voltage (2.5 V) Power for Three Speed Ethernet #1 and for Ethernet Managemen t Interface I/O (2.5V, 3.3V) Power for Three Speed Ethernet #2 I/O (2.5V, 3.3V) Power for Core (1.2 V)
GVDD
LVDD1
LVDD1
LVDD2
C6, D9
LVDD2
VDD
E19, E29, F7, F9, F11,F13, F15, F17, F18, F21, F23, F25, F29, H29, J6, K29, M29, N6, P29, T29, U30, V6, V29, W29, AB29, AC5, AD29, AF6, AF29, AH29, AJ8, AJ12, AJ14, AJ16, AJ18, AJ20, AJ21, AJ23, AJ25, AJ26, AJ27, AJ28, AJ29, AK10 B22, B28, C16, C17, C24, C26, D13, D15, D19, D29, E31, F28, G33, H30, L29, L32, N32, P31, R31, U32, W31, Y29, AA29, AC30, AE31, AF30, AG29, AJ17, AJ30, AK11, AL15, AL19, AL21, AL29, AL30, AM20, AM23, AM24, AM26, AM28, AN11, AN13
VDD
OVDD
PCI, 10/100 Ethernet, and other Standard (3.3 V)
OVDD
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 72 Freescale Semiconductor
Table 54. MPC8347EA (TBGA) Pinout Listing (continued)
Signal MVREF1 M3 Package Pin Number Pin Type I Power Supply DDR Reference Voltage DDR Reference Voltage Notes
MVREF2
AD2
I
No Connection NC W32, AA31, AA32, AA33, AA34, AB31, AB32, AB33, AB34, AC29, AC31, AC33, AC34, AD30, AD32, AD33, AD34, AE29, AE30, AH32, AH33, AH34, AM33, AJ31, AJ32, AJ33, AJ34, AK32, AK33, AK34, AM34, AL33, AL34, AK31, AH30, AC32, AE32, AH31, AL32, AG34, AE33, AF32, AE34, AF34, AF33, AG33, AG32, AL11, AM11, AP10, Y32, Y34, Y31, Y33 -- --
Notes: 1. This pin is an open-drain signal. A weak pull-up resistor (1 k) should be placed on this pin to OVDD 2. This pin is an open-drain signal. A weak pull-up resistor (2-10 k) should be placed on this pin to OVDD. 3. During reset, this output is actively driven rather than three-stated. 4. These JTAG pins have weak internal pull-up P-FETs that are always enabled. 5. This pin should have a weak pull-up if the chip is in PCI host mode. Follow the PCI specifications. 6. This pin must always be tied to GND 7. This pin must always be pulled up to OVDD 8. This pin must always be left not connected. 9. Thermal sensitive resistor. 10. It is recommended that MDIC0 be tied to GRD using an 18 resistor and MDIC1 be tied to DDR power using an 18 resistor.
Table 52 provides the pin-out listing for the MPC8347EA, 620 PBGA package.
Table 55. MPC8347EA (PBGA) Pinout Listing
Signal Package Pin Number PCI PCI1_INTA/IRQ_OUT PCI1_RESET_OUT PCI1_AD[31:0] D20 B21 E19, D17, A16, A18, B17, B16, D16, B18, E17, E16, A15, C16, D15, D14, C14, A12, D12, B11, C11, E12, A10, C10, A9, E11, E10, B9, B8, D9, A8, C9, D8, C8 A17, A14, A11, B10 O O I/O OVDD OVDD OVDD 2 Pin Type Power Supply Notes
PCI1_C/BE[3:0]
I/O
OVDD
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 73
Table 55. MPC8347EA (PBGA) Pinout Listing (continued)
Signal PCI1_PAR PCI1_FRAME PCI1_TRDY PCI1_IRDY PCI1_STOP PCI1_DEVSEL PCI1_IDSEL PCI1_SERR PCI1_PERR PCI1_REQ[0] PCI1_REQ[1]/ CPCI1_HS_ES PCI1_REQ[2:4] PCI1_GNT0 PCI1_GNT1/ CPCI1_HS_LED PCI1_GNT2/ CPCI1_HS_ENUM PCI1_GNT[3:4] M66EN D13 B14 A13 E13 C13 B13 C17 C12 B12 A21 C19 C18, A19, E20 B20 C20 B19 A20, E18 L26 DDR SDRAM Memory Interface MDQ[0:63] AC25, AD27, AD25, AH27, AE28, AD26, AD24, AF27, AF25, AF28, AH24, AG26, AE25, AG25, AH26, AH25, AG22, AH22, AE21, AD19, AE22, AF23, AE19, AG20, AG19, AD17, AE16, AF16, AF18, AG18, AH17, AH16, AG9, AD12, AG7, AE8, AD11, AH9, AH8, AF6, AF8, AE6, AF1, AE4, AG8, AH3, AG3, AG4, AH2, AD7, AB4, AB3, AG1, AD5, AC2, AC1, AC4, AA3, Y4, AA4, AB1, AB2, Y5, Y3 AG13, AE14, AH12, AH10, AE15 AH14 AE13, AH11 AG28, AG24, AF20, AG17, AE9, AH5, AD1, AA2, AG12 I/O GVDD Package Pin Number Pin Type I/O I/O I/O I/O I/O I/O I I/O I/O I/O I I I/O O O O I Power Supply OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD 5 5 5 5 5 5 5 Notes
MECC[0:4]/MSRCID[0:4] MECC[5]/MDVAL MECC[6:7] MDM[0:8]
I/O I/O I/O O
GVDD GVDD GVDD GVDD
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 74 Freescale Semiconductor
Table 55. MPC8347EA (PBGA) Pinout Listing (continued)
Signal MDQS[0:8] MBA[0:1] MA[0:14] Package Pin Number AE27, AE26, AE20, AH18, AG10, AF5, AC3, AA1, AH13 AF10, AF11 AF13, AF15, AG16, AD16, AF17, AH20, AH19, AH21, AD18, AG21, AD13, AF21, AF22, AE1, AA5 AD10 AF7 AG6 AE7, AH7, AH4, AF2 AG23, AH23 AH15, AE24, AE2, AF14, AE23, AD3 AG15, AD23, AE3, AG14, AF24, AD2 AG5, AD4, AH6, AF4 AD22 AG11 AF12 Local Bus Controller Interface LAD[0:31] T4, T5, T1, R2, R3, T2, R1, R4, P1, P2, P3, P4, N1, N4, N2, N3, M1, M2, M3, N5, M4, L1, L2, L3, K1, M5, K2, K3, J1, J2, L5, J3 H1 K5 H2 G1 J4, H3, G2, F1, G3 J5, H4, F2, E1 F3, G4, D1, E2 H5 E3 F4 D2 I/O OVDD Pin Type I/O O O Power Supply GVDD GVDD GVDD Notes
MWE MRAS MCAS MCS[0:3] MCKE[0:1] MCK[0:5] MCK[0:5] MODT[0:3] MBA[2] MDIC0 MDIC1
O O O O O O O O O I/O I/O
GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD GVDD -- -- 9 9 3
LDP[0]/CKSTOP_OUT LDP[1]/CKSTOP_IN LDP[2]/LCS[4] LDP[3]/LCS[5] LA[27:31] LCS[0:3] LWE[0:3]/LSDDQM[0:3]/ LBS[0:3] LBCTL LALE LGPL0/LSDA10/ cfg_reset_source0 LGPL1/LSDWE/ cfg_reset_source1
I/O I/O I/O I/O O O O O O I/O I/O
OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 75
Table 55. MPC8347EA (PBGA) Pinout Listing (continued)
Signal LGPL2/ LSDRAS/LOE LGPL3/LSDCAS/ cfg_reset_source2 LGPL4/LGTA/LUPWAIT/LPBSE LGPL5/cfg_clkin_div LCKE LCLK[0:2] LSYNC_OUT LSYNC_IN C1 Package Pin Number Pin Type O Power Supply OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Notes
C2 C3 B3 E4 D4, A3, C4 U3 Y2 General Purpose I/O Timers
I/O I/O I/O O O O I
GPIO1[0]/DMA_DREQ0/ GTM1_TIN1/ GTM2_TIN2 GPIO1[1]/DMA_DACK0/ GTM1_TGATE1/ GTM2_TGATE2 GPIO1[2]/DMA_DDONE0/ GTM1_TOUT1 GPIO1[3]/DMA_DREQ1/ GTM1_TIN2/ GTM2_TIN1 GPIO1[4]/DMA_DACK1/ GTM1_TGATE2/ GTM2_TGATE1 GPIO1[5]/DMA_DDONE1/ GTM1_TOUT2/ GTM2_TOUT1 GPIO1[6]/DMA_DREQ2/ GTM1_TIN3/ GTM2_TIN4 GPIO1[7]/DMA_DACK2/ GTM1_TGATE3/ GTM2_TGATE4 GPIO1[8]/DMA_DDONE2/ GTM1_TOUT3 GPIO1[9]/DMA_DREQ3/ GTM1_TIN4/ GTM2_TIN3
D27
I/O
OVDD
E26
I/O
OVDD
D28 G25
I/O I/O
OVDD OVDD
J24
I/O
OVDD
F26
I/O
OVDD
E27
I/O
OVDD
E28
I/O
OVDD
H25 F27
I/O I/O
OVDD OVDD
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 76 Freescale Semiconductor
Table 55. MPC8347EA (PBGA) Pinout Listing (continued)
Signal GPIO1[10]/DMA_DACK3/ GTM1_TGATE4/ GTM2_TGATE3 GPIO1[11]/DMA_DDONE3/ GTM1_TOUT4/ GTM2_TOUT3 K24 Package Pin Number Pin Type I/O Power Supply OVDD Notes
G26
I/O
OVDD
USB Port 1 MPH1_D0_ENABLEN/DR_D0_ENABLEN C28 MPH1_D1_SER_TXD/DR_D1_SER_RXD F25 MPH1_D2_VMO_SE0/DR_D2_VMO_SE0 B28 MPH1_D3_SPEED/DR_D3_SPEED MPH1_D4_DP/DR_D4_DP MPH1_D5_DM/DR_D5_DM C27 D26 E25 I/O I/O I/O I/O I/O I/O I/O I/O I I/O O I O O I USB Port 0 MPH0_D0_ENABLEN/ DR_D8_CHGVBUS MPH0_D1_SER_TXD/ DR_D9_DCHGVBUS MPH0_D2_VMO_SE0/ DR_D10_DPPD MPH0_D3_SPEED/ DR_D11_DMMD MPH0_D4_DP/ DR_D12_VBUS_VLD D24 C24 B24 A24 D23 I/O I/O I/O I/O I/O OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD
MPH1_D6_SER_RCV/DR_D6_SER_RCV C26 MPH1_D7_DRVVBUS/DR_D7_DRVVBUS D25 MPH1_NXT/DR_SESS_VLD_NXT MPH1_DIR_DPPULLUP/ DR_XCVR_SEL_DPPULLUP MPH1_STP_SUSPEND/ DR_STP_SUSPEND MPH1_PWRFAULT/ DR_RX_ERROR_PWRFAULT MPH1_PCTL0/DR_TX_VALID_PCTL0 MPH1_PCTL1/DR_TX_VALIDH_PCTL1 MPH1_CLK/DR_CLK B26 E24 A27 C25 A26 B25 A25
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 77
Table 55. MPC8347EA (PBGA) Pinout Listing (continued)
Signal MPH0_D5_DM/ DR_D13_SESS_END MPH0_D6_SER_RCV/DR_D14 MPH0_D7_DRVVBUS/ DR_D15_IDPULLUP MPH0_NXT/ DR_RX_ACTIVE_ID MPH0_DIR_DPPULLUP/ DR_RESET MPH0_STP_SUSPEND/ DR_TX_READY MPH0_PWRFAULT/ DR_RX_VALIDH MPH0_PCTL0/ DR_LINE_STATE0 MPH0_PCTL1/ DR_LINE_STATE1 MPH0_CLK/DR_RX_VALID C23 B23 A23 D22 C22 B22 A22 E21 D21 C21 Programmable Interrupt Controller MCP_OUT IRQ0/MCP_IN/GPIO2[12] IRQ[1:5]/GPIO2[13:17] IRQ[6]/GPIO2[18]/ CKSTOP_OUT IRQ[7]/GPIO2[19]/ CKSTOP_IN E8 J28 K25, J25, H26, L24, G27 G28 O I/O I/O I/O OVDD OVDD OVDD OVDD OVDD 2 Package Pin Number Pin Type I/O I/O I/O I I/O I/O I I/O I/O I Power Supply OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD Notes
J26
I/O
Ethernet Management Interface EC_MDC EC_MDIO Y24 Y25 Gigabit Reference Clock EC_GTX_CLK125 Y26 Three-Speed Ethernet Controller (Gigabit Ethernet 1) TSEC1_COL/GPIO2[20] TSEC1_CRS/GPIO2[21] TSEC1_GTX_CLK M26 U25 V24 I/O I/O O OVDD LVDD1 LVDD1 3 I LVDD1 O I/O LVDD1 LVDD1 2
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 78 Freescale Semiconductor
Table 55. MPC8347EA (PBGA) Pinout Listing (continued)
Signal TSEC1_RX_CLK TSEC1_RX_DV TSEC1_RX_ER/GPIO2[26] TSEC1_RXD[7:4]/GPIO2[22:25] TSEC1_RXD[3:0] TSEC1_TX_CLK TSEC1_TXD[7:4]/GPIO2[27:30] TSEC1_TXD[3:0] TSEC1_TX_EN TSEC1_TX_ER/GPIO2[31] U26 U24 L28 M27, M28, N26, N27 W26, W24, Y28, Y27 N25 N28, P25, P26, P27 V28, V27, V26, W28 W27 N24 Three-Speed Ethernet Controller (Gigabit Ethernet 2) TSEC2_COL/GPIO1[21] TSEC2_CRS/GPIO1[22] TSEC2_GTX_CLK TSEC2_RX_CLK TSEC2_RX_DV/GPIO1[23] TSEC2_RXD[7:4]/GPIO1[26:29] TSEC2_RXD[3:0]/GPIO1[13:16] TSEC2_RX_ER/GPIO1[25] TSEC2_TXD[7]/GPIO1[31] TSEC2_TXD[6]/DR_XCVR_TERM_SEL TSEC2_TXD[5]/DR_UTMI_OPMODE1 TSEC2_TXD[4]/DR_UTMI_OPMODE0 TSEC2_TXD[3:0]/GPIO1[17:20] TSEC2_TX_ER/GPIO1[24] TSEC2_TX_EN/GPIO1[12] TSEC2_TX_CLK/GPIO1[30] P28 AC28 AC27 AB25 AC26 R28, T24, T25, T26 AA25, AA26, AA27, AA28 R25 T27 T28 U28 U27 AB26, AB27, AA24, AB28 R27 AD28 R26 DUART UART_SOUT[1:2]/ MSRCID[0:1]/LSRCID[0:1] UART_SIN[1:2]/ MSRCID[2:3]/LSRCID[2:3] B4, A4 D5, C5 O I/O OVDD OVDD I/O I/O O I I/O I/O I/O I/O I/O O O O I/O I/O I/O I/O OVDD LVDD2 LVDD2 LVDD2 LVDD2 OVDD LVDD2 OVDD OVDD OVDD OVDD OVDD LVDD2 OVDD LVDD2 OVDD 3 Package Pin Number Pin Type I I I/O I/O I I I/O O O I/O Power Supply LVDD1 LVDD1 OVDD OVDD LVDD1 OVDD OVDD LVDD1 LVDD1 OVDD Notes
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 79
Table 55. MPC8347EA (PBGA) Pinout Listing (continued)
Signal UART_CTS[1]/ MSRCID4/LSRCID4 UART_CTS[2]/ MDVAL/ LDVAL UART_RTS[1:2] B5 A5 D6, C6 I2C interface IIC1_SDA IIC1_SCL IIC2_SDA IIC2_SCL E5 A6 B6 E7 SPI SPIMOSI/LCS[6] SPIMISO/LCS[7] SPICLK SPISEL D7 C7 B7 A7 Clocks PCI_CLK_OUT[0:2] PCI_CLK_OUT[3]/LCS[6] PCI_CLK_OUT[4]/LCS[7] PCI_SYNC_IN/PCI_CLOCK PCI_SYNC_OUT RTC/PIT_CLOCK CLKIN Y1, W3, W2 W1 V3 U4 U5 E9 W5 JTAG TCK TDI TDO TMS TRST H27 H28 M24 J27 K26 Test TEST TEST_SEL F28 T3 I I OVDD OVDD 6 6 I I O I I OVDD OVDD OVDD OVDD OVDD 4 3 4 4 O O O I O I I OVDD OVDD OVDD OVDD OVDD OVDD OVDD 3 I/O I/O I/O I OVDD OVDD OVDD OVDD I/O I/O I/O I/O OVDD OVDD OVDD OVDD 2 2 2 2 Package Pin Number Pin Type I/O I/O O Power Supply OVDD OVDD OVDD Notes
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 80 Freescale Semiconductor
Table 55. MPC8347EA (PBGA) Pinout Listing (continued)
Signal Package Pin Number PMC QUIESCE K27 System Control PORESET HRESET SRESET K28 M25 L27 Thermal Management THERM0 B15 Power and Ground Signals AVDD1 C15 Power for e300 PLL (1.2 V) Power for system PLL (1.2 V) Power for DDR DLL (1.2 V) Power for LBIU DLL (1.2 V) -- AVDD1 I -- 8 I I/O I/O OVDD OVDD OVDD 1 2 O OVDD Pin Type Power Supply Notes
AVDD2
U1
AVDD2
AVDD3
AF9
--
AVDD4
U2
AVDD4
GND
A2, B1, B2, D10, D18, E6, E14, E22, F9, F12, F15, F18, F21, F24, G5, H6, J23, L4, L6, L12, L13, L14, L15, L16, L17, M11, M12, M13, M14, M15, M16, M17, M18, M23, N11, N12, N13, N14, N15, N16, N17, N18, P6, P11, P12, P13, P14, P15, P16, P17, P18, P24, R5, R11, R12, R13, R14, R15, R16, R17, R18, R23, T11, T12, T13, T14, T15, T16, T17, T18, U6, U11, U12, U13, U14, U15, U16, U17, U18, V12, V13, V14, V15, V16, V17, V23, V25, W4, Y6, AA23, AB24, AC5, AC8, AC11, AC14, AC17, AC20, AD9, AD15, AD21, AE12, AE18, AF3, AF26 U9, V9, W10, W19, Y11, Y12, Y14, Y15, Y17, Y18, AA6, AB5, AC9, AC12, AC15, AC18, AC21, AC24, AD6, AD8, AD14, AD20, AE5, AE11, AE17, AG2, AG27
--
GVDD
Power for DDR DRAM I/O Voltage (2.5 V)
GVDD
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 81
Table 55. MPC8347EA (PBGA) Pinout Listing (continued)
Signal LVDD1 U20, W25 Package Pin Number Pin Type Power for Three Speed Ethernet #1 and for Ethernet Management Interface I/O (2.5V, 3.3V) Power for Three Speed Ethernet #2 I/O (2.5V, 3.3V) Power for Core (1.2 V) Power Supply LVDD1 Notes
LVDD2
V20, Y23
LVDD2
VDD
J11, J12, J15, K10, K11, K12, K13, K14, K15, K16, K17, K18, K19, L10, L11, L18, L19, M10, M19, N10, N19, P9, P10, P19, R10, R19, R20, T10, T19, U10, U19, V10, V11, V18, V19, W11, W12, W13, W14, W15, W16, W17, W18
VDD
OVDD
B27, D3, D11, D19, E15, E23, F5, F8, F11, PCI, 10/100 F14, F17, F20, G24, H23, H24, J6, J14, J17, Ethernet, and J18, K4, L9, L20, L23, L25, M6, M9, M20, other P5, P20, P23, R6, R9, R24, U23, V4, V6 Standard (3.3 V) AF19 I
OVDD
MVREF1
DDR Reference Voltage DDR Reference Voltage
MVREF2
AE10
I
No Connection NC V1, V2, V5
Notes: 1. This pin is an open-drain signal. A weak pull-up resistor (1 k) should be placed on this pin to OVDD 2. This pin is an open-drain signal. A weak pull-up resistor (2-10 k) should be placed on this pin to OVDD. 3. During reset, this output is actively driven rather than three-stated. 4. These JTAG pins have weak internal pull-up P-FETs that are always enabled. 5. This pin should have a weak pull-up if the chip is in PCI host mode. Follow the PCI specifications. 6. .This pin must always be tied to GND 7. This pin must always be left not connected 8. Thermal sensitive resistor. 9. It is recommended that MDIC0 be tied to GRD using an 18 resistor and MDIC1 be tied to DDR power using an 18 resistor.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 82 Freescale Semiconductor
Clocking
19 Clocking
Figure 40 shows the internal distribution of the clocks.
MPC8347EA e300 core Core PLL core_clk
csb_clk
to DDR memory controller ddr_clk
System PLL
Clock Unit lbiu_clk
DDR Clock Div /2
6 6
MCK[0:5] MCK[0:5]
DDR Memory Device
/n to local bus memory LBIU controller DLL csb_clk to rest of the device CFG_CLKIN_DIV CLKIN PCI Clock Divider
5
LCLK[0:2] LSYNC_OUT LSYNC_IN PCI_CLK/ PCI_SYNC_IN Local Bus Memory Device
PCI_SYNC_OUT
PCI_CLK_OUT[0:4]
Figure 40. MPC8347EA Clock Subsystem
The primary clock source can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. When the MPC8347EA is configured as a PCI host device, CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (/2) and the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICDn] parameters select whether CLKIN or CLKIN/2 is driven out on the PCI_CLK_OUTn signals. PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN, with equal delay to all PCI agent devices in the system, to allow the MPC8347EA to function. When the MPC8347EA is configured as a PCI agent device, PCI_CLK is the primary input clock and the CLKIN signal should be tied to GND.
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Clocking
As shown in Figure 40, the primary clock input (frequency) is multiplied up by the system phase-locked loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk). The csb_clk frequency is derived from a complex set of factors that can be simplified into the following equation: csb_clk = {PCI_SYNC_IN x (1 + CFG_CLKIN_DIV)} x SPMF In PCI host mode, PCI_SYNC_IN x (1 + CFG_CLKIN_DIV) is the CLKIN frequency. The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low (RCWL), which is loaded at power-on reset or by one of the hard-coded reset options. See the chapter on reset, clocking, and initialization in the MPC8349EA Reference Manual for more information on the clock subsystem. The internal ddr_clk frequency is determined by the following equation: ddr_clk = csb_clk x (1 + RCWL[DDRCM]) ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider (/2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate is the same frequency as ddr_clk. The internal lbiu_clk frequency is determined by the following equation: lbiu_clk = csb_clk x (1 + RCWL[LBIUCM]) lbiu_clk is not the external local bus frequency; lbiu_clk passes through the LBIU clock divider to create the external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LBIU clock divider ratio is controlled by LCCR[CLKDIV]. In addition, some of the internal units may have to be shut off or operate at lower frequency than the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory-mapped register after the device exits reset. Table 56 specifies which units have a configurable clock frequency.
Table 56. Configurable Clock Units
Unit TSEC1 TSEC2, I2C1 Default Frequency Options Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk, csb_clk/2, csb_clk/3 Off, csb_clk
csb_clk/3 csb_clk/3 csb_clk/3 csb_clk/3 csb_clk
Security Core USB DR, USB MPH PCI and DMA complex
Table 57 provides the operating frequencies for the MPC8347EA TBGA under recommended operating conditions (see Table 2).
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Clocking
Table 57. Operating Frequencies for TBGA
Characteristic 1 e300 core frequency (core_clk) Coherent system bus frequency (csb_clk) DDR and DDR2 memory bus frequency (MCLK) 2 Local bus frequency (LCLKn) 3 PCI input frequency (CLKIN or PCI_CLK) Security core maximum internal operating frequency USB_DR, USB_MPH maximum internal operating frequency
1
533 MHz 266-533 100-266
667 MHz 266-667 100-333
Unit MHz MHz
100-200
100-200
MHz
16.67-133
16.67-133
MHz
25-66 133 133
25-66 166 166
MHz MHz MHz
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCLK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value of SCCR[ENCCM], SCCR[USBDRCM]and SCCR[USBMPHCM] must be programmed so that the maximum internal operating frequency of the Security core and USB modules does not exceed the respective values listed in this table. 2 The DDR data rate is 2x the DDR memory bus frequency. 3 The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x the csb_clk frequency (depending on RCWL[LBIUCM]).
Table 58 provides the operating frequencies for the MPC8347EA PBGA under recommended operating conditions.
Table 58. Operating Frequencies for PBGA
Characteristic 1 e300 core frequency (core_clk) Coherent system bus frequency (csb_clk) DDR memory bus frequency (MCLK) 2 Local bus frequency (LCLKn) 3 PCI input frequency (CLKIN or PCI_CLK) Security core maximum internal operating frequency USB_DR, USB_MPH maximum internal operating frequency
1
266 MHz 200-266
333 MHz 200-333 100-266 100-133 16.67-133 25-66 133 133
400 MHz 200-400
Unit MHz MHz MHz MHz MHz MHz MHz
The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCLK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value of SCCR[ENCCM], SCCR[USBDRCM]and SCCR[USBMPHCM] must be programmed so that the maximum internal operating frequency of the Security core and USB modules does not exceed the respective values listed in this table. 2 The DDR data rate is 2x the DDR memory bus frequency. 3 The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x the csb_clk frequency (depending on RCWL[LBIUCM]).
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Clocking
19.1
System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 59 shows the multiplication factor encodings for the system PLL.
Table 59. System PLL Multiplication Factors
RCWL[SPMF] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 System PLL Multiplication Factor x 16 Reserved x2 x3 x4 x5 x6 x7 x8 x9 x 10 x 11 x 12 x 13 x 14 x 15
As described in Section 19, "Clocking," The LBIUCM, DDRCM, and SPMF parameters in the reset configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 60 and Table 61 show the expected frequency values for the CSB frequency for select csb_clk to CLKIN/PCI_SYNC_IN ratios.
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Clocking
Table 60. CSB Frequency Options for Host Mode
Input Clock Frequency (MHz)2 CFG_CLKIN_DIV at reset 1 SPMF csb_clk : Input Clock Ratio 2 16.67 25 33.33 66.67
csb_clk Frequency (MHz) Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low High High High High High High High
1 2
0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0010 0011 0100 0101 0110 0111 1000
2:1 3:1 4:1 5:1 6:1 7:1 8:1 9:1 10 : 1 11 : 1 12 : 1 13 : 1 14 : 1 15 : 1 16 : 1 2:1 3:1 4:1 5:1 6:1 7:1 8:1 100 133 166 200 233 100 116 133 150 166 183 200 216 233 250 266 100 125 150 175 200 225 250 275 300 325 100 133 166 200 233 266 300 333
133 200 266 333
133 200 266 333
CFG_CLKIN_DIV selects the ratio between CLKIN and PCI_SYNC_OUT. CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
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Clocking
Table 61. CSB Frequency Options for Agent Mode
Input Clock Frequency (MHz)2 CFG_CLKIN_DIV at reset 1 SPMF csb_clk : Input Clock Ratio 2 16.67 25 33.33 66.67
csb_clk Frequency (MHz) Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low high High High High High High High
1 2
0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0010 0011 0100 0101 0110 0111 1000
2:1 3:1 4:1 5:1 6:1 7:1 8:1 9:1 10 : 1 11 : 1 12 : 1 13 : 1 14 : 1 15 : 1 16 : 1 4:1 6:1 8:1 10 : 1 12 : 1 14 : 1 16 : 1 100 133 166 200 233 266 100 116 133 150 166 183 200 216 233 250 266 100 150 200 250 300 133 200 266 333 100 125 150 175 200 225 250 275 300 325 100 133 166 200 233 266 300 333
133 200 266 333
266
CFG_CLKIN_DIV doubles csb_clk if set high. CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
19.2
Core PLL Configuration
RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300 core clock (core_clk). Table 62 shows the encodings for RCWL[COREPLL]. COREPLL values that are not listed in Table 62 should be considered as reserved.
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Clocking
NOTE
Core VCO frequency = Core frequency x VCO divider VCO divider must be set properly so that the core VCO frequency is in the range of 800-1800 MHz.
Table 62. e300 Core PLL Configuration
RCWL[COREPLL] core_clk : csb_clk Ratio 0-1 nn 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11
1
VCO divider 1
2-5 0000 0001 0001 0001 0001 0001 0001 0001 0001 0010 0010 0010 0010 0010 0010 0010 0010 0011 0011 0011 0011
6 n 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 PLL bypassed (PLL off, csb_clk clocks core directly) 1:1 1:1 1:1 1:1 1.5:1 1.5:1 1.5:1 1.5:1 2:1 2:1 2:1 2:1 2.5:1 2.5:1 2.5:1 2.5:1 3:1 3:1 3:1 3:1 PLL bypassed (PLL off, csb_clk clocks core directly) 2 4 8 8 2 4 8 8 2 4 8 8 2 4 8 8 2 4 8 8
Core VCO frequency = Core frequency x VCO divider. The VCO divider must be set properly so that the core VCO frequency is in the range of 800-1800 MHz.
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Clocking
19.3
Suggested PLL Configurations
Table 63. Suggested PLL Configurations
Table 63 shows suggested PLL configurations for 33 MHz and 66 MHz input clocks.
Ref No. 1
RCWL
400 MHz Device Input Clock Freq (MHz) 2
533 MHz Device Input Clock Freq (MHz)2
667 MHz Device Input Clock Freq (MHz)2
SPMF
CORE PLL
CSB Freq (MHz)
Core Freq (MHz)
CSB Freq (MHz)
Core Freq (MHz)
CSB Freq (MHz)
Core Freq (MHz)
33 MHz CLKIN/PCI_CLK Options 922 723 604 624 803 823 903 923 704 724 804 705 606 904 805 A04 1001 0111 0110 0110 1000 1000 1001 1001 0111 0111 1000 0111 0110 1001 1000 1010 0100010 0100011 0000100 0100100 0000011 0100011 0000011 0100011 0000011 0100011 0000100 0000101 0000110 0000100 0000101 0000100 -- 33 33 33 33 33 -- 233 200 200 266 266 -- -- -- -- -- -- -- -- -- -- 33 33 33 -- 350 400 400 400 400 -- 33 33 33 33 33 -- 233 200 200 266 266 -- -- 233 233 266 -- -- -- -- -- 66 MHz CLKIN/PCI_CLK Options 304 324 403 423 305 404 306 405 504 0011 0011 0100 0100 0011 0100 0011 0100 0101 0000100 0100100 0000011 0100011 0000101 0000100 0000100 0000101 0000100 66 66 66 66 200 200 266 266 -- -- -- -- -- 400 400 400 400 66 66 66 66 66 66 200 200 266 266 200 266 -- -- -- 400 400 400 400 500 533 66 66 66 66 66 66 66 66 66 200 200 266 266 200 266 200 266 333 400 400 400 400 500 533 600 667 667 466 466 533 300 350 400 400 400 400 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 33 300 233 200 200 266 266 300 300 233 233 266 233 200 300 266 333 300 350 400 400 400 400 450 450 466 466 533 583 600 600 667 667
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Clocking
1
The PLL configuration reference number is the hexadecimal representation of RCWL, bits 4-15 associated with the SPMF and COREPLL settings given in the table. 2 The input clock is CLKIN for PCI host mode or PCI_CLK for PCI agent mode.
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Thermal
20 Thermal
This section describes the thermal specifications of the MPC8347EA.
20.1
Thermal Characteristics
Table 64. Package Thermal Characteristics for TBGA
Characteristic Symbol RJA RJMA RJMA RJMA RJMA RJMA RJB RJC JT Value 14 11 11 8 9 7 3.8 1.7 1 Unit C/W C/W C/W *C/W *C/W *C/W *C/W *C/W *C/W Notes 1, 2 1, 3 1, 3 1, 3 1, 3 1, 3 4 5 6
Table 64 provides the package thermal characteristics for the 672 35 x 35 mm TBGA of the MPC8347EA.
Junction-to-ambient natural convection on single-layer board (1s) Junction-to-ambient natural convection on four-layer board (2s2p) Junction-to-ambient (@200 ft/min) on single-layer board (1s) Junction-to-ambient (@ 200 ft/min) on four-layer board (2s2p) Junction-to-ambient (@ 2 m/s) on single-layer board (1s) Junction-to-ambient (@ 2 m/s) on four-layer board (2s2p) Junction-to-board thermal Junction-to-case thermal Junction-to-package natural convection on top
Notes 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal, 1 m/s is approximately equal to 200 linear feet per minute (LFM). 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
Table 65 provides the package thermal characteristics for the 620 29 x 29 mm PBGA of the MPC8347EA.
Table 65. Package Thermal Characteristics for PBGA
Characteristic Junction-to-ambient natural convection on single layer board (1s) Junction-to-ambient natural convection on four layer board (2s2p) Junction-to-ambient (@200 ft/min) on single layer board (1s) Junction-to-ambient (@ 200 ft/min) on four layer board (2s2p) Junction-to-board thermal Junction-to-case thermal Symbol RJA RJMA RJMA RJMA RJB RJC Value 21 15 17 12 6 5 Unit C/W C/W C/W *C/W *C/W *C/W Notes 1, 2 1, 3 1, 3 1, 3 4 5
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Thermal
Table 65. Package Thermal Characteristics for PBGA (continued)
Characteristic Junction-to-package natural convection on top Symbol JT Value 5 Unit *C/W Notes 6
Notes 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
20.2
Thermal Management Information
For the following sections, PD = (VDD x IDD) + PI/O where PI/O is the power dissipation of the I/O drivers. See Table 5 for I/O power dissipation values.
20.2.1
Estimation of Junction Temperature with Junction-to-Ambient Thermal Resistance
TJ = TA + (RJA x PD) where: TJ = junction temperature (C) TA = ambient temperature for the package (C) RJA = junction to ambient thermal resistance (C/W) PD = power dissipation in the package (W)
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
The junction to ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance. Generally, the value obtained on a single layer board is appropriate for a tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. Test cases have demonstrated that errors of a factor of two (in the quantity TJ - TA) are possible.
20.2.2
Estimation of Junction Temperature with Junction-to-Board Thermal Resistance
The thermal performance of a device cannot be adequately predicted from the junction to ambient thermal resistance. The thermal performance of any component is strongly dependent on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For
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Thermal
many natural convection and especially closed box applications, the board temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device. At a known board temperature, the junction temperature is estimated using the following equation:
TJ = TA + (RJA x PD) where: TA = ambient temperature for the package (C) RJA = junction to ambient thermal resistance (C/W) PD = power dissipation in the package (W)
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes.
20.2.3
Experimental Determination of Junction Temperature
To determine the junction temperature of the device in the application after prototypes are available, use the thermal characterization parameter (JT) to determine the junction temperature and a measure of the temperature at the top center of the package case using the following equation:
TJ = TT + (JT x PD) where: TJ = junction temperature (C) TT = thermocouple temperature on top of package (C) JT = junction to ambient thermal resistance (C/W) PD = power dissipation in the package (W)
The thermal characterization parameter is measured per the JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.
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Thermal
20.2.4
Heat Sinks and Junction-to-Case Thermal Resistance
Some application environments require a heat sink to provide the necessary thermal management of the device. When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case-to-ambient thermal resistance:
RJA = RJC + RCA where: RJA = junction to ambient thermal resistance (C/W) RJC = junction to case thermal resistance (C/W) RCA = case to ambient thermal resistance (C/W)
RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. The thermal performance of devices with heat sinks has been simulated with a few commercially available heat sinks. The heat sink choice is determined by the application environment (temperature, air flow, adjacent component power dissipation) and the physical space available. Because there is not a standard application environment, a standard heat sink is not required. Table 66 and Table 67 show heat sink thermal resistance for TBGA and PBGA of the MPC8347EA.
Table 66. Heat Sink and Thermal Resistance of MPC8347EA (TBGA)
35 x 35 mm TBGA Heat Sink Assuming Thermal Grease AAVID 30 x 30 x 9.4 mm Pin Fin AAVID 30 x 30 x 9.4 mm Pin Fin AAVID 30 x 30 x 9.4 mm Pin Fin AAVID 31 x 35 x 23 mm Pin Fin AAVID 31 x 35 x 23 mm Pin Fin AAVID 31 x 35 x 23 mm Pin Fin Wakefield, 53 x 53 x 25 mm Pin Fin Wakefield, 53 x 53 x 25 mm Pin Fin Wakefield, 53 x 53 x 25 mm Pin Fin MEI, 75 x 85 x 12 no adjacent board, extrusion MEI, 75 x 85 x 12 no adjacent board, extrusion MEI, 75 x 85 x 12 no adjacent board, extrusion MEI, 75 x 85 x 12 mm, adjacent board, 40 mm Side bypass Air Flow Thermal Resistance Natural Convection 1 m/s 2 m/s Natural Convection 1 m/s 2 m/s Natural Convection 1 m/s 2 m/s Natural Convection 1 m/s 2 m/s 1 m/s 10 6.5 5.6 8.4 4.7 4 5.7 3.5 2.7 6.7 4.1 2.8 3.1
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Thermal
f
Table 67. Heat Sink and Thermal Resistance of MPC8347EA (PBGA)
29 x 29 mm PBGA Heat Sink Assuming Thermal Grease AAVID 30 x 30 x 9.4 mm Pin Fin AAVID 30 x 30 x 9.4 mm Pin Fin AAVID 30 x 30 x 9.4 mm Pin Fin AAVID 31 x 35 x 23 mm Pin Fin AAVID 31 x 35 x 23 mm Pin Fin AAVID 31 x 35 x 23 mm Pin Fin Wakefield, 53 x 53 x 25 mm Pin Fin Wakefield, 53 x 53 x 25 mm Pin Fin Wakefield, 53 x 53 x 25 mm Pin Fin MEI, 75 x 85 x 12 no adjacent board, extrusion MEI, 75 x 85 x 12 no adjacent board, extrusion MEI, 75 x 85 x 12 no adjacent board, extrusion MEI, 75 x 85 x 12 mm, adjacent board, 40 mm Side bypass Air Flow Thermal Resistance Natural Convection 1 m/s 2 m/s Natural Convection 1 m/s 2 m/s Natural Convection 1 m/s 2 m/s Natural Convection 1 m/s 2 m/s 1 m/s 13.5 9.6 8.8 11.3 8.1 7.5 9.1 7.1 6.5 10.1 7.7 6.6 6.9
Accurate thermal design requires thermal modeling of the application environment using computational fluid dynamics software which can model both the conduction cooling and the convection cooling of the air moving through the application. Simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More detailed thermal models can be made available on request. Heat sink vendors include the following list:
Aavid Thermalloy 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.com Alpha Novatech 473 Sapena Ct. #12 Santa Clara, CA 95054 Internet: www.alphanovatech.com International Electronic Research Corporation (IERC) 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com 603-224-9988
408-567-8082
818-842-7277
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Thermal
Millennium Electronics (MEI) Loroco Sites 671 East Brokaw Road San Jose, CA 95112 Internet: www.mei-thermal.com Tyco Electronics Chip CoolersTM P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com
408-436-8770
800-522-2800
603-635-5102
Interface material vendors include the following:
Chomerics, Inc. 77 Dragon Ct. Woburn, MA 01801 Internet: www.chomerics.com Dow-Corning Corporation Dow-Corning Electronic Materials P.O. Box 994 Midland, MI 48686-0997 Internet: www.dowcorning.com Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com The Bergquist Company 18930 West 78th St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com 781-935-4850
800-248-2481
888-642-7674
800-347-4572
20.3
Heat Sink Attachment
When heat sinks are attached, an interface material is required, preferably thermal grease and a spring clip. The spring clip should connect to the printed circuit board, either to the board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces that can lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint lifetime of the package. The recommended maximum force on the top of the package is 10 lb force (4.5 kg force). Any adhesive attachment should attach to painted or plastic surfaces, and its performance should be verified under the application requirements.
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Thermal
20.3.1
Experimental Determination of the Junction Temperature with a Heat Sink
When a heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimize the size of the clearance to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction to case thermal resistance.
TJ = TC + (RJC x PD) where: TJ = junction temperature (C) TC = case temperature of the package (C) RJC = junction to case thermal resistance (C/W) PD = power dissipation (W)
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System Design Information
21 System Design Information
This section provides electrical and thermal design recommendations for successful application of the MPC8347EA.
21.1
System Clocking
The MPC8347EA includes two PLLs. 1. The platform PLL (AVDD1) generates the platform clock from the externally supplied CLKIN input. The frequency ratio between the platform and CLKIN is selected using the platform PLL ratio configuration bits as described in Section 19.1, "System PLL Configuration." 2. The e300 Core PLL (AVDD2) generates the core clock as a slave to the platform clock. The frequency ratio between the e300 core clock and the platform clock is selected using the e300 PLL ratio configuration bits as described in Section 19.2, "Core PLL Configuration."
21.2
PLL Power Supply Filtering
Each PLL gets power through independent power supply pins (AVDD1, AVDD2 respectively). The AVDD level should always equal to VDD, and preferably these voltages are derived directly from VDD through a low frequency filter scheme. There are a number of ways to provide power reliably to the PLLs, but the recommended solution is to provide five independent filter circuits as illustrated in Figure 41, one to each of the five AVDD pins. Independent filters to each PLL reduce the opportunity to cause noise injection from one PLL to the other. The circuit filters noise in the PLL resonant frequency range from 500 kHz to 10 MHz. It should be built with surface mount capacitors with minimum effective series inductance (ESL). Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. To minimize noise coupled from nearby circuits, each circuit should be placed as closely as possible to the specific AVDD pin being supplied. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of package, without the inductance of vias. Figure 41 shows the PLL power supply filter circuit.
10 VDD 2.2 F 2.2 F Low ESL Surface Mount Capacitors AVDD (or L2AVDD)
GND
Figure 41. PLL Power Supply Filter Circuit
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System Design Information
21.3
Decoupling Recommendations
Due to large address and data buses and high operating frequencies, the MPC8347EA can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC8347EA system, and the MPC8347EA itself requires a clean, tightly regulated source of power. Therefore, the system designer should place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pin of the MPC8347EA. These capacitors should receive their power from separate VDD, OVDD, GVDD, LVDD, and GND power planes in the PCB, with short traces to minimize inductance. Capacitors can be placed directly under the device using a standard escape pattern. Others can surround the part. These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes. In addition, distribute several bulk storage capacitors around the PCB, feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors are 100-330 F (AVX TPS tantalum or Sanyo OSCON).
21.4
Connection Recommendations
To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins of the MPC8347EA.
21.5
Output Buffer DC Impedance
The MPC8347EA drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I2C). To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 42). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN)/2.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 100 Freescale Semiconductor
System Design Information
OVDD
RN
SW2 Data Pad SW1
RP
OGND
Figure 42. Driver Impedance Measurement
Two measurements give the value of this resistance and the strength of the driver current source. First, the output voltage is measured while driving logic 1 without an external differential termination resistor. The measured voltage is V1 = Rsource x Isource. Second, the output voltage is measured while driving logic 1 with an external precision differential termination resistor of value Rterm. The measured voltage is V2 = (1/(1/R1 + 1/R2)) x Isource. Solving for the output impedance gives Rsource = Rterm x (V1/V2 - 1). The drive current is then Isource = V1/Rsource. Table 68 summarizes the signal impedance targets. The driver impedance are targeted at minimum VDD, nominal OVDD, 105C.
Table 68. Impedance Characteristics
Local Bus, Ethernet, DUART, Control, Configuration, Power Management 42 Target 42 Target NA PCI Signals (not including PCI output clocks) 25 Target 25 Target NA PCI Output Clocks (including PCI_SYNC_OUT) 42 Target 42 Target NA
Impedance
DDR DRAM
Symbol
Unit
RN RP Differential
20 Target 20 Target NA
Z0 Z0 ZDIFF

Note: Nominal supply voltages. See Table 1, Tj = 105C.
21.6
Configuration Pin Multiplexing
The MPC8347EA power-on configuration options can be set through external pull-up or pull-down resistors of 4.7 k on certain output pins (see the customer-visible configuration pins). These pins are used as output only pins in normal operation. However, while HRESET is asserted, these pins are treated as inputs, and the value on these pins is latched when PORESET deasserts. Then the input receiver is disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 101
System Design Information
the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed for the output pins.
21.7
Pull-Up Resistor Requirements
The MPC8347EA requires high resistance pull-up resistors (10 k is recommended) on open-drain pins, including I2C pins, the Ethernet Management MDIO pin, and EPIC interrupt pins. Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 43. Take care to ensure that these pins are maintained at a valid deasserted state under normal operating conditions because most have asynchronous behavior, and spurious assertion yields unpredictable results. Refer to the PCI 2.3 specification for all pull-ups required for PCI.
21.8
JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE Std. 1149.1 specification, but it is provided on all processors that implement the PowerPC architecture. The MPC8347EA requires TRST to be asserted during reset conditions to ensure that the JTAG boundary logic does not interfere with normal chip operation. While the TAP controller may be forced to the reset state using only the TCK and TMS signals, systems typically assert TRST during power-on reset. Because the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying TRST to PORESET is not practical. The PowerPC COP function allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to assert TRST independently without causing PORESET. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 43 allows the COP to assert HRESET or TRST independently, while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header are not used, TRST should be tied to PORESET so that it is asserted when the system reset signal (PORESET) is asserted. The COP header shown in Figure 43 adds many benefits--breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features. It requires no more effort than adding an unpopulated footprint for a header when needed. The COP interface has a standard header for connection to the target system, based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). There is no standardized way to number the header, shown in Figure 43, so emulator vendors use different pin numbering schemes. Some headers are numbered top-to-bottom then left-to-right, others use left-to-right then top-to-bottom, and still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering scheme, the signal placement recommended in Figure 43 is common to all known emulators.
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 102 Freescale Semiconductor
System Design Information
PORESET From Target Board Sources (if any) SRESET HRESET 10 k
PORESET SRESET HRESET
13 11
HRESET SRESET
OVDD OVDD 10 k OVDD 10 k OVDD 10 k TRST
1 3 5 7 9 11
2 4 6 8 10 12
4 61 5 15
TRST VDD_SENSE NC CHKSTP_OUT 10 k 2 k
OVDD
CHKSTP_OUT OVDD 10 k OVDD
14 COP Header
2
KEY 13 No pin
CHKSTP_IN 8 TMS 9 1 3 7 2 10 12 16 NC NC NC TDO TDI TCK TCK TMS TDO TDI CHKSTP_IN
15
16
COP Connector Physical Pin Out
Notes: 1. Some systems require power to be fed from the application board into the debugger repeater card via the COP header. The resistor value for VDD_SENSE should be around 20 . 2. Key location; pin 14 is not physically present on the COP header.
Figure 43. JTAG Interface Connection
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 103
Document Revision History
22 Document Revision History
Table 66 provides a revision history of this document.
Table 69. Document Revision History
Revision 3 Date 11/2006 Substantive Change(s) Updated note in introduction. In Table 5, "MPC8347EA Typical I/O Power Dissipation," added GVDD 1.8-V values for DDR2; added table footnote to designate rates that apply only to the TBGA package. In the features list in Section 1, "Overview," corrected DDR data rate to show: * 266 MHz for PBGA parts for all silicon revisions 400 MHz for DDR2 for TBGA parts for silicon Rev. 2 and 3In Section 23, "Ordering Information," replicated note from document introduction. Changed all references to revision 2.0 silicon to revision 3.0 silicon. Changed VIH minimum value in Table 39, "JTAG Interface DC Electrical Characteristics," to OVDD - 0.3. In Table 63, "Suggested PLL Configurations," deleted reference-number rows 902 and 703. In Table 40, "PCI DC Electrical Characteristics," changed high-level input voltage values to min = 2 and max = OVDD + 0.3; changed low-level input voltage values to min = (-0.3) and max = 0.8. In Table 44, "PCI DC Electrical Characteristics," changed high-level input voltage values to min = 2 and max = OVDD + 0.3; changed low-level input voltage values to min = (-0.3) and max = 0.8. Updated DDR2 I/O power values in Table 5, "MPC8347EA Typical I/O Power Dissipation." Removed Table 20, "Timing Parameters for DDR2-400." Changed ADDR/CMD to ADDR/CMD/MODT in Table 9, "DDR and DDR2 SDRAM Output AC Timing Specifications," rows 2 and 3, and in Figure 2, "DDR SDRAM Output Timing Diagram. Changed Min and Max values for VIH and VIL in Table 40,"PCI DC Electrical Characteristics." In Table 51, "MPC8347EA (TBGA) Pinout Listing," and Table 52, "MPC8347EA (PBGA) Pinout Listing," modified rows for MDICO and MDIC1 signals and added note "It is recommended that MDICO be tied to GRD using an 18 resistor and MCIC1 be tied to DDR power using an 18 resistor." In Table 51, "MPC8347EA (TBGA) Pinout Listing," and Table 52, "MPC8347EA (PBGA) Pinout Listing," in row AVDD3 changed power supply from "AVDD3" to "--." Initial Release
2
8/2006
1
4/2006
0
3/2006
23 Ordering Information
This section presents ordering information for the device discussed in this document, and it shows an example of how the parts are marked. The information in this document is accurate for revision 3.x silicon and later (in other words, for devices with part numbers ending in A or B, such as the MPC8347EA or MPC8347EB). For information on revision 1.1 silicon and earlier versions (MPC8347E/MPC8347), see the PowerQUICCTM II Pro Integrated Host Processor Hardware Specifications
23.1
Part Numbers Fully Addressed by this Document
Table 67 shows an analysis of the Freescale part numbering nomenclature for the MPC8347EA. The individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. Also the part numbering scheme includes an application modifier
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 104 Freescale Semiconductor
Ordering Information
to specify special application conditions. Each part number also contains a revision code that refers to the die mask revision number.
Table 70. Part Numbering Nomenclature
MPC nnnn
Product Part Code Identifier MPC 8347
e
Encryption Acceleration Blank = Not included E = included
t
Temperature1 Range Blank = 0 to 105C C= -40 to 105C
pp
Package 2 ZU =TBGA VV = PB free TBGA ZQ = PBGA VR = PB Free PBGA
aa
Processor Frequency 3 e300 core speed AD =266 AG = 400 AJ = 533 AL = 667
a
Platform Frequency D = 266 F = 333
r
Revision Level B = 3.1
Notes: 1. For temperature range = C, processor frequency is limited to 400 with a platform frequency of 266. 2. See Section 17, "Package and Pin Listings" for more information on available package types. 3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other maximum core frequencies.
Table 68 shows the SVR settings by device and package type.
Table 71. SVR Settings
Device MPC8347EA MPC8347A MPC8347EA MPC8347A Package TBGA TBGA PBGA PBGA SVR (Rev. 3.0) 8052_0030 8053_0030 8054_0030 8055_0030
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 105
Ordering Information
23.2
Part Marking
Parts are marked as in the example shown in Figure 44.
MPCnnnnetppaaar core/platform MHZ ATWLYYWW CCCCC *MMMMM Notes: YWWLAZ
TBGA/PBGA
ATWLYYWW is the traceability code. CCCCC is the country code. MMMMM is the mask number. YWWLAZ is the assembly traceability code.
Figure 44. Freescale Part Marking for TBGA or PBGA Devices
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 106 Freescale Semiconductor
Ordering Information
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MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 107
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Document Number: MPC8347EAEC Rev. 3 11/2006

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