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| Low Power, Low Noise and Distortion, Rail-to-Rail Output Amplifier ADA4841-1/ADA4841-2 FEATURES Low power: 1.1 mA/amp Low wideband noise 2.1 nV/Hz 1.4 pA/Hz Low 1/f noise 7 nV/Hz @ 10 Hz 13 pA/Hz @ 10 Hz Low distortion: -105 dBc @ 100 kHz, VO = 2 V p-p High speed 80 MHz, -3 dB bandwidth (G = +1) 12 V/s slew rate 175 ns settling time to 0.1% Low offset voltage: 0.3 mV maximum Rail-to-rail output Power down Wide supply range: 2.7 V to 12 V CONNECTION DIAGRAMS ADA4841-1 TOP VIEW NC 1 (Not to Scale) 8 POWER DOWN -IN 2 +IN 3 -VS 4 7 +VS 05614-001 6 VOUT 5 NC Figure 1. 8-Lead SOIC (R) ADA4841-2 OUT1 1 -IN1 2 +IN1 3 -VS 4 TOP VIEW (Not to Scale) 8 7 6 5 +VS OUT2 -IN2 +IN2 05614-064 Figure 2. 8-Lead MSOP (RM-8) and 8-Lead SOIC_N (R) ADA4841-1 VOUT 1 6 +VS POWER DOWN -IN 05614-099 APPLICATIONS Low power, low noise signal processing Battery-powered instrumentation 16-bit PulSAR(R) ADC drivers -VS 2 +IN 3 5 4 Figure 3. 6-Lead SOT-23 (RJ) GENERAL DESCRIPTION The ADA4841-1/ADA4841-2 are unity gain stable, low noise and distortion, rail-to-rail output amplifiers that have a quiescent current of 1.5 mA maximum. Despite their low power consumption, these amplifiers offer low wideband voltage noise performance of 2.1 nV/Hz and 1.4 pA/Hz current noise, along with excellent spurious-free dynamic range (SFDR) of -105 dBc at 100 kHz. To maintain a low noise environment at lower frequencies, the amplifiers have low 1/f noise of 7 nV/Hz and 13 pA/Hz at 10 Hz. The ADA4841-1/ADA4841-2 output can swing to less than 50 mV of either rail. The input common-mode voltage range extends down to the negative supply. The ADA4841-1/ ADA4841-2 can drive up to 10 pF of capacitive load with minimal peaking. The ADA4841-1/ADA4841-2 provide the performance required to efficiently support emerging 16-bit to 18-bit ADCs and are ideal for portable instrumentation, high channel count, industrial measurement, and medical applications. The ADA4841-1/ ADA4841-2 are ideally suited to drive the AD7685/AD7686, 16-bit PulSAR ADCs. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. The ADA4841-1/ADA4841-2 packages feature Pb-free lead finish. The amplifiers are rated to work over the industrial temperature range (-40C to +125C). -30 -40 VS = 5V G = +1 HARMONIC DISTORTION (dBc) -50 -60 -70 2V p-p THIRD -80 -90 -100 -110 -120 0.01 2V p-p SECOND 05614-048 0.1 FREQUENCY (MHz) 1 Figure 4. Harmonic Distortion One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. ADA4841-1/ADA4841-2 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Connection Diagrams...................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution.................................................................................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 13 Amplifier Description................................................................ 13 DC Errors .................................................................................... 13 Noise Considerations ................................................................. 13 Headroom Considerations........................................................ 14 Capacitance Drive ...................................................................... 15 Input Protection ......................................................................... 15 Power-Down Operation ............................................................ 16 Applications..................................................................................... 17 Typical Performance Values...................................................... 17 16-Bit ADC Driver..................................................................... 17 Reconstruction Filter ................................................................. 17 Layout Considerations............................................................... 18 Ground Plane.............................................................................. 18 Power Supply Bypassing ............................................................ 18 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 20 REVISION HISTORY 3/06--Rev. B to Rev. C Added SOT-23 Package .....................................................Universal Changes to General Description .................................................... 1 Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 4 Changes to Table 3............................................................................ 5 Changes to Input Protection Section ........................................... 15 Changes to Ordering Guide .......................................................... 20 10/05--Rev. A to Rev. B Added ADA4841-2.............................................................Universal Changes to General Description and Features ............................. 1 Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 4 Changes to Table 3............................................................................ 5 Changes to Table 4, Table 5, and Figure 4 ..................................... 6 Changes to Figure 6.......................................................................... 7 Changes to Figure 12, Figure 13, Figure 15, and Figure 16......... 8 Deleted Figure 25; Renumber Sequentially................................. 10 Changes to Figure 24 and Figure 28............................................. 10 Changes to Figure 31...................................................................... 11 Inserted Figure 37; Renumber Sequentially................................ 12 Changes to Amplifier Description Section and Figure 39 ........ 13 Changed DC Performance Considerations Section to DC Errors Section...................................................................... 13 Changes to Noise Considerations Section .................................. 14 Changes to Headroom Considerations Section and Figure 39 15 Changes to Power-Down Operation Section.............................. 16 Changes to 16-Bit ADC Driver Section, Figure 48, and Figure 49 ................................................................ 17 Changes to Power Supply Bypassing Section ............................. 18 Updated Outline Dimensions....................................................... 19 Changes to Ordering Guide .......................................................... 20 9/05--Rev. 0 to Rev. A Changes to Features ..........................................................................1 Changes to Figure 2...........................................................................1 Changes to Figure 12.........................................................................8 Changes to Figure 40...................................................................... 14 Changes to Headroom Considerations Section ......................... 15 7/05--Revision 0: Initial Version Rev. C | Page 2 of 20 ADA4841-1/ADA4841-2 SPECIFICATIONS TA = 25C, VS = 5 V, RL = 1 k, Gain = +1, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Slew Rate Settling Time to 0.1% Settling Time to 0.01% NOISE/HARMONIC PERFORMANCE Harmonic Distortion HD2/HD3 Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance, Common Mode Input Resistance, Differential Mode Input Capacitance, Common Mode Input Capacitance, Differential Mode Input Common-Mode Voltage Range Common-Mode Rejection Ratio (CMRR) MATCHING CHARACTERISTICS (ADA4841-2) Input Offset Voltage Input Bias Current POWER DOWN PIN (ADA4841-1) POWER DOWN Voltage POWER DOWN Voltage Input Current Enable Power Down Switching Speed Enable Power Down OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Limit Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current/Amplifier Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Conditions VO = 0.02 V p-p VO = 2 V p-p G = +1, VO = 9 V step, RL = 1 k G = +1, VO = 8 V step G = +1, VO = 8 V step fC = 100 kHz, VO = 2 V p-p, G = +1 fC = 1 MHz, VO = 2 V p-p f = 100 kHz f = 100 kHz Min 58 12 Typ 80 3 13 650 1000 -111/-105 -80/-67 2.1 1.4 40 1 3 0.1 120 90 25 1 3 VCM = 4 V -5.1 95 +4 115 70 60 Enabled Power down POWER DOWN = +5 V POWER DOWN = -5 V >3.6 <3.2 1 -13 1 40 G > +1 Sourcing, VIN = +VS , RL = 50 to GND Sinking, VIN = -VS , RL = 50 to GND 30% overshoot 4.9 4.955 30 60 15 12 1.5 90 2 -30 300 5.3 0.5 Max Unit MHz MHz V/s ns ns dBc dBc nV/Hz pA/Hz V V/C A A dB M k pF pF V dB V nA V V A A s s V mA mA pF V mA A dB dB VO = 4 V 103 2.7 POWER DOWN = +5 V POWER DOWN = -5 V +VS = +5 V to +6 V, -VS = -5 V +VS = +5 V, -VS = -5 V to +6 V 1.2 40 110 120 95 96 Rev. C | Page 3 of 20 ADA4841-1/ADA4841-2 TA = 25C, VS = 5 V, RL = 1 k, Gain = +1, VCM = 2.5 V, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Slew Rate Settling Time to 0.1% Settling Time to 0.01% NOISE/HARMONIC PERFORMANCE Harmonic Distortion HD2/HD3 Input Voltage Noise Input Current Noise Crosstalk DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance, Common Mode Input Resistance, Differential Mode Input Capacitance, Common Mode Input Capacitance, Differential Mode Input Common-Mode Voltage Range Common-Mode Rejection Ratio (CMRR) MATCHING CHARACTERISTICS (ADA4841-2) Input Offset Voltage Input Bias Current POWER DOWN PIN (ADA4841-1) POWER DOWN Voltage POWER DOWN Voltage Input Current Enable Power Down Switching Speed Enable Power Down OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Limit Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current/Amplifier Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Conditions VO = 0.02 V p-p VO = 2 V p-p G = +1, VO = 4 V step, RL = 1 k G = +1, VO = 2 V step G = +1, VO = 2 V step fC = 100 kHz, VO = 2 V p-p fC = 1 MHz, VO = 2 V p-p f = 100 kHz f = 100 kHz f = 100 kHz Min 54 10 Typ 80 3 12 175 550 -109/-105 -78/-66 2.1 1.4 -117 40 1 3 0.1 124 90 25 1 3 VCM = 1.5 V -0.1 88 +4 115 70 70 Enabled Power down POWER DOWN = 5 V POWER DOWN = 0 V >3.6 <3.2 1 -13 1 40 G > +1 Sourcing, VIN = +VS, RL = 50 to VCM Sinking, VIN = -VS, RL = 50 to VCM 30% overshoot 0.08 to 4.92 0.029 to 4.974 30 60 15 12 1.4 70 2 -30 300 5.3 0.4 Max Unit MHz MHz V/s ns ns dBc dBc nV/Hz pA/Hz dB V V/C A A dB M k pF pF V dB V nA VO = 0.5 V to 4.5 V 103 V A A s s V mA mA pF V mA A dB dB 2.7 POWER DOWN = 5 V POWER DOWN = 0 V +VS = +5 V to +6 V, -VS = 0 V +VS = +5 V, -VS = 0 V to -1 V 1.1 35 110 120 95 96 Rev. C | Page 4 of 20 ADA4841-1/ADA4841-2 TA = 25C, VS = 3 V, RL = 1 k, Gain =+1, VCM = 1.5 V, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Slew Rate Settling Time to 0.1% Settling Time to 0.01% NOISE/HARMONIC PERFORMANCE Harmonic Distortion HD2/HD3 Input Voltage Noise Input Current Noise DC PERFORMANCE Input Offset Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Open-Loop Gain INPUT CHARACTERISTICS Input Resistance, Common Mode Input Resistance, Differential Mode Input Capacitance, Common Mode Input Capacitance, Differential Mode Input Common-Mode Voltage Range Common-Mode Rejection Ratio (CMRR) MATCHING CHARACTERISTICS (ADA4841-2) Input Offset Voltage Input Bias Current POWER DOWN PIN (ADA4841-1) POWER DOWN Voltage POWER DOWN Voltage Input Current Enable Power Down Switching Speed Enable Power Down OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Limit Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current/Amplifier Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Conditions VO = 0.02 V p-p G = +1, VO = 2 V step, RL = 1 k G = +1, VO = 1 V step G = +1, VO = 1 V step fC = 100 kHz, VO = 1 V p-p fC = 1 MHz, VO = 1 V p-p f = 100 kHz f = 100 kHz Min 52 10 Typ 80 12 120 250 -97/-100 -79/-80 2.1 1.4 40 1 3 0.1 123 90 25 1 3 VCM = 0.4 V -0.1 86 +2 115 70 60 Enabled Power down POWER DOWN = 3 V POWER DOWN = 0 V >1.6 <1.2 1 -10 1 40 G > +1 Sourcing, VIN = +VS, RL = 50 to VCM Sinking, VIN = -VS, RL = 50 to VCM 30% overshoot 0.045 to 2.955 0.023 to 2.988 30 60 30 12 1.3 60 2 -30 300 5.3 0.5 Max Unit MHz V/s ns ns dBc dBc nV/Hz pA/Hz V V/C A A dB M k pF pF V dB V nA VO = 0.5 V to 2.5 V 101 V A A s s V mA mA pF V mA A dB dB 2.7 POWER DOWN = 3 V POWER DOWN = 0 V +VS = +3 V to +4 V, -VS = 0 V +VS = +3 V, -VS = 0 V to -1 V 1.1 25 110 120 95 96 Rev. C | Page 5 of 20 ADA4841-1/ADA4841-2 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Supply Voltage Power Dissipation Common-Mode Input Voltage Differential Input Voltage Storage Temperature Range Operating Temperature Range Lead Temperature Junction Temperature Rating 12.6 V See Figure 5 -VS - 0.5 V to +VS + 0.5 V 1.8 V -65C to +125C -40C to +85C JEDEC J-STD-20 150C The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the die due to the amplifier's drive at the output. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). PD = Quiescent Power + (Total Drive Power - Load Power) V V PD = (VS x I S ) + S x OUT 2 RL VOUT 2 - RL Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RMS output voltages should be considered. If RL is referenced to -VS, as in single-supply operation, the total drive power is VS x IOUT. If the rms signal levels are indeterminate, consider the worst case, when VOUT = VS/4 for RL to midsupply. PD = (VS x I S ) + (VS /4 )2 RL THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, JA is specified for device soldered in circuit board for surface-mount packages. Table 5. Thermal Resistance Package Type 8-lead SOIC_N 8-lead MSOP 6-Lead SOT-23 JA 125 130 170 Unit C/W C/W C/W In single-supply operation with RL referenced to -VS, worst case is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing JA. In addition, more metal directly in contact with the package leads and through holes under the device reduces JA. Figure 5 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8-lead MSOP (145C/W), 8-lead SOIC_N (125C/W) and the 6-lead SOT-23 (170C/W) on a JEDEC standard 4-layer board. JA values are approximations. 2.0 Maximum Power Dissipation The maximum safe power dissipation for the ADA4841-1/ ADA4841-2 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the amplifiers. Exceeding a junction temperature of 150C for an extended period can result in changes in silicon devices, potentially causing degradation or loss of functionality. MAXIMUM POWER DISSIPATION (W) 1.5 SOIC 1.0 MSOP SOT-23 0.5 05614-061 0 -55 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 AMBIENT TEMPERATURE (C) Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 6 of 20 ADA4841-1/ADA4841-2 TYPICAL PERFORMANCE CHARACTERISTICS RL = 1 k, unless otherwise noted. 3 VOUT = 2V pp VS = 5V 3 G = +1 VS = 5V VIN = 20mV p-p G = +1 -40C +25C NORMALIZED CLOSED-LOOP GAIN (dB) 0 0 -3 G = +10 G = +2 -6 GAIN (dB) +125C -3 -6 -9 05614-021 05614-028 -12 0.1 1 FREQUENCY (MHz) 10 -9 0.1 1 10 FREQUENCY (MHz) 100 Figure 6. Large Signal Frequency Response vs. Gain 6 VIN = 20mV p-p G = +1 VS = 5V 20pF 20pF WITH 100 SNUBBER Figure 9. Small Signal Frequency Response vs. Temperature 2 1 0 VIN = 20mV p-p G = +1 VS = +5V VS = +3V VS = 5V 3 CLOSED-LOOP GAIN (dB) GAIN (dB) 05614-026 0 0pF -3 -1 -2 -3 -4 05614-029 10pF -6 -5 -6 0.1 -9 0.1 1 10 FREQUENCY (MHz) 100 1 10 FREQUENCY (MHz) 100 Figure 7. Small Signal Frequency Response vs. Capacitive Load 3 VIN = 20mV p-p VS = 5V G = -1 Figure 10. Small Signal Frequency Response vs. Supply Voltage 3 VS = 5V G = +1 NORMALIZED CLOSED-LOOP GAIN (dB) G = +1 10mV p-p 0 G = +10 -3 0 GAIN (dB) -3 2V p-p 400mV p-p 20mV p-p -6 -6 -9 05614-027 100mV p-p 05614-014 -12 0.1 1 10 FREQUENCY (MHz) 100 -9 0.1 1 10 FREQUENCY (MHz) 100 Figure 8. Small Signal Frequency Response vs. Gain Figure 11. Frequency Response for Various VOUT Rev. C | Page 7 of 20 ADA4841-1/ADA4841-2 140 120 100 80 60 40 20 0 -20 10 PHASE MAGNITUDE VS = 5V 0 -20 -30 -40 OPEN-LOOP PHASE (Degrees) VOUT = 2V p-p G = +2 +5V SECOND OPEN-LOOP GAIN (dB) -40 -60 -80 -100 -120 -140 -160 100M HARMONIC DISTORTION (dBc) -50 -60 -70 -80 -90 -100 -110 -120 -130 0.01 5V SECOND 0.1 +3V THIRD +3V SECOND 5V THIRD 05614-047 +5V THIRD 100 1k 10k 100k 1M 10M 05614-042 FREQUENCY (Hz) 1 FREQUENCY (MHz) Figure 12. Open-Loop Gain and Phase vs. Frequency -30 -40 Figure 15. Harmonic Distortion vs. Frequency for Various Supplies 10 VS = 5V VS = + 5V VOUT = 2V p-p HARMONIC DISTORTION (dBc) -50 -60 -70 -80 -90 -100 -110 -120 -130 0.01 0.1 FREQUENCY (MHz) G = +2 SECOND G = +5 SECOND G = +1 SECOND G = +1 THIRD 05614-045 VOLTAGE NOISE (nV/ Hz) G = +5 THIRD G = +2 THIRD 1 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 13. Harmonic Distortion vs. Frequency for Various Gains -30 -40 Figure 16. Voltage Noise vs. Frequency 100 VS = 5V VS = 5V G = +1 8V p-p SECOND HARMONIC DISTORTION (dBc) -50 8V p-p THIRD -60 -70 -80 -90 -100 05614-046 CURRENT NOISE (pA/ Hz) 10 4V p-p THIRD 4V p-p SECOND 1 -120 0.01 2V p-p SECOND 0.1 FREQUENCY (MHz) 1 0.1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 14. Harmonic Distortion vs. Frequency for Various Output Voltages Figure 17. Current Noise vs. Frequency Rev. C | Page 8 of 20 05614-018 -110 2V p-p THIRD 05614-034 ADA4841-1/ADA4841-2 55 COUNT = 190 50 x = 0.36V/C = 1.21V/C 45 OUTPUT VOLTAGE (V) 0.25 G = +2 TIME = 50ns/DIV VS = +5V 0.23 VS = 5V 0.22 VS = +3V 0.24 NUMBER OF PARTS 40 35 30 25 20 15 10 5 0 -5 -4 -2 0 2 4 6 05614-053 0.21 0.20 05614-033 0.19 OFFSET DRIFT DISTRIBUTION (V/C) Figure 18. Input Offset Voltage Drift Distribution 10 9 8 G = +1 VS = 5V Figure 21. Small Signal Transient Response for Various Supplies 0.15 G = +2 VIN = 20mV p-p TIME = 50ns/DIV 0pF 0.13 0.14 OUTPUT VOLTAGE (V) NONLINEARITY (V) 7 6 5 4 3 2 10pF 0.12 0.11 0 0 1 2 VIN (V) 3 4 5 0.09 Figure 19. Nonlinearity vs. VIN 100 80 60 VOFFSET (V) Figure 22. Small Signal Transient Response for Various Capacitive Loads 0.130 0.125 0.120 VS = 5 G = +1 TIME = 50ns/DIV VS = 3V OUTPUT VOLTAGE (V) 40 20 0 -20 05614-036 0.115 0.110 0.105 0.100 VS = 5V -60 -6 0.090 -4 -2 0 VOUT (V) 2 4 6 Figure 20. Input Error Voltage vs. Output Voltage Figure 23. Small Signal Transient Response for Various Supplies Rev. C | Page 9 of 20 05614-030 -40 0.095 05614-031 1 05614-013 0.10 20pF 47pF ADA4841-1/ADA4841-2 6 5 VOUT 4 3 2 1 0 -1 VIN VS = 5V G = +1 TIME = 200ns/DIV 4.5 4.0 3.5 G = +2 VS = 5 TIME = 100ns/DIV +125C 3.0 2.5 -40C 2.0 1.5 1.0 05614-019 INPUT AND OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) +25C 0 Figure 24. Input Overdrive Recovery Figure 27. Slew Rate vs. Temperature 6 5 4 3 2 1 0 -1 VIN 2 VOUT VS = 5V G = +2 TIME = 100ns/DIV 2.0 1.5 1.0 INPUT AND OUTPUT VOLTAGE (V) VS = 5V G = +1 VOUT = 2V p-p TIME = 100ns/DIV VOUT 2.0 1.5 1.0 0.5 0 -0.5 -1.0 05614-041 EXPANDED V OUT (mV) 05614-016 0.5 0.5 0 -0.5 -1.0 VIN VOUT (EXPANDED) 05614-023 -1.5 -2.0 -1.5 -2.0 Figure 25. Output Overdrive Recovery 6 Figure 28. Settling Time 1.2 POWER DOWN PIN 5 4 -40C 3 2 1 0 -1 VS = 5V G = +1 VIN = 1VDC TIME = 200ns/DIV +125C +25C 1.0 0.8 1.5 1.0 VS = 5V VOUT = 2V p-p TIME = 100ns/DIV OUTPUT VOLTAGE (V) 0.5 G = +1 0 POWER DOWN PIN (V) G = +2 0.4 0.2 0 -0.2 -0.5 -1.5 05614-022 Figure 26. Large Signal Transient Response for Various Gains Figure 29. Power-Up Time vs. Temperature Rev. C | Page 10 of 20 05614-039 -1.0 VOUT (V) 0.6 VIN AND V OUT (V) ADA4841-1/ADA4841-2 6 5 4 3 +125C 2 1 0 -1 POWER DOWN PIN +25C -40C 0.4 0.2 0 -0.2 POWER DOWN PIN 1.2 VS = 5V G = +1 VIN = 1VDC 1.0 TIME = 10s/DIV 0.8 VOUT (V) 0.6 0 VS = 5V POWER SUPPLY REJECTION (dB) -20 POWER DOWN PIN (V) -40 +PSR -60 -80 -PSR -100 05614-025 05614-040 -120 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 30. POWER DOWN Time vs. Temperature 1.6 1.4 Figure 33. PSR vs. Frequency 100 VS = 5V +125C VS = 5V CLOSED-LOOP OUTPUT IMPEDANCE () SUPPLY CURRENT/AMPLIFIER (mA) 1.2 1.0 0.8 0.6 0.4 0.2 05614-020 10 +25C 1 -40C 0.1 0.01 05614-024 0 -0.2 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.001 100 1k 10k 100k 1M 10M 100M POWER DOWN PIN (V) FREQUENCY (Hz) Figure 31. Supply Current per Amplifier vs. POWER DOWN Pin Voltage 0 VS = 5V G = +1 Figure 34. Output Impedance vs. Frequency 40 30 INPUT OFFSET VOLTAGE (V) COMMON-MODE REJECTION (dB) -20 20 10 0 VS = 5V -10 -20 -30 VS = +3V VS = +5V -40 -60 -80 -100 05614-009 -120 100 1k 10k 100k 1M 10M 100M -50 -40 -25 -10 5 20 35 50 65 80 95 110 125 FREQUENCY (Hz) TEMPERATURE (C) Figure 32. CMR vs. Frequency Figure 35. Input Offset Voltage vs. Temperature for Various Supplies Rev. C | Page 11 of 20 05614-057 -40 ADA4841-1/ADA4841-2 3.6 -40 G = +1 -50 V = 5V S RL = 1k -60 3.5 INPUT BIAS CURRENT (A) VS = +5V 3.4 CROSSTALK (dB) -70 -80 -90 -100 -110 -120 B TO A 05614-062 3.3 VS = +3V VS = 5V A TO B 3.2 05614-058 -130 -140 10k 100k 1M 10M FREQUENCY (Hz) 100M 3.1 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) 1G Figure 36. Input Bias Current vs. Temperature for Various Supplies 1.6 1.5 1.4 1.3 1.2 1.1 1.0 VS = +5V VS = +3V 0.8 -40 -25 -10 5 20 35 50 65 80 95 110 05614-059 Figure 38. Crosstalk Output to Output SUPPLY CURRENT (mA) VS = 5V 0.9 125 TEMPERATURE (C) Figure 37. Supply Current vs. Temperature for Various Supplies Rev. C | Page 12 of 20 ADA4841-1/ADA4841-2 THEORY OF OPERATION AMPLIFIER DESCRIPTION The ADA4841-1/ADA4841-2 are low power, low noise, precision voltage-feedback op amps for single or dual voltage supply operation. The ADA4841-1/ADA4841-2 are fabricated on ADI's second generation XFCB process and feature trimmed supply current and offset voltage. The 2.1 nV/Hz voltage noise (very low for a 1.1 mA supply current amplifier), 40 V offset voltage, and sub 1 V/C offset drift is accomplished with an input stage made of an undegenerated PNP input pair driving a symmetrical folded cascode. A rail-to-rail output stage provides the maximum linear signal range possible on low voltage supplies and has the current drive capability needed for the relatively low resistance feedback networks required for low noise operation. CMRR, PSRR, and open-loop gain are all typically above 100 dB, preserving the precision performance in a variety of configurations. Gain bandwidth is kept high for this power level to preserve the outstanding linearity performance for frequencies up to 100 kHz. The ADA4841-1 has a powerdown function to further reduce power consumption. All this results in a low noise, power efficient, precision amplifier that is well-suited for high resolution and precision applications. The total output voltage error is the sum of errors due to the amplifier offset voltage and input currents. The output error due to the offset voltage can be estimated as VOUTERROR = VCM VP - VPNOM VOUT RF + + VOFFSETNOM + x 1 + CMRR PSRR A RG where: (4) VOFFSETNOM is the offset voltage at the specified supply voltage. This is measured with the input and output at midsupply. VCM is the common-mode voltage. VP is the power supply voltage. VpNOM is the specified power supply voltage. CMRR is the common-mode rejection ratio. PSRR is the power supply rejection ratio. A is the dc open-loop gain. The output error due to the input currents can be estimated as R VOUTERROR = (RF || RG ) x 1 + F R G R I B - - RS x 1 + F R G x I B+ (5) DC ERRORS Figure 39 shows a typical connection diagram and the major dc error sources. The ideal transfer function (all error sources set to 0 and infinite dc gain) can be written as R VOUT = 1 + F R G x VIP R - F R G RF x VIN (1) Note that setting RS equal to RF||RG compensates for the voltage error due to the input bias current. - VIN + RG IB- + VOS - + VOUT - NOISE CONSIDERATIONS Figure 40 illustrates the primary noise contributors for the typical gain configurations. The total rms output noise is the root-mean-square of all the contributions. 05614-004 - VIP + RS IB+ RF vn _ RG = 4kT x RG RG ien ven vn _ RF = 4kT x RF Figure 39. Typical Connection Diagram and DC Error Sources + vout_en - VOUT R = 1 + F R G xVIP ien (2) Figure 40. Noise Sources in Typical Connection (Noninverting gain, VIN = 0 V) - RF VOUT = R G xVIN (3) (Inverting gain, VIP = 0 V) Rev. C | Page 13 of 20 05614-005 This reduces to the familiar forms for inverting and noninverting op amp gain expressions vn _ RS = 4kT x RS RS ADA4841-1/ADA4841-2 The output noise spectral density can be calculated by vout _ en = R R 2 2 4 kTRf + 1 + F 4 kTRs + ien RS 2 + ven + F 4 kTRg + ien 2 R F 2 R R G G 2 [ ] 2 (6) where: k is Boltzmann's Constant. T is the absolute temperature, degrees Kelvin. ien is the amplifier input current noise spectral density, pA/Hz. ven is the amplifier input voltage spectral density, nV/Hz. RS is the source resistance as shown in Figure 40. RF and RG are the feedback network resistances, as shown in Figure 40. Source resistance noise, amplifier voltage noise (ven), and the voltage noise from the amplifier current noise (ien x RS) are all subject to the noise gain term (1 + RF/RG). Note that with a 2.1 nV/Hz input voltage noise and 1.4 pA/Hz input current, the noise contributions of the amplifier are relatively small for source resistances between approximately 200 and 30 k. Figure 41 shows the total RTI noise due to the amplifier vs. the source resistance. In addition, the value of the feedback resistors used impacts the noise. It is recommended to keep the value of feedback resistors between 250 and 1 k to keep the total noise low. 1000 The input stage positive limit is almost exactly a volt below the positive supply at room temperature. Input voltages above that start to show clipping behavior. The positive input voltage limit increases with temperature with a coefficient of about 2 mV/C. The lower supply limit is nominally below the minus supply; therefore, in a standard gain configuration, the output stage limits the signal headroom on the negative supply side. Figure 42 and Figure 43 show the nominal CMRR behavior at the limits of the input headroom for three temperatures--this is generated using the subtractor topology shown in Figure 44, which avoids the output stage limitation. 300 260 220 180 140 100 60 20 -20 -60 -100 -140 -180 -260 -300 3.00 3.20 3.40 3.60 3.80 4.00 4.20 4.40 4.60 05614-055 COMMON-MODE ERROR (V) +125C +25C -40C -220 4.80 5.00 COMMON-MODE VOLTAGE (V) Figure 42. +CMV vs. Common-Mode Error vs. VOS 0 -50 -100 COMMON-MODE ERROR (V) -150 -200 -250 -300 -350 -400 -450 -500 -550 -600 -650 -40C +25C 100 NOISE (nV/ Hz) AMPLIFIER + RESISTOR NOISE +125C 10 TOTAL AMPLIFIER NOISE 1 05614-007 -700 -750 -800 -6.00 -5.80 -5.60 -5.40 -5.20 -5.00 -4.80 -4.60 -4.40 -4.20 -4.00 COMMON-MODE VOLTAGE (V) SOURCE RESISTANCE NOISE 0.1 10 100 1k SOURCE RESISTANCE () 10k Figure 43. -CMV vs. Common-Mode Error vs. VOS - VCM + + VOUT - 100k Figure 41. RTI Noise vs. Source Resistance HEADROOM CONSIDERATIONS The ADA4841-1/ADA4841-2 are designed to provide maximum input and output signal ranges with 16-bit to 18-bit dc linearity. As the input or output headroom limits are reached, the signal linearity degrades. Rev. C | Page 14 of 20 Figure 44. Common-Range Subtractor 05614-051 05614-054 ADA4841-1/ADA4841-2 Figure 45 shows the amplifier frequency response as a G = -1 inverter with the input and output stage biased near the negative supply rail. 6 VS+ = 5V G = -1 VIN = 20mV p-p 60 G = +1 50 SERIES RESISTANCE () VS- = -150mV VS- = -100mV VS- = -200mV 40 3 VS- = -50mV 0 30 GAIN (dB) 20 -3 VS- = -20mV 10 -6 G = +5 0 10 100 1000 10000 -9 05614-017 CAPACITANCE LOAD (pF) Figure 46. Series Resistance vs. Capacitance Load -12 0.1 1 10 FREQUENCY (MHz) 100 INPUT PROTECTION The ADA4841-1/ADA4841-2 are fully protected from ESD events, withstanding human body model ESD events of 2.5 keV and charge device model events of 1 keV with no measured performance degradation. The precision input is protected with an ESD network between the power supplies and diode clamps across the input device pair, as shown in Figure 47. VCC BIAS ESD VP ESD VEE 05614-006 Figure 45. Small Signal Frequency Response vs. Negative Supply Bias The input voltage (VIN) and reference voltage (VIP) are both at 0 V, (see Figure 39). +VS is biased at +5 V, and -VS is swept from -200 mV to -20 mV. With the input and output voltages biased 200 mV above the bottom rail, the G = -1 inverter frequency response is not much different from what is seen with the input and output voltages biased near midsupply. At 150 mV bias, the frequency response starts to decrease and at 20 mV, the inverter bandwidth is less than half its nominal value. ESD VN ESD CAPACITANCE DRIVE Capacitance at the output of an amplifier creates a delay within the feedback path that, if within the bandwidth of the loop, can create excessive ringing and oscillation. The G = +1 follower topology has the highest loop bandwidth of any typical configuration and, therefore, is the most vulnerable to the effects of capacitance load. A small resistor in series with the amplifier output and the capacitive load mitigates the problem. Figure 46 plots the recommended series resistance vs. capacitance for gains of +1, +2, and +5. TO REST OF AMPLIFIER Figure 47. Input Stage and Protection Diodes For differential voltages above approximately 1.4 V, the diode clamps start to conduct. Too much current can cause damage due to excessive heating. If large differential voltages need to be sustained across the input terminals, it is recommended that the current through the input clamps be limited to below 150 mA. Series input resistors sized appropriately for the expected differential overvoltage provide the needed protection. The ESD clamps start to conduct for input voltages more than 0.7 V above the positive supply and input voltages more than 0.7 V below the negative supply. It is recommended that the fault current be limited to less than 150 mA if an overvoltage condition is expected. Rev. C | Page 15 of 20 05614-050 G = +2 ADA4841-1/ADA4841-2 POWER-DOWN OPERATION Figure 48 shows the ADA4841-1 power-down circuitry. If the POWER DOWN pin is left unconnected, then the base of the input PNP transistor is pulled high through the internal pull-up resistor to the positive supply, and the part is turned on. Pulling the POWER DOWN pin approximately 1.7 V below the positive supply turns the part off, reducing the supply current to approximately 40 A. VCC IBIAS ESD POWER DOWN ESD TO AMPLIFIER BIAS VEE Figure 48. POWER DOWN Circuit The POWER DOWN pin is protected with ESD clamps, as shown in Figure 48. Voltages beyond the power supplies cause these diodes to conduct. The guidelines for limiting the overload current in the input protection section should also be followed for the POWER DOWN pin. 05614-052 Rev. C | Page 16 of 20 ADA4841-1/ADA4841-2 APPLICATIONS TYPICAL PERFORMANCE VALUES To reduce design time and eliminate uncertainty Table 6 provides a convenient reference for typical gains, component values, and performance parameters. RECONSTRUCTION FILTER The ADA4841-1/ADA4841-2 can also be used as a reconstruction filter at the output of DACs for suppression of the sampling frequency. The filter shown in Figure 50 is a two-pole, 500 kHz Sallen-Key LPF with a fixed gain of G = +1.6. C2 1320pF +5V 10F 0.1F R2 249 C1 1320pF 16-BIT ADC DRIVER The combination of low noise, low power, and high speed make the ADA4841-1/ADA4841-2 the perfect driver solution for low power, 16-bit ADCs, such as the AD7685. Figure 49 shows a typical 16-bit single-supply application. There are different challenges to a single-supply, high resolution design, and the ADA4841-1/ADA4841-2 address these nicely. In a single-supply system, a main challenge is using the amplifier in buffer mode with the lowest output noise and preserving linearity compatible with the ADC. Rail-to-rail input amplifiers are usually higher noise than the ADA4841-1/ADA4841-2 and cannot be used in this mode because of the nonlinear region around the crossover point of their input stages. The ADA4841-1/ADA4841-2, which have no crossover region but have a wide linear input range from 100 mV below ground to 1 V below positive rail, solve this problem, as shown in Figure 49. The amplifier, when configured as a follower, has a linear signal range from 0.25 V above the minus supply voltage (limited by the amplifier's output stage) to 1 V below the positive supply (limited by the amplifier input stage). A 0 V to +4.096 V signal range can be accommodated with a positive supply as low as +5.2 V and a negative power supply of -0.25 V. The 5.2 V supply also allows the use of a small, low dropout, low temperature drift ADR364 reference voltage. If ground is used as the amplifier negative supply, then note that at the low end of the input range close to ground, the ADA4841-1/ ADA4841-2 exhibit substantial nonlinearity, as any rail-to-rail output amplifier. The ADA4841-1/ADA4841-2 drive a onepole, low-pass filter. This filter limits the already very low noise contribution from the amplifier to the AD7685. +5.2V 100nF 10F INPUT R1 249 U1 0.1F 10F -5V OUTPUT R3 840 R4 499 Figure 50. Two-Pole 500 kHz Reconstruction Filter Schematic Setting the resistors and capacitors equal to each other greatly simplifies the design equations for the Sallen-Key filter. The corner frequency, or -3 dB frequency, can be described by the equation fC = 1 2R1C1 The quality factor, or Q, is shown in the equation Q= 1 3-K For minimum peaking, set Q equal to 0.707. The gain, or K, of the amplifier is K= R4 +1 R3 ADR364 100nF Resistor values are kept low for minimal noise contribution, offset voltage, and optimal frequency response. ADA4841 0V TO 4.096V 100nF 33 2.7nF REF IN+ VDD VIO SDI SCK SDO CNV 05614-060 -0.25V IN- GND AD7685 Figure 49. ADC Driver Schematic Rev. C | Page 17 of 20 05614-044 ADA4841-1/ADA4841-2 Table 6. Recommended Values and Typical Performance Gain +1 +2 -1 +5 +10 +20 RF () 0 499 499 499 499 499 RG () N/A 499 499 124 54.9 26.1 -3 dB BW (MHz) 77 34 38 11 5 2.3 Slew Rate (V/s) 12.5 12.5 12.5 12 12 11.2 Peaking (dB) 0.9 0.3 0.4 0 0 0 Output Noise ADA4841-1/ ADA4841-2 Only (nV/Hz) 2 4 4 10 20 40 Total Output Noise Including Resistors (nV/Hz) 2 5.73 5.73 11.9 21.1 42.2 Capacitor selection is critical for optimal filter performance. Capacitors with low temperature coefficients, such as NPO ceramic capacitors, are good choices for filter elements. Figure 51 shows the filter response. 5 0 -5 -10 GAIN (dB) POWER SUPPLY BYPASSING Power supply bypassing is a critical aspect in the performance of the ADA4841-1/ADA4841-2. A parallel connection of capacitors from each of the power supply pins to ground works best. A typical connection is shown in Figure 50. Smaller value capacitors offer better high frequency response where larger value electrolytics offer better low frequency performance. Paralleling different values and sizes of capacitors helps to ensure that the power supply pins are provided a low ac impedance across a wide band of frequencies. This is important for minimizing the coupling of noise into the amplifier. This can be especially important when the amplifier PSR is starting to roll off--the bypass capacitors can help lessen the degradation in PSR performance. Starting directly at the ADA4841-1/ADA4841-2 power supply pins, the smallest value capacitor should be placed on the same side of the board as the amplifier, and as close as possible to the amplifier power supply pin. The ground end of the capacitor should be connected directly to the ground plane. Keeping the capacitors' distance short but equal from the load is important and can improve distortion performance. This process should be repeated for the next largest value capacitor. It is recommended that a 0.1 F ceramic 0508 case be used. The 0508 case size offers low series inductance and excellent high frequency performance. A 10 F electrolytic capacitor should be placed in parallel with the 0.1 F capacitor. Depending on the circuit parameters, some enhancement to performance can be realized by adding additional capacitors. Each circuit is different and should be individually analyzed for optimal performance. -15 -20 -25 -30 05614-043 -35 -40 0.03 0.1 1 FREQUENCY (MHz) 10 Figure 51. Filter Frequency Response LAYOUT CONSIDERATIONS To ensure optimal performance, careful and deliberate attention must be paid to the board layout, signal routing, power supply bypassing, and grounding. GROUND PLANE It is important to avoid ground in the areas under and around the input and output of the ADA4841-1/ADA4841-2. Stray capacitance created between the ground plane and the input and output pads of a device are detrimental to high speed amplifier performance. Stray capacitance at the inverting input, along with the amplifier input capacitance, lowers the phase margin and can cause instability. Stray capacitance at the output creates a pole in the feedback loop. This can reduce phase margin and can cause the circuit to become unstable. Rev. C | Page 18 of 20 ADA4841-1/ADA4841-2 OUTLINE DIMENSIONS 2.90 BSC 5.00 (0.1968) 4.80 (0.1890) 6 5 4 8 5 4.00 (0.1574) 3.80 (0.1497) 1 6.20 (0.2440) 1.60 BSC 1 2 3 2.80 BSC 4 5.80 (0.2284) PIN 1 INDICATOR 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 1.75 (0.0688) 1.35 (0.0532) 0.50 (0.0196) x 45 0.25 (0.0099) 0.95 BSC 1.30 1.15 0.90 1.90 BSC 0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE 8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067) 1.45 MAX 0.50 0.30 0.22 0.08 10 4 0 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 0.15 MAX SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 52. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.20 3.00 2.80 Figure 54. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters 3.20 3.00 2.80 PIN 1 8 5 1 5.15 4.90 4.65 4 0.65 BSC 0.95 0.85 0.75 0.15 0.00 0.38 0.22 SEATING PLANE 1.10 MAX 8 0 0.80 0.60 0.40 0.23 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 53. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. C | Page 19 of 20 ADA4841-1/ADA4841-2 ORDERING GUIDE Model ADA4841-1YRZ 1 ADA4841-1YRZ-R71 ADA4841-1YRZ-RL1 ADA4841-1YRJZ-R21 ADA4841-1YRJZ-R71 ADA4841-1YRJZ-RL1 ADA4841-2YRMZ1 ADA4841-2YRMZ-R71 ADA4841-2YRMZ-RL1 ADA4841-2YRZ1 ADA4841-2YRZ-R71 ADA4841-2YRZ-RL1 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 6-Lead SOT-23 6-Lead SOT-23 6-Lead SOT-23 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N Package Option R-8 R-8 R-8 RJ-6 RJ-6 RJ-6 RM-8 RM-8 RM-8 R-8 R-8 R-8 Ordering Quantity 1 1,000 2,500 250 3,000 10,000 1 1,000 3,000 1 1,000 2,500 Branding HQB HQB HQB HRB HRB HRB Z = Pb-free part. (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05614-0-3/06(C) Rev. C | Page 20 of 20 |
Price & Availability of ADA4841-1YRJZ-RL
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