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Preliminary Technical Data
FEATURES
Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators ADCMP606/ADCMP607
FUNCTIONAL BLOCK DIAGRAM
VCCI VCCO (ADCMP607 Only)
LE/HYS INPUT (ADCMP607 Only)
APPLICATIONS
High speed instrumentation Clock and data signal restoration Logic level shifting or translation Pulse spectroscopy High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Pulse-width modulators Current-/voltage-controlled oscillators Automatic test equipment (ATE)
12 Q
SDN INPUT (ADCMP607 Only)
Figure 1.
11 VEE 10 Q
VCCO 1 VCCI 2 VEE 3
PIN 1 INDICATOR
9 VEE 8 LE/HYS 7 SDN
ADCMP607
TOP VIEW (Not to Scale)
Figure 2.LFCSP Pin Configuration
GENERAL DESCRIPTION
The ADCMP606/ADCMP607 are very fast comparators fabricated on Analog Devices' proprietary XFCB2 process. These comparators are exceptionally versatile and easy to use. Features include an input range from VEE - 0.5 V to VCC + 0.5 V, low noise CML-compatible output drivers, and TTL-/CMOScompatible latch inputs with adjustable hysteresis and/or shutdown inputs. The device offers 1 ns propagation delay with 2 ps RMS random jitter (RJ). Overdrive and slew rate dispersion are typically less than 50 ps. A flexible power supply scheme allows the devices to operate with a single +2.5 V positive supply and a -0.5 V to +3.0 V input signal range up to a +5.5 V positive supply with a -0.5 V to +6 V input signal range. The ADCMP607 features split input/output supplies with no sequencing restrictions to support a wide input signal range with independent output level control and power savings. The CML-compatible output stage is fully back-matched for superior performance. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. On the ADCMP607, high speed latch and programmable hysteresis features are also provided with a unique single-pin control option. The ADCMP606 is available in a 6-lead SC70 package, and the ADCMP607 is available in a 12-lead LSCFP package.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
VEE 5
05917-003
VN 6
VP 4
05917-001
10 mV sensitivity rail to rail at VCC = 2.5 V Input common-mode voltage from -0.2 V to VCC + 0.2 V CML-compatible output stage 1 ns propagation delay 50 mW at 2.5 V Shutdown pin (ADCMP607 only) Single-pin control for programmable hysteresis and latch (ADCMP607 only) Power supply rejection > 60 dB -40C to +125C operation
VP NONINVERTING INPUT
Q OUTPUT
ADCMP606/ ADCMP607
VN INVERTING INPUT
CML Q OUTPUT
ADCMP606/ADCMP607 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Electrical Characteristics ................................................................. 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7
Preliminary Technical Data
Application Information...................................................................9 Power/Ground Layout and Bypassing........................................9 CML-Compatible Output Stage ..................................................9 Using/Disabling the Latch Feature..............................................9 Optimizing Performance........................................................... 10 Comparator Propagation Delay Dispersion ........................... 10 Comparator Hysteresis .............................................................. 10 Crossover Bias Point .................................................................. 11 Minimum Input Slew Rate Requirement ................................ 11 Typical Application Circuits ......................................................... 12 Timing Information ....................................................................... 13
REVISION HISTORY
3/06--Revision PrA: Preliminary Version
Rev. PrA | Page 2 of 16
Preliminary Technical Data ELECTRICAL CHARACTERISTICS
VCCI = VCCO = 3.0 V, TA = 25C, unless otherwise noted. Table 1.
Parameter DC INPUT CHARACTERISTICS Voltage Range Common-Mode Range Differential Voltage Offset Voltage Bias Current Offset Current Capacitance Resistance, Differential Mode Resistance, Common Mode Active Gain Common-Mode Rejection Symbol VP, VN Conditions VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V VCC = 2.5 V to 5.5 V Min -0.5 -0.2 -5.0 -5.0 2.0 0.1 V to VCC -0.5 V to VCC + 0.5 V AV CMRR VCCI = 2.5 V, VCCO = 2.5 V, VCM = -0.2 V to 2.7 V VCCI = 5.5 V, VCCO = 5.5 V, VCM = -0.2 V to 5.7 V RHYS =
ADCMP606/ADCMP607
Typ
Max VCC + 0.5 V VCC + 0.2 V VCC +5.0 +5.0 2.0
Unit V V V mV A A pF k k dB dB dB mV
VOS IP, IN CP, CN
2 TBD 100 100 54 50 60 0.1
Hysteresis LATCH ENABLE PIN CHARACTERISTICS (ADCMP606 Only) VIH VIL IIH IOL HYSTERESIS MODE AND TIMING Hysteresis Mode Bias Voltage Minimum Resistor Value Latch Setup Time Latch Hold Time Latch-to-Output Delay Latch Minimum Pulse Width SHUTDOWN PIN CHARACTERISTICS (ADCMP607 Only) VIH VIL IIH IOL Sleep Time Wake-Up Time DC OUTPUT CHARACTERISTICS Output Voltage High Level Output Voltage Low Level Minimum Output Low Level (ADCMP607)
Hysteresis is shut off Latch mode guaranteed VIH = VCC VIL = 0.4 V Current sink 0 A Hysteresis = 16 mV VOD = 100 mV VOD = 100 mV VOD = 100 mV VOD = 100 mV
2.0 -0.2
+0.4
VCC +0.8 0.2 -0.2 1.35
V V mA mA V k ns ns ns ns
1.145 150
1.25 8 5 1 1
tS tH tPLOH, tPLOL tPL
tSD tH VOH VOL
Comparator is operating Shutdown guaranteed VIH = VCC VIL = 0 V ICC < 500 A VOD = 10 mV, output valid VCCO = 2.5 V to 5.5 V RI = 50 , VCCO = 2.5 V RI = 50 , VCCO = 2.5 V VCCI = 2.5 V, TA = -40C (internal termination only)
2.0 -0.2
+0.4
VCCO +0.6 0.3 -0.3
50 80 VCC - 0.1 VCC - 0.35 TBD VCC + 0.1 VCC - 0.5
V V mA mA ns ns V V
Rev. PrA | Page 3 of 16
ADCMP606/ADCMP607
Parameter AC PERFORMANCE Propagation Delay Symbol tPD Conditions VCC = 2.5 V to 5.5 V, VOD = 5 mV VCC = 2.5 V to 5.5 V, VOD = 200 mV VOD = 5 mV 10 mV < VOD < 2.5 V 5 mV < VOD < 2.5 V 0.05 V/ns to 2.5 V/ns 300 ps to 20 ns 1 V/ns, VCM = 2.5 V 0 < VCM < VCC >50% output swing VOD = 200 mV, 5 V/ns, PRBS31 - 1 NRZ, 0.25 Gbps VOD = 200 mV, 5 V/ns, PRBS31 - 1 NRZ, 0.525 Gbps tPD/PW < 50 ps 10% to 90% 10% to 90% 50% 2.5 2.5 -3.0 -5.5 Min
Preliminary Technical Data
Typ 1 1 40 TBD TBD TBD TBD TBD TBD TBD TBD TBD 300 150 150 20 5.5 5.5 +3.0 +5.5 23 25 0.8 22.5 57 125 -50 Max Unit ns ns ps ps ps ps ps ps ps Gbps ps ps ps ps ps ps V V V V mA mA mA mA mW mW dB
Propagation Delay Skew--Rising to Falling Transition Overdrive Dispersion Slew Rate Dispersion Pulse-Width Dispersion 10% to 90% Duty Cycle Dispersion Common-Mode Dispersion Toggle Rate Deterministic Jitter CML Outputs RMS Random Jitter Minimum Pulse Width Rise Time Fall Time Output skew POWER SUPPLY Input Supply Voltage Range Output Supply Voltage Range Positive Supply Differential (ADCMP607) Positive Supply Differential (ADCMP607) Positive Supply Current Positive Supply Current Input Section Supply Current (ADCMP607) Output Section Supply Current (ADCMP607) Power Dissipation Power Supply Rejection
DJ RJ PWMIN tR tF tSKEW VCCI VCCO VCCI - VCCO VCCI - VCCO IVCC IVCC IVCCI IVCCO PD PD PSRR
Operating Nonoperating VCC = 2.5 V VCC = 5.5 V VCCI = 2.5 V to 5 V VCCI = 2.5 V to 5.5 V VCC = 2.5 V VCC = 5.5 V VCCI = 2.5 V to 5 V
Rev. PrA | Page 4 of 16
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltages Input Supply Voltage (VCCI to GND) Output Supply Voltage (VCCO to GND) Positive Supply Differential (VCCI - VCCO) Input Voltages Input Voltage Differential Input Voltage Maximum Input/Output Current Shutdown Control Pin Applied Voltage (HYS to GND) Maximum Input/Output Current Latch/Hysteresis Control Pin Applied Voltage (HYS to GND) Maximum Input/Output Current Output Current Temperature Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range Rating -0.5 V to +6.0 V -0.5 V to +6.0 V -6.0 V to +6.0 V
ADCMP606/ADCMP607
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
-0.5 V to VCCI + 0.5 V (VCCI + 0.5 V) 50 mA -0.5 V to VCCO + 0.5 V 50 mA -0.5 V to VCCO + 0.5 V 50 mA 50 mA -40C to +125C 150C -65C to +150C
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance
Package Type ADCMP606 SC70 6-lead ADCMP607 LSCFP 12-lead
1
JA 1 426 62
Unit C/W C/W
Measurement in still air.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. PrA | Page 5 of 16
ADCMP606/ADCMP607 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Preliminary Technical Data
11 VEE
12 Q
VCCO 1
PIN 1 INDICATOR
10 Q
9 VEE 8 LE/HYS 7 SDN
Q1
6
Q VCCI /VCCO
05917-002
VCCI 2 VEE 3
ADCMP607
TOP VIEW (Not to Scale)
ADCMP606
VEE 2 VP 3 TOP VIEW (Not to Scale)
5
4
VN
Figure 3. ADCMP606 Pin Configuration
Figure 4. ADCMP607 Pin Configuration
Table 4. ADCMP606 (SC70-6) Pin Function Descriptions
Pin No. 1 2 3 4 5 6 Mnemonic Q VEE VP VN VCCI/VCCO Q Description Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN. Negative Supply Voltage. Noninverting Analog Input. Inverting Analog Input. Input Section Supply/Output Section Supply. Shared pin. Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN.
Table 5. ADCMP607 (LSCFP-12) Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 Heat Sink Paddle Mnemonic VCCO VCCI VEE VP VEE VN SDN LE/HYS VEE Q VEE Q VEE Description Output Section Supply. Input Section Supply. Negative Supply Voltage. Noninverting Analog Input. Negative Supply Voltage. Inverting Analog Input. Shutdown. Drive this pin low to shut down the device. Latch/Hysteresis Control. Bias with resistor or current for hysteresis adjustment; drive low to latch. Negative Supply Voltage. Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided that the comparator is in compare mode. Negative Supply Voltage. Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided that the comparator is in compare mode. The metallic back surface of the package is electrically connected to VEE. It can be left floating because Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired.
Rev. PrA | Page 6 of 16
VEE 5
05917-003
VN 6
VP 4
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
VCCI = VCCO = 3.3 V, TA = 25C, unless otherwise noted.
ADCMP606/ADCMP607
Figure 5. Propagation Delay vs. Input Overdrive
Figure 8. Rise/Fall Time vs. Temperature
Figure 6. Propagation Delay vs. Input Common Mode
Figure 9.
Figure 7. Propagation Delay vs. Temperature
Figure 10. Input Bias Current vs. Input Common Mode
Rev. PrA | Page 7 of 16
ADCMP606/ADCMP607
Preliminary Technical Data
Figure 11. Input Bias Current vs. Temperature
Figure 13. Input Offset Voltage vs. Temperature
Figure 12. Hysteresis vs. VCC
Rev. PrA | Page 8 of 16
Preliminary Technical Data APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP606 and ADCMP607 comparators are very high speed devices. Despite the low noise output stage, it is essential to use proper high speed design techniques to achieve the specified performance. Because comparators are uncompensated amplifiers, feedback in any phase relationship is likely to cause oscillations or undesired hysteresis. Of critical importance is the use of low impedance supply planes, particularly the output supply plane (VCCO) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. It is also important to adequately bypass the input and output supplies. Multiple high quality 0.01 F bypass capacitors should be placed as close as possible to each of the VCCI and VCCO supply pins and should be connected to the GND plane with redundant vias. At least one of these should be placed to provide a physically short return path for output currents flowing back from ground to the VCC pin. High frequency bypass capacitors should be carefully selected for minimum inductance and ESR. Parasitic layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies.
ADCMP606/ADCMP607
If these high speed signals must be routed more than a centimeter, then either microstrip or strip line techniques are required to ensure proper transition times and to prevent excessive output ringing and pulse-width-dependent propagation delay dispersion. It is also possible to operate the outputs with only the internal termination if greater output swing is desired. This can be especially useful for driving inputs on CMOS devices intended for full swing ECL and PECL. VCCO must be kept high enough that the specified minimum output low level (see the Electrical Characteristics section) is not violated and the line length driven is as short as possible.
USING/DISABLING THE LATCH FEATURE
The latch input of the ADCMP607 is designed for maximum versatility. It can safely be left floating, or it can be driven low by any standard TTL/CMOS device as a high speed latch. In addition, the pin can be operated as a hysteresis control pin with a bias voltage of 1.25 V nominal and an input resistance of approximately 7000 , allowing the comparator hysteresis to be easily controlled by either a resistor or an inexpensive CMOS DAC. Driving this pin high or floating the pin removes all hysteresis. Hysteresis control and latch mode can be used together if an open drain, an open collector, or a three-state driver is connected parallel to the hysteresis control resistor or current source. Due to the programmable hysteresis feature, the logic threshold of the latch pin is approximately 1.1 V regardless of VCC.
CML-COMPATIBLE OUTPUT STAGE
Specified propagation delay dispersion performance can be achieved by using proper transmission line terminations. The outputs of the ADCMP606 and ADCMP607 are designed to drive 400 mV directly into a 50 cable or into transmission lines terminated using either microstrip or strip line techniques with 50 referenced to VCC. The CML output stage is shown in the simplified schematic diagram in Figure 14. Each output is backterminated with 50 for best transmission line matching.
VCCO
50
Q Q
16mA
05917-013
GND
Figure 14. Simplified Schematic Diagram of CML-Compatible Output Stage
Rev. PrA | Page 9 of 16
ADCMP606/ADCMP607
OPTIMIZING PERFORMANCE
As with any high speed comparator, proper design and layout techniques are essential for obtaining the specified performance. Stray capacitance, inductance, inductive power and ground impedances, or other layout issues can severely limit performance and often cause oscillation. Large discontinuities along input and output transmission lines can also limit the specified pulsewidth dispersion performance. The source impedance should be minimized as much as is practicable. High source impedance, in combination with the parasitic input capacitance of the comparator, causes an undesirable degradation in bandwidth at the input, thus degrading the overall response. Thermal noise from large resistances can easily cause extra jitter with slowly slewing input signals; higher impedances encourage undesired coupling.
Preliminary Technical Data
INPUT VOLTAGE 1V/ns VN VOS 10V/ns
Q/Q OUTPUT
Figure 16. Propagation Delay--Slew Rate Dispersion
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often desirable in a noisy environment, or when the differential input amplitudes are relatively small or slow moving. Figure 17 shows the transfer function for a comparator with hysteresis. As the input voltage approaches the threshold (0.0 V, in this example) from below the threshold region in a positive direction, the comparator switches from low to high when the input crosses +VH/2, and the new switching threshold becomes -VH/2. The comparator remains in the high state until the new threshold, -VH/2, is crossed from below the threshold region in a negative direction. In this manner, noise or feedback output signals centered on 0.0 V input cannot cause the comparator to switch states unless it exceeds the region bounded by VH/2.
OUTPUT
COMPARATOR PROPAGATION DELAY DISPERSION
The ADCMP606/ADCMP607 comparators are designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mV to VCCI - 1 V. Propagation delay dispersion is the variation in propagation delay that results from a change in the degree of overdrive or slew rate (that is, how far or how fast the input signal exceeds the switching threshold). Propagation delay dispersion is a specification that becomes important in high speed, time-critical applications, such as data communication, automatic test and measurement, and instrumentation. It is also important in event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (Figure 15 and Figure 16). ADCMP606/ADCMP607 dispersion is typically 500mV OVERDRIVE
VOH
VOL
-VH 2
0
+VH 2
Figure 17. Comparator Hysteresis Transfer Function
INPUT VOLTAGE 10mV OVERDRIVE VN VOS
The customary technique for introducing hysteresis into a comparator uses positive feedback from the output back to the input. One limitation of this approach is that the amount of hysteresis varies with the output logic levels, resulting in hysteresis that is not symmetric about the threshold. The external feedback network can also introduce significant parasitics that reduce high speed performance and induce oscillation in some cases. The ADCMP607 comparator offers a programmable hysteresis feature that can significantly improve accuracy and stability. Connecting an external pull-down resistor or a current source from the LE/HYS pin to GND, varies the amount of hysteresis in a predictable, stable manner. Leaving the LE/HYS pin disconnected or driving it high removes the hysteresis. The
Q/Q OUTPUT
Figure 15. Propagation Delay--Overdrive Dispersion
05917-014
DISPERSION
Rev. PrA | Page 10 of 16
05917-016
INPUT
05917-015
DISPERSION
Preliminary Technical Data
maximum hysteresis that can be applied using this pin is approximately 160 mV. Figure 18 illustrates the amount of hysteresis applied as a function of the external resistor value, and Figure TBD illustrates hysteresis as a function of the current. The hysteresis control pin appears as a 1.25 V bias voltage seen through a series resistance of 7k 20% throughout the hysteresis control range. The advantages of applying hysteresis in this manner are improved accuracy, improved stability, reduced component count, and maximum versatility. An external bypass capacitor is not recommended on the HYS pin because it impairs the latch function and often degrades the jitter performance of the device. As described in the Using/Disabling the Latch Feature section, hysteresis control need not compromise the latch function.
ADCMP606/ADCMP607
CROSSOVER BIAS POINT
In both op amps and comparators, rail-to-rail inputs of this type have a dual front-end design. Certain devices are active near the VCC rail and others are active near the VEE rail. At some predetermined point in the common-mode range, a crossover occurs. At this point, normally VCC/2, the direction of the bias current reverses and the measured offset voltages and currents change. The ADCMP606/ADCMP607 slightly elaborate on this scheme. With VCC less than 4 V, this crossover is at the expected VCC/2, but with VCC greater than 4 V, the crossover point instead follows VCC 1:1, bringing it to approximately 3 V with VCC at 5 V. This means that at any voltage, the comparator input characteristics more closely resemble the inputs of nonrail-to-rail ground sensing comparators, such as the AD8611.
MINIMUM INPUT SLEW RATE REQUIREMENT
(Remove if device is stable.) As with most high speed comparators without hysteresis, a minimum slew rate must be met to ensure that the device does not oscillate as the input signal crosses the threshold. This oscillation is due in part to the high input bandwidth of the comparator in combination with feedback parasitics inherent in the package and PC board. A minimum slew rate of TBD V/s ensures clean output transitions from the ADCMP606/ADCMP607 comparators unless hysteresis is programmed. In many applications, chattering due to the absence of hysteresis is not harmful.
Figure 18. Hysteresis vs. RHYS Control Resistor
Rev. PrA | Page 11 of 16
ADCMP606/ADCMP607 TYPICAL APPLICATION CIRCUITS
2.5V TO 5V 0.1F INPUT 2k
Preliminary Technical Data
5V 50
50 50 CML OUTPUT
05917-018
50 CML PWM OUTPUT
2k
ADCMP606
ADCMP606
INPUT 2.5V 50mV
0.1F
Figure 19. Self-Biased, 50% Slicer
INPUT 2.5V REF 10k
10k
3.3V
ADCMP601
50 50 CML OUTPUT
05917-019
10k
150pF
LE/HYS
05917-022
100k
LVDS 100
ADCMP606
Figure 23. Oscillator and Pulse-Width Modulator
Figure 20. LVDS to CML
2.5V TO 5V
5V
50
50
10k
ADCMP607
50 50
82pF
ADCMP607
LE/HYS
CML OUTPUT
DIGITAL INPUT
74 VHC 1G07
150k
LE/HYS
05917-020
CONTROL VOLTAGE
10k 10k
150k
Figure 21. Current-Controlled Oscillator
Figure 24. Hysteresis Adjustment with Latch
+2.5V VCCI
VCCO 50 50
VCCI
3.3V 1N4001
VCCO 50 50 3.3V PECL
05917-021
ADCMP607
OUTPUT
LVDS
100
ADCMP607
-2.5V VEE
Figure 25.Ground-Referenced CML with 3 V Input Range
Figure 22.Fake PECL Levels Using a Series Diode
Rev. PrA | Page 12 of 16
05917-024
05917-023
CONTROL VOLTAGE 0V TO 2.5V
Preliminary Technical Data TIMING INFORMATION
ADCMP606/ADCMP607
Figure 26 illustrates the ADCMP606/ADCMP607 timing relationships. Table 6 provides definitions of the terms shown in the figure.
1.1V LATCH ENABLE
tS tH
tPL
DIFFERENTIAL INPUT VOLTAGE
VIN VOD
VN VOS
tPDL
Q OUTPUT
tPLOH
50%
tPDH
tF
50%
Q OUTPUT
tR
Figure 26. System Timing Diagram
Table 6. Timing Descriptions
Symbol tPDH tPDL tR tF VOD Timing Input to output high delay Input to output low delay Output rise time Output fall time Voltage overdrive Description Propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output low-to-high transition. Propagation delay measured from the time the input signal crosses the reference ( the input offset voltage) to the 50% point of an output high-to-low transition. Amount of time required to transition from a low to a high output as measured at the 20% and 80% points. Amount of time required to transition from a high to a low output as measured at the 20% and 80% points. Difference between the input voltages VA and VB.
Rev. PrA | Page 13 of 16
05917-025
tPLOL
ADCMP606/ADCMP607 NOTES
Preliminary Technical Data
Rev. PrA | Page 14 of 16
Preliminary Technical Data NOTES
ADCMP606/ADCMP607
Rev. PrA | Page 15 of 16
ADCMP606/ADCMP607 NOTES
Preliminary Technical Data
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05917-0-3/06(PrA)
T T
Rev. PrA | Page 16 of 16

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