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PD - 95473
SMPS MOSFET
IRFB260NPBF
l l
HEXFET(R) Power MOSFET
Applications High frequency DC-DC converters Lead-Free
VDSS
200V
RDS(on) max
0.040
ID
56A
Benefits Low Gate-to-Drain Charge to Reduce Switching Losses l Fully Characterized Capacitance Including Effective COSS to Simplify Design, (See App. Note AN1001) l Fully Characterized Avalanche Voltage and Current
l
TO-220AB
Absolute Maximum Ratings
Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS dv/dt TJ TSTG Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torqe, 6-32 or M3 screw
Max.
56 40 220 380 2.5 20 10 -55 to + 175 300 (1.6mm from case ) 10 lbf*in (1.1N*m)
Units
A W W/C V V/ns C
Thermal Resistance
Parameter
RJC RCS RJA Junction-to-Case Case-to-Sink, Flat, Greased Surface Junction-to-Ambient
Typ.
--- 0.50 ---
Max.
0.40 --- 62
Units
C/W
Notes
through
are on page 8
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1
7/7/04
IRFB260NPBF
Static @ TJ = 25C (unless otherwise specified)
Parameter Drain-to-Source Breakdown Voltage V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) Gate Threshold Voltage V(BR)DSS IDSS IGSS Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Min. 200 --- --- 2.0 --- --- --- --- Typ. --- 0.26 --- --- --- --- --- --- Max. Units Conditions --- V VGS = 0V, ID = 250A --- V/C Reference to 25C, ID = 1mA 0.040 VGS = 10V, ID = 34A 4.0 V VDS = VGS, ID = 250A 25 VDS = 200V, VGS = 0V A 250 VDS = 160V, VGS = 0V, TJ = 150C 100 VGS = 20V nA -100 VGS = -20V
Dynamic @ TJ = 25C (unless otherwise specified)
gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss Coss Coss eff. Parameter Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Min. 29 --- --- --- --- --- --- --- --- --- --- --- --- --- Typ. --- 150 24 67 17 64 52 50 4220 580 140 5080 230 500 Max. Units Conditions --- S VDS = 50V, ID = 34A 220 ID = 34A 37 nC VDS = 160V 100 VGS = 10V --- VDD = 100V --- ID = 34A ns --- R G = 1.8 --- VGS = 10V --- VGS = 0V --- VDS = 25V --- pF = 1.0MHz --- VGS = 0V, VDS = 1.0V, = 1.0MHz --- VGS = 0V, VDS = 160V, = 1.0MHz --- VGS = 0V, VDS = 0V to 160V
Avalanche Characteristics
Parameter
EAS IAR EAR Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy
Typ.
--- --- ---
Max.
450 34 38
Units
mJ A mJ
Diode Characteristics
IS
ISM
VSD trr Qrr ton
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol 56 --- --- showing the A G integral reverse --- --- 220 S p-n junction diode. --- --- 1.3 V TJ = 25C, IS = 34A, VGS = 0V --- 240 360 ns TJ = 25C, IF = 34A --- 2.1 3.2 C di/dt = 100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRFB260NPBF
1000
ID, Drain-to-Source Current (A)
100
ID, Drain-to-Source Current (A)
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
1000
100
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
4.5V
10
10
4.5V
1
1
20s PULSE WIDTH Tj = 25C
0.1 0.1 1 10 100
20s PULSE WIDTH Tj = 175C
0.1 0.1 1 10 100
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000.00
3.5
I D = 56A
ID, Drain-to-Source Current ()
T J = 175C
RDS(on) , Drain-to-Source On Resistance
3.0
100.00
2.5
(Normalized)
2.0
10.00
TJ = 25C
1.5
1.0
1.00 3.0 5.0 7.0
VDS = 15V 20s PULSE WIDTH
9.0 11.0 13.0 15.0
0.5
0.0 -60 -40 -20 0 20 40 60 80
V GS = 10V
100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature
( C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
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3
IRFB260NPBF
100000 VGS = 0V, f = 1 MHZ Ciss = C + Cgd, C gs ds SHORTED Crss = C gd Coss = C + C ds gd
12
I D = 34A
10
VDS = 160V VDS = 100V VDS = 40V
10000
C, Capacitance(pF)
Ciss
1000
VGS , Gate-to-Source Voltage (V)
7
Coss
100
5
Crss
2
10 1 10 100 1000
0 0 30 60 90 120 150
VDS, Drain-to-Source Voltage (V)
QG, Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000.00
1000
OPERATION IN THIS AREA LIMITED BY R DS(on)
100.00 T J = 175C 10.00
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100
100sec 10 1msec Tc = 25C Tj = 175C Single Pulse 1 1 10 100
1.00
T J = 25C VGS = 0V
0.10 0.0 0.5 1.0 1.5 2.0 VSD, Source-toDrain Voltage (V)
10msec 1000
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRFB260NPBF
60
V DS VGS RG
RD
50
D.U.T.
+
40
-VDD
ID , Drain Current (A)
10V
30
Pulse Width 1 s Duty Factor 0.1 %
20
Fig 10a. Switching Time Test Circuit
VDS 90%
10
0 25 50 75 100 125 150 175
TC , Case Temperature
( C)
Fig 9. Maximum Drain Current Vs. Case Temperature
10% VGS
td(on) tr t d(off) tf
Fig 10b. Switching Time Waveforms
1
(Z thJC )
D = 0.50
0.1
0.20 0.10
Thermal Response
0.05 0.02 0.01 0.01 SINGLE PULSE (THERMAL RESPONSE) P DM t1 t2 Notes: 1. Duty factor D = 2. Peak T 0.001 0.00001 0.0001 0.001 0.01 t1/ t 2 +TC 1
J = P DM x Z thJC
0.1
t 1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFB260NPBF
15V
850
ID TOP 14A 24A 34A
VDS
L
DRIVER
680
BOTTOM
RG
20V
D.U.T
IAS tp
+ V - DD
EAS , Single Pulse Avalanche Energy (mJ)
A
510
0.01
Fig 12a. Unclamped Inductive Test Circuit
340
V(BR)DSS tp
170
0 25 50 75 100 125 150 175
Starting T , Junction Temperature J
( C)
I AS
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
QG
50K 12V .2F .3F
10 V
QGS
QGD
VGS
3mA
D.U.T.
+ V - DS
VG
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
6
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IRFB260NPBF
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 14. For N-Channel HEXFET(R) Power MOSFETs
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7
IRFB260NPBF
TO-220AB Package Outline
2.87 (.113) 2.62 (.103) 10.54 (.415) 10.29 (.405) 3.78 (.149) 3.54 (.139) -A6.47 (.255) 6.10 (.240) -B4.69 (.185) 4.20 (.165) 1.32 (.052) 1.22 (.048)
4 15.24 (.600) 14.84 (.584)
1.15 (.045) MIN 1 2 3
LEAD ASSIGNMENTS IGBTs, CoPACK 1 - GATE 21- GATE DRAIN 1- GATE 32- DRAINSOURCE 2- COLLECTOR 3- EMITTER 3- SOURCE 4 - DRAIN
LEAD ASSIGNMENTS
HEXFET
14.09 (.555) 13.47 (.530)
4- DRAIN
4.06 (.160) 3.55 (.140)
4- COLLECTOR
3X 3X 1.40 (.055) 1.15 (.045)
0.93 (.037) 0.69 (.027) M BAM
3X
0.55 (.022) 0.46 (.018)
0.36 (.014)
2.54 (.100) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH
2.92 (.115) 2.64 (.104)
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
E XAMPLE : T H IS IS AN IR F 1010 L OT CODE 1789 AS S E MB LE D ON WW 19, 1997 IN T H E AS S E MB L Y LINE "C" INT E R NAT IONAL R E CT IF IE R L OGO AS S E MB L Y L OT CODE PAR T NU MB E R
Note: "P" in assembly line position indicates "Lead-Free"
DAT E CODE YE AR 7 = 1997 WE E K 19 L INE C
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. Starting TJ = 25C, L = 0.78mH RG = 25, IAS = 34A. ISD 34, di/dt 480A/s, VDD V(BR)DSS, TJ 175C
Pulse width 300s; duty cycle 2%. Coss eff. is a fixed capacitance that gives the same charging
time as Coss while VDS is rising from 0 to 80% VDSS
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.7/04
8
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