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NCP5181 High Voltage High and Low Side Driver
The NCP5181 is a High Voltage Power MOSFET Driver providing two outputs for direct drive of 2 N-channel power MOSFETs arranged in a half-bridge (or any other high-side + low-side) configuration. It uses the bootstrap technique to insure a proper drive of the High-side power switch. The driver works with 2 independent inputs to accommodate any topology (including half-bridge, asymmetrical half-bridge, active clamp and full-bridge...).
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IN_HI IN_LO GND DRV_LO
VBOOT DRV_HI BRIDGE VCC
* * * * * * * * * * * * *
High Voltage Range: up to 600 V dV/dt Immunity 50 V/nsec Gate Drive Supply Range from 10 V to 20 V High and Low DRV Outputs Output Source / Sink Current Capability 1.1 A / 2.4 A 3.3 V and 5 V Input Logic Compatible Up to VCC Swing on Input Pins Matched Propagation Delays between Both Channels Outputs in Phase with the Inputs Independent Logic Inputs to Accommodate All Topologies Under VCC LockOut (UVLO) for Both Channels Pin to Pin Compatible with IR2181(S) These are Pb-Free Devices
8 1 SOIC-8 D SUFFIX CASE 751 PDIP-8 P SUFFIX CASE 626
MARKING DIAGRAMS
8 5181 ALYWX G 1 NCP5181P, 5181 = Specific Device Code A = Assembly Location L = Wafer Lot Y, YY = Year W, WW = Work Week G, G = Pb-Free Package NCP5181P AWL YYWWG
Applications
* High Power Energy Management * Half-bridge Power Converters * Any Complementary Drive Converters (asymmetrical half-bridge, * *
active clamp) Full-bridge Converters Bridge Inverters for UPS Systems
PIN ASSIGNMENT
PIN IN_HI IN_LO GND DRV_LO VCC VBOOT DRV_HI BRIDGE FUNCTION Logic Input for High Side Driver Output In Phase Logic Input for Low Side Driver Output In Phase Ground Low Side Gate Drive Output Low Side and Main Power Supply Bootstrap Power Supply High Side Gate Drive Output Bootstrap Return or High Side Floating Supply Return
ORDERING INFORMATION
Device NCP5181PG NCP5181DR2G Package PDIP-8 (Pb-Free) SOIC-8 (Pb-Free) Shipping 50 Units/Tube 2.500/Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2006
1
March, 2006 - Rev. 2
Publication Order Number: NCP5181/D
NCP5181
Vbulk C1 GND C3 5 SG3526 MC34025 TL594 GND GND 1 2 3 GND VCC U1 VBOOT 8 7 6 4 Q2 C6 D2 Out- IN_HI DRV_HI IN_LO Bridge GND DRV_LO NCP51XX D4 C4 Q1 C3 C5 T1 D1 L1 Out+
VCC
GND U2 R1 D3 GND
Figure 1. Typical Application
VCC VCC UV DETECT VBOOT
IN_HI
PULSE TRIGGER
LEVEL SHIFTER GND
S R
Q Q DRV_HI
GND
UV DETECT VCC
BRIDGE
IN_LO
DELAY
DRV_LO
GND GND GND GND
Figure 2. Detailed Block Diagram
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NCP5181
MAXIMUM RATINGS
Rating Main power supply voltage VHV: High Voltage BRIDGE pin VHV: Floating supply voltage VHV: High side output voltage Low side output voltage Allowable output slew rate Inputs IN_HI, IN_LO ESD Capability: HBM model (all pins except pins 6-7-8) Machine model (all pins except pins 6-7-8) Latch up capability per Jedec JESD78 Power dissipation and thermal characteristics PDIP8: Thermal resistance, Junction-to-Air SO-8: Thermal resistance, Junction-to-Air Operating junction temperature C/W RqJA RqJA TJ_min TJ_max 100 178 -55 +150 C Symbol VCC VBRIDGE VBOOT - VBRIDGE VDRV_HI VDRV_LO dVBRIDGE/dt VIN_XX Value -0.3 to 20 -1 to 600 0 to 20 VBRIDGE-0.3 to VBOOT+0.3 -0.3 to VCC+0.3 50 -1.0 to VCC+0.3 2.0 200 Unit V V V V V V/ns V kV V
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
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NCP5181
ELECTRICAL CHARACTERISTICS (VCC = Vboot = 15 V, Vgnd = Vbridge, -40C < TA < 125C, Outputs loaded with 1 nF)
Rating Symbol TA -40C to 125C Units
OUTPUT SECTION
Min Output high short circuit pulsed current VDRV = 0 V, PW 10 ms, (Note 1) Output low short circuit pulsed current VDRV = VCC, PW 10 ms, (Note 1) Output resistor (Typical value @ 25C only) Source Output resistor (Typical value @ 25C only) Sink IDRVhigh IDRVlow ROH ROL - - - - Typ 1.4 2.2 5 2 Max - - 12 8 A A W W
DYNAMIC OUTPUT SECTION
Rating Turn-on propagation delay (Vbridge = 0 V) Turn-off propagation delay (Vbridge = 0 V or 50 V) (Note 2) Output voltage rise time (from 10% to 90% @ VCC = 15 V) with 1 nF load Output voltage falling edge (from 90% to 10% @ VCC = 15 V) with 1 nF load Propagation delay matching between the High side and the Low side @ 25C (Note 3) Minimum input pulse width that changes the output Symbol tON tOFF tr tf Dt tPW Min - - - - - - Typ 100 100 40 20 20 - Max 170 170 60 40 35 100 Units ns ns ns ns ns ns
INPUT SECTION
Low level input voltage threshold Input pull-down resistor (VIN < 0.5 V) High level input voltage threshold VIN RIN VIN - - 2.3 - 200 - 0.8 - - V kW V
SUPPLY SECTION
VCC UV Start-up voltage threshold VCC UV Shut-down voltage threshold Hysteresis on VCC Vboot Start-up voltage threshold reference to bridge pin (Vboot_stup = Vboot - Vbridge) Vboot UV Shut-down voltage threshold Hysteresis on Vboot Leakage current on high voltage pins to GND (VBOOT = VBRIDGE = DRV_HI = 600 V) Consumption in active mode (VCC = Vboot, fsw = 100 kHz and 1 nF load on both driver outputs) Consumption in inhibition mode (VCC = Vboot) VCC current consumption in inhibition mode Vboot current consumption in inhibition mode VCC_stup VCC_shtdwn VCC_hyst Vboot_stup Vboot_shtdwn Vboot_shtdwn IHV_LEAK ICC1 ICC2 ICC3 ICC4 7.9 7.3 0.3 7.9 7.3 0.3 - - - - - 8.9 8.2 0.7 8.9 8.2 0.7 0.5 4.5 250 215 35 9.8 9.0 - 9.8 9.0 - 40 6.5 400 - - V V V V V V mA mA mA mA mA
*Note: see also characterization curves 1. Guaranteed by design. 2. Turn-off propagation delay @ Vbridge = 600 V is guaranteed by design 3. See characterization curve for Dt parameters variation on the full range temperature. 4. Timing diagram definition see Figures 4, 5 and 6.
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NCP5181
IN_HI IN_LO
DRV_HI DRV_LO
Figure 3. Input/Output Timing Diagram
IN_HI IN_LO ton
50%
50%
tr
toff 90% 90%
tf
DRV_HI DRV_LO
10%
10%
Figure 4. Switching Time Waveform Definitions
IN_LO 50% IN_HI ton toff 50%
Delta_t DRV_HI toff 90% DRV_LO
90%
10% Delta_t
ton 10%
Figure 5. Delay Matching Waveforms Definition
IN_LO & IN_HI
50% ton_HI Delta_t
50% toff_HI 90% 10% Delta_t
DRV_HI
ton_LO ton_LO DRV_LO 10% 90%
Figure 6. Other Delay Matching Waveforms Definition http://onsemi.com
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NCP5181
TYPICAL CHARACTERISTICS
160 Ton PROPAGATION DELAY (ns) 140 120 100 80 60 40 20 0 -40 -20 0 20 40 60 80 100 120 ton High Side ton Low Side Ton PROPAGATION DELAY (ns) 140 ton High Side 120 100 ton Low Side 80 60 40 20 0 10 12 14 16 18 20 TEMPERATURE (C) SUPPLY VOLTAGE; VCC = Vboot (V)
Figure 7. Turn-on Propagation Delay vs. Temperature
180 Toff PROPAGATION DELAY (ns) Toff PROPAGATION DELAY (ns) 160 140 120 100 80 60 40 20 0 -40 -20 0 20 40 60 80 100 120 toff Low Side toff High Side 160 140
Figure 8. Turn-on Propagation Delay vs. VCC Voltage (VCC = Vboot)
toff High Side 120 100 80 60 40 20 0 10 12 14 16 18 20 toff Low Side
TEMPERATURE (C)
SUPPLY VOLTAGE; VCC = Vboot (V)
Figure 9. Turn-off Propagation Delay vs. Temperature
130 Ton PROPAGATION DELAY (ns) Toff PROPAGATION DELAY (ns) 130
Figure 10. Turn-off Propagation Delay vs. VCC Voltage (VCC = Vboot)
110
110
90
90
70
70
50 0 10 20 30 40 50 BRIDGE PIN VOLTAGE (V)
50 0 10 20 30 40 50 BRIDGE PIN VOLTAGE (V)
Figure 11. High Side Turn-on Propagation Delay vs. VBRIDGE Voltage
Figure 12. High Side Turn-off Propagation Delay vs. VBRIDGE Voltage
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NCP5181
TYPICAL CHARACTERISTICS
40 35 TURN-ON RISE TIME (ns) TURN-ON RISE TIME (ns) 30 tr High Side 25 tr Low Side 20 15 10 5.0 0 -40 -20 0 20 40 60 80 100 120 35 30 tr Low Side 25 20 tr High Side 15 10 5.0 0 10 12 14 16 18 20 TEMPERATURE (C) SUPPLY VOLTAGE; VCC = Vboot (V)
Figure 13. Turn-on Rise Time vs. Temperature
30 TURN-OFF FALL TIME (ns) TURN-OFF FALL TIME (ns) 25 tf Low Side 20 15 10 5.0 0 -40 tf High Side 20 18 16 14 12 10 8.0 6.0 4.0 2.0 0 -20 0 20 40 60 80 100 120
Figure 14. Turn-on Rise Time vs. VCC Voltage (VCC = Vboot)
tf Low Side
tf High Side
10
12
14
16
18
20
TEMPERATURE (C)
SUPPLY VOLTAGE; VCC = Vboot (V)
Figure 15. Turn-off Fall Time vs. Temperature
40 35 30 25 20 15 10 5 0 -40 -20 0 20 40 60
Figure 16. Turn-off Fall Time vs. VCC Voltage (VCC = Vboot)
PROPAGATION DELAY MATCHING (ns)
80
100
120
TEMPERATURE (C)
Figure 17. Propagation Delay Matching Between High Side and Low Side Driver
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NCP5181
TYPICAL CHARACTERISTICS
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -40 -20 0 20 40 60 80 100 120 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 10 12 14 16 18 20
LOW LEVEL INPUT VOLTAGE THRESHOLD (V)
TEMPERATURE (C)
LOW LEVEL INPUT VOLTAGE THRESHOLD (V)
SUPPLY VOLTAGE; VCC = Vboot (V)
Figure 18. Low Level Input Voltage Threshold vs. Temperature
2.5 HIGH LEVEL INPUT VOLTAGE THRESHOLD (V) HIGH LEVEL INPUT VOLTAGE THRESHOLD (V) 2.5
Figure 19. Low Level Input Voltage Threshold vs. VCC Voltage
2.0
2.0
1.5
1.5
1.0
1.0
0.5 0 -40
0.5 0
-20
0
20
40
60
80
100
120
10
12
14
16
18
20
TEMPERATURE (C)
SUPPLY VOLTAGE; VCC = Vboot (V)
Figure 20. High Level Input Voltage Threshold vs. Temperature
LEAKAGE CURRENT TO GND (mA) 4.0 HIGH SIDE LEAKAGE CURRENT TO GND (mA) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -40 -20 0 20 40 60 80 TEMPERATURE (C) 100 120 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0
Figure 21. High Level Input Voltage Threshold vs. VCC Voltage
100
200 300 400 BRIDGE PIN VOLTAGE (V)
500
600
Figure 22. Leakage Current on High Voltage Pins (600 V) to Ground vs. Temperature
Figure 23. Leakage Current on High Voltage Pins to Ground vs. Vbridge Voltage (Vbridge = Vboot = VDRV_HI)
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NCP5181
TYPICAL CHARACTERISTICS
100 BOOTSTRAP SUPPLY CURRENT (mA) BOOTSTRAP SUPPLY CURRENT (mA) 100
80
80
60
60
40
40
20 0 -40
20 0 10
-20
0
20
40
60
80
100
120
12
14
16
18
20
TEMPERATURE (C)
BOOTSTRAP SUPPLY VOLTAGE (V)
Figure 24. High Side Supply Current vs. Temperature
500 VCC SUPPLY CURRENT (mA) VCC SUPPLY CURRENT (mA) 500 400
Figure 25. High Side Supply Current vs. Bootstrap Supply Voltage
400
300
300
200
200
100 0 -40
100 0
-20
0
20
40
60
80
100
120
10
12
14
16
18
20
TEMPERATURE (C)
VCC, SUPPLY VOLTAGE (V)
Figure 26. VCC Supply Current vs. Temperature
10 UVLO SHUTDOWN VOLTAGE th (V) UVLO STARTUP VOLTAGE th (V) 9.8 9.6 9.4 9.2 Vboot UVLO stup th 9.0 8.8 VCC UVLO stup th 8.6 8.4 8.2 8.0 -40 -20 0 20 40 60 80 100 120 9.0 8.8 8.6 8.4 8.2 8.0 7.8 7.6 7.4
Figure 27. VCC Supply Current vs. VCC Supply Voltage
VCC UVLO shtdwn th
Vboot UVLO shtdwn th
7.2 7.0 -40 -20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 28. UVLO Start Up Voltage vs. Temperature
Figure 29. UVLO Shut Down Voltage vs. Bootstrap Supply Voltage
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NCP5181
TYPICAL CHARACTERISTICS
35 ICC + Iboot CURRENT SUPPLY (mA) 30 25 Rgate = 10 W 20 Rgate = 0 W 15 10 5.0 0 0 100 200 300 400 500 600 SWITCHING FREQUENCY (kHz) ICC + Iboot CURRENT SUPPLY (mA) Cload = 1 nF / Q = 15 nC Rgate = 22 W 60 Cload = 2.2 nF / Q = 33 nC 50 40 30 Rgate = 10 W 20 10 0 0 100 200 300 400 500 600 SWITCHING FREQUENCY (kHz) Rgate = 0 W Rgate = 22 W
Figure 30. ICC1 Consumption vs. Switching Frequency with 15 nC Load on Each Driver
80 70 60 50 40 30 20 10 0 0 100 200 300 400 500 600 SWITCHING FREQUENCY (kHz) 140
Figure 31. ICC1 Consumption vs. Switching Frequency with 33 nC Load on Each Driver
ICC + Iboot CURRENT SUPPLY (mA)
Cload = 3.3 nF / Q = 50 nC Rgate = 22 W Rgate = 10 W Rgate = 0 W
ICC + Iboot CURRENT SUPPLY (mA)
Cload = 6.6 nF / Q = 100 nC 120 100
Rgate = 22 W Rgate = 10 W Rgate = 0 W
80 60 40 20 0 0 100 200 300 400 500 600 SWITCHING FREQUENCY (kHz)
Figure 32. ICC1 Consumption vs. Switching Frequency with 50 nC Load on Each Driver
Figure 33. ICC1 Consumption vs. Switching Frequency with 100 nC Load on Each Driver
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NCP5181
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AG
A
8 5
-X-
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP5181
PACKAGE DIMENSIONS
8 LEAD PDIP CASE 626-05 ISSUE L
8 5
-B-
1 4
NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --- 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --- 10_ 0.030 0.040
F
NOTE 2
-A- L
C -T-
SEATING PLANE
J N D K
M
M TA
M
H
G 0.13 (0.005) B
M
The product described herein (NCP5181), is covered by U.S. patent: 6,362, 067. There may be some other patent pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP5181/D

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