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STA501
40V 3.5A DOUBLE POWER HALF BRIDGE
s
MINIMUM INPUT OUTPUT PULSE WIDTH DISTORTION 200m RdsON COMPLEMENTARY DMOS OUTPUT STAGE CMOS COMPATIBLE LOGIC INPUTS THERMAL PROTECTION THERMAL WARNING OUTPUT UNDER VOLTAGE PROTECTION
MULTIPOWER BCD TECHNOLOGY
s
s s s s
PowerSO36
ORDERING NUMBER: STA501
DESCRIPTION STA501 is a monolithic dual half bridge stage in Multipower BCD Technology. The device is particularly designed to make the output stage of a mono All-Digital High Efficiency AUDIO APPLICATION CIRCUIT
+3.3V
IBIAS CONFIG PWRDN R57 10K R59 10K C58 100nF PWRDN FAULT
23 24 25 27 26
TRI-STATE
TH_WAR
TH_WAR VDD VDD
28 21 22 33 34
C58 100nF
C60 100nF
w
C53 100nF
w
VSS VSS
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35 36 31 20 19 32 1 10 11
.D
PROTECTIONS & LOGIC
t a
S a
M17
e h
15 VCC 14 12 13 29 30 16 17 7
(DDXTM) amplifier capable to deliver 50W @ THD = 10% at Vcc 30V output power on 8 load. The input pins have threshold proportional to Ibias pin voltage.
t e
C30 1F C31 1F
U 4
.c
m o
+VCC C55 1000F
GND VCCB GND GND GND
N.C. N.C. VCCA C32 1F OUTA OUTA
REGULATORS
VCCSIGN
8 9 M15
L113 22H C110 100nF C109 330pF R103 6 R104 20
VCCSIGN INA GND-Reg GND-Clean INB
INA
6
GNDA
4 M16
VCCB C33 1F OUTB OUTB
R102 6 C111 100nF
3 2
C107 100nF C108 470nF C106 100nF
INB GNDSUB N.C. N.C.
L112 22H
M14
5
GNDB
D02AU1447
September 2003
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STA501
PIN FUNCTION
N 1 35 ; 36 15 12 7 4 14 13 6 5 16 ; 17 10 ; 11 8;9 2;3 29 30 31 32 21 ; 22 33 ; 34 25 26 27 24 28 19 23 18 20 Pin GND-SUB Vcc Sign Vcc Vcc Vcc Vcc GND GND GND GND N.C. N.C. OUTA OUTB GND GND INA INB Vdd Vss PWRDN TRI-STATE FAULT GND TH-WAR GND-clean IBIAS NC GND-Reg Thermal warning advisor Logical ground High logical state setting voltage Not connected Ground for regulator Vdd Input of half bridge Input of half bridge 5V Regulator referred to ground 5V Regulator referred to +Vcc Stand-by pin Hi-Z pin Fault pin advisor Output half bridge Output half bridge Substrate ground Signal Positive Supply Positive Supply Positive Supply Positive Supply Positive Supply Negative Supply Negative Supply Negative Supply Negative Supply Description
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STA501
FUNCTIONAL PIN STATUS
PIN NAME FAULT FAULT * TRI-STATE TRI-STATE PWRDN PWRDN THWAR THWAR* Logical value 0 1 0 1 0 1 0 1 IC -STATUS Fault detected (Short circuit, or Thermal ..) Normal Operation All powers in Hi-Z state Normal operation Low absorpion Normal operation Temperature of the IC =130C Normal operation
* : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor.
PIN CONNECTION
VCCSign VCCSign VSS VSS INB INA GND GND TH_WAR FAULT TRI-STATE PWRDN GND IBIAS VDD VDD GND-Reg GND-Clean
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
D02AU1449
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
GND-SUB OUTB OUTB VCC GND GND VCC OUTA OUTA N.C N.C. VCC GND GND VCC N.C. N.C. N.C.
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STA501
ABSOLUTE MAXIMUM RATINGS
Symbol VCE Vmax Top Tstg, Tj Parameter DC Supply Voltage (Pin 4,7,12,15) Maximum Voltage on pins 23 to 32 Operating Temperature Range Storage and Junction Temperature Value 40 5.5 0 to 70 -40 to 150 Unit V V C C
THERMAL DATA
Symbol Tj-case TjSD Twarn thSD Parameter Thermal Resistance Junction to Case (thermal pad) Thermal shut-down junction temperature Thermal warning temperature Thermal shut-down hysteresis 150 130 25 Min. Typ. Max. 2.5 Unit C/W C C C
ELECTRICAL CHARACTERISTCS (Ibias = 3.3V; Vcc = 30V; Tamb = 25C unless otherwise specified)
Symbol RdsON Idss gN gP Dt_s Dt_d td ON td OFF tr tf VCC VIN-H VIN-L IIN-H Parameter Power Pchannel/Nchannel MOSFET RdsON Power Pchannel/Nchannel leakage Idss Power Pchannel RdsON Matching Power Nchannel RdsON Matching Low current Dead Time (static) Id=1A Vcc=35V Id=1A Id=1A see test circuit no.1; see fig. 1 95 95 10 20 50 100 100 25 25 10 36 Ibias/2 +300mV Ibias/2 -300mV Pin voltage = Ibias 1 Test conditions Min. Typ. 200 Max. 270 50 Unit m A % % ns ns ns ns ns ns V V V A
High current Dead Time (dinamic) L=22H; C = 470nF; Rl = 8 Id=3.5A; see fig. 3 Turn-on delay time Turn-off delay time Rise time Fall time Supply voltage operating voltage High level input voltage Low level input voltage Hi level Input current Resistive load Resistive load Resistive load Resistive load; as fig. 1
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STA501
ELECTRICAL CHARACTERISTCS (continued)
Symbol IIN-L Parameter Low level input current Test conditions Pin voltage = 0.3V Ibias = 3.3V Ibias = 3.3V Ibias = 3.3V PWRDN = 0 0.8 1.7 3 Min. Typ. 1 35 Max. Unit A A V V mA
IPWRDN-H Hi level PWRDN pin input current VL VH IVCCPWRDN IFAULT Low logical state voltage VL (pin PWRDN, TRISTATE) (note 1) High logical state voltage VH (pin PWRDN, TRISTATE) (note 1) Supply Current from Vcc in Power Down Output Current pins FAULT -TH-WARN when FAULT CONDITIONS Supply current from Vcc in Tristate Supply current from Vcc in operation (both channel switching) Isc (short circuit current limit) Undervoltage protection threshold Output minimum pulse width
Vpin = 3.3V Vcc=30V; Tri-state=0 Input pulse width = 50% Duty; Switching Frequency = 384Khz; No LC filters; 3.5
1 22 80
mA mA mA
IVCC-hiz IVCC
IVCC-q IOUT-SH VOV
6 7
8
A V
No Load
70
150
ns
Notes: 1. The following table explains the VL, VH variation with Ibias
Ibias 2.7 3.3 5
VLmin 0.7 0.8 0.85
VHmax 1.5 1.7 1.85
Unit V V V
LOGIC TRUTH TABLE (see fig. 2)
TRI-STATE 0 1 1 1 1 INA x 0 0 1 1 INB x 0 1 0 1 Q1 OFF OFF OFF ON ON Q2 OFF OFF ON OFF ON Q3 OFF ON ON OFF OFF Q4 OFF ON OFF ON OFF OUTPUT MODE Hi-Z DUMP NEGATIVE POSITIVE Not used
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STA501
Figure 1. Test Circuit.
OUTY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t Duty cycle = 50%
M58
DTr OUTY
M57
DTf
INY
R 8
+ -
V67 = vdc = Vcc/2
D02AU1448
gnd
Figure 2.
+VCC
Q1 INA OUTA
Q2 OUTB INB
Q3
Q4
GND
D02AU1450
Figure 3.
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B
DTout(A) M58 Q1 OUTA Rload=8 L67 22 C69 470nF DTout(B) L68 22 C70 470nF Q2 OUTB M64
DTin(A) INA
DTin(B) INB
Iout=3.5A M57 Q3
Iout=3.5A Q4 M63
C71 470nF
Duty cycle A and B: Fixed to have DC output current of 3.5A in the direction shown in figure
D02AU1451
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STA501
DIM. A A2 A4 A5 a1 b c D D1 D2 E E1 E2 E3 E4 e e3 G H h L N s
MIN. 3.25 0.8
mm TYP.
MAX. 3.5 3.3 1 0.075 0.38 0.32 16 9.8
MIN. 0.128 0.031
inch TYP.
MAX. 0.138 0.13 0.039 0.003 0.015 0.012 0.630 0.38
OUTLINE AND MECHANICAL DATA
0.2 0 0.22 0.23 15.8 9.4 1 13.9 10.9 5.8 2.9 0.65 11.05 0 15.5 0.8 0.075 0 15.9 0.61 1.1 1.1 0.031 10 (max) 8 (max) 14.5 11.1 2.9 6.2 3.2 0.547 0.429 0.228 0.114 0 0.008 0.009 0.622 0.37
0.008
0.039 0.57 0.437 0.114 0.244 1.259 0.026 0.435 0.003 0.625 0.043 0.043
PowerSO36 (SLUG UP)
(1) "D and E1" do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006") (2) No intrusion allowed inwards the leads.
7183931
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STA501
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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