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KM44C16000B, KM44C16100B
CMOS DRAM
16M x 4bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 16,777,216 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time(-45, -5 or -6), package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. This 16Mx4 Fast Page Mode DRAM family is fabricated using Samsungs advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
* Part Identification - KM44C16000B(5.0V, 8K Ref.) - KM44C16100B(5.0V, 4K Ref.) * Active Power Dissipation Unit : mW Speed -45 -5 -6 * Refresh Cycles Part NO. KM44C16000B* KM44C16100B Refresh cycle 8K 4K Refresh time Normal 64ms
RAS CAS W
* Fast Page Mode operation * CAS-before-RAS refresh capability * RAS-only and Hidden refresh capability * Fast parallel test mode capability * TTL(5.0V) compatible inputs and outputs * Early Write or output enable controlled write * JEDEC Standard pinout * Available in Plastic SOJ and TSOP(II) packages * +5.0V10% power supply 4K 715 660 605
8K 550 495 440
FUNCTIONAL BLOCK DIAGRAM
Control Clocks Vcc Vss
VBB Generator
Refresh Control Refresh Counter Memory Array 16,777,216 x 4 Cells
Sense Amps & I/O
* Access mode & RAS only refresh mode : 8K cycle/64ms CAS-before-RAS & Hidden refresh mode : 4K cycle/64ms * Performance Range Speed -45 -5 -6
Refresh Timer
Row Decoder Data in Buffer DQ0 to DQ3 Data out Buffer OE
tRAC
45ns 50ns 60ns
tCAC
12ns 13ns 15ns
tRC
80ns 90ns 110ns
tPC
31ns 35ns 40ns
A0~A12 (A0~A11)*1 A0~A10 (A0~A11)*1
Row Address Buffer Col. Address Buffer Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
KM44C16000B, KM44C16100B
CMOS DRAM
PIN CONFIGURATION (Top Views)
* KM44C160(1)00BK
* KM44C160(1)00BS
VCC DQ0 DQ1 N.C N.C N.C N.C W RAS A0 A1 A2 A3 A4 A5 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VSS DQ3 DQ2 N.C N.C N.C CAS OE A12(N.C)* A11 A10 A9 A8 A7 A6 VSS
VCC DQ0 DQ1 N.C N.C N.C N.C W RAS A0 A1 A2 A3 A4 A5 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VSS DQ3 DQ2 N.C N.C N.C CAS OE A12(N.C)* A11 A10 A9 A8 A7 A6 VSS
(K : 400mil SOJ)
(S : 400mil TSOP(II))
* (N.C) : N.C for 4K Refresh product
Pin Name A0 - A12 A0 - A11 DQ0 - 3 VSS RAS CAS W OE VCC N.C
Pin Function Address Inputs(8K Product) Address Inputs(4K Product) Data In/Out Ground Row Address Strobe Column Address Strobe Read/Write Input Data Output Enable Power(+5.0V) No Connection
KM44C16000B, KM44C16100B
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol VIN,VOUT VCC Tstg PD IOS Rating -1.0 to +7.0 -1.0 to +7.0 -55 to +150 1 50
CMOS DRAM
Units V V C W mA
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70C)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.4 -1.0*2 Typ 5.0 0 Max 5.5 0 VCC+1.0*1 0.8 Units V V V V
*1 : VCC+2.0V at pulse width20ns which is measured at VCC *2 : -2.0 at pulse width20ns which is measured at VSS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter Input Leakage Current (Any input 0VINVCC+0.5V, all other pins not under test=0 Volt) Output Leakage Current (Data out is disabled, 0VVOUTVCC) Output High Voltage Level(IOH=-5mA) Output Low Voltage Level(IOL=4.2mA) Symbol II(L) IO(L) VOH VOL Min -5 -5 2.4 Max 5 5 0.4 Units uA uA V V
KM44C16000B, KM44C16100B
DC AND OPERATING CHARACTERISTICS (Continued)
Symbol Power Speed KM44C16000B ICC1 Dont care -45 -5 -6 Dont Care -45 -5 -6 -45 -5 -6 Dont Care -45 -5 -6 100 90 80 2 100 90 80 70 60 50 1 100 90 80 Max
CMOS DRAM
Units KM44C16100B 130 120 110 2 130 120 110 80 70 60 1 130 120 110 mA mA mA mA mA mA mA mA mA mA mA mA mA mA
ICC2
Normal
ICC3
Dont care
ICC4
Dont care
ICC5
Normal
ICC6
Dont care
ICC1* : Operating Current (RAS and CAS, Address cycling @tRC=min.) ICC2 : Standby Current (RAS=CAS=W=VIH) ICC3* : RAS-only Refresh Current (CAS=VIH, RAS, Address cycling @tRC=min.) ICC4* : Fast Page Mode Current (RAS=VIL, CAS, Address cycling @tPC=min.) ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V) ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min)
*Note : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one fast page mode cycle time, tPC.
KM44C16000B, KM44C16100B
CAPACITANCE (TA=25C, VCC=5.0V, f=1MHz)
Parameter Input capacitance [A0 ~ A12] Input capacitance [RAS, CAS, W, OE] Output capacitance [DQ0 - DQ3] Symbol CIN1 CIN2 CDQ Min -
CMOS DRAM
Max 5 7 7 Units pF pF pF
AC CHARACTERISTICS (0CTA70C, See note 1,2)
Test condition : VCC=5.0V10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay Transition time (rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold time referenced to CAS Read command hold time referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data set-up time Data hold time Symbol Min -45 Max Min 90 133 45 12 23 0 0 1 25 45 12 45 12 18 13 5 0 8 0 8 23 0 0 0 8 8 13 12 0 10 10K 33 22 10K 13 50 0 0 1 30 50 13 50 13 20 15 5 0 10 0 10 25 0 0 0 10 10 15 13 0 10 10K 37 25 10K 13 50 50 13 25 0 0 1 40 60 15 60 15 20 15 5 0 10 0 10 30 0 0 0 10 10 15 15 0 10 10K 45 30 10K 13 50 -5 Max Min 110 153 60 15 30 -6 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 9 9 8 8 4 10 3,4,10 3,4,5 3,10 3 6 2 Units Note
tRC tRWC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH
80 115
KM44C16000B, KM44C16100B
AC CHARACTERISTICS (Continued)
Parameter Refresh period (4K, Normal) Refresh period (8K, Normal) Write command set-up time CAS to W delay time RAS to W delay time Column address to W delay time CAS precharge W delay time CAS set-up time (CAS -before-RAS refresh) CAS hold time (CAS -before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Fast Page mode cycle time Fast Page mode read-modify-write cycle time CAS precharge time (Fast Page cycle) RAS pulse width (Fast Page cycle) RAS hold time from CAS precharge OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Write command set-up time (Test mode in) Write command hold time (Test mode in) W to RAS precharge time (C-B-R refresh) W to RAS hold time (C-B-R refresh) RAS pulse width (C-B-R self refresh) RAS precharge time (C-B-R self refresh) CAS hold time (C-B-R self refresh) Symbol Min -45 Max 64 64 0 32 67 43 48 5 10 5 26 31 70 9 45 28 12 12 0 12 10 15 10 10 100 80 -50 13 13 0 13 10 15 10 10 100 90 -50 13 200K 35 76 10 50 30 13 13 0 15 10 15 10 10 100 110 -50 200K 0 36 73 48 53 5 10 5 30 40 85 10 60 35 Min -5 Max 64 64 0 38 83 53 60 5 10 5 Min -6
CMOS DRAM
Units Max 64 64 ms ms ns ns ns ns ns ns ns ns 35 ns ns ns ns 200K ns ns 15 ns ns 13 ns ns ns ns ns ns us ns ns
Note
tREF tREF tWCS tCWD tRWD tAWD tCPWD tCSR tCHR tRPC tCPA tPC tPRWC tCP tRASP tRHCP tOEA tOED tOEZ tOEH tWTS tWTH tWRP tWRH tRASS tRPS tCHS
7 7 7 7
3
6
11 11
13,14,15 13,14,15 13,14,15
KM44C16000B, KM44C16100B
TEST MODE CYCLE
Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time Column Address to RAS lead time CAS to W delay time RAS to W delay time Column Address to W delay time Fast Page mode cycle time Fast Page mode read-modify-write cycle time RAS pulse width (Fast Page cycle) Access time from CAS precharge OE access time OE to data delay OE command hold time Symbol Min -45 Max Min 95 138 50 17 28 50 17 17 50 28 37 72 48 36 75 50 200K 31 17 17 17 18 18 10K 10K 55 18 18 55 30 41 78 53 40 81 55 200K 35 18 18 20 55 18 30 10K 10K 65 20 20 65 35 43 88 58 45 90 65 -5 Max Min 115 160 -6
CMOS DRAM
( Note 11 )
Units Max ns ns 65 20 35 10K 10K ns ns ns ns ns ns ns ns ns ns ns ns ns 200K 40 20 ns ns ns ns ns 3 7 7 7 3,4,10,12 3,4,5,12 3,10,12 Note
tRC tRWC tRAC tCAC tAA tRAS tCAS tRSH tCSH tRAL tCWD tRWD tAWD tPC tPRWC tRASP tCPA tOEA tOED tOEH
85 120
KM44C16000B, KM44C16100B
NOTES
CMOS DRAM
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL load and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. tOFF(min)and tOEZ(max) define the time at which the output achieves the open circuit condition and are not referenced Voh or Vol. 7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCStWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWDtCWD(min), tRWDtRWD(min) and tAWDtAWD(min), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in read-modify-write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 11. These specifications are applied in the test mode. 12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 13. If tRASS100us, then RAS precharge time must use tRPS instead of tRP. 14. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K/8K) cycles of burst refresh must be executed within 64ms before and after self refresh, in order to meet refresh specification. 15. For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.
KM44C16000B, KM44C16100B
READ CYCLE
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCSH tCRP
CAS VIH VIL -
tRCD
tRSH tCAS tRAL tCAH
COLUMN ADDRESS
tCRP
tRAD tASR
A VIH VIL -
tRAH
tASC
ROW ADDRESS
tRCS
W VIH VIL -
tRCH tRRH tOFF tAA tOEZ tOEA tCAC
OE
VIH VIL -
DQ0 ~ DQ3(7) VOH VOL -
tRAC OPEN
tCLZ
DATA-OUT
Dont care Undefined
KM44C16000B, KM44C16100B
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRAS
RAS VIH VIL -
tRC
tRP
tCSH tCRP
CAS VIH VIL -
tRCD
tRSH tCAS tRAL tCAH
COLUMN ADDRESS
tCRP
tRAD tASR
A VIH VIL -
tRAH
tASC
ROW ADDRESS
tCWL tRWL tWCS
W VIH VIL -
tWCH tWP
OE
VIH VIL -
DQ0 ~ DQ3(7) VIH VIL -
tDS
tDH
DATA-IN
Dont care Undefined
KM44C16000B, KM44C16100B
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRP
tCSH tCRP
CAS VIH VIL -
tRCD
tRSH tCAS tRAL tCAH
COLUMN ADDRESS
tCRP
tRAD tASR tRAH tASC
A
VIH VIL -
ROW ADDRESS
tCWL tRWL
W VIH VIL -
tWP
OE
VIH VIL -
tOED tDS
tOEH tDH
DATA-IN
DQ0 ~ DQ3(7) VIH VIL -
Dont care Undefined
KM44C16000B, KM44C16100B
READ - MODIFY - WRTIE CYCLE
CMOS DRAM
tRWC tRAS
RAS VIH VIL -
tRP
tCRP
CAS VIH VIL -
tRCD tRAD tRAH
tRSH tCAS tCAH tCSH
tASR
VIH VIL -
tASC
COLUMN ADDRESS
A
ROW ADDR
tAWD tCWD
W VIH VIL -
tRWL tCWL tWP
OE
VIH VIL -
tRWD tOEA tCLZ tCAC tAA tRAC
VALID DATA-OUT
tOED tOEZ
DQ0 ~ DQ3(7) VI/OH VI/OL -
tDS
tDH
VALID DATA-IN
Dont care Undefined
KM44C16000B, KM44C16100B
FAST PAGE READ CYCLE
CMOS DRAM
tRASP
RAS VIH VIL o
tRP tRHCP
tCRP
CAS VIH VIL -
tPC tRCD tCAS tRAD tASC tCSH tCAH
COLUMN ADDRESS
tCP tCAS
o
tCP
tRSH tCAS
tASR
A VIH VIL ROW ADDR
tRAH
tASC
tCAH
o o
tASC
tCAH
COLUMN ADDRESS
COLUMN ADDRESS
tRCS
W VIH VIL -
tRCH
tRCS
o
tRAL tRCS
tRRH tRCH
tCAC tOEA
OE VIH VIL -
tCAC tOEA
o o
tCAC tOEA
tAA
DQ0 ~ DQ3(7) VOH VOL -
tRAC tCLZ
tOEZ
VALID DATA-OUT
tAA tOFF tCLZ
tOEZ
VALID DATA-OUT
tAA tOFF tCLZ
VALID DATA-OUT
tOFF tOEZ
Dont care Undefined
KM44C16000B, KM44C16100B
FAST PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRASP
RAS VIH VIL o
tRP tRHCP
tCRP
CAS VIH VIL -
tPC tRCD tCAS tRAD tASC tCP tCAS
o
tPC tCP tRSH tCAS tRAL
tASR
A VIH VIL -
tRAH
tCSH tCAH
COLUMN ADDRESS
tASC
tCAH
o o
tASC
tCAH
ROW ADDR
COLUMN ADDRESS
COLUMN ADDRESS
tWCS
W VIH VIL -
tWCH tWP tCWL
tWCS tWP
tWCH
o
tWCS
tWCH tWP tCWL tRWL
tCWL
o o
OE
VIH VIL -
DQ0 ~ DQ3(7) VIH VIL -
tDS
tDH
tDS
tDH
o
tDS
tDH
VALID DATA-IN
VALID DATA-IN
o
VALID DATA-IN
Dont care Undefined
KM44C16000B, KM44C16100B
FAST PAGE READ - MODIFY - WRITE CYCLE
CMOS DRAM
tRASP
RAS VIH VIL -
tRP
tCSH tRCD tRSH tCP tCAS tRAD tRAH tASR tASC
COL. ADDR
tCRP tCAS tPRWC
CAS
VIH VIL -
tCAH
tRAL tASC
COL. ADDR
tCAH
A
VIH VIL -
ROW ADDR
tRCS
W VIH VIL -
tRWL tCWL tWP tCWD tAWD tRWD tOEA tOED tCAC tAA tOEZ tDH tDS tCWD tAWD tCPWD tOEA tCAC tAA tOEZ tOED tDH tDS tCWL tWP
OE
VIH VIL -
DQ0 ~ DQ3(7) VI/OH VI/OL -
tRAC tCLZ
tCLZ
VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN
Dont care Undefined
KM44C16000B, KM44C16100B
RAS - ONLY REFRESH CYCLE
NOTE : W, OE, DIN = Dont care DOUT = OPEN tRC tRP
CMOS DRAM
tRAS
RAS VIH VIL -
tCRP
CAS VIH VIL -
tRPC
tCRP
tASR
A VIH VIL ROW ADDR
tRAH
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE, A = Dont care tRC tRP
RAS VIH VIL -
tRAS
tRP
tRPC tCP tRPC tCSR tWRP tWRH tCHR
CAS
VIH VIL -
W
VIH VIL -
DQ0 ~ DQ3(7) VOH VOL -
tOFF OPEN
Dont care Undefined
KM44C16000B, KM44C16100B
HIDDEN REFRESH CYCLE ( READ )
CMOS DRAM
tRC tRAS
RAS VIH VIL -
tRC tRP tRAS tRP
tCRP
CAS VIH VIL -
tRCD
tRSH
tCHR
tRAD tASR
A VIH VIL -
tRAH
tASC
tCAH
COLUMN ADDRESS
ROW ADDRESS
tRAL tRCS
W VIH VIL -
tWRH
tAA
OE VIH VIL -
tOEA tCAC tOFF tOEZ
DATA-OUT
DQ0 ~ DQ3(7) VOH VOL -
tRAC OPEN
tCLZ
Dont care Undefined
KM44C16000B, KM44C16100B
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
CMOS DRAM
tRC
RAS VIH VIL -
tRC tRP tRAS tRP
tRAS
tCRP
CAS VIH VIL -
tRCD tRAD
tRSH
tCHR
tASR
A VIH VIL -
tRAH
tASC
tCAH
COLUMN ADDRESS
ROW ADDRESS
tRAL
VIH VIL -
tWRH tWRP
tWCS tWP
tWCH
W
OE
VIH VIL -
tDS
DQ0 ~ DQ3(7) VIH VIL -
tDH
DATA-IN
Dont care Undefined
KM44C16000B, KM44C16100B
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Dont care
CMOS DRAM
tRP
RAS VIH VIL -
tRASS
tRPS tRPC tCHS
tRPC tCP
CAS
VIH VIL -
tCSR
DQ0 ~ DQ3(7) VOH VOL -
tOFF OPEN tWRP tWRH
W
VIH VIL -
TEST MODE IN CYCLE
NOTE : OE, A = Dont care
tRC tRP
RAS VIH VIL -
tRAS
tRP
tRPC tCP tRPC tCSR tWTS tWTH tCHR
CAS
VIH VIL -
W
VIH VIL -
DQ0 ~ DQ3(7) VOH VOL -
tOFF OPEN
Dont care Undefined
KM44C16000B, KM44C16100B
PACKAGE DIMENSION
32 SOJ 400mil
CMOS DRAM
Units : Inches (millimeters)
#32 0.435 (11.06) 0.445 (11.30) 0.400 (10.16) 0.360 (9.15) 0.380 (9.65) 0.010 (0.25) TYP 0.018 (0.45) 0.030 (0.75) 0~8
O
0.006 (0.15) 0.012 (0.30)
#1 0.027 (0.69) MIN 0.841 (21.36) MAX 0.820 (20.84) 0.830 (21.08) 0.148 (3.76) MAX 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53)
0.0375 (0.95)
0.050 (1.27)
32 TSOP(II) 400mil
Units : Inches (millimeters)
0.455 (11.56) 0.471 (11.96)
0.400 (10.16)
0.004 (0.10) 0.010 (0.25) 0.841 (21.35) MAX 0.821 (20.85) 0.829 (21.05) 0.047 (1.20) MAX
0.037 (0.95)
0.050 (1.27)
0.002 (0.05) MIN 0.012 (0.30) 0.020 (0.50)

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