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MC74HC4066A Quad Analog Switch/ Multiplexer/Demultiplexer
High-Performance Silicon-Gate CMOS
The MC74HC4066A utilizes silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low O F F -c h a n n e l l e a k a g e c u r r e n t . T h i s b i l a t e r a l s w i t c h / multiplexer/demultiplexer controls analog and digital voltages that may vary across the full power-supply range (from VCC to GND). The HC4066A is identical in pinout to the metal-gate CMOS MC14016 and MC14066. Each device has four independent switches. The device has been designed so the ON resistances (RON) are more linear over input voltage than RON of metal-gate CMOS analog switches. The ON/OFF control inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. For analog switches with voltage-level translators, see the HC4316A.
Features http://onsemi.com MARKING DIAGRAMS
14 PDIP-14 MC74HC4066AN N SUFFIX AWLYYWWG CASE 646 1
14 1
14 14 1 SOIC-14 D SUFFIX CASE 751A 1 HC4066AG AWLYWW
* * * * * * * * * *
Fast Switching and Propagation Speeds High ON/OFF Output Voltage Ratio Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Wide Power-Supply Voltage Range (VCC - GND) = 2.0 to 12.0 V Analog Input Voltage Range (VCC - GND) = 2.0 to 12.0 V Improved Linearity and Lower ON Resistance over Input Voltage than the MC14016 or MC14066 Low Noise Chip Complexity: 44 FETs or 11 Equivalent Gates Pb-Free Packages are Available
14 14 1 TSSOP-14 DT SUFFIX CASE 948G 1
HC40 66A ALYWG G
14 SOEIAJ-14 F SUFFIX CASE 965 1 A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location) 74HC4066A ALYWG
14 1
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
October, 2006 - Rev. 8
1
Publication Order Number: MC74HC4066A/D
MC74HC4066A
PIN ASSIGNMENT
XA YA YB XB
B ON/OFF CONTROL C ON/OFF CONTROL
LOGIC DIAGRAM
XA
A ON/OFF CONTROL
1 2 3 4 5 6 7
14 13 12 11 10 9 8
VCC
A ON/OFF CONTROL D ON/OFF CONTROL
1 13 4 5 8 6 11 12
2
YA
XD YD YC XC
XB
B ON/OFF CONTROL
3
YB
ANALOG OUTPUTS/INPUTS
GND
XC
C ON/OFF CONTROL
9
YC
FUNCTION TABLE
On/Off Control Input L H State of Analog Switch Off On
XD
D ON/OFF CONTROL
10
YD
ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD PIN 14 = VCC PIN 7 = GND
ORDERING INFORMATION
Device MC74HC4066AN MC74HC4066ANG MC74HC4066AD MC74HC4066ADG MC74HC4066ADR2 MC74HC4066ADR2G MC74HC4066ADTR2 MC74HC4066ADTR2G MC74HC4066AFEL MC74HC4066AFELG Package PDIP-14 PDIP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* SOEIAJ-14 SOEIAJ-14 (Pb-Free) 2000 / Tape & Reel 2500 / Tape & Reel 55 Units / Rail 25 Units / Rail Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74HC4066A
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MAXIMUM RATINGS
VCC VIS Vin I PD SymbolIIIIIIIIIIIIII Parameter Positive DC Supply Voltage (Referenced to GND) Analog Input Voltage (Referenced to GND) Digital Input Voltage (Referenced to GND) DC Current Into or Out of Any Pin Power Dissipation in Still Air, Value Unit V V V - 0.5 to + 14.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 25 750 500 450 mA Plastic DIP EIAJ/SOIC Package TSSOP Package mW Tstg TL Storage Temperature - 65 to + 150 260 C C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating - Plastic DIP: - 10 mW/C from 65 to 125C EIAJ/SOIC Package: - 7 mW/C from 65 to 125C TSSOP Package: - 6.1 mW/C from 65 to 125C For high frequency or heavy load considerations, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIS Vin TA Parameter
Min 2.0
Max
Unit V V V V
Positive DC Supply Voltage (Referenced to GND) Analog Input Voltage (Referenced to GND) Digital Input Voltage (Referenced to GND) Static or Dynamic Voltage Across Switch
12.0 VCC VCC 1.2
GND GND -
VIO* tr, tf
Operating Temperature, All Package Types Input Rise and Fall Time, ON/OFF Control Inputs (Figure 10)
-55 0 0 0 0 0
+ 125 1000 600 500 400 250
C ns
VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 9.0 V VCC = 12.0 V
*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)
VCC V
Guaranteed Limit v 85C 1.5 2.1 3.15 6.3 8.4 0.5 0.9 1.35 2.7 3.6
Symbol VIH
Parameter
Test Conditions
- 55 to 25C 1.5 2.1 3.15 6.3 8.4 0.5 0.9 1.35 2.7 3.6
v 125C 1.5 2.1 3.15 6.3 8.4 0.5 0.9 1.35 2.7 3.6
Unit V
Minimum High-Level Voltage ON/OFF Control Inputs
Ron = Per Spec
2.0 3.0 4.5 9.0 12.0 2.0 3.0 4.5 9.0 12.0
VIL
Maximum Low-Level Voltage ON/OFF Control Inputs
Ron = Per Spec
V
Iin
Maximum Input Leakage Current ON/OFF Control Inputs
Vin = VCC or GND Vin = VCC or GND VIO = 0 V
12.0
0.1 2 4
1.0 20 40
1.0 40 160
mA mA
ICC
Maximum Quiescent Supply Current (per Package)
6.0 12.0
NOTE: Information on typical parametric values can be found in the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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MC74HC4066A
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)
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Guaranteed Limit v 85C - - 160 85 85 - - 85 60 60 - 25 20 20 Symbol Ron Parameter Test Conditions VCC V - 55 to 25C - - 120 70 70 - - 70 50 50 - 20 15 15 v 125C - - 200 100 100 - - 120 80 80 - 30 25 25 Unit W Maximum "ON" Resistance Vin = VIH VIS = VCC to GND IS v 2.0 mA (Figures 1, 2) 2.0 3.0 4.5 9.0 12.0 Vin = VIH VIS = VCC or GND (Endpoints) IS v 2.0 mA (Figures 1, 2) Vin = VIH VIS = 1/2 (VCC - GND) IS v 2.0 mA Vin = VIL VIO = VCC or GND Switch Off (Figure 3) 2.0 3.0 4.5 9.0 12.0 2.0 4.5 9.0 12.0 DRon Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package W Ioff Maximum Off-Channel Leakage Current, Any One Channel 12.0 0.1 0.5 1.0 mA Ion Maximum On-Channel Leakage Current, Any One Channel Vin = VIH VIS = VCC or GND (Figure 4) 12.0 0.1 0.5 1.0 mA At supply voltage (VCC) approaching 3 V the analog switch-on resistance becomes extremely non-linear. Therefore, for low-voltage operation, it is recommended that these devices only be used to control digital signals. NOTE: Information on typical parametric values can be found in the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
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Guaranteed Limit v 85C 50 40 13 13 13 90 70 38 28 28 90 50 32 32 32 10 Symbol tPLH, tPHL Parameter VCC V - 55 to 25C 40 30 10 10 10 80 60 30 25 25 80 45 25 25 25 10 v 125C 60 50 15 15 15 Unit ns Maximum Propagation Delay, Analog Input to Analog Output (Figures 8 and 9) 2.0 3.0 4.5 9.0 12.0 2.0 3.0 4.5 9.0 12.0 2.0 3.0 4.5 9.0 12.0 - - - tPLZ, tPHZ Maximum Propagation Delay, ON/OFF Control to Analog Output (Figures 10 and 11) 110 80 45 30 30 ns tPZL, tPZH Maximum Propagation Delay, ON/OFF Control to Analog Output (Figures 10 and 1 1) 100 60 37 37 37 10 ns C Maximum Capacitance ON/OFF Control Input pF Control Input = GND Analog I/O Feedthrough 35 1.0 35 1.0 35 1.0 NOTES: 1. For propagation delays with loads other than 50 pF, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 15 CPD Power Dissipation Capacitance (Per Switch) (Figure 13)* pF * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)
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MC74HC4066A
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
IIIIIIIIIIIIIIIIIIIII I II I I I IIIIIIIIIIIII I III I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III I I I IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII II III I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I III I I I I IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II II I IIIIIIIIIIIIIIIIIIIII I I I I I III I I IIIIIIIIIIIII IIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIII I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I II I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II III I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII
Symbol BW Parameter Test Conditions VCC V Limit* 25C 54/74HC 150 160 160 Unit Maximum On-Channel Bandwidth or Minimum Frequency Response (Figure 5) Off-Channel Feedthrough Isolation (Figure 6) fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads - 3 dB RL = 50 W, CL = 10 pF fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W, CL = 50 pF fin = 1.0 MHz, RL = 50 W, CL = 10 pF 4.5 9.0 12.0 4.5 9.0 12.0 4.5 9.0 12.0 4.5 9.0 12.0 4.5 9.0 12.0 4.5 9.0 12.0 4.5 9.0 12.0 MHz - - 50 - 50 - 50 - 40 - 40 - 40 60 130 200 30 65 100 dB - Feedthrough Noise, Control to Switch (Figure 7) Vin v 1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS = 0 A RL = 600 W, CL = 50 pF RL = 10 kW, CL = 10 pF mVPP - Crosstalk Between Any Two Switches (Figure 12) fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W, CL = 50 pF fin = 1.0 MHz, RL = 50 W, CL = 10 pF - 70 - 70 - 70 - 80 - 80 - 80 dB THD Total Harmonic Distortion (Figure 14) fin = 1 kHz, RL = 10 kW, CL = 50 pF THD = THDMeasured - THDSource VIS = 4.0 VPP sine wave VIS = 8.0 VPP sine wave VIS = 11.0 VPP sine wave % 4.5 9.0 12.0 0.10 0.06 0.04 *Guaranteed limits not tested. Determined by design and verified by qualification.
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MC74HC4066A
400 350 300 RON @ 2 V 250 200 150 100 50 0 0.00 0.20 0.40 0.60 0.80 1.00 +25 C +125C -55C
1.20
1.40
1.60
1.80
2.00
Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
Figure 1a. Typical On Resistance, VCC = 2.0 V
200 180 160 RON @ 3 V 140 120 100 80 60 40 20 +25 C +125C -55C
0 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 2.40 2.60 2.80 3.00 Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
Figure 1b. Typical On Resistance, VCC = 3.0 V
200 180 160 RON @ 4.5 V 140 120 100 80 60 40 20 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 +25 C +125C -55C
Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
Figure 1c. Typical On Resistance, VCC = 4.5 V http://onsemi.com
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MC74HC4066A
90 80 70 RON @ 6 V 60 50 40 30 20 10 0 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 +25 C +125C -55C 4.00 4.50 5.00 5.50 6.00
Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
Figure 1d. Typical On Resistance, VCC = 6.0 V
90 80 70 RON @ 9V 60 50 40 30 20 10 0 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 +25 C +125C -55C
Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
Figure 1e. Typical On Resistance, VCC = 9.0 V
60 50 RON @ 12 V 40 30 20 10 0 0.00 +25 C +125C -55C 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 11.00 12.00
Vis, INPUT VOLTAGE (VOLTS), REFERENCED TO GROUND
Figure 1f. Typical On Resistance, VCC = 12.0 V http://onsemi.com
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MC74HC4066A
PLOTTER
PROGRAMMABLE POWER SUPPLY - +
MINI COMPUTER
DC ANALYZER
VCC DEVICE UNDER TEST
ANALOG IN
COMMON OUT
GND
Figure 2. On Resistance Test Set-Up
VCC VCC GND VCC A OFF 14 VCC A GND ON 14 N/C VCC
7
SELECTED CONTROL INPUT
VIL 7
SELECTED CONTROL INPUT
VIH
Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up
Figure 4. Maximum On Channel Leakage Current, Test Set-Up
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MC74HC4066A
VCC 14 fin 0.1mF ON
VOS fin 0.1mF
VIS OFF RL SELECTED CONTROL INPUT 7
VCC 14
VOS
CL*
dB METER
CL*
dB METER
7
SELECTED CONTROL INPUT
VCC
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 5. Maximum On-Channel Bandwidth Test Set-Up
Figure 6. Off-Channel Feedthrough Isolation, Test Set-Up
VCC/2 14 RL OFF/ON
VCC
VCC/2
RL IS
VOS CL* VCC ANALOG IN tPLH 50% 50% GND tPHL
VCC GND
Vin 1 MHz tr = tf = 6 ns CONTROL
7
SELECTED CONTROL INPUT
ANALOG OUT *Includes all probe and jig capacitance.
Figure 7. Feedthrough Noise, ON/OFF Control to Analog Out, Test Set-Up
Figure 8. Propagation Delays, Analog In to Analog Out
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MC74HC4066A
VCC 14 ANALOG IN ON ANALOG OUT CL* 50% ANALOG OUT 50% tPZH tPHZ 90% VOH HIGH IMPEDANCE TEST POINT CONTROL 90% 50% 10% tPZL tPLZ tr tf VCC GND HIGH IMPEDANCE 10% VOL
7
SELECTED CONTROL INPUT
VCC
*Includes all probe and jig capacitance.
Figure 9. Propagation Delay Test Set-Up
Figure 10. Propagation Delay, ON/OFF Control to Analog Out
VIS VCC fin RL ON 0.1 mF TEST POINT OFF VCC OR GND RL SELECTED CONTROL INPUT 7 VCC/2 RL CL* RL CL* 14 VOS
POSITION 1 WHEN TESTING tPHZ AND tPZH 1 2 VCC 1 2 ON/OFF CL* SELECTED CONTROL INPUT 7 *Includes all probe and jig capacitance. POSITION 2 WHEN TESTING tPLZ AND tPZL VCC 14 1 kW
VCC/2
VCC/2
*Includes all probe and jig capacitance.
Figure 11. Propagation Delay Test Set-Up
Figure 12. Crosstalk Between Any Two Switches, Test Set-Up
VCC A 14 N/C OFF/ON N/C 0.1 mF fin ON RL SELECTED CONTROL INPUT VCC/2 7 SELECTED CONTROL INPUT VCC CL* VIS
VCC
VOS TO DISTORTION METER
7
ON/OFF CONTROL *Includes all probe and jig capacitance.
Figure 13. Power Dissipation Capacitance Test Set-Up
Figure 14. Total Harmonic Distortion, Test Set-Up
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MC74HC4066A
0 -10 -20 -30 dBm -40 -50 -60 -70 -80 -90 1.0 2.0 FREQUENCY (kHz) 3.0 DEVICE SOURCE FUNDAMENTAL FREQUENCY
Figure 15. Plot, Harmonic Distortion
APPLICATION INFORMATION The ON/OFF Control pins should be at VCC or GND logic levels, VCC being recognized as logic high and GND being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to VCC or GND through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked-up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages VCC and GND. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below GND. In the example
below, the difference between VCC and GND is twelve volts. Therefore, using the configuration in Figure 16, a maximum analog signal of twelve volts peak-to-peak can be controlled. When voltage transients above VCC and/or below GND are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 17. These diodes should be small signal, fast turn-on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with Mosorbs (MosorbTM is an acronym for high current surge protectors). Mosorbs are fast turn-on devices ideally suited for precise DC protection with no inherent wear out mechanism.
VCC = 12 V + 12 V 0V SELECTED CONTROL INPUT 7 ANALOG I/O 14 ON ANALOG O/I + 12 V 0V Dx
VCC 16 ON Dx VCC SELECTED CONTROL INPUT 7
VCC Dx
Dx
OTHER CONTROL INPUTS (VCC OR GND)
OTHER CONTROL INPUTS (VCC OR GND)
Figure 16. 12 V Application
Figure 17. Transient Suppressor Application
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11
MC74HC4066A
+5 V +5 V
ANALOG SIGNALS R* R* R* R* 5 6 14 15 R* = 2 TO 10 kW
14
ANALOG SIGNALS
ANALOG SIGNALS HCT BUFFER 5 6 14 15
14
ANALOG SIGNALS
LSTTL/ NMOS
HC4066A
LSTTL/ NMOS
HC4066A
CONTROL INPUTS 7
CONTROL INPUTS 7
a. Using Pull-Up Resistors
b. Using HCT Buffer Figure 18. LSTTL/NMOS to HCMOS Interface
VDD = 5 V
VCC = 5 TO 12 V
13 3 5 7 9 11 14
1
16
ANALOG SIGNALS
14 HC4066A
ANALOG SIGNALS
MC14504
2 4 6 10
5 6 14 15 CONTROL INPUTS 7
8
Figure 19. TTL/NMOS-to-CMOS Level Converter Analog Signal Peak-to-Peak Greater than 5 V (Also see HC4316A)
CHANNEL 4
1 OF 4 SWITCHES 1 OF 4 SWITCHES COMMON I/O 1 OF 4 SWITCHES 1 OF 4 SWITCHES - INPUT 1 OF 4 SWITCHES + 0.01 mF 1 2 34 CONTROL INPUTS LF356 OR EQUIVALENT OUTPUT
CHANNEL 3
CHANNEL 2
CHANNEL 1
Figure 20. 4-Input Multiplexer
Figure 21. Sample/Hold Amplifier
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12
MC74HC4066A
PACKAGE DIMENSIONS
PDIP-14 CASE 646-06 ISSUE P
14
8
B
1 7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10 _ 0.38 1.01
A F N -T-
SEATING PLANE
L C
H
G
D 14 PL
K
M
J M
DIM A B C D F G H J K L M N
0.13 (0.005)
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13
MC74HC4066A
PACKAGE DIMENSIONS
SOIC-14 CASE 751A-03 ISSUE H
-A-
14 8
-B-
P 7 PL 0.25 (0.010)
M
B
M
1
7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
G C -T-
SEATING PLANE
R X 45 _
F
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04 1 0.58
14X
14X
1.52
1.27 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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14
MC74HC4066A
PACKAGE DIMENSIONS
TSSOP-14 CASE 948G-01 ISSUE B
14X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V N
S
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K
0.15 (0.006) T U
S
J J1
SECTION N-N
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
SOLDERING FOOTPRINT*
7.06 1
0.36
14X
14X
1.26
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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15
EEE CCC EEE CCC CCC
A -V-
K1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 -W- K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_
0.65 PITCH
DIMENSIONS: MILLIMETERS
MC74HC4066A
PACKAGE DIMENSIONS
SOEIAJ-14 CASE 965-01 ISSUE A
14
8
LE Q1 E HE M_ L DETAIL P
1
7
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.004 0.008 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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16
MC74HC4066A/D

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