 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| MC74HCT74A Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs High-Performance Silicon-Gate CMOS The MC74HCT74A is identical in pinout to the LS74. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device consists of two D flip-flops with individual Set, Reset, and Clock inputs. Information at a D-input is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q outputs are available from each flip-flop. The Set and Reset inputs are asynchronous. Features http://onsemi.com MARKING DIAGRAMS 14 PDIP-14 N SUFFIX CASE 646 1 14 14 1 SOIC-14 D SUFFIX CASE 751A 1 A L, WL Y, YY W, WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package HCT74AG AWLYWW MC74HCT74AN AWLYYWWG 14 1 * * * * * * * * Output Drive Capability: 10 LSTTL Loads TTL NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1.0 mA In Compliance With the JEDEC Standard No. 7.0 A Requirements Chip Complexity: 136 FETs or 34 Equivalent Gates Pb-Free Packages are Available LOGIC DIAGRAM RESET 1 DATA 1 CLOCK 1 SET 1 RESET 2 DATA 2 CLOCK 2 SET 2 1 2 3 4 13 12 11 10 Value 34 Units ea. ns PIN 14 = VCC PIN 7 = GND 9 8 Q2 Q2 5 6 Q1 Q1 PIN ASSIGNMENT RESET 1 DATA 1 CLOCK 1 SET 1 Q1 Q1 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC RESET 2 DATA 2 CLOCK 2 SET 2 Q2 Q2 FUNCTION TABLE Inputs Set Reset Clock Data L H L H H H H H H L L H H H H H X X X X X X H L X X X Outputs Q Q H L L H H* H* H L L H No Change No Change No Change (c) Semiconductor Components Industries, LLC, 2006 October, 2006 - Rev. 10 III I IIIIIIIIIIIIIII II IIIIIIIIIIIIIII II III I IIIIIIIIIIIIIII II II IIIIIIIIIIIIIII IIIIIIIIIIIIIII II II IIIIIIIIIIIIIII IIIIIIIIIIIIIII II IIII I IIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIII Design Criteria Internal Gate Count Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product 1.5 5.0 mW pJ .0075 Equivalent to a two-input NAND gate. 1 L H *Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. Publication Order Number: MC74HCT74A/D MC74HCT74A II I I I I I IIIIIIIII I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII I II I II IIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIII III I II II I I III I I I I I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIII I I I I II I I I I I II I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIII III I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I III I I I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I II I III I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II III I I I IIIIIIIIIIIIIIIIIIIIIII III I I III I I III I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III III I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II II I I IIIIIIIIIIIIIIIIIIIIIII I III I II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIII III II I II I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II I I III IIIIIIIIIIIIIIIIIIIIIII II II I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I I III II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII II IIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII IIIIIII I IIII IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS VCC Vin Iin Vout Iout PD SymbolIIIIIIIIIIIIII Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0III V V V - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 25 50 750 500 DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA DC Output Current, per Pin ICC DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Plastic DIP SOIC Package mW _C _C Tstg TL - 65 to + 150 260 Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating -- Plastic DIP: -10mW/_C from 65_ to 125_C SOIC Package: -7mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol VCC TA Parameter Min 4.5 0 Max 5.5 Unit V V DC Supply Voltage (Referenced to GND) Vin, Vout tr, tf DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC 500 - 55 0 + 125 _C ns DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit v 85_C 2.0 2.0 0.8 0.8 4.4 5.4 Symbol VIH VIL Parameter Test Conditions VCC V 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 - 55 to 25_C 2.0 2.0 0.8 0.8 4.4 5.4 v 125_C 2.0 2.0 0.8 0.8 4.4 5.4 3.7 0.1 0.1 0.4 80 Unit V V V Minimum High-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 mA Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL |Iout| v 4.0 mA Vin = VIH or VIL |Iout| v 20 mA Vin = VIH or VIL |Iout| v 4.0 mA Maximum Low-Level Input Voltage VOH Minimum High-Level Output Voltage 3.98 0.1 0.1 3.84 0.1 0.1 VOL Maximum Low-Level Output Voltage V 0.26 2.0 0.33 20 Iin Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Vin = VCC or GND 0.1 1.0IIII mA 1.0 mA ICC Vin = VCC or GND Iout = 0 mA DICC Additional Quiescent Supply Current 2.9 2.4 5.5 mA 1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Vin = 2.4 V, Any One Input Vin = VCC or GND, Other Inputs lout = 0 mA -55_CIIIIII 25_C to 125_CIII http://onsemi.com 2 MC74HCT74A AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V 10%, CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol fmax Parameter Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) - 55 to 25_C 30 24 24 15 10 v 85_C 24 30 30 19 10 v 125_C 20 36 36 22 10 Unit MHz ns ns ns III I I I II I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I III I I I II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I II I I I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I I I II I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII I I I I II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIII I I IIII III I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII I I IIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII II tPLH, tPHL tPLH, tPHL tTLH, tTHL Cin Maximum Propagation Delay, Clock to Q or Q (Figures 1 and 4) Maximum Propagation Delay, Set or Reset to Q or Q (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Input Capacitance pF 2. For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 32 2f CPD Power Dissipation Capacitance (Per Enabled Output)* pF 3. Used to determine the no-load dynamic power consumption: P D = CPD VCC ON Semiconductor High-Speed CMOS Data Book (DL129/D). + ICC VCC . For load considerations, see Chapter 2 of the TIMING REQUIREMENTS (VCC = 5.0 V 10%, CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit v 85_C - 55 to 25_C v 125_C Symbol tsu th Parameter Fig. 3 3 2 1 2 1 Min 15 3 6 Max Min 19 3 8 Max Min 22 3 9 Max Units ns ns ns ns ns ns Minimum Setup Time, Data to Clock Minimum Hold Time, Clock to Data trec tw tw Minimum Recovery Time, Set or Reset Inactive to Clock Minimum Pulse Width, Clock 15 15 19 19 22 22 Minimum Pulse Width, Set or Reset tr, tf Maximum Input Rise and Fall Times 500 500 500 ORDERING INFORMATION Device MC74HCT74AN MC74HCT74ANG MC74HCT74AD MC74HCT74ADG MC74HCT74ADR2 MC74HCT74ADR2G Package PDIP-14 PDIP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) 2500 / Tape & Reel 55 Units / Rail 25 Units / Rail Shipping For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 3 MC74HCT74A SWITCHING WAVEFORMS tr CLOCK 2.7 V 1.3 V 0.3 V tw 1/fmax tPLH Q OR Q 90% 1.3 V 10% tTLH tTHL tPHL Q OR Q tf 3V GND Q OR Q tw SET OR RESET 1.3 V tPHL 1.3 V tPLH 1.3 V trec 1.3 V 3V GND 3V GND CLOCK Figure 1. Figure 2. VALID 3V DATA 1.3 V GND tsu th 3V 1.3 V CLOCK GND DEVICE UNDER TEST TEST POINT OUTPUT C L* *Includes all probe and jig capacitance Figure 3. Figure 5. SET 4, 10 2, 12 5, 9 Q DATA CLOCK 3, 11 6, 8 Q 1, 13 RESET Figure 4. Expanded Logic Diagram http://onsemi.com 4 MC74HCT74A PACKAGE DIMENSIONS PDIP-14 CASE 646-06 ISSUE P 14 8 B 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10 _ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10 _ 0.38 1.01 A F N -T- SEATING PLANE L C H G D 14 PL K M J M DIM A B C D F G H J K L M N 0.13 (0.005) http://onsemi.com 5 MC74HCT74A PACKAGE DIMENSIONS SOIC-14 CASE 751A-03 ISSUE H -A- 14 8 -B- P 7 PL 0.25 (0.010) M B M 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. G C -T- SEATING PLANE R X 45 _ F D 14 PL 0.25 (0.010) K M M S J TB A S SOLDERING FOOTPRINT* 7X DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 7.04 1 0.58 14X 14X 1.52 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 6 MC74HCT74A/D |
Price & Availability of MC74HCT74A06
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |