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| MC74VHC1G126 Noninverting 3-State Buffer The MC74VHC1G126 is an advanced high speed CMOS noninverting 3-state buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffered 3-state output which provides high noise immunity and stable output. The MC74VHC1G126 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74VHC1G126 to be used to interface 5 V circuits to 3 V circuits. Features http://onsemi.com MARKING DIAGRAMS 5 5 1 SC-88A/SOT-353/SC-70 DF SUFFIX CASE 419A W2 M G G M * * * * * * * High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 1 mA (Max) at TA = 25C Power Down Protection Provided on Inputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 58; Equivalent Gates = 15 Pb-Free Packages are Available 1 5 5 1 TSOP-5/SOT-23/SC-59 DT SUFFIX CASE 483 1 W2 M G G OE 1 5 VCC W2 = Device Code M = Date Code* G = Pb-Free Package (Note: Microdot may be in either location) *Date Code orientation and/or position may vary depending upon manufacturing location. IN A 2 PIN ASSIGNMENT GND 3 4 OUT Y 1 2 3 OE IN A GND OUT Y VCC Figure 1. Pinout (Top View) 4 5 OE IN A EN OUT Y A Input FUNCTION TABLE OE Input H H L Y Output L H Z Figure 2. Logic Symbol L H X ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. (c) Semiconductor Components Industries, LLC, 2007 1 February, 2007 - Rev. 14 Publication Order Number: MC74VHC1G126/D MC74VHC1G126 MAXIMUM RATINGS Symbol VCC VIN VOUT IIK IOK IOUT ICC PD qJA TL TJ Tstg VESD DC Supply Voltage DC Input Voltage DC Output Voltage Input Diode Current Output Diode Current DC Output Current, per Pin DC Supply Current, VCC and GND Power dissipation in still air Thermal resistance Lead temperature, 1 mm from case for 10 secs Junction temperature under bias Storage temperature ESD Withstand Voltage Human Body Model (Note 1) Machine Model (Note 2) Charged Device Model (Note 3) Above VCC and Below GND at 125C (Note 4) SC-88A, TSOP-5 SC-88A, TSOP-5 VOUT < GND; VOUT > VCC VCC = 0 High or Low State Characteristics Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to 7.0 -0.5 to VCC + 0.5 -20 +20 +25 +50 200 333 260 +150 -65 to +150 > 2000 > 200 N/A 500 Unit V V V mA mA mA mA mW C/W C C C V ILatchup Latchup Performance mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Tested to EIA/JESD22-A114-A 2. Tested to EIA/JESD22-A115-A 3. Tested to JESD22-C101-A 4. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN VOUT TA tr , tf DC Supply Voltage DC Input Voltage DC Output Voltage Operating Temperature Range Input Rise and Fall Time VCC = 3.3 V 0.3 V VCC = 5.0 V 0.5 V Characteristics Min 2.0 0.0 0.0 -55 0 0 Max 5.5 5.5 VCC +125 100 20 Unit V V V C ns/V Device Junction Temperature versus Time to 0.1% Bond Failures NORMALIZED FAILURE RATE Junction Temperature C 80 90 100 110 120 130 140 Time, Hours 1,032,200 419,300 178,700 79,600 37,000 17,800 8,900 Time, Years 117.8 47.9 20.4 9.4 4.2 2.0 1.0 FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR TJ = 130 C TJ = 120 C TJ = 110 C TJ = 100 C TJ = 80 C 100 TIME, YEARS TJ = 90 C 1 1 10 1000 Figure 3. Failure Rate vs. Time Junction Temperature http://onsemi.com 2 MC74VHC1G126 DC ELECTRICAL CHARACTERISTICS Symbol VIH Parameter Minimum High-Level Input Voltage Test Conditions VCC (V) 2.0 3.0 4.5 5.5 2.0 3.0 4.5 5.5 VIN = VIH or VIL IOH = -50 mA VIN = VIH or VIL IOH = -4 mA IOH = -8 mA VOL Maximum Low-Level Output Voltage VIN = VIH or VIL VIN = VIH or VIL IOL = 50 mA VIN = VIH or VIL IOL = 4 mA IOL = 8 mA IOZ IIN ICC Maximum 3-State Leakage Current Maximum Input Leakage Current Maximum Quiescent Supply Current VIN = VIH or VIL VOUT = VCC or GND VIN = 5.5 V or GND VIN = VCC or GND 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 5.5 0 to 5.5 5.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.2 5 0.1 1.0 2.0 3.0 4.5 TA = 25C Min 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 2.5 1.0 20 Typ Max TA 85C Min 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 1.9 2.9 4.4 2.34 3.66 0.1 0.1 0.1 0.52 0.52 2.5 1.0 40 mA mA mA V Max -55 TA 125C Min 1.5 2.1 3.15 3.85 0.5 0.9 1.35 1.65 Max Unit V VIL Maximum Low-Level Input Voltage V VOH Minimum High-Level Output Voltage VIN = VIH or VIL V V V II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I I I II I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII II I I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I I I IIIIIIIIII I I I I III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII II III I IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I IIII IIIIIIIIII III II I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I I II I I I II I I I III I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I IIIIIIIIII III II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II II I I II I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII II I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII AC ELECTRICAL CHARACTERISTICS Cload = 50 pF, Input tr = tf = 3.0 ns Symbol tPLH, tPHL Parameter Test Conditions Min TA = 25C Typ 4.5 6.4 3.5 4.5 4.5 6.4 3.5 4.5 6.5 8.0 4.8 7.0 4.0 6.0 TA 85C -55 TA 125C Min Max Max 8.0 11.5 5.5 7.5 Min Max Unit ns Maximum Propagation Delay, Input A to Y (Figures 3. and 5.) VCC = 3.3 0.3 V CL = 15 pF CL = 50 pF VCC = 5.0 0.5 V CL = 15 pF CL = 50 pF VCC = 3.3 0.3 V CL = 15 pF RL = 1000 W CL = 50 pF VCC = 5.0 0.5 V CL = 15 pF RL = 1000 W CL = 50 pF VCC = 3.3 0.3 V CL = 15 pF RL = 1000 W CL = 50 pF VCC = 5.0 0.5 V CL = 15 pF RL = 1000 W CL = 50 pF 9.5 13.0 6.5 8.5 12.0 16.0 8.5 10.5 11.5 15.0 tPZL, tPZH Maximum Output Enable Time, Input OE to Y (Figures 4. and 5.) 8.0 11.5 5.1 7.1 9.5 13.0 6.0 8.0 ns 8.5 10.5 14.5 18.0 10.0 12.0 10 tPLZ, tPHZ Maximum Output Disable Time, Input OE to Y (Figures 4. and 5.) 9.7 13.2 6.8 8.8 10 11.5 15.0 ns 8.0 10.0 10 CIN Maximum Input Capacitance pF pF COUT Maximum 3-State Output Capacitance (Output in High Impedance State) Typical @ 25C, VCC = 5.0 V 8.0 CPD Power Dissipation Capacitance (Note 5) pF 5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. http://onsemi.com 3 MC74VHC1G126 SWITCHING WAVEFORMS OE VCC GND tPZL Y 50% VCC tPZH Y 50% VCC tPHZ tPLZ HIGH IMPEDANCE VOL + 0.3V VOH - 0.3V HIGH IMPEDANCE 50% A tPLH 50% tPHL 50% VCC VCC GND Y Figure 4. Switching Waveforms Figure 5. TEST POINT OUTPUT DEVICE UNDER TEST C L* DEVICE UNDER TEST TEST POINT OUTPUT 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. CL * *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 6. Test Circuit Figure 7. Test Circuit INPUT Figure 8. Input Equivalent Circuit ORDERING INFORMATION Device MC74VHC1G126DFT1 M74VHC1G126DFT1G MC74VHC1G126DFT2 M74VHC1G126DFT2G MC74VHC1G126DTT1 M74VHC1G126DTT1G Package SC-88A/SOT-353/SC-70 SC-88A/SOT-353/SC-70 (Pb-Free) SC-88A/SOT-353/SC-70 SC-88A/SOT-353/SC-70 (Pb-Free) TSOP-5/SOT-23/SC-59 TSOP-5/SOT-23/SC-59 (Pb-Free) 3000 Units / Tape & Reel Shipping For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 4 MC74VHC1G126 PACKAGE DIMENSIONS SC-88A / SOT-353 / SC70 CASE 419A-02 ISSUE H A G 5 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 419A-01 OBSOLETE. NEW STANDARD 419A-02. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. S 1 2 3 -B- DIM A B C D G H J K N S D 5 PL 0.2 (0.008) M B M N J C INCHES MIN MAX 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 BSC --- 0.004 0.004 0.010 0.004 0.012 0.008 REF 0.079 0.087 MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC --- 0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20 H K SOLDERING FOOTPRINT* 0.50 0.0197 0.65 0.025 0.65 0.025 0.40 0.0157 mm inches 1.9 0.0748 SCALE 20:1 *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 5 MC74VHC1G126 PACKAGE DIMENSIONS TSOP-5 CASE 483-02 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL TRIMMED LEAD IS ALLOWED IN THIS LOCATION. TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2 FROM BODY. DIM A B C D G H J K L M S MILLIMETERS MIN MAX 3.00 BSC 1.50 BSC 0.90 1.10 0.25 0.50 0.95 BSC 0.01 0.10 0.10 0.26 0.20 0.60 1.25 1.55 0_ 10 _ 2.50 3.00 NOTE 5 2X D 5X 0.20 C A B 5 1 2 4 3 0.10 T 0.20 T L G A B S M K DETAIL Z 2X DETAIL Z J C 0.05 H T SEATING PLANE SOLDERING FOOTPRINT* 1.9 0.074 0.95 0.037 2.4 0.094 1.0 0.039 0.7 0.028 SCALE 10:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 6 MC74VHC1G126/D |
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