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MC74VHCT08A Quad 2-Input AND Gate
The MC74VHCT08A is an advanced high speed CMOS 2-input AND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The VHCT inputs are compatible with TTL levels. This device can be used as a level converter for interfacing 3.3 V to 5.0 V, because it has full 5.0 V CMOS level output swings. The VHCT08A input structures provide protection when voltages between 0 V and 5.5 V are applied, regardless of the supply voltage. The output structures also provide protection when VCC = 0 V. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V systems to 3.0 V systems.
Features
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14 SOIC-14 D SUFFIX CASE 751A 1 VHCT08AG AWLYWW
1
14 TSSOP-14 DT SUFFIX CASE 948G 1 VHCT 08A ALYWG G
* * * * * * * * * * * *
High Speed: tPD = 4.3 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 2 mA (Max) at TA = 25C TTL-Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: Human Body Model; > 2000 V, Machine Model; > 200 V Chip Complexity: 24 FETs or 6 Equivalent Gates Pb-Free Packages are Available*
1
14 SOEIAJ-14 M SUFFIX CASE 965 1 VHCT08 ALYWG
1
A = Assembly Location WL, L = Wafer Lot Y, YY = Year WW, W = Work Week G or G = Pb-Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
1
March, 2006 - Rev. 5
Publication Order Number: MC74VHCT08A/D
MC74VHCT08A
A1 B1 A2 B2 A3 B3 A4 B4 1 2 4 5 9 10 12 13 3 VCC Y1 14 B4 13 A4 12 Y4 11 B3 10 A3 9 Y3 8
6
Y2 Y = AB
8
Y3
1 A1
2 B1
3 Y1
4 A2
5 B2
6 Y2
7 GND
11
Y4
(Top View) Figure 2. Pinout: 14-Lead Packages
Figure 1. Logic Diagram FUNCTION TABLE
Inputs A L L H H B L H L H Output Y L L L H
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III I I I I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I III IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII II
II I I IIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIII II II IIIIIIIIIIIIIIIIIIIIIII II I II IIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIII I II III I I IIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II III I II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II IIIIIIII I I II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I
Rating Symbol VCC Vin Value Unit V V V DC Supply Voltage DC Input Voltage -0.5 to +7.0 -0.5 to +7.0 DC Output Voltage Vout IIK -0.5 to VCC +0.5 -20 20 25 50 Input Diode Current mA mA mA mA Output Diode Current IOK Iout DC Output Current, per Pin DC Supply Current, VCC and GND Pins ICC Power Dissipation in Still Air, SOIC Packages TSSOP Package Storage Temperature PD 500 450 mW C Tstg -65 to +150
MAXIMUM RATINGS*
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Derating - SOIC Packages: - 7 mW/C from 65 to 125C TSSOP Package: - 6.1 mW/C from 65 to 125C
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol VCC Vin Min 4.5 0 0 Max 5.5 5.5 Unit V V V
DC Supply Voltage DC Input Voltage
DC Output Voltage
Vout TA
VCC
Operating Temperature
-40 0
+ 85III C 20 ns/V
Input Rise and Fall Time VCC = 5.0 V 0.5 V
tr, tf
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1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per gate). CPD is used to determine the no-load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.7
II II I IIIIIIIII IIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I I I I II II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I II I I I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I II I II III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIII IIIIIIIIIIIIIIII I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII III IIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I II I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I II I I I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIII IIII I IIIII I I II I I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIII IIIIII IIIIIIIIIII II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I II I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIII I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I I II I I I II I I I I I I I I II I II I I II I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIII IIIII II II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIII IIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I II I I I I II IIII I I II I I I I I I I I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I II I I I I I I I I II I I I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII I I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) DC ELECTRICAL CHARACTERISTICS
Power Dissipation Capacitance (Note 1) Maximum Input Capacitance Maximum Propagation Delay, Input A or B to Y Output Leakage Current Quiescent Supply Current Maximum Quiescent Supply Current Maximum Input Leakage Current Maximum Low-Level Output Voltage VIN = VIH or VIL Minimum High-Level Output Voltage VIN = VIH or VIL Maximum Low-Level Input Voltage Minimum High-Level Input Voltage Characteristic Parameter VCC = 5.0 0.5V CL = 15 pF CL = 50 pF VCC = 3.0 0.3V CL = 15 pF CL = 50 pF Test Conditions VIN = VCC or GND Input: VIN = 3.4 V Test Conditions VIN = VIH or VIL IOL = 4 mA IOL = 8 mA VIN = VIH or VIL IOL = 50 mA VIN = VIH or VIL IOH = -4 mA IOH = -8 mA VIN = VIH or VIL IOH = - 50 mA VIN = 5.5 V or GND VOUT = 5.5 V
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50pF, VCC = 5.0 V)
Maximum Low Level Dynamic Input Voltage
Minimum High Level Dynamic Input Voltage
Quiet Output Minimum Dynamic VOL
Quiet Output Maximum Dynamic VOL
Characteristic
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MC74VHCT08A
Symbol
IOPD
ICCT
VOH
VOL
VIH
ICC
VIL
IIN
Symbol
Symbol
VOLV
VIHD
VOLP
VILD
tPLH, tPHL
CPD
Cin
3 0 to 5.5 VCC (V) 0.0 5.5 5.5 3.0 4.5 3.0 4.5 3.0 4.5 3.0 4.5 3.0 4.5 5.5 3.0 4.5 5.5 Min TA = 25C 2.58 3.94 Min 2.9 4.4 1.2 2.0 2.0 Typ 4.3 5.8 6.2 8.7 4 -0.3 Typ 0.3 TA = 25C Typical @ 25C, VCC = 5.0V Typ 0.0 0.0 3.0 4.5 8.8 12.3 Max 5.9 7.9 10 TA = 25C 1.35 0.1 0.36 0.36 0.53 0.8 0.8 Max 0.5 2.0 0.1 0.1 Min TA 85C 20 2.48 3.80 Min 2.9 4.4 1.2 2.0 2.0 TA 85C 10.5 14.0 Max 7.0 9.0 10 1.50 1.0 0.44 0.44 0.53 0.8 0.8 Max 5.0 0.1 0.1 20 -0.8 Max 1.5 3.5 0.8 Max TA 125C 2.34 3.66 TA 125C Min 2.9 4.4 1.2 2.0 2.0 14.0 17.5 Max 9.0 11.0 10 1.65 0.52 0.52 0.53 0.8 0.8 Max 0.1 0.1 10 40 1.0II mA Unit Unit pF pF ns V V V V Unit mA mA V V V V mA
MC74VHCT08A
3.0V A or B 1.5V GND tPLH tPHL VOH Y 1.5V VOL *Includes all probe and jig capacitance DEVICE UNDER TEST OUTPUT TEST POINT
C L*
Figure 3. Switching Waveforms
Figure 4. Test Circuit
ORDERING INFORMATION
Device MC74VHCT08ADR2 MC74VHCT08ADR2G MC74VHCT08ADTR2 MC74VHCT08ADTR2G MC74VHCT08AM MC74VHCT08AMG MC74VHCT08AMEL MC74VHCT08AMELG Package SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* SOEIAJ-14 SOEIAJ-14 (Pb-Free) SOEIAJ-14 SOEIAJ-14 (Pb-Free) 2000 Units / Tape & Reel 50 Units / Rail 2500 Units / Tape &Reel 2500 Units / Tape & Reel Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *These packages are inherently Pb-Free.
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MC74VHCT08A
PACKAGE DIMENSIONS
SOIC-14 D SUFFIX CASE 751A-03 ISSUE G
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
TSSOP-14 CASE 948G-01 ISSUE A
14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E K
0.15 (0.006) T U
S
J J1
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
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CCC EEE CCC EEE CCC
A -V-
K1
DIM A B C D F G H J J1 K K1 L M
MC74VHCT08A
PACKAGE DIMENSIONS
SOEIAJ-14 CASE 965-01 ISSUE A
14
8
LE Q1 E HE M_ L DETAIL P
1
7
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.004 0.008 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74VHCT08A/D

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