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High Performance Multibit - DAC with SACD Playback AD1955
FUNCTIONAL BLOCK DIAGRAM
MASTER CLOCK INPUT CONTROL DATA INPUT 3 DSD BITSTREAM INPUT 4 DIGITAL SUPPLY
FEATURES 5 V Power Supply Stereo Audio DAC System Accepts 16-/18-/20-/24-Bit Data Supports 24-Bit, 192 kHz Sample Rate PCM Audio Data Supports SACD Bit Stream and External Digital Filter Interface Accepts a Wide Range of PCM Sample Rates Including: 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz Multibit Sigma-Delta Modulator with "Perfect Differential Linearity Restoration" for Reduced Idle Tones and Noise Floor Data Directed Scrambling DAC--Low Sensitivity to Jitter Supports SACD Playback with "Bit Expansion" Filter Differential Current Output for Optimum Performance 8.64 mA p-p Differential Output 120 dB SNR/DNR (not muted) at 48 kHz Sample Rate (A-Weighted Stereo) 123 dB SNR/DNR (Mono) -110 dB THD + N 110 dB Stop-Band Attenuation with 0.0002 dB Pass-Band Ripple 8 Oversampling Digital Filter On-Chip Clickless Volume Control Supports SACD-Mute Pattern Detection Supports 64 fS/128 fS DSD SACD with Phase Mode Internal Digital Filter Pass-Through for External Filter Master Clock: 256 fS, 512 fS, 768 f S Hardware and Software Controllable Clickless Mute Serial (SPI) Control for Serial Mode, Number of Bits, Sample Rate, Volume, Mute, De-Emphasis, Mono Mode Digital De-Emphasis for 32 kHz, 44.1 kHz, and 48 kHz Sample Rates Flexible Serial Data Port with Right-Justified, LeftJustified, I2S, and DSP Modes 28-Lead SSOP Plastic Package APPLICATIONS High End DVD Audio SACD CD Home Theater Systems Automotive Audio Systems Sampling Musical Keyboards Digital Mixing Consoles Digital Audio Effects Processors
AUTO-CLOCK DIVIDER 16-/20-/24-BIT AUDIO DATA/ EXTERNAL DIGITAL FILTER INPUT 3/4 MUX
SPI CONTROL
DSD FILTER
SERIAL DATA INTERFACE
EXTERNAL FILTER I/F
RESET
MUTE DIGITAL FILTER ENGINE S/H ANALOG SUPPLY ZERO FLAGS
NOISE-SHAPED SCRAMBLING
MULTIBIT MODULATOR
I-DAC
I-DAC
VOLTAGE REFERENCE
L-CH R-CH DIFFERENTIAL CURRENT OUTPUT
PRODUCT OVERVIEW
The AD1955 is a complete, high performance, single-chip, stereo digital audio playback system. It is comprised of a multibit sigmadelta modulator, high performance digital interpolation filters, and continuous-time differential current output DACs. Other features include an on-chip clickless stereo attenuator and mute capability, programmed through an SPI compatible serial control port. The AD1955 is fully compatible with all known DVD audio formats including 192 kHz as well as 96 kHz sample frequencies and 24 bits. It is also backward compatible by supporting 50 s/ 15 s digital de-emphasis intended for "redbook" compact discs, as well as de-emphasis at 32 kHz and 48 kHz sample rates. The AD1955 has a very flexible serial data input port that allows for glueless interconnection to a variety of ADCs, DSPs, SACD decoders, external digital filters, AES/EBU receivers, and (continued on page 12)
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
AD1955-SPECIFICATIONS
TEST CONDITIONS
(Unless otherwise noted.)
Analog Supply Voltages (AVDD) . . . . . . . . . . . . . . . . . . . . 5 V Digital Supply Voltages (DVDD) . . . . . . . . . . . . . . . . . . . . 5 V Reference Current (IREF) . . . . . . . . . . . . . . . . . . . . . 0.960 mA Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 25C Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.288 MHz Input Signal . . . . . . . . . . . . . . . . . 984.375 Hz, 0 dB Full Scale Input Sample Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 kHz Measurement Bandwidth . . . . . . . . . . . . . . . . 20 Hz to 20 kHz Word Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Bits Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 pF Load Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 k Input Voltage HI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 V Input Voltage LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 V
ANALOG PERFORMANCE
Parameter Resolution
(See figures. IREF = 0.960 mA, VBIAS = 2.80 V.)
Min Typ 24 120 123 119 120 123 119 -110 8.64 100 -3.24 2.245 2.39 -90 2.505 6 0.26 114 Max Unit Bits dB dB dB dB dB dB dB mA p-p pF mA dB V % dB ppm/C dB Degrees dB dB
SIGNAL-TO-NOISE RATIO (20 Hz to 20 kHz)* Differential Output (A-Weighted, RMS) (Stereo) Differential Output (A-Weighted, RMS) (Mono) Single-Ended (A-Weighted, RMS) (Stereo) DYNAMIC RANGE (20 Hz to 20 kHz, -60 dB Input)* Differential Output (A-Weighted, RMS) (Stereo) Differential Output (A-Weighted, RMS) (Mono) Single-Ended (A-Weighted, RMS) (Stereo) Total Harmonic Distortion + Noise (Stereo) at 0 dBFS ANALOG OUTPUTS Differential Output Range (Full Scale) Output Capacitance at Each Output Pin Output Bias Current, Each Output Out-of-Band Energy (0.5 Reference Voltage fS to 100 kHz)
114
-102.5
DC ACCURACY Gain Error Interchannel Gain Mismatch Gain Drift Interchannel Crosstalk (EIAJ Method) Interchannel Phase Deviation Mute Attenuation De-Emphasis Gain Error
0.01 25 -125 0.1 -100
0.1
*Measured with Audio Precision System Two Cascade in RMS Mode. Averaging Mode will show approximately 2 dB better performance. Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications). Specifications subject to change without notice.
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AD1955 DIGITAL I/O
Parameter Input Voltage HI (VIH) Input Voltage LO (VIL) Input Leakage (IIH @ VIH = 2.4 V) Input Leakage (IIL @ VIL = 0.8 V) High Level Output Voltage (VOH) IOH = 1 mA Low Level Output Voltage (VOL) IOL = 1 mA Input Capacitance
Specifications subject to change without notice.
(-40 C to +85 C, unless otherwise noted.)
Min 2.2 -3 -3 2.4 0.8 +3 +3 0.4 20 Typ Max Unit V V A A V V pF
TEMPERATURE
Parameter Specifications Guaranteed Functionality Guaranteed Storage
Specifications subject to change without notice.
Min -40 -55
Typ 25
Max +85 +125
Unit C C C
POWER
Parameter SUPPLIES Voltage, Digital Voltage, Analog Analog Current Analog Current--Reset Digital Current Digital Current--Reset DISSIPATION Operation--Both Supplies Operation--Analog Supply Operation--Digital Supply POWER SUPPLY REJECTION RATIO 1 kHz 300 mV p-p Signal at Analog Supply Pins 20 kHz 300 mV p-p Signal at Analog Supply Pins
Specifications subject to change without notice.
Min 4.50 4.50
Typ 5 5 20 20 22 2 210 100 110 -77 -72
Max 5.50 5.50
Unit V V mA mA mA mA mW mW mW dB dB
DIGITAL FILTER CHARACTERISTICS
Sample Rate (kHz) 44.1 48 96 192 Pass Band (kHz) DC-20 DC-21.8 DC-39.95 DC-87.2 Stop Band (kHz) 24.1-328.7 26.23-358.28 56.9-327.65 117-327.65 Stop-Band Attenuation (dB) 110 110 115 95 Pass-Band Ripple (dB) 0.0002 0.0002 0.0005 0/-0.04 (DC - 21.8 kHz) 0/-0.5 (DC - 65.4 kHz) 0/-1.5 (DC - 87.2 kHz)
Specifications subject to change without notice.
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AD1955
SPECIFICATIONS (continued)
GROUP DELAY
Chip Mode INT8 INT4 INT2 Mode Mode Mode Group Delay Calculation 5553/(128 fS) 5601/(64 fS) 5659/(32 fS) fS (kHz) 48 96 192 Group Delay 903.8 911.6 921 Unit s s s
Specifications subject to change without notice.
DIGITAL TIMING
Parameter tDMP tDML tDMH tDBH tDBL tDBP tDLS tDLH tDWH tDWL tDDS tDDH tDPHS tDSDS tDSDH tDSKP tDSKH tDSKL tDMP tDML tDMH tCLS tCLH tCDS tCDH tRSTL
(Guaranteed over -40 C to +85 C, AVDD = DVDD = 5.0 V
Description MCLK Period (FMCLK = 256 FLRCLK) MCLK LO Pulsewidth (All Modes) MCLK HI Pulsewidth (All Modes) BCLK/EF_BCLK High BCLK/EF_BCLK Low BCLK/EF_BCLK Period LRCLK/EF_WCLK Setup LRCLK Hold (DSP Serial Port Mode Only) EF_WCLK High EF_WCLK Low SDATA/EF_LDATA/EF_RDATA Setup SDATA/EF_LDATA/EF_RDATA Hold DSD_PHASE Setup DSD_DATA Setup DSD_DATA Hold DSD_SCLK Period DSD_SCLK High DSD_SCLK Low CCLK Period CCLK LO Pulsewidth CCLK HI Pulsewidth CLATCH Setup CLATCH Hold CDATA Setup CDATA Hold RST LO Pulsewidth
10%.)
Min 50 0.4 0.4 20 20 60 0 15 20 20 0 20 20 5 5 60 20 20 50 15 10 0 15 0 5 10 tDMP tDMP Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Specifications subject to change without notice.
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AD1955
ABSOLUTE MAXIMUM RATINGS * PACKAGE CHARACTERISTICS
Parameter DVDD to DGND AVDD to AGND Digital Inputs Analog Outputs AGND to DGND Reference Voltage Soldering
Min -0.3 -0.3 DGND - 0.3 AGND - 0.3 -0.3
Max 6 6 DVDD + 0.3 AVDD + 0.3 +0.3 (AVDD + 0.3)/2 300 10
Unit V V V V V C sec
Package (Thermal Resistance [Junction-to-Ambient]) JC (Thermal Resistance [Junction-to-Case])
JA
Typ 109.0 39.0
Unit C/W C/W
*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model AD1955ARS AD1955ARSRL EVAL-AD1955EB
Temperature -40C to +85C -40C to +85C
Package Description 28-Lead SSOP 28-Lead SSOP Evaluation Board
Package Option* RS-28 RS-28 on 13" Reels
*RS = Shrink Small Outline Package
PIN CONFIGURATION
DVDD 1 LRCLK/EF_WCLK 2 BCLK/EF_BCLK 3 SDATA/EF_LDATA 4 EF_RDATA 5 DSD_SCLK 6 DSD_LDATA 7
28 27 26 25 24
DGND MCLK CCLK CLATCH CDATA PD/RST
TOP VIEW 22 MUTE DSD_RDATA 8 (Not to Scale) 21 ZEROL DSD_PHASE 9 AGND 10 IOUTR+ 11 IOUTR- 12 FILTR 13 IREF 14
20 19 18 17 16 15
AD1955
23
ZEROR AGND IOUTL+ IOUTL- FILTB AVDD
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1955 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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PIN FUNCTION DESCRIPTIONS
Pin No. 1 2 3 4
I/O Input Input Input
Mnemonic DVDD LRCLK/EF_WCLK BCLK/EF_BCLK SDATA/EF_LDATA
Description Digital Power Supply Connected to Digital 5 V Supply Left/Right Clock Input for Input Data in PCM Mode Word Clock in External Filter Mode Bit Clock Input for Input Data in PCM Mode Bit Clock Input in External Filter Mode MSB First, Twos Complement Serial Audio Data Two Channel (left and right), 16-Bit to 24-Bit Data in PCM Mode Left Channel Data in External Filter Mode Not used in PCM Mode Right channel data in External Filter Mode Serial Clock Input for DSD Data. This clock should be 64 44.1 kHz, 2.8224 MHz or 128 44.1 kHz, 5.6448 MHz in Normal Mode, 128 44.1 kHz, 5.6448 MHz or 256 44.1 kHz, 11.2896 MHz in Phase Mode. DSD Left Channel Data Input DSD Right Channel Data Input DSD Phase Reference Signal. This clock should be 64 44.1 kHz, 2.8224 MHz. If not used, this pin should be connected low. Analog Ground Right Channel Positive Analog Output Right Channel Negative Analog Output Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage reference with parallel 10 F and 0.1 F capacitors to AGND. Connection Point for External Bias Resistor Analog Power Supply Connected to Analog 5 V Supply Filter Capacitor Connection with Parallel 10 F and 0.1 F Capacitors to AGND Left Channel Negative Analog Output Left Channel Positive Analog Output Analog Ground Right Channel Zero Flag Output. This pin goes high when the right channel has no signal input or the DSD mute pattern is detected. Left Channel Zero Flag Output. This pin goes high when the left channel has no signal input or the DSD mute pattern is detected. Mute. Assert high to mute both stereo analog outputs. Deassert low for normal operation. Power Down/Reset. The AD1955 is placed in a reset state and the digital circuitry is powered down when this pin is held low. The AD1955 is reset on the rising edge of this signal. The serial control port registers are reset to the default values. Connect high for normal operation. Serial Control Input, MSB First, Containing 16 Bits of Unsigned Data. Used for specifying control information and channel-specific attenuation. Latch Input for Control Data Clock Input for Control Data. Control input data must be valid on the rising edge of CCLK. CCLK may be continuous or gated. Master Clock Input. Connect to an external clock source. Digital Ground
5 6
Input I/O
EF_RDATA DSD_SCLK
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Input Input I/O
DSD_LDATA DSD_RDATA DSD_PHASE AGND
Output Output Output
IOUTR+ IOUTR- FILTR IREF AVDD
Output Output Output Output Output Input Input
FILTB IOUTL- IOUTL+ AGND ZEROR ZEROL MUTE PD/RST
24 25 26 27 28
Input Input Input Input
CDATA CLATCH CCLK MCLK DGND
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Typical Performance Characteristics-AD1955
TPC 1. Pass-Band Response, 8
Mode, 48 kHz Sample Rate
TPC 4. Complete Response, 4
Mode, 96 kHz Sample Rate
TPC 2. Complete Response, 8
Mode, 48 kHz Sample Rate
TPC 5. Pass-Band Response, 2 Sample Rate
Mode, 192 kHz
TPC 3. 44 kHz Pass-Band Response 4 Sample Rate
Mode, 96 kHz
TPC 6. Complete Response, 2 Sample Rate
Mode, 192 kHz
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AD1955
TPC 7. DSD Digital Filter Pass Band
TPC 10. FFT Plot, DNR = 121 dBFS (A-Weight), PCM SR = 48 kHz, -60 dBFS @ 1 kHz
TPC 8. DSD Digital Filter Response, Input Sample Rate = 2.8224 MHz
TPC 11. FFT Plot, SNR = 121 dBFS (A-Weight), PCM SR = 48 kHz with Zero Input
TPC 9. FFT Plot, THD + N = -110 dBFS, PCM SR = 48 kHz, 0 dBFS @ 1 kHz
TPC 12. Linearity, PCM SR = 48 kHz, 0 dBFS to -140 dBFS Input @ 200 Hz
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TPC 13. THD + N vs. Amplitude Plot, PCM SR = 48 kHz, 0 dBFS to -120 dBFS Input @ 1 kHz
TPC 16. Wideband FFT Plot, PCM SR = 48 kHz, 0 dBFS @ 20 kHz
TPC 14. THD + N vs. Frequency Plot, PCM SR = 48 kHz, 0 dBFS Input
TPC 17. De-emphasis Frequency Response, PCM SR = 32 kHz, 0 dBFS Input
TPC 15. FFT Plot, PCM SR = 48 kHz, 0 dBFS @ 20 kHz, BW = 22 kHz
TPC 18. De-emphasis Frequency Response, PCM SR = 44.1 kHz, 0 dBFS Input
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AD1955
TPC 19. De-emphasis Frequency Response, PCM SR = 48 kHz, 0 dBFS Input
TPC 22. FFT Plot, PCM SR = 96 kHz, Zero Input, BW = 22 kHz
TPC 20. FFT Plot, PCM SR = 96 kHz, 0 dBFS @ 1 kHz, BW = 22 kHz
TPC 23. Wideband FFT Plot, PCM SR = 96 kHz, 0 dBFS Input @ 37 kHz
TPC 21. FFT Plot, PCM SR = 96 kHz, -60 dBFS @ 1 kHz, BW = 22 kHz
TPC 24. FFT Plot, PCM SR = 192 kHz, 0 dBFS Input @ 1 kHz
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TPC 25. FFT Plot, PCM SR = 192 kHz, -60 dBFS Input @ 1 kHz
TPC 28. FFT Plot, 64 0 dBFS @ 1 kHz
fS DSD, SR = 44.1 kHz,
TPC 26. FFT Plot, PCM SR = 192 kHz, Zero Input
TPC 29. FFT Plot, 64 -60 dBFS @ 1 kHz
fS DSD, SR = 44.1 kHz,
TPC 27. Wideband FFT Plot, PCM SR = 192 kHz, 0 dBFS @ 60 kHz
TPC 30. FFT Plot, 64
fS DSD, SR = 44.1 kHz, Zero Input
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AD1955
TPC 31. FFT Plot, 64 0 dBFS @ 10 kHz
fS DSD, SR = 44.1 kHz,
TPC 32. Wideband FFT Plot, 64 SR = 44.1 kHz, 0 dBFS @ 10 kHz
fS DSD,
(continued from page 1) sample rate converters. The AD1955 can be configured in leftjustified, I2S, right-justified, or DSP serial port compatible modes. It can support MSB first, twos complement format, 16, 18, 20, and 24 bits in all standard PCM modes. The AD1955 also has an interface for SACD playback and an external digital filter interface for use with an external digital interpolation filter or HDCD decoder. The AD1955 uses a 5 V power supply. It is fabricated on a single monolithic integrated circuit and is housed in a 28-lead SSOP package for operation over the temperature range -40C to +85C.
OPERATING FEATURES Serial Data Input Port
Serial Data Format in PCM Mode
The supported formats are shown in Figure 1. For detailed timing, see Figure 2. In Left-Justified Mode, LRCLK is high for the left channel and low for the right channel. Data should be valid on the rising edge of BCLK. The MSB is left-justified to an LRCLK transition, with no MSB delay. In I2S Mode, LRCLK is low for the left channel and high for the right channel. Data should be valid on the rising edge of BCLK. The MSB is left-justified to an LRCLK transition but with a single BCLK period delay. In DSP serial port mode, LRCLK must pulse high for at least one bit clock period before the MSB of the left channel is valid, and LRCLK must pulse high again for at least one bit clock period before the MSB of the right channel is valid. Data should be valid on the falling edge of BCLK. The DSP serial port mode can be used with any word length up to 24 bits. In this mode, it is the responsibility of the DSP to ensure that the left data is transmitted with the first LRCLK pulse after RESET, and that synchronism is maintained from that point forward. In Right-Justified Mode (16 bits shown), LRCLK is high for the left channel and low for the right channel. Data should be valid on the rising edge of BCLK. In normal operation, there are 64 bit clocks per frame (or 32 per half-frame). When the SPI word length control bits (Bits 2 and 3 in Control Register 0) are set to 24 bits (0:0), the serial port will begin to accept data starting at the eighth bit clock pulse after the LRCLK transition. When the word length control bits are set to 20-bit mode, data is accepted starting at the 12th bit clock position. In 18-bit mode, data is accepted starting at the 14th bit clock position. In 16-bit mode, data is accepted starting at the 16th bit clock position. Note that the AD1955 is capable of a 32 fS BCLK frequency "packed mode" where the MSB is left-justified to an LRCLK transition, and the LSB is right-justified to the next LRCLK transition. LRCLK is high for the left channel, and low for the right channel. Data is valid on the rising edge of BCLK. Packed mode can be used when the AD1955 is programmed in LeftJustified Mode. -12- REV. 0
The AD1955's flexible serial data input port accepts standard PCM audio data and external digital filter output data in twos complement, MSB-first format in PCM/External Digital Filter Mode, and a dedicated SACD serial port accepts DSD bit stream data in SACD Mode. If the PCM Mode is selected by Control Register 0 Bits 12 and 13, the left channel data field always precedes the right channel data field. The serial data format and word length in PCM Mode are set by the mode select bits (Bits 4 and 5 and Bits 2 and 3, respectively) in the SPI control register. In all data formats except for the Right-Justified Mode, the serial port will accept an arbitrary number of bits up to a limit of 24 (extra bits will not cause an error, but they will be truncated internally). In Right-Justified Mode, Control Register 0, Bits 2 and 3 are used to set the word length to 16, 18, 20, or 24 bits. The default on power up is 24-bit, I2S. In the External Digital Filter Mode, selected by Control Register 0 Bits 12 and 13, Bits 2 and 3 are used to set the word length to 16, 18, 20, or 24 bits and the format is set with Bits 4 and 5. For a burst-mode clock, the format should be set to left-justified. DSP Mode is not used. The LRCLK is always falling-edge active. The default on power-up is 24-bit mode in PCM and External Digital Filter Mode. In SACD Mode, selected by Control Register 0 Bits 12 and 13, the SACD port will accept a DSD bit stream. When the SPI Control Port is not being used, the SPI pins (24, 25, and 26) should be tied to DGND or DVDD.
AD1955
Serial Data Format in External Digital Filter Mode
In the External Digital Filter Mode, the AD1955 will accept up to 24-bit serial, twos complement, MSB-first data from an external digital filter, an HDCD decoder, or a general-purpose DSP. If the External Digital Filter Mode is selected by Control Register 0, Bits 12 and 13, Pin 2 to Pin 5 are assigned as the word clock input (EF_WCLK, Pin 2), bit clock input (EF_BCLK, Pin 3), left channel data input (EF_LDATA, Pin 4), and right channel data input (EF_RDATA, Pin 5), respectively, to accept 8fS (48 kHz), 4fS (96 kHz), or 2fS (196 kHz) oversampled data. Left and right channel data should be valid on the rising edge of EF_BCLK. The mode can be set to Left- or Right-Justified. A burst mode BCLK can be used in Left-Justified Mode.
Serial Data Format in SACD Mode
In the SACD Mode, the AD1955 accepts a 256fS, 512fS, or 768fS Master Clock, where fS is nominally 44.1 kHz. In Slave Mode, by default, the rising edge of DSD_SCLK should coincide with the rising edge of MCLK. Control Register 1, Bit 2 should be set to 1 if the rising edge of DSD_SCLK coincides with the falling edge of MCLK. In Master Mode this bit can be used to select the MCLK edge used to generate the DSD clock outputs.
Zero Detection
When the AD1955 detects that the audio input data is continuously zero during 1024 LRCLK periods in PCM Mode or 8192 LRCLK periods in 8fS External Digital Filter Mode, ZEROL (Pin 21) or ZEROR (Pin 20) is set to active. When the AD1955 is in SACD Mode, it will detect an SACD mute pattern. If the input bit stream shows a mute pattern for about 22 ms, the AD1955 will set ZEROL (Pin 21) or ZEROR (Pin 20) to active. The outputs can be set to active high or low using Control Register 1, Bit 8.
Reset/Power-Down
In the SACD Mode, the AD1955 supports both normal mode or phase modulation mode, which are selected by Control Register 1, Bit 6. If normal mode is selected, DSD_SCLK, DSD_LDATA, and DSD_RDATA are used to interface with DSD decoder chip. In this mode, the DSD data is clocked in the AD1955 using the rising edge of DSD_SCLK with a 64fS rate, 2.8224 MHz. DSD_PHASE pin should be connected LOW. If Phase Modulation Mode is selected, the DSD_PHASE pin is also used to interface with the DSD decoder. In this mode, a 64fS DSD_PHASE signal is used as a reference signal to receive the data from the decoder. The DSD data is clocked into the AD1955 with a 128fS DSD_SCLK. The AD1955 can operate as a master or slave device. In Master Mode, the AD1955 will output DSD_SCLK and DSD_PHASE (if in Phase Modulation Mode) to a DSD decoder and will support Normal Mode and Phase Modulation Mode 0. In Slave Mode, the AD1955 will accept DSD_SCLK and DSD_PHASE (if in Phase Modulation Mode) from a DSD decoder and supports all of the normal and phase modulation modes. When the SACD Port is not being used, the SACD pins (Pins 6, 7, 8, and 9) should be tied to a valid logic level. Please note that there are weak pull-ups (0.6 mA typical) on DSD_SCLK and DSD_PHASE.
Master Clock
The AD1955 will be reset when the PD/RST pin is set low. The part may be powered down using Bit 15, Control Register 0.
Audio Outputs
Active I/V converters should be used, which will hold the DAC outputs at a constant voltage level. Passive I/V conversion should not be used, since the DAC performance will be seriously degraded. For best THD + N performance over temperature, a reference voltage of 2.80 V should be used with the I/V converters. For a lower parts count, the voltage at FILTR can be used. In this instance, THD + N performance at high temperature can be improved by reducing IREF, with an attendant reduction in gain (linear dependence) and DNR/SNR (square-root dependence). The AD1955 audio outputs sink a current proportional to the input signal, superimposed on a steady bias current. The current-to-voltage (I/V) converters used need to be able to supply this bias current, as well as the signal current, or a resistor or current source can be used to a positive voltage to null this current in order to center the range of the I/V converters. If pull-up resistors are used to bring the output of the I/V converters to 0 V for maximum headroom and THD balance, as shown in the applications circuits, the following equation can be used: RPULLUP = [VSUPPLY - VBIAS ] [ IBIAS + (VBIAS RI /V )]
The AD1955 must be set to the proper sample rate and master clock rate using Control Registers 0 and 1. The allowable master clock frequencies for each interpolation mode are shown below. In the External Filter Mode, the AD1955 accepts master clock frequencies depending on the input sample rate as shown below.
PCM Mode
Interpolation Mode 48 kHz (INT 8x) Mode 96 kHz (INT 4x) Mode 192 kHz (INT 2x) Mode
64
Allowable Master Clock Frequencies ( fS) 96 128 192 256 384 512
768
Nominal Input Sample Rate (kHz) 32, 44.1, 48 88.2, 96 176.4, 192
*
* *
* * *
* *
*
External Filter Mode
Input Sample Rate 8 x fS 4 x fS 2 x fS
64
Allowable Master Clock Frequencies ( fS) 96 128 192 256 384 512
768
Nominal Input Sample Rate (to External Filter) (kHz) 32, 44.1, 48 88.2, 96 176.4, 192
*
* *
* * *
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* *
*
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AD1955
For example, with the stereo circuits given in Figures 7 through 10, this gives:
Serial Control Port
[12.0 V - 2.80 V ] [ 3.24 mA + (2.80 V
A 2.00 k resistor is used.
2.00 K ) = 1.98 k
]
The supply used should be as quiet as possible.
The AD1955 has an SPI compatible control port to permit programming the internal control registers. The SPI control port is a 3-wire serial port. Its format is similar to the Motorola SPI format except that the input data-word is 16 bits wide. The serial bit clock may be completely asynchronous to the sample rate of the DAC. The following figure shows the format of the SPI signal Note that the CCLK may be continuous or a 16-clock burst.
SPI REGISTER DEFINITIONS Table I. DAC Control Register 0 Table II. DAC Control Register 1
Bit 15 14 13:12
Description Power-Down Mute Data Format
Value 0 1 0 1 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00
Definition Operation Powered Down Not Muted Muted PCM External DF SACD Slave SACD Master Stereo Not Allowed Mono Left Mono Right 48 kHz 96 kHz 192 kHz Reserved None 44.1 kHz 32 kHz 48 kHz IS Right-Justified DSP Left-Justified 24 bits 20 bits 18 bits 16 bits
2
Bit 10:9
Description MCLK Mode
Value 00 01 10 11 0 1 0 1 0 1 00 01 10 11 0 1 0 1 01
Definition 256 fS 512 fS 768 fS Reserved Active High Active Low 64 fS 128 fS Normal Phase Mode Phase 0 Phase 1 Phase 2 Phase 3 Normal Inverted Rising Edge Falling Edge
8 7 6 5:4
Zero Flag Polarity SACD Bit Rate SACD Mode SACD Phase Select
11:10
Output Format
9:8
PCM Sample Rate
3 2 1:0
SACD Bit Inversion SACD MCLK to BCLK Phase SPI Register Address
7:6
De-Emphasis Curve Select
5:4
PCM/EF Serial Data Format
Default = 0
Table III. DAC Volume Registers
Bit 15:2 1:0
Description Volume SPI Register Address
Value 14-Bit Unsigned 10 11
Definition
3:2
PCM/EF Serial Data Width
1:0
SPI Register Address
Left Volume Right Volume
Default = Full Volume
Default = 0
-14-
REV. 0
AD1955
LRCLK BCLK SDATA
MSB LSB MSB LSB
LEFT CHANNEL
RIGHT CHANNEL
I2S MODE -16 TO 24 BITS PER CHANNEL RIGHT CHANNEL
LRCLK BCLK SDATA
MSB
LEFT CHANNEL
LSB
MSB
LSB
RIGHT-JUSTIFIED MODE - SELECT NUMBER OF BITS PER CHANNEL
LRCLK BCLK SDATA
MSB MSB LSB
DSP MODE - 16 TO 24 BITS PER CHANNEL
LRCLK BCLK SDATA
MSB
LEFT CHANNEL
LSB MSB
RIGHT CHANNEL
LSB
LEFT-JUSTIFIED MODE - 16 TO 24 BITS PER CHANNEL 1/fS NOTES 1. DSP MODE DOES NOT IDENTIFY CHANNEL. 2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE, WHICH IS 2 fS. 3. BCLK FREQUENCY IS NORMALLY 64 LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 1. Supported Serial Data Formats
tDBH
BCLK
tDBP
tDBL tDLS
L/RCLK
SDATA LEFT-JUSTIFIED MODE
tDDS
MSB MSB-1
tDDH
SDATA I2S-JUSTIFIED MODE
tDDS
MSB
tDDH
SDATA RIGHT-JUSTIFIED MODE 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 16-BIT CLOCKS (16-BIT DATA)
tDDS
MSB
tDDS
LSB
tDDH
tDDH
Figure 2. Serial Data Port Timing
REV. 0
-15-
AD1955
DSD_DATA NORMAL MODE DSD_BCLK D0 D1
DSD_DATA
D0
D0
DSD_BCLK
DSD_PHASE_0 PHASE MOD MODE
DSD_PHASE_1
DSD_PHASE_2
DSD_PHASE_3
Figure 3. DSD Modes
DSD_PHASE
tDSKP tDPHS tDSKH
DSD_SCLK
tDSDS
DSD_LDATA, DSD_RDATA
tDSKL
tDSDH
Figure 4. DSD Serial Port Timing
tCLATCHH tCLKL
CLATCH
tCLKH
CCLK CDATA D15 D14 D0
tCDH tCDS
Figure 5. Serial Control Port Timing
-16-
REV. 0
AD1955
DVDD AVDD
L2 600Z
L3 600Z
CONNECT VBIAS TO VREFA FOR BEST PERFORMANCE OR VREF FOR LOWER PARTS COUNT VREF VBIAS
AVDD C1 0.1 F C2 0.1 F
OR
R56 2.21k VREFA
DVDD MCLK RDATA SDATA BCLK LRCLK DSD_PHASE DSD_RDATA DSD_LDATA DSD_SCLK CDATA CLATCH CCLK MUTE ZEROR ZEROL PD/RST MCLK EF_RDATA SDATA/EF_LDATA BCLK/EF_BCLK LRCLK/EF_WCLK DSD_PHASE DSD_RDATA DSD_LDATA DSD_SCLK
AVDD
VREFA 2.80V IOUTL+ IOUTL+ R57 2.80k IOUTL- IOUTL-
U1
+
C43 47 F
C44 0.1 F
IOUTR+
IOUTR+
IOUTR- CDATA CLATCH CCLK MUTE ZEROR ZEROL IREF PD/RST DGND AGND1 AGND2 FILTR FILTB
IOUTR-
AD1955
VREF 2.39V C5 0.1 F
+
C4 10 F
+
C6 47 F
R1 2.49k
C3 0.1 F
600Z L1
Figure 6. DAC Power Supply and Bypass
REV. 0
-17-
AD1955
12V R6 100 R2 2.00k IOUTL+ AD797 C7 OPEN C9 100pF C8 OPEN IOUTL- AD797 VBIAS R4 402 NL+ NL- OUT +12V NL+ OUT NL- R9 1.00k C12 390pF COMP R10 1.00k R12 1.00k C13 470pF C14 470pF R11 1.00k -3dB at 100 kHz J1
XLR MALE
R5 2.00k C10 100pF
R3 2.00k
U2-A
COMP
+ - G
U3-A
LEFT DIRECT OUT 6VRMS
R7 100 R8 2.00k
C11 100pF 0.1 F
+
4.7 F
AD797 0.1 F
+
4.7 F
OP AMP BYPASS DUPLICATE FOR EACH PART -12V
Figure 7. Left Channel Differential Output
12V R17 100 R13 2.00k IOUTR+ AD797 C15 OPEN C17 100pF C16 OPEN IOUTR- AD797 VBIAS R15 402 NL+ NL- OUT +12V NL+ OUT NL- R20 1.00k C20 390pF COMP R21 1.00k R23 1.00k C21 470pF C22 470pF R22 1.00k -3dB at 100 kHz J2 R14 2.00k R16 2.00k C18 100pF
U4-A
COMP
XLR MALE
+ - G
U5-A
RIGHT DIRECT OUT 6VRMS
R18 100 R19 2.00k
C19 100pF 0.1 F
+
4.7 F
AD797 0.1 F
+
4.7 F
OP AMP BYPASS DUPLICATE FOR EACH PART -12V
Figure 8. Right Channel Differential Output
-18-
REV. 0
AD1955
12V R28 100 R24 2.00k R25 2.00k R27 2.00k C26 100pF
U6-A
COMP
R33 226 R31 681 R34 324 C28 5.6nF
C30 2.7nF
R37 100
IOUTL+
AD797
C23 OPEN C25 100pF C24 OPEN IOUTL-
U8-A
COMP
R38 332
-3dB at 75 kHz
OUT NL- NL+
J3 LEFT FILTER OUT 2VRMS
AD797 OUT
C29 5.6nF
U7-A
COMP AD797
R32 681
NL- NL+
C32 3.9nF
R39 OPEN
VBIAS
R26 402
OUT NL- NL+
R29 100 C27 100pF R36 226
R35 324 C31 2.7nF
+12V
R30 2.00k
+
0.1 F
4.7 F
AD797 0.1 F
+
4.7 F
OP AMP BYPASS DUPLICATE FOR EACH PART -12V
Figure 9. Left Channel Single-Ended Output
12V R44 100 R40 2.00k R41 2.00k R43 2.00k C36 100pF
U9-A
COMP
R47 681
R49 226 R50 324 C38 5.6nF
C40 2.7nF
R53 100
IOUTR+
AD797
C33 OPEN C35 100pF C34 OPEN IOUTR-
U11-A
COMP
R54 332
-3dB at 75 kHz
OUT NL- NL+
J4 RIGHT FILTER OUT 2VRMS
AD797 OUT
R48 681 C39 5.6nF
U10-A
COMP AD797
NL- NL+
C42 3.9nF
R55 OPEN
VBIAS
R42 402
OUT NL- NL+
R45 100 C37 100pF R52 226
R51 324 C41 2.7nF
+12V
R46 2.00k
+
0.1 F
4.7 F
AD797 0.1 F
+
4.7 F
OP AMP BYPASS DUPLICATE FOR EACH PART -12V
REV. 0
Figure 10. Right Channel Single-Ended Output -19-
AD1955
12V R6 100 R2 1.00k R3 1.00k R5 1.00k C10 100pF
U2-A
COMP AD797
IOUTL+ IOUTR- C7 OPEN
OUT C9 100pF NL- NL+
R9 1.00k C12 390pF
R11 1.00k
-3dB at 100 kHz
J1
XLR MALE
+ - R12 1.00k C13 470pF C14 470pF G
C8 OPEN IOUTL-
U3-A
COMP AD797 R10 1.00k
MONO DIRECT OUT 6VRMS
IOUTR+ VBIAS
R4 402 NL+ NOTE REVERSE POLARITY OF RIGHT CHANNEL OUTPUTS
OUT NL- +12V SET CONTROL REGISTER 0, BITS 11:10 TO SELECT LEFT OR RIGHT CHANNEL R7 100 R8 1.00k AD797 0.1 F C11 100pF 0.1 F
+
4.7 F
+
4.7 F
OP AMP BYPASS DUPLICATE FOR EACH PART -12V
Figure 11. Mono Differential Output
12V R28 100 R24 1.00k IOUTL+ IOUTR- R25 1.00k R27 1.00k C26 100pF
U6-A
COMP
R31 681
R33 226 R34 324 C28 5.6nF
C30 2.7nF
R37 100
AD797
C23 OPEN C25 100pF C24 OPEN IOUTL-
U8-A
COMP
R38 332
-3dB at 75 kHz
OUT NL- NL+
J3 MONO FILTER OUT 2VRMS
AD797 OUT
C29 5.6nF
U7-A
COMP AD797
R32 681
NL- NL+
C32 3.9nF
R39 OPEN
IOUTR+ VBIAS R26 402 NOTE REVERSE POLARITY OF RIGHT CHANNEL OUTPUTS
OUT NL- NL+
R29 100 C27 100pF R36 226
R35 324 C31 2.7nF SET CONTROL REGISTER 0, BITS 11:10 TO SELECT LEFT OR RIGHT CHANNEL
+12V
R30 1.00k
+
0.1 F
4.7 F
AD797 0.1 F
+
4.7 F
OP AMP BYPASS DUPLICATE FOR EACH PART -12V
Figure 12. Mono Single-Ended Output
-20-
REV. 0
AD1955
OUTLINE DIMENSIONS
Dimensions shown in millimeters
28-Lead Shrink Small Outline Package (SSOP) (RS-28)
10.50 10.20 9.90
28
15
5.60 5.30 5.00
1 14
8.20 7.80 7.40
2.00 MAX
1.85 1.75 1.65
0.10 COPLANARITY 0.25 0.09
0.05 MIN
0.65 BSC
0.38 0.22
SEATING PLANE
8 4 0
0.95 0.75 0.55
COMPLIANT TO JEDEC STANDARDS MO-150AH
REV. 0
-21-
-22-
-23-
-24-
C02805-0-10/02(0)
PRINTED IN U.S.A.
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