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Features
* * * * * * * *
Supply-voltage Range 3V to 4.6V (Regulated) Auxiliary Voltage Regulator On-chip (3.2V to 4.6V) Low Current Consumption Few Low-cost External Components No Mechanical Tuning Required Supports Multiple Reference Clocks (10.368 MHz/13.824 MHz) Fast Settling Synthesizer (864 kHz Channel Spacing) TX Preamplifier with 3 dBm Output Power at 2.45 GHz (4 Programmable Power Levels) * Ramp-signal Generator for Power Ramping and Power Control of External SiGe Power Amplifier (T7024 and T7026)
Electrostatic sensitive device. Observe precautions for handling.
2.4 GHz WDECT/ISM Single-chip Transceiver T2803
1. Description
The T2803 is an RF IC for low-power applications in the 2.45 GHz ISM band. The QFN48-packaged IC is a complete transceiver including image rejection mixer, IF amplifier, FM demodulator, baseband filter, RSSI, TX preamplifier, power-ramping generator for power amplifiers, integrated synthesizer, fully integrated VCO and Gaussian data filter for TX. No mechanical tuning is necessary in production. Figure 1-1. Block Diagram
MIXER OUT IF_IN IR MIXER RF_IN DEMOD BB FILTER RAMP_OUT RAMP_SET RAMP GEN RAMP D/A D/A RSSI DEMOD DAC RSSI IF AMP 1 DEMOD IF_TANK IF AMP 2 BB_OUT TANK CF
VCO TX/RX SWITCH
GF TX_DATA
PC TX_OUT TX DRIVER f :n
PD
3-WIRE BUS
CLOCK DATA ENABLE
VCO REG
AUX REG
CP
RC f :n
CTRL LOGIC
RX_ON TX_ON PU_RX/TX PU_PLL
VREG_VCO VS_VCO VREG VS_REG OLE GND_VCO PU_REG REG_CTRL VTUNE
CP I_CPSW
LD
REF_CLK
Rev. 4572I-DECT-07/05
Table 1-1.
Name AUX REG BBF CP DAC DEMOD GF IF AMP1 IF AMP2 IR MIXER PC PD RAMP GEN RC RSSI TX DRIVER
Functional Block Description
Description Auxiliary voltage regulator Baseband filter Charge pump D/A converter for demodulator tuning Demodulator Gaussian filter for transmit data 1st intermediate frequency amplifier 2nd intermediate frequency amplifier Image rejection mixer Programmable counter Phase detector Ramp-signal generator Reference counter Received signal-strength indicator Buffer amplifier for TX_OUT Switches VCO signal to IR MIXER respectively TX DRIVER Voltage-controlled oscillator Voltage regulator for VCO
TX/RX SWITCH VCO VCO REG
2. Pin Configuration
Figure 2-1. Pinning QFN48
PU_PLL TX_ON RAMP_SET PU_RX/TX GND_PLL TX_DATA VS_MIXER I_CPSW RX_ON
48 47 46 45 44 43 42 41 40 39 38 37 CLOCK DATA ENABLE REF_CLK LD PU_REG VS_PLL VREG REG_CTRL VS_REG GND_CP VS_CP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
BB_CF DEMOD_TANK2 GND_VCO DEMOD_TANK1 VREG_VCO REG_DEC DAC_DEC VS_VCO BB_OUT VTUNE GND1 CP
OLE
36 35 34 33 32 31
RAMP_OUT IF_IN2 IF_IN1 VS_IF TX_OUT GND3 RF_IN2 RF_IN1 GND2 IF_TANK2 IF_TANK1 RSSI
T2803
30 29 28 27 26 25
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Table 2-1.
Pin
Pin Description
Symbol Function Configuration
VS_PLL
1
CLOCK
3-wire-bus: Clock input
7
2
DATA
3-wire-bus: Data input
CLOCK DATA ENABLE 1,2,3 5k 5k
3
ENABLE
3-wire-bus: Enable input
GND_PLL 43
VS_PLL 7
4
REF_CLK
Reference-frequency input
REF_CLK 4
10k
10k
GND_PLL 43
LD 5 100
5
LD
Lock-detect output
GND_PLL 43
PU_REG 6
6
PU_REG
Power-up input for auxiliary voltage regulator
25k
25k
GND_PLL 43
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Table 2-1.
Pin
Pin Description (Continued)
Symbol Function Configuration
VS_PLL 7 GND1 VS_REG 10 VS_CP 12 VS_VCO 14 18
GND2 28
7
VS_PLL
PLL supply voltage
VS_IF 33
GND3 31
GND_VCO 16
GND_CP 11 VS_MIXER 42 GND_PLL 43
VS_REG 10 VS_PLL 7 REG_CTRL 9 VREG 8
8
VREG
Auxiliary voltage-regulator output
9
REG_CTRL
Auxiliary voltage-regulator control output
10
VS_REG
Auxiliary voltage-regulator supply voltage
GND_PLL 43
VS_CP 12
11 12 13
GND_CP VS_CP CP
Charge-pump ground Charge-pump supply voltage Charge-pump output
VS_PLL 7
CP 13
GND_PLL 43 GND_CP 11
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Table 2-1.
Pin
Pin Description (Continued)
Symbol Function Configuration
VS_VCO 14
14 15 16
VS_VCO VREG_VCO GND_VCO
VCO voltage-regulator supply voltage VCO voltage-regulator control output VCO ground
VS_PLL 7
VREG_VCO 15
GND_PLL 43
GND_VCO 16
VREG_VCO 15 VS_PLL 7
17
VTUNE
VCO tuning voltage input
VTUNE 17
GND_PLL 43 GND_VCO 16
VS_PLL 7 GND1 VS_REG 10 VS_CP 12 VS_VCO 14 GND3 18
GND2 28
18
GND1
Ground
VS_IF 33
31
GND_VCO 16
GND_CP 11 VS_MIXER 42 GND_PLL 43
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Table 2-1.
Pin
Pin Description (Continued)
Symbol Function Configuration
VS_MIXER 42 VS_IF 33 10k DEMOD TANK1 19 10k DEMOD TANK2 20
19
DEMOD_TANK1
Demodulator tank circuit
20
DEMOD_TANK2
Demodulator tank circuit
GND2 28
GND1 18
VREG_VCO 15 VS_PLL 7
10k
21
DAC_DEC
Decoupling pin
DAC_DEC 21
GND_PLL 43 GND_VCO 16
400
VREG_VCO 15 VS_IF 33 2k
22
REG_DEC
Decoupling pin for VCO_REG
REG_DEC 22 42k GND2 28 GND_VCO 16
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Table 2-1.
Pin
Pin Description (Continued)
Symbol Function Configuration
VS_IF 33
23
BB_CF
Baseband filter corner-frequency control input
BB_CF 23
GND2 28 GND1 18
VS_IF 33
24
BB_OUT
Baseband filter output
BB_OUT 24
GND1 18
GND2 28
VS_IF 33
25
RSSI
Received signal strength indicator output
RSSI 25 13k GND2 28
VS_IF 33
26
IF_TANK1
IF tank circuit
IF_TANK1 26 27
27
IF_TANK2
IF tank circuit
GND2 28
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Table 2-1.
Pin
Pin Description (Continued)
Symbol Function
VS_PLL 7 GND1 VS_REG 10 VS_CP 12 VS_VCO 14 GND3 18
Configuration
GND2 28
28
GND2
Ground
VS_IF 33
31
GND_VCO 16
GND_CP 11 VS_MIXER 42 GND_PLL 43
VS_MIXER 42
29
RF_IN1
RF input of image reject mixer
RF_IN1 29 RF_IN2 30
30
RF_IN2
RF input of image reject mixer
GND2 28
VS_PLL 7 GND1 VS_REG 10 VS_CP 12 VS_VCO 14 GND3 18
GND2 28
31
GND3
Ground
VS_IF 33
31
GND_VCO 16
GND_CP 11 VS_MIXER 42 GND_PLL 43
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Table 2-1.
Pin
Pin Description (Continued)
Symbol Function Configuration
TX_OUT 32
32
TX_OUT
TX driver amplifier output for PA
GND3 31
VS_PLL 7 GND1 VS_REG 10 VS_CP 12 VS_VCO 14 GND3 18
GND2 28
33
VS_IF
IF amplifier supply voltage
VS_IF 33
31
GND_VCO 16
GND_CP 11 VS_MIXER 42 GND_PLL 43
VS_IF 33
34
IF_IN1
IF input of IF amplifier
IF_IN1 34 90k IF_IN2 35
35
IF_IN2
IF input of IF amplifier
GND2 28
VS_MIXER 42 VS_IF 33
36
RAMP_OUT
Ramp-generator output for PA power ramping
RAMP_OUT 36
GND2 28
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Table 2-1.
Pin
Pin Description (Continued)
Symbol Function Configuration
VS_MIXER 42 VS_IF 33
37
RAMP_SET
Slew-rate setting of ramping signal
1k 100
RAMP SET 37
GND2 28
VS_IF 33
38
RX_ON
RX control input
39
TX_ON
TX control input
RX_ON TX_ON 38, 39
5k
5k
GND2 28 GND1 18
VS_IF 33
VS_MIXER 42
40
MIXER_OUT1
Mixer output to SAW filter
MIXER_OUT1 40
270
270 MIXER_OUT2 41
41
MIXER_OUT2
Mixer output to SAW filter
GND2 28
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Table 2-1.
Pin
Pin Description (Continued)
Symbol Function Configuration
VS_PLL 7 GND1 VS_REG 10 VS_CP 12 18
GND2 28
42
VS_MIXER
Mixer supply voltage
VS_VCO 14 GND3 31
43
GND_PLL
PLL ground
VS_IF 33
GND_VCO 16
GND_CP 11 VS_MIXER 42 GND_PLL 43
VS_PLL 7
44
OLE
Open loop enable input
OLE 44 5k 5k
GND_PLL 43
PU_RX/TX 45
45
PU_RX/TX
RX/TX power-up input
25k
25k
GND18 18
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Table 2-1.
Pin
Pin Description (Continued)
Symbol Function Configuration
20k
10k
140k
10k
10k
PU PLL 46
25k
25k
46
PU_PLL
PLL power-up input
GND PLL 43 5k 5k
VS_PLL 7
VS_PLL 7
47
TX_DATA
TX data input of Gaussian filter
TX_DATA 47
2.5k
GND_PLL 43
VS_PLL 7
48
I_CPSW
Charge-pump current control input
I_CPSW 48
5k
GND_PLL 43
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3. Functional Description
3.1 Receiver
The RF signal at RF_IN is fed to an image rejection mixer IR_MIXER with its differential outputs MIXER_OUT1 and MIXER_OUT2 driving an IF-SAW filter at 110.592 MHz or 112.32 MHz. The IF_AMP1 and IF_AMP2 IF amplifiers with an external IF_TANK and an integrated RSSI function feed the signal to the demodulator DEMOD working at f = fIF/2 ( 55 MHz) and finally to an integrated baseband filter BB. For demodulator tunning in production an integrated 5-bit digital-to-analog (D/A) converter is provided to control the on-chip varicap diode.
3.2
Transmitter
The transmit data at TX_DATA is filtered by an integrated Gaussian Filter GF and fed to the fully integrated VCO operating at twice the output frequency. After modulation the signal is frequency-divided by 2 and fed via a TX/RX SWITCH to the TX_DRIVER. This bus-controlled driver amplifier supplies typically +3 dBm output power at TX_OUT. A ramp-signal generator RAMP_GEN, providing a ramp signal at RAMP_OUT for the external power amplifier, is integrated. The slope of the ramp signal is controlled by a capacitor at the RAMP_SET pin.
3.3
Synthesizer
The IR_MIXER, the TX_DRIVER and the programmable counter PC are driven by the fully integrated VCO (including on-chip inductors and varactors). The output signal is frequency-divided to supply the desired frequency to the TX_DRIVER, 0/90 degree phase shifter for the IR_MIXER and to be used by the PC for the phase detector PD (fPD = 1.728 MHz). Open loop modulation is supported.
3.4
Power Supply
An integrated bandgap-stabilized voltage regulator for use with an external low-cost PNP transistor is implemented. Multiple power-down and current saving modes are provided.
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Figure 3-1.
PLL Principle
RF_IN
Programable counter PC "- Main counter MC "- Swallow counter SC fVCO = fPD x (SMC x 32 + SSC) fVCO ext. loop filter Phase frequency detector PD fPD = 1.728 MHz PA driver Charge pump VCO Divider by 2 Mixer VCO DAC GF_DATA
Gaussian filter GF
Reference counter RC REF_CLK 10.368 MHz 13.824 MHz SRC 6 8
6.912 MHz
1.152 Mbit/s
PLL reference Frequency REF_CLK Baseband controller
TX_DATA
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Table 3-1 shows the LO frequencies for RX and TX for the DECT band plus additional channels for the extended DECT band. Intermediate frequencies of 110.592 MHz and 112.32 MHz are supported.
Table 3-1.
Mode
LO Frequencies
fIF/MHz Channel C0 C1 fANT/MHz 2401.056 2401.920 ... 2481.408 2482.272 2401.056 2401.920 ... 2481.408 2482.272 2401.056 2401.920 ... 2481.408 2482.272 fVCO/MHz 2401.056 2401.920 ... 2481.408 2482.272 2290.464 2291.328 ... 2370.816 2371.680 2288.736 2289.600 ... 2369.088 2369.952 SMC 86 86 ... 89 89 82 82 ... 85 85 82 82 ... 85 85 SSC 27 28 ... 24 25 27 28 ... 24 25 25 26 ... 22 23 N 2779 2780 ... 2872 2873 2651 2652 ... 2744 2745 2649 2650 ... 2742 2743
TX
-
... C93 C94 C0
RX
110.592 (for 10.368 MHz REF_CLK recommended)
C1 ... C93 C94 C0
RX
112.320 (for 13.824 MHz REF_CLK recommended)
C1 ... C93 C94
Formula TX: RX:
fANT = fVCO = 864 kHz x (32 x SMC + SSC) fANT = 864 kHz x (32 x SMC + SSC) + fIF
4. Control Signals
Table 4-1.
Signal I_CPSW PU_REG PU_RX/TX PU_PLL RX_ON TX_ON OLE Data Word 1, bit D0
Control Signals - Functions
Functions Charge pump current control Activates AUX voltage regulator supplying the complete transceiver Activates RX/TX blocks Activates PLL circuits: PC, PD, CP, RC, VCO Activates RX circuits: BBF, DEMOD, IF AMP, IR MIXER Activates TX circuits: TX-DRIVER, RAMP GEN, Starts RAMP SIGNAL at RAMP OUT Activates open loop mode of the PLL Activates GF
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Table 4-2.
Modes PU_REG PU_VCO PU_RX/TX PU_PLL RX_ON TX_ON BB filter Demodulator
Control Signals - Modes
TX Mode 1 1 1 1 0 1 OFF OFF OFF OFF OFF ON ON ON ON ON ON ON ON 56 mA RX Mode 1 1 1 1 1 0 ON ON ON ON ON OFF OFF OFF ON ON OFF ON ON 85 mA RSSI Only 1 1 1 1 1 1 OFF OFF ON ON ON OFF OFF OFF ON ON OFF ON ON 82 mA
IF amplifiers and RSSI IR mixer RX switch TX switch TX driver Ramp generator Programmable counter Voltage-controlled oscillator Gaussian filter Phase detector/charge pump Reference counter Typical current consumption at VS = 3.2V
5. Serial Programming Bus
The transceiver is programmed by the 3-wire bus (CLOCK, DATA and ENABLE). After setting enable signal to low condition, on the rising edge of the clock signal, the data is transferred bit by bit into the shift register, starting with the MSB-bit. When the enable signal has returned to high condition, the programmed information is loaded into the addressed latches according to the address bit condition (last bit). Additional leading bits are ignored and there is no check made how many pulses arrived during enable low condition. During enable low condition, the bus current is increased to speed up the bus logic. The programming of the transceiver is separated into two data words. Data word 1 controls mainly the channel information together with settings, which are closely related with the channel. Data word 2 holds setup information, which is adjusted during production.
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5.1
MSB Data bits D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 RC SC MC VS x 0
Data Word 1
LSB Address bit D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A0 GFCS 0 0 0 0 CPCS GF 1
D11 = x: do not care
5.2
Data Word 2
E12 E11 E10 PA E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 x x TEST A0 0
DEMODDAC/RAMPDAC x
E3, E4, E5 = x: do not care
6. Data Word 1 Programs
6.1 PLL Settings
Table 6-1. With the Reference Counter bits D22-D22
RC (Reference Counter) D22 0 1 SRC 6 8 REF_CLK 10.368 MHz 13.824 MHz
Table 6-2.
D16 0 0 ... 1 1
With the Main Counter bits D13-D16
MC (Main Counter) D15 0 0 ... 1 1 D14 0 0 ... 1 1 D13 0 1 ... 0 1 SMC 80 81 ... 94 95
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Table 6-3.
D21 0 0 0 ... 1 1 1
With the Swallow Counter bits D17-D21
SC (Swallow Counter) D20 0 0 0 ... 1 1 1 D19 0 0 0 ... 1 1 1 D18 0 0 1 ... 0 1 1 D17 0 1 0 ... 1 0 1 SSC 0 1 2 ... 29 30 31
6.2
VCO Selection
Table 6-4. With bit D12
VCO Selection D12 0 1 VCO Mode VCO 1 VCO 2
6.3
Gaussian Filter On/off
Table 6-5.
D0 0 1
With bit D0, GF is used only in TX mode
GF (Gaussian Filter) OFF ON
6.4
GFCS Adjustment
Table 6-6. With bits D7-D9, only in TX mode effective for setting the frequency deviation of the modulation
GFCS (Gaussian Filter Settings) D9 0 0 0 0 1 1 1 1 D8 0 0 1 1 0 0 1 1 D7 0 1 0 1 0 1 0 1 GFCS 60% 70% 80% 90% 100% 110% 120% 130%
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6.5 CPCS Adjustment
Table 6-7. With bits D1-D2
CPCS (Charge-Pump Current Settings) D2 0 0 1 1 Note: D1 0 1 0 1 CPCS -1 0 1 2
Used to adjust the charge pump current. This can be used to compensate the change of the tuning sensitivity over frequency and device tolerances.
7. Data Word 2 Programs
7.1 DEMODDAC Adjustment
Table 7-1.
E10 0 0 0 ... 1 1 1 Note:
With bits E6-E10
Demod DAC Voltage E9 0 0 0 ... 1 1 1 E8 0 0 0 ... 1 1 1 E7 0 0 1 ... 0 1 1 E6 0 1 0 ... 1 0 1 fIFcenter % -5 ... ... ... ... ... 5
Only in RX mode effective. Used to tune the demodulator center frequency and allows to compensate tolerances of external components and the T2803.
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7.2
RAMPDAC Adjustment for TX Mode
Table 7-2.
E10 0 0 0 ... 1 1 ... 1 1 Note:
With bits E6-E10
RAMPDAC Voltage (at Pin 36 RAMP_OUT) E9 0 0 0 ... 0 1 ... 1 1 E8 0 0 0 ... 1 0 ... 1 1 E7 0 0 1 ... 1 0 ... 1 1 E6 0 1 0 ... 1 0 ... 0 1 VRAMP_OUT 1.1V ... ... ... 1.68V 1.7V ... ... 1.7V
Only in TX mode effective. Used to control the power of the external PA by adjusting the ramping voltage
7.3
TEST Mode Settings
Table 7-3.
E2 0 0 0 0 1 1 1 1 Note:
With bits E0-E2
E1 0 0 1 1 0 0 1 1 E0 0 1 0 1 0 1 0 1 Signal at Lock Detect Output Lock detect PC out/2 RC out/2 do not care Lock detect PC out/2 RC out/2 GFTEST: RC out CP Mode Active Active Active Active Active Active Active Active
In normal operation Lock detect output is used. All other settings are for test only.
7.4
Output Power Settings
Table 7-4. With bits E11-E12
PA (Output Power Settings) E12 0 0 1 1 Note: E11 0 1 0 1 PA -21 dBm -11 dBm -4 dBm +3 dBm
Use of maximum power (+3 dBm) for external PA is recommended.
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Figure 7-1.
DATA CLOCK ENABLE TPER TL TS TC TH
3-wire Bus Protocol Timing Diagram
TEC
TT
Table 7-5.
Description Clock period
3-wire bus Protocol Table
Symbol TPER TS TH TC TL TEC TT Minimum Value 125 60 60 125 200 0 250 Unit ns ns ns ns ns ns ns
Set time data to clock Hold time data to clock Clock pulse width Set time enable to clock Hold time enable to data Time between two protocols
Figure 7-2.
TX DATA Timing
RefCLK
TX_DATA TS TH
Set-up time TX DATA Hold time TX DATA
TS TH
> 8 ns > 8 ns
When using REFCLK = 10.368 MHz, TS and TH must be considered for falling and rising edge of REFCLK
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8. Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages refer to GND Parameters Supply voltage regulator Supply voltage Logic input voltage Junction temperature Storage temperature Pin 10 7, 12, 14, 33, 42 1, 2, 3, 38, 39, 44-48 Symbol VS_REG VS VIN Tjmax Tstg -40 Min. 3.2 3.0 -0.3 Max. 4.7 4.7 VS 125 150 Unit V V V C C
9. Thermal Resistance
Parameters Junction ambient Symbol
RthJA
Value
25
Unit
K/W
10. Handling
Do not operate this part near strong electrostatic fields. This IC meets class 1 ESD test requirement (HBM in accordance to EIA/JESD22-A114-A (October 97) and class A ESD test requirement (MM) in accordance to EIA/JESD22-A115A.
11. Operating Range
Parameters Supply voltage regulator Supply voltage Supply voltage charge pump Ambient temperature Pin 10 7, 14, 33, 42 12 Symbol VS_REG VS VSCP Tamb Min. 3.2 2.9 VS -10 Typ. 3.6 3.0 Max. 4.6 4.6 4.6 +60 Unit V V V C
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12. Electrical Characteristics
Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25C Parameters IR Mixer (Pins 29, 30, 40 and 41) Input impedance Image rejection ratio DSB noise figure Conversion gain Input intercept point Output impedance IF Amplifier (Pins 26, 27, 34 and 35) Input impedance Lower cut-off frequency Upper cut-off frequency Power gain Bandwidth of external tank circuit Noise figure RSSI (Pins 25, 34 and 35) RSSI sensitivity RSSI compression RSSI dynamic range RSSI resolution RSSI rise time RSSI fall time Quiescent output voltage Maximum output voltage Slope of the RSSI has to be steady Pin = 30 to 100 dBV, pin 25 Pin = 100 to 30 dBV, pin 25 At Pin < 20 dBV at IF_IN1, IF_IN2, pin 25 At Pin = 100 dBV at IF_IN1, IF_IN2, pin 25 at Pin = -75 dBm at IR-mixer input Quality factor of external tank circuit approximately 20, fres = FIF/2, pin 24 Nominal deviation of signal 400 kHz, pin 24 Pin 23: C = 68 pF Pin 24 (see bus protocol E6 to E10) VCO 1, D12 VS = 1 VCO 2, D12 VS = 0 Pin 17 At IF_IN1,2; pins 34 and 35 At IF_IN1,2; pins 34 and 35 Pmin Pmax DR Acc tr tf Vout Vout 20 100 80 2 1 1 0.4 1.9 dBV dBV dB dB s s V V Pins 26 and 27 Pins 34 and 35 (differential) Zin fl3dB fu3dB Gp BW3dB NF 1200 - j480 90 130 85 10 9 MHz MHz dB MHz dB Pins 29 or 30 (single ended) Pins 40 and 41 Pins 29 or 30 (single ended) Rload = 200 Pins 29 or 30 (single ended) Pin 40 and 41 (differential) Zin IRR NFDSB = NFSSB Gconv IIP3 ZOUT 110 + j12 20 10 11 -7 175 + j145 dB dB dB dBm Test Conditions/Pins Symbol Min. Typ. Max. Unit
FM Demodulator, BB-filter (Pins 19, 20, 23 and 24) Co-channel rejection ratio Sensitivity Amplitude of recovered signal Corner frequency Output voltage DC range DEMOD_DAC range VCOs Frequency range Tuning gain Frequency control voltage range fvco fvco Gtune Vtune 0.4 2289 2289 200 2.8 2483 2483 MHz MHz MHz/V V CCRR S A fc VoutDC fIFcenter 1 5 10 0.5 450 680 VS - 1 dB V/MHz mVpp kHz V %
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12. Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25C Parameters PLL Scaling factor prescaler Scaling factor main counter Scaling factor swallow counter External reference input frequency External reference input voltage Scaling factor reference counter Charge Pump (Pin 13) Output current Output current Current scaling Leakage current Tx data rate Tx data filter clock Frequency deviation Frequency deviation scaling TX Driver (Pin 32) Maximum output power Minimum output power RF leakage Output impedance Ramp Generator (Pins 36 and 37) Minimum output voltage Maximum output voltage Rise time Fall time (see bus protocol E6-E10) Cramp = 270 pF at pin 37 Cramp = 270 pF at pin 37 Vmin Vmax tr tf 1.1 5 5 0.7 1.8 V V s s At L = 5.6 nH, pin 32 (see bus protocol E11-E12) At L = 5.6 nH, pin 32 (see bus protocol E11-E12) In RX mode At L = 5.6 nH, 2.5 GHz, pin 32 PTX PTX Pleak ZOUT 13+j40 3 -21 -47 dBm dBm dBm GFFM = GFFM_nom x GFCS (see bus protocol D7 ... D9) 6 taps in filter fTXFCLK GFFM_nom GFCS 60 VCP = VVS_CP/2, I_CPSW = 1, pin 48 VCP = VVS_CP/2, I_CPSW = 0, pin 48 ICP = ICP_nom + CPCS x ICP_step (see bus protocol D1 ... D2) OLE = 1 ICP_nom ICP_nom ICP_step IL 7.5 1.2 0.2 100 1152 6.912 400 130 mA mA mA pA kBit/s MHz kHz % AC coupled sinewave, pin 4 AC coupled sinewave, pin 4 SPSC SMC SSC fREF_CLK VREF_CLK SRC 50 6/8 0 10.368 13.824 250 32/33 82-89 31 MHz MHz mVRMS Test Conditions/Pins Symbol Min. Typ. Max. Unit
Gaussian Transmit Filter (Gaussian Shape B x T = 0.5)
Lock Detect and Test Mode Output (Pin 5) Locked = 1, unlocked = 0 Lock detect output, test mode output Test modes (see bus protocol E0 ... E2) Leakage current Saturation voltage Output voltage VCO Regulator (Pins 14, 15 and 12) Output voltage VSVCO = 3V, pin 15 VREG_VCO 2.6 2.7 2.8 V VOH = 4.6V IOL = 0.5 mA VSREG = 3V, pin 8 LD IL VSL VREG 2.9 3.0 5 0.4 3.1 A V V
Auxiliary Regulator (Pins 8, 9 and 10)
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12. Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS_REG = 3.2 V, Tamb = 25C Parameters 3-wire Bus Clock fClock 6.912 MHz Logic Input Levels (CLOCK, DATA, ENABLE, RX_ON, TX_ON, OLE, TX_DATA, DATA_HOLD) (Pins 1, 2, 3, 38, 39, 44, 47 and 48) High input level Low input level High input current Low input current Standby Control (Pins 6, 45 and 46) Power Up PU_REG = 1 PU_RX/TX = 1 PU_PLL = 1 High input level Standby PU_REG = 0 PU_RX/TX = 0 PU_PLL = 0 Low input level Power Up PU_REG = 1 PU_RX/TX = 1 PU_PLL = 1 High input current Standby PU_xxxx = 0 Low input current Settling Time VS = 0 active operation Settling Time standby active operation Settling Time active operation standby =1 =0 =1 =0 ViH ViL IiH IiL -5 -5 1.5 0.5 5 5 V V A A Test Conditions/Pins Symbol Min. Typ. Max. Unit
Pin 6 Pin 45 Pin 46
VPU_REG VPU_RX/TX VPU_PLL VPU_REG,OFF VPU_RX/TX,OFF VPU_PLL,OFF
2.0
V
Pin 6 Pin 45 Pin 46
0.7
V
VPU = 3V, pin 6 VPU = 4.6V, pin 45 VPU = 3V, pin 46 VPU = 4.6V VPU = 0V, pin 6 VPU = 0.5V, pins 45, 46 Switched from VS = 0 to VS = 3V Switched from PU = 0 to PU = 1 Switched from PU = 1 to standby RX
IPU_REG IPU_RX/TX IPU_PLL
20 60 100 200
30 80 125 300
40 100 150 400 0.1 1
A A A A A A s s s mA mA mA mA
IPU,OFF tsoa tssa tsas IS IS IS IS IS ICP 1 < 10 < 10 <2 85 82 54 56
Power Supply (Pins 7, 10, 12, 14, 33 and 42) RSSI only TX TX (GF active) Standby current Supply current CP PU_RX/TX = GND VVS_CP = 3V, PLL in lock condition, Pin 13
Total supply current
10
A A
25
4572I-DECT-07/05
Figure 12-1. Typical Application Circuit
RAMP_OUT 47 pF TX_OUT
RF_IN
180 nH 100 nH
SAW
Filter TFS 112B
47 pF
18 pF
27 pF 68 pF
GND3 31 RF_IN2 30 RF_IN1 29 VS_IF 33 GND2 28 RSSI 25
RSSI
IF_IN2 35
IF_IN1 34
RAMP_OUT 36
TX_OUT 32
27 pF 56 pF 37 RAMP_SET RX_ON TX_ON 38 RX_ON 39 TX_ON
IF_TANK2 27
IF_TANK1 26
150 nH
BB_OUT 24 BB_CF 23 REG_DEC 22 DAC_DEC 21
BB_OUT 68 pF
2.2 nF 100 pF TBD TBD
40 MIXER_OUT1 41 MIXER_OUT2 42 VS_MIXER 43 GND_PLL OLE PU_RX/TX PU_PLL TX_DATA
I_CPSW
T2803
DEMOD_TANK2 20 DEMOD_TANK1 19 GND1 18 VTUNE 17 GND_VCO 16 VREG_VCO 15
44 OLE 45 PU_RX/TX 46 PU_PLL
4 REF_CLOCK
22 nF
47 TX_DATA
3 ENABLE
VS_VCO 14
9 REG_CTRL 11 GND_CP 6 PU_REG 10 VS_REG 7 VS_PLL 12 VS_CP
180
150 nF
48 I_CPSW
1 CLOCK 2 DATA
CP 13
8 VREG
5 LD
56 pF
470 nF
CLOCK DATA ENABLE REF_CLK
LD
220 pF
PU_REG
4.7 nF
VCC
BC808
or similar
tantal
tantal
26
T2803
4572I-DECT-07/05
T2803
13. Ordering Information
Extended Type Number T2803-PLQ T2803-PLQW Package QFN48 QFN48, Pb-free, halogen-free Remarks Taped and reeled Taped and reeled MOQ 4000 pcs. 4000 pcs.
14. Package Information
27
4572I-DECT-07/05
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4572I-DECT-07/05

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