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DAC7541A
Low Cost 12-Bit CMOS Four-Quadrant Multiplying DIGITAL-TO-ANALOG CONVERTER
FEATURES
q FULL FOUR-QUADRANT MULTIPLICATION q 12-BIT END-POINT LINEARITY q DIFFERENTIAL LINEARITY 1/2LSB MAX OVER TEMPERATURE q MONOTONICITY GUARANTEED OVER TEMPERATURE q TTL-/CMOS-COMPATIBLE q SINGLE +5V TO +15V SUPPLY q LATCH-UP RESISTANT q 7521/7541/7541A REPLACEMENT q PACKAGES: Plastic DIP, Plastic SOIC q LOW COST
DESCRIPTION
The Burr-Brown DAC7541A is a low cost 12-bit, four-quadrant multiplying digital-to-analog converter. Laser-trimmed thin-film resistors on a monolithic CMOS circuit provide true 12-bit integral and differential linearity over the full specified temperature range. DAC7541A is a direct, improved pin-for-pin replacement for 7521, 7541, and 7541A industry standard parts. In addition to a standard 18-pin plastic package, the DAC7541A is also available in a surface-mount plastic 18-pin SOIC.
VREF
10k
10k
10k
10k
20k
20k
20k
20k
20k
20k
SPDT NMOS Switches 10k Bit 1 (MSB) Bit 2 Bit 3 Bit 11 Bit 12 (LSB)
IOUT 2 IOUT 1 RFB
Digital Inputs (DTL-/TTL-/CMOS-compatible) Logic: A switch is closed to IOUT 1 for its digital input in a "HIGH" state.
Switches shown for digital inputs "HIGH".
International Airport Industrial Park * Mailing Address: PO Box 11400 Tel: (520) 746-1111 * Twx: 910-952-1111 * Cable: BBRCORP *
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* Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd. * Tucson, AZ 85706 Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132 PDS-639C Printed in U.S.A. September, 1993
1987 Burr-Brown Corporation
SBAS147
SPECIFICATIONS
ELECTRICAL
At +25C, +VDD = +12V or +15V, VREF = +10V, VPIN 1 = V PIN 2 = 0V, unless otherwise specified. DAC7541A PARAMETER ACCURACY Resolution Relative Accuracy Differential Non-linearity Gain Error GRADE All J K J K J K TA = +25C 12 1 1/2 1 1/2 6 1 TA = TMAX, TMIN(1) 12 1 1/2 1 1/2 8 3 UNITS Bits LSB max LSB max LSB max LSB max LSB max LSB max TEST CONDITIONS/COMMENTS
1LSB = 0.024% of FSR. 1/2LSB = 0.012% of FSR. All grades guaranteed monotonic to 12 bits, TMIN to TMAX. Measured using internal RFB and includes effect of leakage current and gain T.C. Gain error can be trimmed to zero. Typical value is 2ppm/C. All digital inputs = 0V. All digital inputs = VDD.
Gain Temperature Coefficient (Gain/Temperature) Output Leakage Current: Out1 (Pin 1) Out2 (Pin 2) REFERENCE INPUT Voltage (Pin 17 to GND) Input Resistance (Pin 17 to GND)
ALL J, K J, K All All
5 5 -10/+10 7-18
5 10 10 -10/+10 7-18
ppm/C max nA max nA max V min/max k min/max
Typical input resistance = 11k. Typical input resistance temperature coefficient is -50ppm/C. DIGITAL INPUTS VIN (Input HIGH Voltage) VIL (Input LOW Voltage) IIN (Input Current) CIN (Input Capacitance)(2) All All All All All All All All 2.4 0.8 1 8 0.01 +5 to +16 2 100 2.4 0.8 1 8 0.02 +5 to +16 2 500 V min V max A max pF max % per % max V min to V max mA max A max
Logic inputs are MOS gates. IIN typ (25C) = 1nA VIN = 0V VDD = +11.4V to +16V Accuracy is not guaranteed over this range. All digital inputs VIL or VIN. All digital inputs 0V or VDD.
POWER SUPPLY REJECTION Gain/VDD POWER SUPPLY VDD Range IDD
NOTES: (1) Temperature ranges are: = 0C to + 70C for JP, KP, JU and KU versions. (2) Guaranteed by design but not production tested.
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for design guidance only and are not production tested. VDD = +15V, VREF = +10V except where stated, VPIN 1 = VPIN 2 = 0V, output amp is OPA606 except where stated. DAC7541A PARAMETER PROPAGATION DELAY (from Digital Input change to 90% of final Analog Output) DIGITAL-TO-ANALOG GLITCH IMPULSE MULTIPLYING FEEDTHROUGH ERROR (VREF to Out1) OUTPUT CURRENT SETTLING TIME All All OUTPUT CAPACITANCE COUT 1 (Pin 1) COUT 2 (Pin 2) COUT 1 (Pin 1) COUT 2 (Pin 2) All All All All 0.6 1.0 100 60 70 100 -- -- 100 60 70 100 s typ s max pF max pF max pF max pF max To 0.01% of Full Scale Range. Out1 Load = 100, CEXT = 13pF. Digital Inputs: 0V to VDD or VDD to 0V. Digital Inputs = VIH Digital Inputs = VIH Digital Inputs = VIL Digital Inputs = VIL GRADE TA = +25C TA = TMAX, TMIN(1) UNITS TEST CONDITIONS/COMMENTS Out1 Load = 100, CEXT = 13pF. Digital Inputs = 0V to VDD or VDD to 0V. VREF = 0V, all digital inputs 0V to VDD or VDD to 0V. Measured using OPA606 as output amplifier.
All All
100 1000
-- --
ns typ nV-s typ
All
1.0
--
mVp-p max
VREF = 10V, 10kHz sine wave.
NOTE: (1) Temperature ranges are: = 0C to + 70C for JP, KP, JU and KU versions.
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ABSOLUTE MAXIMUM RATINGS(1)
VDD (Pin 16) to Ground ...................................................................... +17V VREF (Pin 17) to Ground ..................................................................... +25V VRPB (Pin 18) to Ground ..................................................................... 25V Digital Input Voltage (pins 4-15) to Ground ............................... -0.4V, VDD VPIN 1, VPIN 2 to Ground ............................................................. -0.4V, VDD Power Dissipation (any Package): To +75C ..................................................................................... 450mW Derates above +75C .............................................................. -6mW/C Lead Temperature (soldering, 10s) ................................................ +300C Storage Temperature: Plastic Package ......................................... +125C NOTE: (1) Stresses above those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
PIN CONNECTIONS
Top View DIP/SOIC
IOUT 1 IOUT 2 GND Bit 1 (MSB) Bit 2 Bit 3 Bit 4 Bit 5 Bit 6
1 2 3 4 DAC7541A 5 6 7 8 9
18 RFB 17 VREF 16 +VDD 15 Bit 12 (LSB) 14 Bit 11 13 Bit 10 12 Bit 9 11 Bit 8 10 Bit 7
ELECTROSTATIC DISCHARGE SENSITIVITY
The DAC7541A is an ESD (electrostatic discharge) sensitive device. The digital control inputs have a special FET structure, which turns on when the input exceeds the supply by 18V, to minimize ESD damage. However, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. When not in use, devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are removed. BURN-IN SCREENING Burn-in screening is an option available for the models in the Ordering Information table. Burn-in duration is 160 hours at the indicated temperature (or equivalent combination of time and temperature). All units are tested after burn-in to ensure that grade specifications are met. To order burn-in, add "-BI" to the base model number. ORDERING INFORMATION
MODEL DAC7541AJP DAC7541AKP DAC7541AJU DAC7541AKU PACKAGE Plastic DIP Plastic DIP Plastic SOIC Plastic SOIC TEMPERATURE RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C
PACKAGE INFORMATION
MODEL DAC7541JP DAC7541KP DAC7541JU DAC7541KU DAC7541JP-BI DAC7541KP-BI PACKAGE Plastic DIP Plastic DIP Plastic SOIC Plastic SOIC Plastic DIP Plastic DIP PACKAGE DRAWING NUMBER(1) 218 218 219 219 218 218
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book.
RELATIVE ACCURACY (LSB) 1 1/2 1 1/2
GAIN ERROR (LSB) 6 1 6 1
BURN-IN SCREENING OPTION See text for details. MODEL DAC7541AJP-BI DAC7541AKP-BI PACKAGE Plastic DIP Plastic DIP TEMPERATURE RANGE 0C to +70C 0C to +70C RELATIVE ACCURACY (LSB) 1 1/2 BURN-IN TEMP. (160 Hours)(1) +85C +85C
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
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DAC7541A
PAD 1 2 3 4 5 6 7 8 9
FUNCTION IOUT1 IOUT2 GND Bit 1 (MSB) Bit 2 Bit 3 Bit 4 Bit 5 Bit 6
PAD 10 11 12 13 14 15 16 17 18
FUNCTION Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 (LSB) +VDD VREF RFEEDBACK
Substrate Bias: Isolated. NC: No Connection.
MECHANICAL INFORMATION
MILS (0.001") Die Size Die Thickness Min. Pad Size Metalization 104 x 105 5 20 3 4x4 MILLIMETERS 2.64 x 2.67 0.13 0.51 0.08 0.10 x 0.10 Aluminum
DIE TOPOLOGY DAC7541A
TYPICAL PERFORMANCE CURVES
TA = +25C, V DD = +15V, unless otherwise noted.
GAIN ERROR vs SUPPLY VOLTAGE 3 5/2
Feedthrough (% FSR)
FEEDTHROUGH ERROR vs FREQUENCY 10
1
Gain Error (LSB)
2 3/2 1 1/2 0 0 5 10 15 Supply Voltage (V)
0.10
0.010
0.001 100 1k 10k Frequency (Hz) 100k 1M
LINEARITY vs SUPPLY VOLTAGE 3/2 5/4
SUPPLY CURRENT vs SUPPLY VOLTAGE 3/2 5/4
Linearity Error (LSB)
Supply Current (A)
1 3/4 1/2 1/4 0 0 5 10 15 Supply Voltage (V)
1 3/4 VIH = +2.4V 1/2 1/4 0 0 5 10 Supply Voltage (V) VIH = VDD 15
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DISCUSSION OF SPECIFICATIONS
RELATIVE ACCURACY This term (also known as linearity) describes the transfer function of analog output to digital input code. The linearity error describes the deviation from a straight line between zero and full scale. DIFFERENTIAL NONLINEARITY Differential nonlinearity is the deviation from an ideal 1LSB change in the output, from one adjacent output state to the next. A differential nonlinearity specification of 1.0LSB guarantees monotonicity. GAIN ERROR Gain error is the difference in measure of full-scale output versus the ideal DAC output. The ideal output for the DAC7541A is -(4095/4096) X (VREF). Gain error may be adjusted to zero using external trims. OUTPUT LEAKAGE CURRENT The measure of current which appears at Out1 with the DAC loaded with all zeros, or at Out2 with the DAC loaded with all ones. MULTIPLYING FEEDTHROUGH ERROR This is the AC error output due to capacitive feedthrough from VREF to Out1 with the DAC loaded with all zeros. This test is performed at 10kHz. OUTPUT CURRENT SETTLING TIME This is the time required for the output to settle to a tolerance of 0.5LSB of final value from a change in code of all zeros to all ones, or all ones to all zeros. PROPAGATION DELAY This is the measure of the delay of the internal circuitry and is measured as the time from a digital code change to the point at which the output reaches 90% of final value. DIGITAL-TO-ANALOG GLITCH IMPULSE This is the measure of the area of the glitch energy measured in nV-seconds. Key contributions to glitch energy are digital word-bit timing differences, internal circuitry timing differences, and charge injected from digital logic. MONOTONICITY Monotonicity assures that the analog output will increase or stay the same for increasing digital input codes. The DAC7541A is guaranteed monotonic to 12 bits. POWER SUPPLY REJECTION Power supply rejection is the measure of the sensitivity of the output (full scale) to a change in the power supply voltage.
CIRCUIT DESCRIPTION
The DAC7541A is a 12-bit multiplying D/A converter consisting of a highly stable thin-film R-2R ladder network and 12 pairs of current steering switches on a monolithic chip. Most applications require the addition of a voltage or current reference and an output operational amplifier. A simplified circuit of the DAC7541A is shown in Figure 1. The R-2R inverted ladder binarily divides the input currents that are switched between IOUT 1 and IOUT 2 bus lines. This switching allows a constant current to be maintained in each ladder leg independent of the input code. The input resistance at VREF (Figure 1) is always equal to RLDR (RLDR is the R/2R ladder characteristic resistance and is equal to value "R"). Since RIN at the VREF pin is constant, the reference terminal can be driven by a reference voltage or a reference current, AC or DC, of positive or negative polarity.
VREF
10k
10k
10k
20k S1
20k S2
20k S3
20k S12
20k
IOUT 2 IOUT 1 RFB Bit 1 (MSB) Bit 2 Bit 3 Bit 12 (LSB)
Digital Inputs (DTL-/TTL-/CMOS-compatible) Switches shown for digital inputs "HIGH".
FIGURE 1. Simplified DAC Circuit. EQUIVALENT CIRCUIT ANALYSIS Figures 2 and 3 show the equivalent circuits for all digital inputs low and high, respectively. The reference current is switched to IOUT 2 when all inputs are low and IOUT 1 when inputs are high. The IL current source is the combination of surface and junction leakages to the substrate; the 1/4096 current source represents the constant one-bit current drain through the ladder terminal. DYNAMIC PERFORMANCE Output Impedance The output resistance, as in the case of the output capacitance, is also modulated by the digital input code. The resistance looking back into the IOUT 1 terminal may be anywhere between 10k (the feedback resistor alone when all digital inputs are low) and 7.5k (the feedback resistor in parallel with approximately 30k of the R-2R ladder network resistance when any single bit logic is high). The static accuracy and dynamic performance will be affected by this modulation. The gain and phase stability of the output
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DAC7541A
RFB R = 10k IOUT 1 IL IREF VREF 1/4096 IL 90pF 60pF
IREF VREF 1/4096 IL 90pF
RFB R = 10k R 10k IOUT 1
R 10k IOUT 2
IL 55pF IOUT 2
FIGURE 2. DAC7541A Equivalent Circuit (All inputs LOW). amplifier, board layout, and power supply decoupling will all affect the dynamic performance of the DAC7541A. The use of a compensation capacitor may be required when highspeed operational amplifiers are used. It may be connected across the amplifier's feedback resistor to provide the necessary phase compensation to critically dampen the output. See Figures 4 and 6.
FIGURE 3. DAC7541A Equivalent Circuit (All inputs HIGH).
BINARY INPUT MSB LSB 1111 1111 1111 1000 0000 0000 0000 0000 0001 0000 0000 0000 ANALOG OUTPUT -VREF (4095/4096) -VREF (2048/4096) -VREF (1/4096) 0V
TABLE I. Unipolar Codes. C1 phase compensation (10 to 25pF) in Figure 4 may be required for stability when using high speed amplifiers. C1 is used to cancel the pole formed by the DAC internal feedback resistance and output capacitance at Out1. R1 in Figure 5 provides full scale trim capability--load the DAC register to 1111 1111 1111, adjust R1 for VOUT = - VREF (4095/4096). Alternatively, full scale can be adjusted by omitting R1 and R2 and trimming the reference voltage magnitude. BIPOLAR FOUR-QUADRANT OPERATION Figure 6 shows the connections for bipolar four-quadrant operation. Offset can be adjusted with the A1 to A2 summing resistor, with the input code set to 1000 0000 0000. Gain may be adjusted by varying the feedback resistor of A2. The input/output relationship is shown in Table II.
BINARY INPUT MSB LSB 1111 1111 1111 1000 0000 0000 0111 1111 1111 0000 0000 0000 ANALOG OUTPUT +VREF (2047/2048) 0V -VREF (1/2048) -VREF (2048/2048)
APPLICATIONS
OP AMP CONSIDERATIONS The input bias current of the op amp flows through the feedback resistor, creating an error voltage at the output of the op amp. This will show up as an offset through all codes of the transfer characteristics. A low bias current op amp such as the OPA606 is recommended. Low offset voltage and VOS drift are also important. The output impedance of the DAC is modulated with the digital code. This impedance change (approximately 10k to 30k) is a change in closed-loop gain to the op amp. The result is that VOS will be multiplied by a factor of one to two depending on the code. This shows up as a linearity error. Offset can be adjusted out using Figure 4. Gain may be adjusted using Figure 5. UNIPOLAR BINARY OPERATION (Two-Quadrant Multiplication) Figure 4 shows the analog circuit connections required for unipolar binary (two-quadrant multiplication) operation. With a DC reference voltage or current (positive or negative polarity) applied at pin 17, the circuit is a unipolar D/A converter. With an AC reference voltage or current, the circuit provides two-quadrant multiplication (digitally controlled attenuation). The input/output relationship is shown in Table I.
TABLE II. Bipolar Codes.
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MSB B1 * 16 4 5 * 6 * 7 * 8 * 9 * * * * * B12 VOUT = -VREF 10 11 12 13 14 15 RF 18 1 2 +15V DAC7541A VREF C1 VOUT OPA604
(
B1 2
+
B2 4
+
B3 8
+***+
B12 4096
)
-10V VREF +10V 0 VOUT - 4095 V 4096 REF
17
Out1 Out2 3
10k Single-Point Ground +VCC
Where: BN = 1 if the BN digital input is HIGH. BN = 0 if the BN digital input is LOW.
FIGURE 4. Basic Connection With Op Amp VOS Adjust: Unipolar (two-quadrant) Multiplying Configuration.
MSB B1 * 16 4 5 * 6 * 7 * 8 * 9 * * * * * B12 R1 200 R2 200k
10 11 12 13 14 15 18 1
+15V DAC7541A VREF 3
17
OPA604 2 10k
+VCC
FIGURE 5. Basic Connection With Gain Adjust (allows adjustment up or down).
47 +VDD 16 VREF 17 4...15 3 5k Bits 1-12 18 C1 33pF 1 DAC7541A 2 A1 A2 OPA604 or 1/2 OPA2604 OPA604 or 1/2 OPA2604 10k VOUT 20k 20k
VOUT = +VREF
(
B1 1
+
B2 2
+
B3 4
+***+
B12 2048
-1
)
FIGURE 6. Bipolar Four-Quadrant Multiplier.
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DAC7541A
DIGITALLY CONTROLLED GAIN BLOCK The DAC7541A may be used in a digitally controlled gain block as shown in Figure 7. This circuit gives a range of gain from one (all bits = one) to 4096 (LSB = one). The transfer function is: -VIN VOUT = B1 B2 B3 B12 + + +***+ 2 4 8 4096
Bits 1 to 12
VIN
18 1 2 3
16 17
VDD
(
)
DAC7541A
All bits off is an illegal state, as division by zero is impossible (no op amp feedback). Also, errors increase as gain increases, and errors are minimized at major carries (only one bit on at a time).
VOUT OPA604
FIGURE 7. Digitally Programmable Gain Block.
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Oct-2003
PACKAGING INFORMATION
ORDERABLE DEVICE DAC7541AJP DAC7541AJU DAC7541AKP DAC7541AKU DAC7541AKU/1K STATUS(1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE PACKAGE TYPE PDIP SOP PDIP SOP SOP PACKAGE DRAWING N DTC N DTC DTC PINS 18 18 18 18 18 PACKAGE QTY 20 43 20 43 1000
(1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
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