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Integrated Circuit Systems, Inc.
ICS844002I-01
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
FEATURES
* Two LVDS outputs * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input * Supports the following output frequencies: 156.25MHz, 125MHz, 62.5MHz * VCO range: 560MHz - 680MHz * RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.41ps (typical) * Full 2.5V supply mode * -40C to 85C ambient operating temperature * Available in both, standard and RoHS/Lead-Free compliant packages
GENERAL DESCRIPTION
The ICS844002I-01 is a 2 output LVDS Synthesizer optimized to generate Ethernet HiPerClockSTM reference clock frequencies and is a member of the HiPerClocks T M family of high performance clock solutions from ICS. Using a 25MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz and 62.5MHz. The ICS844002I-01 uses ICS' 3 rd generation low phase noise VCO technology and can achieve <1ps typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS844002I-01 is packaged in a small 20-pin TSSOP package.
IC S
FREQUENCY SELECT FUNCTION TABLE
F_SEL1 F_SEL0 0 0 1 1 0 1 0 1 M Divider Value 25 25 25 Not Used N Divider Value 4 5 10 Output Frequency (MHz) (25MHz Reference) 156.25 125 62.5 Not Used
PIN ASSIGNMENT
nc VDDO Q0 nQ0 MR nPLL_SEL nc VDDA F_SEL0 VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDDO Q1 nQ1 GND VDD nXTAL_SEL REF_CLK XTAL_IN XTAL_OUT F_SEL1
ICS844002I-01
BLOCK DIAGRAM
F_SEL[1:0] Pulldown nPLL_SEL Pulldown REF_CLK Pulldown
25MHz
2
20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View
Q0
1
1
F_SEL[1:0] 0 0 /4 0 1 /5 10 11 /10 not used
nQ0
XTAL_IN
OSC
XTAL_OUT nXTAL_SEL
Pulldown
0
Phase Detector
VCO 625MHz
(w/25MHz Reference)
0
Q1 nQ1
M = 25 (fixed)
MR
Pulldown
844002AGI-01
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Integrated Circuit Systems, Inc.
ICS844002I-01
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
Type Description No connect. Output supply pins. Differential output pair. LVDS interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and REF_CLK as input to the dividers. Pulldown When LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. Analog supply pin. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Pulldown LVCMOS/LVTTL clock input. Selects between cr ystal or REF_CLK inputs as the the PLL Reference Pulldown source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH. LVCMOS/LVTTL interface levels. Power supply ground. Differential output pair. LVDS interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 7 2, 20 3, 4 5 Name nc VDDO Q0, nQ0 MR Unused Power Ouput Input
6 8 9, 11 10, 16 12, 13 14 15 17 18, 19
nPLL_SEL VDDA F_SEL0, F_SEL1 VDD XTAL_OUT, XTAL_IN REF_CLK nXTAL_SEL GND nQ1, Q1
Input Power Input Power Input Input Input Power Output
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF k
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Integrated Circuit Systems, Inc.
ICS844002I-01
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
4.6V -0.5V to VDD + 0.5V 10mA 15mA 73.2C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = -40C TO 85C
Symbol VDD VDDA VDDO IDD IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 2.375 Typical 2.5 2.5 2.5 Maximum 2.625 2.625 2.625 85 9 70 Units V V V mA mA mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = -40C TO 85C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage REF_CLK, MR, Input F_SEL0, F_SEL1, High Current nPLL_SEL, nXTAL_SEL REF_CLK, MR, Input F_SEL0, F_SEL1, Low Current nPLL_SEL, nXTAL_SEL Test Conditions VDD = 2.5V VDD = 2.5V VDD = VIN = 2.625V Minimum Typical 1.7 -0.3 Maximum VDD + 0.3 0.7 150 Units V V A
IIL
VDD = 2.625V, VIN = 0V
-150
A
TABLE 3C. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = -40C TO 85C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 0.7 Test Conditions Minimum 240 40 1.1 50 1.5 Typical Maximum 550 Units mV mV V mV
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REV. A JANUARY 5, 2006
Integrated Circuit Systems, Inc.
ICS844002I-01
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
Test Conditions Minimum 22.4 Typical 25 Maximum 27.2 50 7 1 Units MHz pF mW
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant crystal. Fundamental
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = VDDO = 2.5V5%, TA = -40C TO 85C
Symbol fOUT t sk(o) t jit(O) tR / tF Parameter Output Frequency Output Skew; NOTE 1, 2 156.25MHz, (1.875MHz - 20MHz) RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time 125MHz, (1.875MHz - 20MHz) 62.5MHz,(1.875MHz - 20MHz) 20% to 80% 250 Test Conditions F_SEL[1:0] = 00 F_SEL[1:0] = 01 F_SEL[1:0] = 10 Minimum 140 112 56 5 0.41 0.44 0.47 550 52 Typical Maximum 170 136 68 20 Units MHz MHz MHz ps ps ps ps ps %
odc Output Duty Cycle 48 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot.
844002AGI-01
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Integrated Circuit Systems, Inc.
ICS844002I-01
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE
AT
156.25MHZ
0 -10 -20 -30 -40 -50 -60
Ethernet Filter 156.25MHz
RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.41ps (typical)
NOISE POWER dBc Hz
-70 -80 -90 -100 -110
Raw Phase Noise Data
-120 -130 -140 -150 -160 -170 -180 -190 1k 10k
100k
Phase Noise Result by adding Ethernet Filter to raw data
1M
10M
100M
OFFSET FREQUENCY (HZ)
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REV. A JANUARY 5, 2006
Integrated Circuit Systems, Inc.
ICS844002I-01
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VDD, VDDO VDDA
Noise Power
Phase Noise Plot
2.5V5% POWER SUPPLY Float GND + -
Qx
SCOPE
LVDS
nQx
Phase Noise Mask
f1
Offset Frequency
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx
RMS PHASE JITTER
80% Qx nQy Qy
tsk(o)
80% VSW I N G
Clock Outputs
20% tR tF
20%
OUTPUT SKEW
nQ0, nQ1 Q0, Q1
t PW
PERIOD
PROPAGATION DELAY
VDD out
t
odc =
t PW t PERIOD
x 100%
out
VOS/ VOS
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OFFSET VOLTAGE SETUP
VDD out
DC Input
LVDS
100
VOD/ VOD out
DIFFERENTIAL OUTPUT VOLTAGE SETUP
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DC Input
LVDS
Integrated Circuit Systems, Inc.
ICS844002I-01
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS844002I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA.
2.5V VDD .01F VDDA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844002I-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 25MHz, 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p
Figure 2. CRYSTAL INPUt INTERFACE
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Integrated Circuit Systems, Inc.
ICS844002I-01
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
OUTPUTS
LVDS All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS:
CRYSTAL INPUT: For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from XTAL_IN to ground. REF_CLK INPUT: For applications not requiring the use of the reference clock, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the REF_CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
2.5V LVDS DRIVER TERMINATION
Figure 3 shows a typical termination for LVDS driver in characteristic impedance of 100 differential (50 single) transmission line environment. For buffer with multiple LDVS driver, it is recommended to terminate the unused outputs.
2.5V 2.5V LVDS_Driv er + R1 100
-
100 Ohm Differential TransmissionLine 100 Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
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REV. A JANUARY 5, 2006
Integrated Circuit Systems, Inc.
ICS844002I-01
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844002I-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS844002I-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results.
* *
Power (core)MAX = VDD_MAX * IDD_MAX = 2.625V * 85mA = 223mW Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 2.625V * 70mA = 184mW
Total Power_MAX = 223mW + 184mW = 407mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature qJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.407W * 66.6C/W = 112C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA FOR 20-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Meters per Second)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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Integrated Circuit Systems, Inc.
ICS844002I-01
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS844002I-01 is: 2914
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ICS844002I-01
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
20 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL MIN N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 20 1.20 0.15 1.05 0.30 0.20 6.60 Millimeters MAX
Reference Document: JEDEC Publication 95, MO-153
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REV. A JANUARY 5, 2006
Integrated Circuit Systems, Inc.
ICS844002I-01
FEMTOCLOCKSTM CRYSTAL-TOLVDS FREQUENCY SYNTHESIZER
Marking Package 20 Lead TSSOP 20 Lead TSSOP 20 Lead "Lead-Free" TSSOP 20 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS844002AGI-01 ICS844002AGI-01T ICS844002AGI-01LF ICS844002AGI-01LFT ICS44002AI01 ICS44002AI01 ICS4002AI01L ICS4002AI01L
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 844002AGI-01
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