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Ordering number : ENN7236
w as DVD systems, home theater systems, and digital TV
a D . Overview w The a w LC708728V isfor high-performance stereo D/A converter developed high-end audio applications such
sets. It supports 16 to 32-bit word length PCM data as its digital input format, and supports sampling rates up to 192 kHz. It can also be used in a DSD (Direct Stream Digital) compatible mode by supplying a 64-bit stream for each input channel. This IC is formed from serial interface port, digital interpolation filter, multi-bit converter, and stereo D/A converter functions. It includes muting and attenuator circuits that can be controlled individually for each channel. The operating mode can be selected to be either software control mode or hardware control mode. In software control mode, the IC can be controlled by a microcontroller over a 2-wire or 3-wire serial port. In this mode, a wide range of functions, including muting, attenuation, and phase inversion can be controlled. DSD mode can only be used in hardware control mode. This IC is optimal for use as an interface for AC-3, DTS, and MPEG audio decoders for surround control, and for use in DVD players that support DVD-A.
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CMOS LSI
LC708728V
High-Performance 24-Bit 192 kHz D/A Converter Features Built-in Electronic Volume Control and DSD Support
Features
* Stereo D/A converter that supports both 24-bit PCM and 1-bit DSD * Signal-to-noise ratio: 106 dB (48 kHz, A weighted) * Total harmonic distortion: -97 dB * D/A converter sampling frequency: 8 kHz to 192 kHz * Control modes: Either software or hardware mode can be selected. * Built-in microprocessor interface (either 2-wire or 3wire) * Input data formats I2S, left/right justified, DSP 16, 20, 24, and 32 bits * Built-in electronic volume control with independent left and right channel controls 0 to 127.5 dB in 0.5 dB steps * Operating voltage range: 3.0 to 5.5 V * Package: 20-pin SSOP
* This LSI is designed and produced by Wolfson Microelectronics Ltd., and sold by SANYO Electric Co., Ltd. based on corroboration between Wolfson Microelectronics Ltd. and SANYO Electric Co., Ltd. * CCB is the registered trademark of SANYO Electric Co., Ltd. * CCB is the original bus format of SANYO Electric Co., Ltd. and all bus addresses are controlled by SANYO Electric Co., Ltd.
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Applications
DVD audio and DVD "universal" players Home theater systems Digital TVs Digital broadcast receivers
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
52504TN (OT) No. 7236-1/31
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LC708728V
Package Dimensions
unit: mm 20-pin SSOP
[LC708728V]
DM0015.A
b
20
e
11
E1
E
GAUGE PLANE 1 10
D 0.25 c A A2 A1 -C0.10 C
SEATING PLANE
L
SANYO: 20-pin SSOP
Symbols MIN A A1 A2 b c D e E E1 L 7.40 5.00 0.55 0 ---- 0.05 1.65 0.22 0.09 6.90
Dimendions (mm) NOM ---- ---- 1.75 ---- ---- 7.20 0.65 BSC 7.80 5.30 0.75 4 8.20 5.60 0.95 8 MAX 2.0 ---- 1.85 0.38 0.25 7.50
REF:
JEDEC.95, MO-150
Notes: A. Linear dimensions are all stated in mm. B. This figure is subject to change without notification. C. The body dimensions do not include burrs and protrusions of up to 0.20 mm. D. Complies with JEDEC.95 MO-150, VARIATION=AE. Further details are provided in these specifications.
No. 7236-2/31
LC708728V Block Diagram
2 MODE LATI S
SCKDSD SDIDEM MUTEB CSBIWL
ZERO
LC708728V
CONTROL INTERFACE
PCM/DSD MUTE/ ATTEN SERIAL INTERFACE MUTE/ ATTEN DIGITAL FILTERS SIGMA DELTA MODULATOR MUX LEFT DAC LOW PASS FILTER VOUTL SIGMA DELTA MODULATOR LOW PASS FILTER
BCKIN LRCIN DIN
MUX
RIGHT DAC
VOUTR
VMID
MCLK
AVDD DVDD
VREFP VREFN AGND
DGND
Pin Assignment
LRCIN DIN BCKIN MCLK ZERO DGND DVDD VOUTR AGND AVDD 1 2 3 4 5 6 7 8 9 10 Top view 20 19 18 17 16 LATI S SCKDSD SDIDEM MUTEB MODE CSBIWL VREFP VREFN VMID VOUTL
2
LC708728V
15 14 13 12 11
No. 7236-3/31
LC708728V Pin Functions
Pin No. 1 Pin LRCIN Type Digital input Function D/A converter sampling rate clock input: PCM input mode Right channel DSD bit stream input: DSD input mode Serial audio data input: PCM input mode Left channel DSD bit stream input: DSD input mode Audio data bit clock input Master clock input IZD detection flag Digital GND Digital VDD Right channel D/A converter output Analog GND Analog VDD Left channel D/A converter output Mid-rail decoupling point D/A converter n-channel VREF pin. Connect this pin to AGND. (Do not supply a level lower than AGND to this pin.) D/A converter p-channel VREF pin. Connect this pin to AVDD. (Do not supply a level lower than AVDD to this pin.) Software mode: 3-wire serial control chip select Hardware mode: Input word length Control mode selection (Low: hardware, high: software) Muting control (Low: muting on, high: muting off, high impedance (Z) : enable auto-muting) Software mode: 3-wire or 2-wire serial control data input Hardware mode: Deemphasis selection Software mode: 3-wire or 2-wire serial control clock input Hardware mode: DSD bit stream operation selection Software mode: 3-wire serial control load input Hardware mode: Input data format selection
2 3 4 5 6 7 8 9 10 11 12 13
DIN BCKIN MCLK ZERO DGND DVDD VOUTR AGND AVDD VOUTL VMID VREFN
Digital input Digital input Digital input Digital output (open drain) Power supply Power supply Analog output Power supply Power supply Analog output Analog output Power supply
14
VREFP
Power supply
15 16 17
CSBIWL MODE MUTEB
Digital input (pulled up) Digital input (pulled down) Bidirectional digital
18
SDIDEM
Bidirectional digital
19
SCKDSD LATI2S
Digital input (pulled down)
20
Digital input (pulled up)
Note: Each digital input pin is provided with a Schmitt trigger input buffer.
No. 7236-4/31
LC708728V Absolute Maximum Ratings The absolute maximum ratings given here are only stress ratings. This device may be permanently damaged if it is operated continuously above any of these limits. Device function operating limits under the specified test conditions and the guaranteed performance specifications are shown in the electrical characteristics. ESD Sensitive Device. This device is fabricated in a CMOS process. As a result, it can be easily damaged by excessive electrostatic voltages. Appropriate anti-static measures must be taken when handling or storing this device.
Ratings min -0.3 -0.3 DGND - 0.3 AGND - 0.3 typ max +7 +7 DVDD + 0.3 AVDD + 0.3 50 Topr Tstg -25 -65 +85 +150 +240 +183
Parameter Digital system supply voltage Analog system supply voltage Digital input voltage range Analog input voltage range Master clock frequency Operating temperature Storage temperature Maximum mounting temperature (soldering time: 10 s) Maximum mounting temperature (soldering time: 2 m)
Symbol
Conditions
Unit V V V V MHz C C C C
Note: The potential difference between the analog system ground and the digital system ground must be 0.3 V or less.
Allowable Operating Ranges
Parameter Digital system supply voltage Analog system supply voltage GND Potential difference between DGND and AGND Analog system supply current Digital system supply current Analog system supply current Digital system supply current AVDD = 5 V DVDD = 5 V AVDD = 3.3 V DVDD = 3.3 V Symbol DVDD AVDD AGND, DGND -0.3 Test Conditions Ratings min 3.0 3.0 0 0 19 8 18 4 +0.3 typ max 5.5 5.5 Unit V V V V mA mA mA mA
Electrical Characteristics Test conditions at Ta = 25C, AVDD, DVDD = 5 V, AGND = 0 V, DGND = 0 V, fs = 48 kHz, MCLK = 256 fs (Unless otherwise specified.)
Parameter [Digital Logic Levels (TTL levels)] Low-level input voltage High-level input voltage Low-level output voltage High-level output voltage [Analog Reference Levels] Reference voltage Voltage divider resistance RVMID VMID (VREFP - VREFN) / 2 - 50 mV (VREFP - VREFN) / 2 12 (VREFP - VREFN) / 2 + 50 mV V k VIL VIH VOL VOH IOL = 1 mA IOH = 1 mA AVDD - 0.3 V 2.0 AGND + 0.3 V 0.8 V V V V Symbol Test Conditions Ratings min typ max Unit
Continued on next page.
No. 7236-5/31
LC708728V
Continued from preceding page.
Parameter Symbol Test Conditions Ratings min typ 1.1 x AVDD/5 100 106 106 106 105 103 106 -97 100 106 100 max Unit
[D/A Converter Output (Load = 10 k, 50 pF)] 0 dB Fs, Full scale output voltage SNR (*1, 2, 3) SNR (*1, 2, 3) SNR (*1, 2, 3) SNR (*1, 2, 3) SNR (*1, 2, 3) SNR (*1, 2, 3) THD (*1, 2, 3) THD + N (Dynamic range, *2) D/A converter channel separation [Analog Output Levels] Load = 10 k, 0 dBFs Output level Inter-channel gain mismatch To midrail or a.c. coupled Minimum load resistance Maximum load capacitance DC output level [Power On Reset (POR)] POR threshold value 2.4 V To midrail or a.c. coupled (AVDD = 3.3 V) 5 V or 3.3 V Load = 10 k, 0 dBFs, (AVDD = 3.3 V) 1.1 0.726 1 1 600 100 (VREFP - VREFN) / 2 VRMS VRMS %FSR k pF V At DAC outputs A-weighted when fs = 48 kHz A-weighted when fs = 96 kHz A-weighted when fs = 192 kHz A-weighted when fs = 48 kHz AVDD, DVDD = 3.3 V A-weighted when fs = 96 kHz AVDD, DVDD = 3.3 V Not `A' weighted when fs = 48 kHz 1 kHz, 0 dBFs 1 kHz, -60 dBFs Vrms dB dB dB dB dB dB dB dB dB
Notes:*1.SNR is measured for the 20 to 20 kHz bandwidth with a 1 kHz full scale input and a silent input (all bits 0) and with an A-weighting filter inserted. *2.All characteristics measurements are performed with both a 20 kHz low-pass filter and an A-weighting filter inserted. Measurement in this state results in a higher THD + N and a lower SNR than those of the normal electrical characteristics. The low-pass filter is also effective for out-of-band noise, and although it has no audible effect, it does influence the characteristics shown above. *3.VMID must be decoupled with 10 F and 0.1 F capacitors. (Using values smaller than these will degrade the device characteristics.)
No. 7236-6/31
LC708728V Power Supply Timing
DVDD 1/2DVDD
AVDD tPSU
1/2AVDD
Figure 1 Power Supply Timing Requirements
Test conditions at Ta = 25C, AVDD, DVDD = 5 V, AGND = 0 V, DGND = 0 V, fs = 48 kHz, MCLK = 256 fs (Unless otherwise specified.)
Parameter [Power Application Timing] DVDD setup time after the rise of AVDD tPSU Time interval between DVDD/2 and AVDD/2 10 ms Symbol Test Conditions Ratings min typ max Unit
Master Clock Timing
tMCLKL MCLK tMCLKH tMCLKY
Figure 2 Master Clock Timing Overview
Test conditions at Ta = 25C, AVDD, DVDD = 5 V, AGND = 0 V, DGND = 0 V, fs = 48 kHz, MCLK = 256 fs (Unless otherwise specified.)
Parameter [Master Clock Timing] MCLK master clock pulse width (high) MCLK master clock pulse width (low) MCLK master clock cycle time MCLK duty cycle tMCLKH tMCLKL tMCLKY 13 13 26 40:60 60:40 ns ns ns Symbol Test Conditions Ratings min typ max Unit
Digital Audio Interface
tBCH BCKIN tBCY tBCL
LRCIN tDS DIN tDH tLRH tLRSU
Figure 3 Digital Audio Interface Timing
No. 7236-7/31
LC708728V Test conditions at Ta = 25C, AVDD, DVDD = 5 V, AGND = 0 V, DGND = 0 V, fs = 48 kHz, MCLK = 256 fs (Unless otherwise specified.)
Parameter [Audio Data Input Timing] BCKIN cycle time BCKIN pulse width (high) BCKIN pulse width (low) LRCIN setup time before the BCKIN rising edge LRCIN hold time from the BCKIN rising edge DIN setup time before the BCKIN rising edge DIN hold time from the BCKIN rising edge tBCY tBCH tBCL tLRSU tLRH tDS tDH 40 16 16 8 8 8 8 ns ns ns ns ns ns ns Symbol Test Conditions Ratings min typ max Unit
DSD Audio Monophase Interface
tBCH MCLK tBCY DIN/LRCIN tDS tDH tBCL
Figure 4 Normal DSD Timing Overview Test conditions at Ta = 25C, AVDD, DVDD = 5 V, AGND = 0 V, DGND = 0 V, fs = 48 kHz, MCLK = 256 fs (Unless otherwise specified.)
Parameter [Audio Data Input Timing] MCLK cycle time MCLK pulse width (high) MCLK pulse width (low) DIN/LRCIN setup time before the MCLK rising edge DIN/LRCIN hold time from the MCLK rising edge tBCY tBCH tBCL tDS tDH 160 160 10 10 344 ns ns ns ns ns Symbol Test Conditions Ratings min typ max Unit
DSD Audio Biphase Interface
tPH tBCY BCKIN tBCH MCLK tSU DIN/LRCIN D0 tHD D1 tMCY D1 D2 D2 tBCL tMCL tMCH
Figure 5 Biphase DSD Timing Overview
No. 7236-8/31
LC708728V Test conditions at Ta = 25C, AVDD, DVDD = 5 V, AGND = 0 V, DGND = 0 V, fs = 48 kHz, MCLK = 256 fs (Unless otherwise specified.)
Parameter [Audio Data Input Timing] BCKIN cycle time BCKIN pulse width (high) BCKIN pulse width (low) MCLK cycle time MCLK pulse width (high) MCLK pulse width (low) Phase shift between BCKIN and MCLK Data setup time before the BCKIN falling edge Data hold time before the BCKIN rising edge tBCY tBCH tBCL tMCY tMCH tMCL tPH tSU tHD 10 10 160 160 80 80 162.8 81.4 81.4 325.5 162.8 162.8 20 ns ns ns ns ns ns ns ns ns Symbol Test Conditions Ratings min typ max Unit
Microcontroller Three-Wire Interface Timing
CSBIWL tCSSU tCSSH tCSL
tCSH
LATI2S tSCY tSCH SCKDSD tSCL tCSS tSCS
SDIDEM tDSU tDHO
LSB
Figure 6 Program Register Input Timing - Three-Wire Serial Control Mode
No. 7236-9/31
LC708728V Test conditions at Ta = 25C, AVDD, DVDD = 5 V, AGND = 0 V, DGND = 0 V, fs = 48 kHz, MCLK = 256 fs (Unless otherwise specified.)
Parameter [Program Register Input] From the SCKDSD rising edge to the LATI2S rising edge SCKDSD pulse cycle time SCKDSD pulse width (low) SCKDSD pulse width (high) Setup time from SDIDEM to SCKDSD Hold time from SCKDSD to SDIDEM LATI2S pulse width (low) LATI2S pulse width (high) From the LATI2S rising edge to the SCKDSD rising edge Setup time from CSBIWL to LATI2S Hold time from LATI2S to CSBIWL tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS tCSSU tCSSH 40 80 20 20 20 20 20 20 20 20 20 ns ns ns ns ns ns ns ns ns ns ns Symbol Test Conditions Ratings min typ max Unit
Microcontroller Two-Wire Interface Timing
tSCY SCKDSD tSSU SDIDEM tSHD tSCF
tSCH tSCL tDHD tDSU t SCR tDR tESU
tDF
Figure 7 Program Register Input Timing - Two-Wire Serial Control Mode
No. 7236-10/31
LC708728V Test conditions at Ta = 25C, AVDD, DVDD = 5 V, AGND = 0 V, DGND = 0 V, fs = 48 kHz, MCLK = 256 fs (Unless otherwise specified.)
Parameter [Program Register Input] SCKDSD pulse cycle time SCKDSD pulse width (low) SCKDSD pulse width (high) Data setup time for the start signal from SDIDEM to SCKDSD Data hold time for the start signal from SCKDSD to SDIDEM Data setup time from SDIDEM to SCKDSD Data hold time from SCKDSD to SDIDEM SCKDSD rise time SCKDSD fall time SDIDEM rise time SDIDEM fall time Data setup time for the stop signal from SDIDEM to SCKDSD tSCY tSCL tSCH tSSU tSHD tDSU tDHD tSCR tSCF tDR tDF tESU 80 20 20 10 10 20 20 5 5 5 5 10 ns ns ns ns ns ns ns ns ns ns ns ns Symbol Test Conditions Ratings min typ max Unit
Notes: 1. The device address in 2-wire mode is 001101X (binary). The last bit can be selected by the user. 2. The CSBIWL pin indicates the last bit of the chip address in 2-wire interface mode. 3. When using 2-wire mode, we recommend that the LATI2S pin be connected to either DGND or DVSS to prevent the interface from being switched to 3-wire mode by noise.
No. 7236-11/31
LC708728V Functional Description Overview The LC708728V is a high-performance D/A converter designed for digital audio equipment. This IC is optimal for DVD players, AV receivers, and other high-end audio equipment. The LC708728V is a 2-channel high-performance stereo D/A converter that integrates digital interpolation filters, a multibit circuit, and smoothing filters in the output stage on the same chip. In addition to including an electronic volume control, the LC708728V also supports a variety of digital input signal formats and can be controlled over either a 2-wire or 3-wire microcontroller control interface. This microcontroller control interface can use the control signals from industry standard microcontrollers, DSPs, and other devices directly. The LC708728V is controlled either by hardware control (pin level settings) or software control (control over a 2-wire or 3-wire serial interface). The MODE pin (pin 16) sets the control mode. The software interface can operate asynchronously with the audio data interface. In this case, the control data is synchronized within the IC with the processing of audio data. The master clock frequency can be selected from 256, 384, 512, and 768 fs. The sampling rate is selected automatically in hardware mode, but can be controlled from the microprocessor in software mode. If an appropriate system clock is supplied, applications can select sampling rates from under 8 ks/s to 96 ks/s. If the master clock is set to either 128 or 192 fs, a sampling rate of 192 ks/s may be selected. The LC708728V supports right justified, left justified, I2S, and an extremely flexible DSP serial port interface as audio data interfaces. In hardware mode, the serial control interface pins are used to select the input data format. In this case, applications can set the input format type (I2S or right justified), the input word length (20 or 24 bits), and deemphasis function. A 64 fs data clock and independent bit streams for each of the left and right channels must be input in DSD mode. The bit stream data is input to the DIN and LRCIN pins, and that data is supplied to the internal D/A converters. In hardware mode, the SCKDSD pin (pin 19) input level controls switching between normal mode and DSD mode. See figure 4 for details. Additionally, DSD mode supports phase modulation. Since in this method most of the audio spectral energy is removed from the data stream by supplying the audio data as a Manchester encoded bit stream, the digital signal corruption that occurs during analog output can be held to a minimum. The input data is sampled with a double-speed clock (BCKIN) to make it easier to demodulate the phase modulated data. See figure 5 for details. This device is supplied in a miniature 20-pin SSOP package. Clock Supply In typical digital audio systems, there is only one clock system that is used to generate the reference clock that synchronizes all audio data processing. This clock is usually called the master clock. In the LC708728V, a master clock generated externally to the IC is directly supplied to the MCLK input pin, and no software settings are required to select the sampling rate. In this IC, MCLK is used to drive the D/A converter path. The D/A converter sampling clock, the D/A converter digital filter clock, and the D/A converter digital audio interface timing and synchronization system are formed on the D/A converter path. When this IC is included in systems that have multiple signal sources used for reference clocks, the clock source with the lowest jitter must be selected to get the maximum characteristics from the D/A converters. Since this IC only operates in slave mode, the master clock must be supplied from external circuits.
No. 7236-12/31
LC708728V Digital Audio Interface The audio data is sent to the internal D/A converter filters from the digital audio interface. This IC support the five most common audio formats. * Left justified * Right justified * I2S mode * DSP early mode * DSP late mode All of the above formats are MSB first and support 16-, 20-, 24-, and 32-bit word lengths. (However, 32-bit data is not supported in right justified mode.) The data input (DIN) and the L/R clock input (LRCIN) can be sampled on either the rising or falling edge of the bit clock input (BCKIN). In the left justified, right justified, and I2S modes, data is input through the DIN pin. This audio data is time division multiplexed data, and is divided into left and right channel data internally for processing according to the state of the L/R clock input at the LRCIN pin. The LRCIN input is also used as a timing reference that indicates the start or end of the data word. The minimum number of BCKIN cycles per one LRCIN period is twice the selected word length. Inversely, the LRCIN must hold the low or high level for the minimum word count of BCKIN inputs. When this condition is met, an arbitrary mark/space ratio can be used for the LRCIN input. When one LRCIN period consists of 32 BCKIN imputs, this IC automatically invalidates all previous settings and switches to 16-bit mode. When one LRCIN period consists of any value other than 32 BCKIN periods, the preset values are used. In DSP early or late mode, data is input through the DIN pin. This audio data is time division multiplexed data, and LRCIN is used as a frame synchronization signal to identify the MSB in the first word. The minimum number of BCKIN inputs per one LRCIN period is twice the selected word length. If the position of the rising edge is set accurately, an arbitrary mark/space ratio can be used for the LRCIN input. (See figures 11 and 12.) Left Justified Mode In left justified mode, the MSB is sampled on the first BCKIN rising edge following an LRCIN transition. LRCIN is high during left-channel data word input, and low during right-channel data word input.
1/fs LEFT CHANNEL LRCIN BCKIN DIN
1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n
RIGHT CHANNEL
MSB
LSB
MSB
LSB
Figure 8 Left Justified Mode Timing Chart
No. 7236-13/31
LC708728V Right Justified Mode In right justified mode, the LSB is sampled on the BCKIN rising edge that precedes the LRCIN transition. LRCIN is high for the left data word and low for the right data word.
1/fs LEFT CHANNEL LRCIN BCKIN DIN
1 2 3 n 1 2 3 n
RIGHT CHANNEL
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Figure 9 Right Justified Mode Timing Chart
I2S Mode In I2S mode, the MSB is sampled on the second BCKIN rising edge following the LRCIN transition. LRCIN is low for the left data word and high for the right data word.
1/fs LEFT CHANNEL LRCIN BCKIN
1 BCKIN 1 BCKIN 3 n-2 n-1 n 1 2 3 n-2 n-1 n 1 2
RIGHT CHANNEL
DIN
MSB
LSB
MSB
LSB
Figure 10 I2S Mode Timing Chart
DSP Early Mode In DSP early mode, the first bit is sampled on the BCKIN rising edge that follows the BCKIN on which the LRCIN low to high transition was detected. BCKIN edges are not allowed between data words. The word order is left channel first, right channel second.
1 BCKIN
1/fs
1 BCKIN
LRCIN BCKIN
LEFT CHANNEL RIGHT CHANNEL
1 2 n-1 n
NO VALID DATA
DIN
1 MSB
2
n-1 n LSB
Input Word Length (IWL)
Figure 11 DSP Early Mode Timing Chart
No. 7236-14/31
LC708728V DSP Late Mode In DSP late mode, the first bit is sampled on the BCKIN rising edge on which the LRCIN low to high transition was detected. BCKIN edges are not allowed between data words. The word order is left channel first, right channel second.
1/fs
LRCIN BCKIN
LEFT CHANNEL RIGHT CHANNEL
1 2 n-1 n
NO VALID DATA
1
DIN
1 MSB
2
n-1 n LSB
Input Word Length (IWL)
Figure 12 DSP Late Mode Timing Chart Audio Data Sampling Rate The LC708728V master clock supports audio sampling rates from 128 to 768 fs. Here, fs is the audio data sampling rate (LRCIN), and is one of 32, 44.1, 48, 96, or 128 kHz. In this IC, the internal digital filter and noise shaper circuits are operated using the master clock. This IC includes a master clock detection circuit that automatically detects the relationship between the master clock frequency and the sampling rate. Although this detection circuit automatically corrects if the error is within 32 clock cycles, if an error of over 32 clock cycles occurs, D/A converter operation is stopped and the output is muted automatically. We recommend that the master clock be synchronized with LRCIN. Also note that phase differences and jitter with respect to this clock are allowed. See table 1 for details.
Sampling rate (LRCIN) 32 kHz 44.1 kHz 48 kHz 96 kHz 192 kHz 128 fs 4.096 5.6448 6.114 12.288 24.576 192 fs 6.144 8.467 9.216 18.432 36.864
Master clock frequency (MHz) (MCLK) 256 fs 8.192 11.2896 12.288 24.576 None 384 fs 12.288 16.9340 18.432 36.864 None 512 fs 16.384 22.5792 24.576 None None 768 fs 24.576 33.8688 36.864 None None
Table 1 Master Clock Frequency vs. Sampling Rate
Hardware DSD Mode DSD mode is set up by setting the MODE pin low and the SCKDSD pin high. In this mode, the built-in digital filters are bypassed and the bit stream data is supplied to the D/A converters directly. The data converted by the D/A converters passes through internal low-pass filters and is then output. See figures 27 to 30 for details. Two data transfer formats are supported: monophase and biphase. In monophase mode, the DSD data is directly sampled after the rising edge of the 64fs MCLK signal. In biphase mode, data is supplied in a Manchester encoded format. In Manchester encoding, a bit transition occurs at every data bit. As a result, corruption of the analog output due to spectral energy is held to an absolute minimum. Based on a 128 fs clock signal input to the BCKIN pin, data is sampled on the BCKIN signal falling edge when MCLK is low. See figures 4 and 5 for details.
No. 7236-15/31
LC708728V
Hardware Control Mode The LC708728V operates in hardware mode when the MODE pin is set to the low level. Muting and Auto-Mute Operation Muting operation can be controlled directly by supplying an input to the MUTEB pin (pin 17) in either operating mode, hardware mode or software mode. The auto-mute function is also controlled with this pin. Normally, the MUTEB pin is an active-low input. However, when this pin is set to the open state (floating), it becomes an output pin and functions as an infinite zero detection pin. See table 2 for details. See the description of the ZERO pin (pin 5) for more information.
MUTEB pin 0 1 State The D/A converter outputs are muted. Normal operation IZD (auto-mute) mode. The MUTEB pin functions as the IZD state indicator flag. Open (floating) Low output: IZD detected High output: IZD not detected
Table 2 Muting and Auto-Mute Control
Figure 13 presents an overview of the start and stop of muting operation (48 kHz, full-scale sine wave). The upper signal is the D/A converter output level and the lower signal is the input to the MUTE pin. When muting is turned on, the D/A converter output starts to decay geometrically from the input sample DC level at the point muting started. The attenuation progresses so that the output level reaches the VMID level after 64 sample periods. When the muting is turned off, the output is restarted immediately from the sampled data at the point the muting is turned off.
0
0.001
0.002
0.003 Time(s)
0.004
0.005
0.006
Figure 13 Soft Muting Start and Stop Overview
No. 7236-16/31
LC708728V The auto-mute function monitors both the left and right channels to determine whether or not a zero level has been input for a period of 1024 samples. If the zero level continues for over 1024 in both the left and right channels, the auto-mute function activates and sets the IC internal AUTOMUTED flag to the active state. Since this flag is wired to the MUTEB pin through a 10 k resistor, the auto-mute function will be enabled if the MUTEB pin is open (floating). When the MUTEB pin is set to the high level, the auto-mute function is disabled. As a result, unless the IZD register bit is set in software, the mute function will not be turned on. When the MUTEB pin is used as an I/O pin (the case where it can be set to any of the high, low, and floating states), it is possible to both control the muting operation directly with an input to this pin and use the auto-mute function as well. When the MUTEB pin is set to the open (floating) state, the application can monitor the AUTOMUTED output. This allows the muting of the whole system that this IC is part of to be controlled by monitoring the state of this pin. Figure 14 shows the internal equivalent circuit for the MUTEB pin.
IZD (register bit) AUTOMUTED (internal signal) 10 k
MUTEB pin
SOFTMUTE (internal signal)
MUT (register bit)
Figure 14 MUTEB Pin Internal Equivalent Circuit
Input Format Selection In hardware control mode, the input data format is set with the LATI2S (pin 20) and CSBIWL (pin 15) pins. See table 3 for details.
LATI2S 0 0 1 1 CSBIWL 0 1 0 1 Input data mode 24-bit, right justified 20-bit, right justified 16-bit, I2S mode 24-bit, I2S mode
Table 3 Input Data Format Selection Note: In 24-bit I2S mode, if there are both high and low periods in the input to the LRCIN pin that last for over 24 cycles of the BCKIN clock, the IC will support data formats with an arbitrary bit width up to 24 bits. If the LRCIN period is exactly 32 cycles of the CBKIN clock, this IC automatically sets up 16-bit data mode.
No. 7236-17/31
LC708728V Deemphasis Control In hardware control mode, deemphasis is controlled using the SDIDEM pin (pin 18). See table 4 for details.
SDIDEM 0 1 Deemphasis Off On
Table 4 Deemphasis Control Software Control Interface This IC can be set up and controlled over either a 2-wire or a 3-wire (SPI compatible) software interface. Control Mode Setting This IC's operating mode can be set to either hardware control mode or software control mode. The MODE pin is used to set the control mode.
Mode 0 1 Control mode Hardware control mode Software control mode
Table 5 Control Mode Selection Three-Wire Control Mode (SPI Compatible) In this mode, the IC is controlled using three pins: SDIDEM, SCKDSD, and LATI2S. The program data is input to the SDIDEM pin, the program data latching clock signal is input to the SCKDSD pin, and the external signal that latches the whole program data word is applied to the LATI2S pin. Figure 14 presents an overview of the SDIDEM, SCKDSD, and LATI2S signal timing.
2
LATI S SCKDSD
SDIDEM
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Figure 15 Three-Wire Control Mode Timing Overview Notes: 1. B[15:9] are the control address bits. 2. B[8:0] are the control data bits. 3. The CSBIWL pin must be held at the low level when data is written. (See figure 6.)
No. 7236-18/31
LC708728V
Two-Wire Control Mode In this mode, the IC is controlled using two pins: SDIDEM and SCKDSD. The program data is input to the SDIDEM pin and external the program data latching clock signal is input to the SCKDSD pin. Figure 16 presents an overview of the timing. This IC has the address 001101X (binary), which indicates that it is an audio device. Of these bits, the value of the last address bit (shown as an X) depends on the input to the CSBIWL pin. The CSBIWL pin must be connected to either DVDD or DVSS. In 2-wire control mode, two LC708728V chips in the same system can be controlled referencing this addresss and using by the same control signal by setting the CSBIWL pin low on one chip and high on the other. Since the LATI2S pin is not used in 2-wire control mode, it must be connected to either DVDD or DVSS. Note that if the input level on the LATI2S pin goes from low to high or high to low during a control operation in 2-wire mode, the operating mode will switch to 3-wire mode. If the LC708728V switches from 2-wire control mode to 3-wire control mode, it will not return to 2-wire mode unless the MODE pin input is changed or power to the device is turned off.
SDIDEM SCKDSD START
R ADDR
R/W
ACK
DATA B15-8
ACK
DATA B7-0
ACK
STOP
Figure 16 Two-Wire Control Mode Timing Overview
Register Map The LC708728V includes four 16-bit program registers. Data is transferred to these register by inputting that data from the SDIMEM pin in either 2-wire control mode or 3-wire control mode.
B15 M0 M1 M2 M3 0 0 0 0 B14 0 0 0 0 B13 0 0 0 0 B12 0 0 0 0 Address B11 0 0 0 0 B10 0 0 1 1 B9 0 1 0 1 B8 UPDATEL UPDATAR 0 IZD B7 LAT7 RAT7 0 0 B6 LAT6 RAT6 0 0 B5 LAT5 RAT5 IW2 BCP B4 LAT4 RAT4 IW1 REV Data B3 LAT3 RAT3 IW0 0 B2 LAT2 RAT2 B1 LAT1 RAT1 B0 LAT0 RAT0 MUT I2S
PWDN DEEMPH ATC LRP
Table 6 Program Register Mapping
No. 7236-19/31
LC708728V
Register address (A3, A2, A1, A0) 0000 DACL attenuation Bits [7:0] 8 Symbol LAT [7:0] UPDATEL Default 11111111 (0 dB) 0 Description Left channel attenuation data for the 0.5 dB step attenuator. See table 9. Left channel attenuator load control 0: Save DACL in an intermediate register. (The output does not change.) 1: Save DACL and update the attenuation in both channels. 0001 DACR attenuation [7:0] 8 RAT [7:0] UPDATER 11111111 (0 dB) 0 Right channel attenuation data for the 0.5 dB step attenuator. See table 9. Right channel attenuator load control 0: Save DACL in an intermediate register. (The output does not change.) 1: Save DACL and update the attenuation in both channels. 0010 D/A converter control 0 MUT 0 Soft muting control 0: Muting off 1: Muting on 1 DEEMPH 0 Deemphasis control 0: Deemphasis off 1: Deemphasis on 2 PWDN 0 Low power mode control 0: Normal operation. The output is active. 1: Low power mode. The output is muted. [5:3] 0011 Interface control 0 1 IW [2:0] I2S LRP 0 0 0 Audio data format selection. See table 14. Audio data format selection. See table 14. LRCIN/DSP mode selection 0: LRCIN normal/DSP late mode 1: LRCIN inverted/DSP early mode 2 ATC 0 Attenuator control 0: Use the set attenuations for the left and right channels. 1: Use the left channel attenuation data for the right channel. 4 5 REV BCP 0 0 Output phase inversion BCKIN polarity 0: Normal 1: Inverted 8 IZD 0 IZD and auto-mute control 0: IZD function disabled 1: IZD function enabled
Table 7 Register Bit Allocations
No. 7236-20/31
LC708728V Attenuation Control Both the left and right channels provide digital attenuation control in the signal path prior to conversion to analog by the A/D converter. While the default attenuation is 0 dB, the level can be controlled over the range 0 dB to 127.5 dB in 0.5 dB steps with the 8-bit attenuation control register. The attenuation control registers have a dual structure so that after the left and right channel attenuation values are set in the corresponding registers, the left and right outputs can be set to the modified values with the same timing. Attenuation values set in advance can be reflected in the output by controlling the UPDATE bit in each of these registers. See table 8 for details.
Register address 0000 D/A converter left channel attenuation control 8 UPDATEL 0 Bits [7:0] Symbol LAT [7:0] Default 11111111 (0 dB) Description D/A converter left channel attenuation data In 0.5 dB steps Attenuation data load control 0: The value of LAT[7:0] is transferred to an internal register. (The output does not change) 1: The left channel attenuation value is changed to that of the internal register, and the left and right channel attenuation values are both changed. (The output value changes.) 0001 D/A converter right channel attenuation control 8 UPDATER 0 [7:0] RAT [7:0] 11111111 (0 dB) D/A converter right channel attenuation data In 0.5 dB steps Attenuation data load control 0: The value of RAT[7:0] is transferred to an internal register. (The output does not change.) 1: The right channel attenuation value is changed to that of the internal register, and the left and right channel attenuation values are both changed. (The output value changes.)
Table 8 Attenuation Control Register Map
Notes: 1. The UPDATE bits are not latched internally. As a result, when the UPDATEL (or UPDATER) bit is 0, the set attenuation value is transferred to the internal register, but is not reflected in the D/A converter output. However, when UPDATEL (or UPDATER) is set to 1, either the internal register value or the value written to LAT (or RAT)[7:0] when the UPDATE bit was set is reflected in the output starting with the next input sample after the UPDATE bit was set. 2. Changing the attenuation value rapidly or over a large level can result in "zipper" noise appearing in the output. Therefore, care is required when changing the attenuation value. Output Attenuation The left and right channel attenuation is controlled using the values set in the LAT and RAT registers. Table 9 shows the correspondence between the attenuation setting value and the actual attenuation level.
XAT [7:0] 00 (hex) 01 (hex) : : : FE (hex) FF (hex)
Attenuation level - dB (mute) -127.5 dB : : : -0.5 dB 0 dB
Table 9 Attenuation Control Levels
No. 7236-21/31
LC708728V Mute Mode (Software Mute) The software muting function is controlled by setting the MUT register.
Register address 0010 D/A converter control Bit 0 Symbol MUT Default value 0 Soft muting selection 0: Normal operation 1: Soft muting enabled (both left and right channels) Description
Table 10 Software Mute Control
De-Emphasis Mode The deemphasis function is controlled by setting the DEEMPH register.
Register address 0010 D/A converter control Bit 1 Symbol DEEMPH Default value 0 Deemphasis mode selection 0: Deemphasis off 1: Deemphasis on Description
Table 11 Deemphasis Setting
Power Down Mode The power down mode is controlled by setting the PWDN register. In power down mode, the left and right channel D/A converter outputs are set to the VMID level and the IC internal operations transits to a power down operating mode. Note that when the IC switches to power down mode, all previously input audio data and control register values are cleared. When returning to normal operation from power down mode, the first 16 samples of the audio data input after returning to normal mode are ignored to initialize the internal FIR filters.
Register address 0010 D/A converter control Bit 2 Symbol PWDN Default value 0 Power down mode selection 0: Normal operation 1: Power down mode Description
Table 12 Power Down Mode Control
Digital Audio Interface Control Register The LC708728V features a digital audio interface that is an expanded version of the digital audio interface provided by the Wolfson Microelectronics WM8716. The digital audio input format is set using the IWL[2:0] bits in the M2 register and the I2S bit in the M3 register.
Register address 0010 D/A converter control 0011 Interface control 0 Bit 5:3 Symbol IWL [2:0] I2S 0 Input data format selection Default value 000000 Input data format selection Description
Table 13 Digital Audio Input Data Format Selection
No. 7236-22/31
LC708728V
IW2 0 0 0 0 0 0 0 0 1 1 1 1 1 I2S 0 0 0 0 1 1 1 1 0 0 0 0 1 IWL1 0 0 1 1 0 0 1 1 0 0 1 1 0 IWL0 0 1 0 1 0 1 0 1 0 1 0 1 0 Digital audio data input format (*) 16 bits Right justified mode 20 bits Right justified mode 24 bits Right justified mode 24 bits Left justified mode 16 bits I2S mode 24 bits I2S mode 20 bits I2S mode 20 bits Left justified mode 16 bits DSP mode 20 bits DSP mode 24 bits DSP mode 32 bits DSP mode 16 bits Left justified mode
Table 14 Digital Audio Data Input Format Settings *: In all of the above modes, the input data is signed two's complement data. Also, only 24-bit data is input to the digital filters. When the data format is either 16 or 20 bits, zeros are automatically inserted in the unused bits in the low order end of the word. When a 32-bit data format is used, the lower 8 bits of the data are handled as being 0. LRCIN (Left/right clock) Polarity selection In left justified, right justified, and I2S mode, the polarity of the L/R clock input to the LRCIN pin is controlled by the LRP register setting. When this bit is set to 1, the LRCIN polarity is set to the opposite state of that shown in figures 8, 9, and 10. While the left and right channel signals can be swapped by using this function, note that using this function results in the occurrence of a 1-sample phase difference.
Register address 0011 Interface control
Bit 1
Symbol LRP
Default value 0 LRCIN polarity setting 0: Normal operation 1: Left and right channels swapped
Description
Table 15 LRCIN Polarity Selection
Also note that this bit is used to switch between early and late modes in DSP mode. (See figures 11 and 12.)
Register address 0011 Interface control
Bit 1
Symbol LRP
Default value 0 DSP mode format setting 0: DSP late mode 1: DSP early mode
Description
Table 16 Input Format Control in DSP Mode
In DSP early mode, data sampling starts from the second BCKIN rising edge counted from the LRCIN rising edge. In contrast, data sampling starts from the BCKIN rising edge immediately after the LRCIN rising edge in DSP late mode. BCKIN edges are not allowed between words in either of these modes. Note that the order of the data is left channel first, then right channel.
No. 7236-23/31
LC708728V Attenuator Control Mode Control of left and right channel attenuation can be performed with just the left channel attenuation control by setting the ATC register. That is, after the ATC register is set, the left channel attenuation data (the LAT register value) is used as the attenuation data for both the left and right channels. The set value of the ATC register is applied starting with the first audio sample after ATC is set.
Register address 0011 Interface control Bit 2 Symbol ATC Default value 0 Attenuator control mode 0: Normal operation (The RAT value is used for right channel attenuator control.) 1: ATC enabled (The LAT value is used for right channel attenuator control.) Description
Table 17 Attenuator Control Mode Output Phase Inversion Mode The phase of the output signal can be inverted by setting the REV register bit.
Register address 0011 Interface control Bit 4 Symbol REV Default value 0 Analog output phase setting 0: Normal phase 1: Inverted phase Description
Table 18 Output Phase Inversion Mode Control BCKIN Polarity Control Mode Normally, LRCIN and DIN are sampled on the BCKIN rising edge. Thus it is desirable that LRCIN and DIN change value on the BCKIN falling edge. This IC can be used in a system in which LRCIN and DIN change value on the BCKIN rising edge by setting this register. If the BCP register is set to 1, the BCKIN polarity shown in figures 8 to 12 is inverted.
Register address 0011 Interface control
Bit 5
Symbol BCP
Default value 0 BCKIN polarity control
Description
0: Normal phase (Data is latched on the BCKIN rising edge.) 1: Inverted phase (Data is latched on the BCKIN falling edge.)
Table 19 BCKIN Polarity Control Mode
IZD Detection Mode Applications can set whether or not auto-muting is performed when over 1024 samples of 0-valued data are input by setting the IZD register.
Register address 0011 Interface control Bit 8 Symbol IZD Default value 0 Description IZD detection control and auto-mute control 0: IZD detection function disabled (Auto-mute disabled) 1: IZD detection function enabled (Auto-mute enabled)
Table 20 IZD Detection Mode Control
No. 7236-24/31
LC708728V Digital Filter Characteristics
Ratings min typ 0.487 fs 0.05 -60 dB dB max
Parameter Pass band edge Pass band ripple Stop band attenuation
Symbol -3 dB f < 0.444 fs f > 0.555 fs
Test Conditions
Unit
Table 21 Digital Filter Characteristics
D/A Converter and Digital Filter Response
0
0.2 0.15
-20 0.1
Response (dB)
Response (dB)
-40
0.05 0 -0.05 -0.1
-60
-80
-100 -0.15 -120 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3 -0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 17 D/A Converter and Digital Filter Frequency Response - 44.1, 48 and 96 kHz
Figure 18 D/A Converter and Digital Filter Ripple - 44.1, 48 and 96 kHz
0.2 0 0 -20 -0.2
Response (dB)
-40
Response (dB)
-0.4
-60
-0.6
-0.8 -80 -1 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
0
0.2
0.4 0.6 Frequency (Fs)
0.8
1
Figure 19 D/A Converter and Digital Filter Frequency Response - 192 kHz
Figure 20 D/A Converter and Digital Filter Ripple - 192 kHz
No. 7236-25/31
LC708728V Digital Deemphasis Characteristics
0
1 0.5
-2
0
Response (dB)
-4
Response (dB)
-0.5 -1 -1.5 -2
-6
-8
-2.5
-10 0 2 4 6 8 10 Frequency (kHz) 12 14 16
-3 0 2 4 6 8 10 Frequency (kHz) 12 14 16
Figure 21 Deemphasis Frequency Response (32 kHz)
Figure 22 Deemphasis Error (32 kHz)
0
0.4 0.3
-2 0.2
Response (dB)
-4
Response (dB)
0.1 0 -0.1 -0.2
-6
-8 -0.3 -10 0 5 10 Frequency (kHz) 15 20 -0.4 0 5 10 Frequency (kHz) 15 20
Figure 23 Deemphasis Frequency Response (44.1 kHz)
Figure 24 Deemphasis Error (44.1 kHz)
0
1 0.8
-2
0.6 0.4
Response (dB)
-4
Response (dB)
0.2 0 -0.2 -0.4
-6
-8
-0.6 -0.8
-10 0 5 10 15 Frequency (kHz) 20
-1 0 5 10 15 Frequency (kHz) 20
Figure 25 Deemphasis Frequency Response (48 kHz)
Figure 26 Deemphasis Error (48 kHz)
No. 7236-26/31
LC708728V DSD Mode Characteristics
5 0 0 -10 -5 -10
Response (dB)
-20
Response (dB)
0 500 1000 Frequency (kHz) 1500 2000
-15 -20 -25 -30
-30
-40
-50
-35 -40 -45 0 50 100 150 200 250 Frequency (kHz) 300 350 400
-60
Figure 27 DSD Frequency Response - No post filter
Figure 28 DSD Frequency Response - No post filter
0
0
-20 -2
Response (dB)
-40
Response (dB)
-4
-60
-80
-6
-100 -8 -120 0 50 100 150 200 250 Frequency (kHz) 300 350 400 0 10 20 30 Frequency (kHz) 40 50 60
Figure 29 DSD Frequency Response - Fourth-order post filter
Figure 30 DSD Frequency Response - Fourth-order post filter
No. 7236-27/31
LC708728V Application Circuit Example
DVDD 7 + C1 C2 6 DVDD AVDD VREFP DGND AGND VREFN 15 20 CSBIWL LATI2S SCKDSD SDIDEM MUTEB VOUTR 16 MODE 8 + 11 + 1 4 3 2 LRCIN MCLK BCKIN DIN C7 C6 9 10 14 + C3 C4 C5 AVDD
DGND
13 AGND
Software I/F or Hardware control
19 18 17
Software/Hardware control mode select
LC708728V
VOUTL
AC-Coupled VOUTR/L to external LPF
Audio serial data I/F
5
ZERO
VMID
12 + C8 C9
AGND
Notes: 1. AGND and DGND must be connected as close to the LC708728V itself as possible. 2. The C2, C3, C4, and C8 capacitors must be located as close to the LC708728V as possible. 3. We recommend using capacitors with the lowest ESR possible to get the best possible performance from the LC708728V.
Figure 31 Application Circuit Example
Recommended Component Values for the Application Circuit Example
Component C1, C5 C2 to C4 C6, C7 C8 C9 Recommended value 10 F 0.1 F 10 F 0.1 F 10 F DVDD and AVDD/VREFP decoupling DVDD and AVDD/VREFP decoupling Output AC coupling capacitors used to exclude the midrail DC level from the output. VMID pin reference decoupling capacitors Description
Table 22 Recommended Component Values
No. 7236-28/31
LC708728V Application Circuit Example (DSD mode)
DVDD 7 + C1 C2 6 DVDD 15 20 19 18 CSBIWL LATI2S SCKDSD SDIDEM MUTEB VOUTR 16 DGND MODE 8 + C7 11 + 1 4 3 2 LRCIN MCLK BCKIN DIN C6 DVDD AVDD VREFP DGND AGND VREFN 9 10 14 + C3 C4 C5 AVDD
DGND
13 AGND
MUTE Control
17
LC708728V
VOUTL
AC-Coupled VOUTR/L to external LPF
DSD right bitstream DSD bit clock DSD biphase mode clock DSD left bitstream
5
ZERO
VMID
12 + C8 C9
AGND
Notes: 1. AGND and DGND must be connected as close to the LC708728V itself as possible. 2. The C2, C3, C4, and C8 capacitors must be located as close to the LC708728V as possible. 3. We recommend using capacitors with the lowest ESR possible to get the best possible performance from the LC708728V. 4. In monophase DSD mode, the BCKIN pin (pin 3) must be connected to DVDD. In biphase DSD mode, two BCKIN cycles must be applied for every bit input.
Figure 32 DSD Mode Application Circuit Example
Recommended Component Values for the DSD Mode Application Circuit Example
Component C1, C5 C2 to C4 C6, C7 C8 C9 Recommended value 10 F 0.1 F 10 F 0.1 F 10 F DVDD and AVDD decoupling DVDD and AVDD decoupling Output AC coupling capacitors used to exclude the midrail DC level from the output. VMID pin reference decoupling capacitors Description
Table 23 Recommended Component Values
No. 7236-29/31
LC708728V DSD Mode Connection Example
64fs
BCKA
MCLK
SACD playback DSP
DSAR
Right channel data Left channel data
LRCIN
LC708728V
DSAL
DIN
Figure 33 Monophase Mode Connection
BCKA
128fs
BCKIN
BCKD
64fs Right channel data
MCLK
SACD playback DSP
DSAR
LC708728V
LRCIN
Left channel data DSAL DIN
Figure 34 Biphase Mode Connection
* DSD mode is set up by setting the SCKDSD pin high while holding the MODE pin low. * DSD mode can only be used in hardware mode.
Recommended Analog Low Pass Filter for the PCM Data Format (Option)
4.7 k
4.7 k
+VS
_
10 F
51
+
47 k
1.8 k
7.5 k
+
680 pF 1.0 F -VS
Figure 35 Recommended Low Pass Filter (Option)
No. 7236-30/31
LC708728V
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of May, 2004. Specifications and information herein are subject to change without notice. PS No. 7236-31/31

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