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MT88L70 3 Volt Integrated DTMF Receiver
Data Sheet Features
* * * * * * * * * 2.7 - 3.6 volt operation Complete DTMF receiver Low power consumption Internal gain setting amplifier Adjustable guard time Central office quality Power-down mode Inhibit mode Functionally compatible with Zarlink's MT8870D
Ordering Information MT88L70AE MT88L70AS MT88L70AN MT88L70ASR MT88L70ANR MT88L70AE1 MT88L70AN1 MT88L70ANR1 MT88L70AS1 MT88L70ASR1 18 18 20 18 20 18 20 20 18 18 Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin PDIP SOIC SSOP SOIC SSOP PDIP* SSOP* SSOP* SOIC* SOIC* Tubes Tubes Tubes Tape & Tape & Tubes Tubes Tape & Tubes Tape &
August 2005
Reel Reel Reel Reel
* Pb Free Matte Tin -40C to +85C
Applications
* * * * * * Paging systems Repeater systems/mobile radio Credit card systems Remote control Personal computers Telephone answering machine
VDD VSS VRef
Description
The MT88L70 is a complete 3 Volt, DTMF receiver integrating both the bandsplit filter and digital decoder functions. The filter section uses switched capacitor techniques for high and low group filters; the decoder uses digital counting techniques to detect and decode all 16 DTMF tone-pairs into a 4-bit code. External component count is minimized by on chip provision of a differential input amplifier, clock oscillator and latched three-state bus interface.
INH
PWDN
Bias Circuit
VRef Buffer Q1 High Group Filter Dial Tone Filter Low Group Filter Zero Crossing Detectors Digital Detection Algorithm Code Converter and Latch Q2 Q3 Q4
Chip Chip Power Bias IN + IN GS
to all Chip Clocks
St GT
Steering Logic
OSC1
OSC2
St/GT
ESt
STD
TOE
Figure 1 - Functional Block Diagram 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT88L70
Data Sheet
IN+ INGS VRef INH PWDN OSC1 OSC2 VSS
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
VDD St/GT ESt StD Q4 Q3 Q2 Q1 TOE
IN+ INGS VRef INH PWDN NC OSC1 OSC2 VSS
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VDD St/GT ESt StD NC Q4 Q3 Q2 Q1 TOE
18 PIN PDIP/SOIC
20 PIN SSOP
Figure 2 - Pin Connections Pin Description Pin # 18 1 2 3 4 5 6 7 8 9 10 1114 15 20 1 2 3 4 5 6 8 9 10 11 1215 17 Name IN+ INGS VRef INH Non-Inverting Op-Amp (Input). Inverting Op-Amp (Input). Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor. Reference Voltage (Output). Nominally VDD/2 is used to bias inputs at mid-rail (see Figure 5 and Figure 6). Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C and D. This pin input is internally pulled down. Description
PWDN Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This pin input is internally pulled down. OSC1 OSC2 VSS TOE Clock (Input). Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2 completes the internal oscillator circuit. Ground (Input). 0 V typical. Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is pulled up internally.
Q1-Q4 Three State Data (Output). When enabled by TOE, provide the code corresponding to the last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high impedance. StD Delayed Steering (Output).Presents a logic high when a received tone-pair has been registered and the output latch updated; returns to logic low when the voltage on St/GT falls below VTSt. Early Steering (Output). Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low.
16
18
ESt
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Zarlink Semiconductor Inc.
MT88L70
Pin Description Pin # 18 17 20 19 Name St/GT Description
Data Sheet
Steering Input/Guard time (Output) Bidirectional. A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. Positive power supply (Input). +3 V typical. No Connection.
18
20 7, 16
VDD NC
Functional Description
The MT88L70 monolithic DTMF receiver offers small size, low power consumption and high performance, with 3 volt operation. Its architecture consists of a bandsplit filter section, which separates the high and low group tones, followed by a digital counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus. Filter Section Separation of the low-group and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies. The filter section also incorporates notches at 350 and 440 Hz for exceptional dial tone rejection. Each filter output is followed by a single order switched capacitor filter section which smooths the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF signals. Decoder Section Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the detector recognizes the presence of two valid tones (this is referred to as the "signal condition" in some industry specifications) the "Early Steering" (ESt) output will go to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state (see "Steering Circuit"). Steering Circuit Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes vc (see Figure 3) to rise as the capacitor discharges. Provided signal condition is maintained (ESt remains high) for the validation period (tGTP), vc reaches the threshold (VTSt) of the steering logic to register the tone pair, latching its corresponding 4-bit code (see Table 1) into the output latch. At this point the GT output is activated and drives vc to VDD. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the delayed steering output flag (StD) goes high, signalling that a received tone pair has been registered. The contents of the output latch are made available on the 4-bit output bus by raising the three state control input (TOE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (dropout) too short to be considered a valid pause. This facility, together with the capability of selecting
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MT88L70
Data Sheet
the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements.
Digit ANY 1 2 3 4 5 6 7 8 9 0 * # A B C D A B C D
TOE L H H H H H H H H H H H H H H H H H H H H
INH X X X X X X X X X X X X X L L L L H H H H
ESt H H H H H H H H H H H H H H H H H L L L L
Q4 Z 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
Q3 Z 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
Q2 Z 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
Q1 Z 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
undetected, the output code will remain the same as the previous detected code
Table 1 - Functional Decode Table
L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE X = DON`T CARE
Guard Time Adjustment In many situations not requiring selection of tone duration and interdigital pause, the simple steering circuit shown in Figure 3 is applicable. Component values are chosen according to the formula: tREC=tDP+tGTP tID=tDA+tGTA The value of tDP is a device parameter (see Figure 7) and tREC is the minimum signal duration to be recognized by the receiver. A value for C of 0.1 F is recommended for most applications, leaving R to be selected by the designer.
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Zarlink Semiconductor Inc.
MT88L70
VDD
Data Sheet
VDD St/GT ESt R StD MT88L70
C vc
tGTA=(RC)In(VDD/VTSt) tGTP=(RC)In[VDD/(VDD-VTSt)]
Figure 3 - Basic Steering Circuit Different steering arrangements may be used to select independently the guard times for tone present (tGTP) and tone absent (tGTA). This may be necessary to meet system specifications which place both accept and reject limits on both tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity. Increasing tREC improves talk-off performance since it reduces the probability that tones simulated by speech will maintain signal condition long enough to be registered. Alternatively, a relatively short tREC with a long tDO would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figure 4. Power-down and Inhibit Mode A logic high applied to pin 6 (PWDN) will power down the device to minimize the power consumption in a standby mode. It stops the oscillator and the functions of the filters. Inhibit mode is enabled by a logic high input to the pin 5 (INH). It inhibits the detection of tones representing characters A, B, C, and D. The output code will remain the same as the previous detected code (see Table 1).
VDD C1 St/GT
tGTP=(RPC1) In [VDD / (VDD-VTSt)] tGTA=(R1C1) In (VDD / VTSt) RP = (R1R2) / (R1 + R2)
R1 ESt
R2 a) decreasing tGTP; (tGTP < tGTA) tGTP=(R1C1) In [VDD / (VDD-VTSt)]
VDD C1 St/GT
tGTA=(RPC1) In (VDD / VTSt) RP = (R1R2) / (R1 + R2)
R1 ESt
R2 b) decreasing tGTA; (tGTP > tGTA)
Figure 4 - Guard Time Adjustment
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MT88L70
Differential Input Configuration
Data Sheet
The input arrangement of the MT88L70 provides a differential-input operational amplifier as well as a bias source (VRef) which is used to bias the inputs at mid-rail. Provision is made for connection of a feedback resistor to the opamp output (GS) for adjustment of gain. In a single-ended configuration, the input pins are connected as shown in Figure 6 with the op-amp connected for unity gain and VRef biasing the input at 1/2VDD. Figure 5 shows the differential configuration, which permits the adjustment of gain with the feedback resistor R5.
C1
R1
IN+ + IN-
MT88L70
C2
R4 GS R3 R2 R5 VRef
DIFFERNTIAL INPUT AMPLIFIER C1 = C2 = 10 nF All resistors are 1% tolerance. R1 = R4 = R5 = 100 k All capacitors are 5% tolerance. R2 = 60 k, R3, = 37.5 k R2R5 R3 = R2 + R5 R5 VOLTAGE GAIN (AV diff) = R1 INPUT IMPEDANCE (ZINDIFF) = 2 R12 + 1 C
2
Figure 5 - Differential Input Configuration Crystal Oscillator The internal clock circuit is completed with the addition of an external 3.579545 MHz crystal and is connected as shown in Figure 6 (Single-ended Input Configuration).
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Zarlink Semiconductor Inc.
MT88L70
Applications
Data Sheet
A single-ended input configuration is shown in Figure 6. For applications with differential signal inputs the circuit shown in Figure 5 may be used.
VDD C1 DTMF Input R1 IN+ INR2 GS VRef INH PDWN X-tal OSC1 OSC2 VSS MT88L70 VDD St/GT ESt StD Q4 Q3 Q2 Q1 TOE NOTES: R1, R2 = 100 k 1% R3 = 300 k 1% C1,C2 = 100 nF 5% X-tal = 3.579545 MHz 0.1% VDD = 3.0V + 20% / -10% R3 C2
Figure 6 - Single-Ended Input Configuration
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MT88L70
Absolute Maximum Ratings Parameter 1 2 3 4 5 DC Power Supply Voltage Voltage on any pin Current at any pin (other than supply) Storage temperature Package power dissipation Symbol VDD VI II TSTG PD -65 VSS-0.3 Min. Max. 7
Data Sheet
Units V V mA C mW
VDD+0.3 10 +150 500
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Derate above 75 C at 16 mW / C. All leads soldered to board.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated. Parameter 1 2 3 4 DC Power Supply Voltage Operating Temperature Crystal/Clock Frequency Crystal/Clock Freq.Tolerance Sym. VDD TO fc fc Min. 2.7 -40 3.579545 0.1 Typ. 3.0 Max. 3.6 +85 Units V C MHz % Test Conditions
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - VDD = 3.0 V+ 20%/-10%, VSS = 0 V, -40C TO +85C, unless otherwise stated. Characteristics 1 2 3 4 5 6 7 8 9 10
I N P U T S S U P P L Y
Sym. IDDQ IDD PO VIH VIL IIH/IIL ISO ISI RIN VTSt
Min.
Typ. 1 2.0 6
Max. 10 5.5
Units A mA mW V
Test Conditions PWDN=VDD fc=3.579545 MHz VDD = 3.0 V VDD = 3.0 V VIN = VSS or VDD TOE (pin 10) = 0, VDD = 3.0 V INH = VDD, PWDN = VDD, VDD = 3.0 V @ 1 kHz
Standby supply current Operating supply current Power consumption High level input Low level input voltage Input leakage current Pull up (source) current Pull down (sink) current Input impedance (IN+, IN-) Steering threshold voltage
2.1 0.9 0.05 4 15 10 0.465VDD 5 15 40
V A A A M V
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MT88L70
DC Electrical Characteristics - VDD = 3.0 V+ 20%/-10%, VSS = 0 V, -40C TO +85C, unless otherwise stated. Characteristics 11 12 13 14 15 16
O U T P U T S
Data Sheet
Sym. VOL VOH IOL IOH VRef ROR
Min.
Typ.
Max.
VSS+0.03
Units V V mA mA V k
Test Conditions No load No load VOUT = 0.4 V VOUT = 3.6 V, VDD = 3.6 V No load
Low level output voltage High level output voltage Output low (sink) current Output high (source) current VRef output voltage VRef output resistance
VDD-0.03
1.5 1.0
8 3.0 0.512VDD 1
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
Operating Characteristics - VDD = 3.0 V+20%/-10%, VSS = 0 V, -40C TO +85C, unless otherwise stated. Gain Setting Amplifier Characteristics 1 2 3 4 5 Input leakage current Input resistance Input offset voltage Power supply rejection Common mode rejection Sym. IIN RIN VOS PSRR CMRR 50 40 10 25 Min. Typ. Max. 100 Units nA M mV dB dB 1 kHz VSS + 0.75 V VIN VDD-0.75 biased at VRef =1.5 V Test Conditions VSS VIN VDD
6 7 8 9 10 11
DC open loop voltage gain Unity gain bandwidth Output voltage swing Maximum capacitive load (GS) Resistive load (GS) Common mode range
AVOL fC VO CL RL VCM
32 0.30 2.2 100 50 1.5
dB MHz Vpp pF k Vpp No Load Load 100 k to VSS @ GS
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MT88L70
Data Sheet
AC Electrical Characteristics - VDD = 3.0 V +20%/-10%, VSS = 0 V, -40C TO +85C, using Test Circuit shown in Fig. 6. Characteristics 1 Valid input signal levels (each tone of composite signal) Negative twist accept Positive twist accept Frequency deviation accept Frequency deviation reject Third zone tolerance Noise tolerance 1.5% 2 Hz 3.5% -16 -12 dB dB Sym Min. -34 15.4 Typ Max -4.0 489 8 8 Units dBm mVRMS dB dB Notes* 1,2,3,5,6,9 Min @ VDD=3.6 V Max @ VDD=2.7 V 2,3,6,9,12 2,3,6,9,12 2,3,5,9 2,3,5,9 2,3,4,5,9,10 2,3,4,5,7,9,10 2,3,4,5,8,9,11
2 3 4 5 6 7 8
Dial zone tolerance +22 dB Typical figures are at 25 C and are for design aid only: not guaranteed and not subject to production testing.
1. dBm= decibels above or below a reference power of 1 mW into a 600 ohm load. 2. Digit sequence consists of all DTMF tones. 3. Tone duration= 40 ms, tone pause= 40 ms. 4. Signal condition consists of nominal DTMF frequencies. 5. Both tones in composite signal have an equal amplitude. 6. Tone pair is deviated by 1.5% 2 Hz. 7. Bandwidth limited (3 kHz) Gaussian noise. 8. The precise dial tone frequencies are (350 Hz and 440 Hz) 2%. 9. For an error rate of better than 1 in 10,000. 10. Referenced to lowest level frequency component in DTMF signal. 11. Referenced to the minimum valid accept level. 12. Guaranteed by design and characterization.
*NOTES
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Zarlink Semiconductor Inc.
MT88L70
Data Sheet
AC Electrical Characteristics - VDD = 3.0 V+20%/-10%, VSS = 0 V, -40C To +85C, using Test Circuit shown in Figure 6. Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
C L O C K O U T P U T S T I M I N G
Sym. tDP tDA tREC tREC tID tDO tPQ tPStD tQStD tPTE tPTD tPU tPD fC tLHCL tHLCL DCCL CLO
Min. 5 0.5 20
Typ. 11 4
Max. 14 8.5 40 40
Units ms ms ms ms ms ms s s s ns ns ms ms MHz ns ns % pF
Conditions Note 1 Note 1 Note 2 Note 2 Note 2 Note 2 TOE=VDD TOE=VDD TOE=VDD load of 10 k, 50 pF load of 10 k, 50 pF Note 3
Tone present detect time Tone absent detect time Tone duration accept Tone duration reject Interdigit pause accept Interdigit pause reject Propagation delay (St to Q) Propagation delay (St to StD) Output data set up (Q to StD) Propagation delay (TOE to Q ENABLE) Propagation delay (TOE to Q DISABLE) Power-up time Power-down time Crystal/clock frequency Clock input rise time Clock input fall time Clock input duty cycle Capacitive load (OSC2)
20 11 20 5.0 50 130 30 20 3.5759 3.5795 3.5831 110 110 40 50 60 15
P D W N
Ext. clock Ext. clock Ext. clock
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. *NOTES: 1. Used for guard-time calculation purposes only and tested at -4 dBm. 2. These, user adjustable parameters, are not device specifications. The adjustable settings of these minimums and maximums are recommendations based upon network requirements. 3. With valid tone present at input, t PU equals time from PDWN going low until ESt going high.
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MT88L70
D EVENTS A B C E F G
Data Sheet
tREC
Vin
tREC
TONE #n
tID
TONE #n + 1
tDO
TONE #n + 1
tDP
ESt
tDA tGTP tGTA VTSt tPQ
St/GT
tQStD
#n
Q1-Q4
DECODED TONE # (n-1)
HIGH IMPEDANCE
# (n + 1)
tPSrD
StD TOE
tPTD
tPTE
EXPLANATION OF EVENTS A) TONE BURSTS DETECTED, TONE DURATION INVALID, OUTPUTS NOT UPDATED. B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS. C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT VALID TONE. D) OUTPUTS SWITCHED TO HIGH IMPEDANCE STATE. E) TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN OUTPUTS (CURRENTLY HIGH IMPEDANCE). F) ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, OUTPUTS REMAIN LATCHED. G) END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, OUTPUTS REMAIN LATCHED UNTIL NEXT VALID TONE. EXPLANATION OF SYMBOLS Vin DTMF COMPOSITE INPUT SIGNAL. ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES. St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT. Q1-Q 4 4-BIT DECODED TONE OUTPUT. StD DELAYED STEERING OUTPUT. INDICATES THAT VALID FREQUENCIES HAVE BEEN PRESENT/ABSENT FOR THE REQUIRED GUARD TIME THUS CONSTITUTING A VALID SIGNAL. TOE TONE OUTPUT ENABLE (INPUT). A LOW LEVEL SHIFTS Q 1-Q 4 TO ITS HIGH IMPEDANCE STATE. tREC MAXIMUM DTMF SIGNAL DURATION NOT DETECTED AS VALID. tREC MINIMUM DTMF SIGNAL DURATION REQUIRED FOR VALID RECOGNITION. tID MINIMUM TIME BETWEEN VALID DTMF SIGNALS. tDO MAXIMUM ALLOWABLE DROP OUT DURING VALID DTMF SIGNAL. tDP TIME TO DETECT THE PRESENCE OF VALID DTMF SIGNALS. tDA TIME TO DETECT THE ABSENCE OF VALID DTMF SIGNALS. tGTP GUARD TIME, TONE PRESENT. tGTA GUARD TIME, TONE ABSENT.
Figure 7 - Timing Diagram
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