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HY62UF16406C Series
256Kx16bit full CMOS SRAM
Document Title
256K x16 bit 2.7 ~ 3.3V Super Low Power FCMOS Slow SRAM
Revision History
Revision No 00 01 02 History Initial Draft Changed Logo Changed Isb1 values Draft Date Dec.20.2000 Mar.23.2001 Jun.07.2001 Remark Final Final Final
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.02 / Jun.01 Hynix Semiconductor
HY62UF16406C Series
DESCRIPTION
The HY62UF16406C is a high speed, super low power and 4Mbit full CMOS SRAM organized as 256K words by 16bits. The HY62UF16406C uses high performance full CMOS process technology and is designed for high speed and low power circuit technology. It is particularly well-suited for the high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 1.2V.
FEATURES
* Fully static operation and Tri-state output * TTL compatible inputs and outputs * Battery backup -. 1.2V(min) data retention * Standard pin configuration -. 48-ball uBGA
Product No.
Voltage (V)
Speed (ns) 55/70
Operation Current/Icc(mA) 5
HY62UF16406C-I 2.7~3.3 Note 1. I : Industrial 2. Current value is max.
Standby Current(uA) LL SL 15 6
Temperature (C) -40~85
PIN CONNECTION
1 2 /OE /UB 3 A0 A3 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 /CS1 IO2 IO4 IO5 IO6 6 CS2 IO1
ADD INPUT BUFFER
BLOCK DIAGRAM
ROW DECODER SENSE AMP
A B C D E F G H
/LB IO9
I/O1
COLUMN DECODER
IO10 IO11 A5 Vss Vcc IO12 A17 IO13 NC
IO3 Vcc Vss IO7
A17
I/O8 DATA I/O BUFFER
PRE DECODER
MEMORY ARRAY 256K x 16
WRITE DRIVER
I/O9
BLOCK DECODER
IO15 IO14 A14 IO16 NC NC A8 A12 A9
I/O16
/WE IO8 A11 NC
FBGA
/CS1 CS2 /OE /LB /UB /WE
PIN DESCRIPTION
Pin Name /CS1, CS2 /WE /OE /LB /UB
Pin Function Chip Select Write Enable Output Enable Lower Byte Control (I/O1~I/O8) Upper Byte Control (I/O9~I/O16)
Pin Name I/O1~I/O16 A0~A17 Vcc Vss NC
Pin Function Data Inputs/Outputs Address Inputs Power (2.7~3.3V) Ground No Connection
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HY62UF16406C Series
ORDERING INFORMATION
Part No. HY62UF16406C-DM(I) HY62UF16406C-SM(I) Note 1. I : Industrial Speed 55/70 55/70 Power LL-part SL-part Temp. I I Package uBGA uBGA
ABSOLUTE MAXIMUM RATINGS (1)
Symbol VIN, VOUT Vcc TA TSTG PD TSOLDER Parameter Input/Output Voltage Power Supply Operating Temperature Storage Temperature Power Dissipation Ball Soldering Temperature & Time Rating -0.3 to 3.6 -0.3 to 4.6 -40 to 85 -55 to 150 1.0 260 * 10 Unit V V C C W C*sec Remark
HY62UF16406C-I
Note 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and the functional operation of the device under these or any other conditions above those indicated in the operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS1 H X X L L CS2 X L X H H /WE X X X H H /OE X X X H L /LB X X H L X L H L L H L /UB X X H X L H L L H L L Mode Deselected Output Disabled Read I/O Pin I/O1~I/O8 I/O9~I/O16 Hi-Z Hi-Z DOUT Hi-Z DOUT DIN Hi-Z DIN Hi-Z Hi-Z Hi-Z DOUT DOUT Hi-Z DIN DIN Power Standby Active Active
L
H
L
X
Write
Active
Note: 1. H=VIH, L=VIL, X=don't care (VIL or VIH) 2. /UB, /LB(Upper, Lower Byte enable) These active LOW inputs allow individual bytes to be written or read. When /LB is LOW, data is written or read to the lower byte, I/O 1 -I/O 8. When /UB is LOW, data is written or read to the upper byte, I/O 9 -I/O 16.
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HY62UF16406C Series
RECOMMENDED DC OPERATING CONDITION
Symbol Vcc Vss VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 2.7 0 2.2 -0.31. Typ 3.0 0 Max. 3.3 0 Vcc+0.3 0.6 Unit V V V V
Note : 1. Undershoot : VIL = -1.5V for pulse width less than 30ns 2. Undershoot is sampled, not 100% tested.
DC ELECTRICAL CHARACTERISTICS
TA = -40C to 85C Sym Parameter ILI Input Leakage Current ILO Output Leakage Current Test Condition Vss < VIN < Vcc Vss < VOUT < Vcc, /CS1 = VIH or CS2=VIL or /OE = VIH or /WE = VIL or /UB = VIH , /LB = VIH /CS1 = VIL, CS2=VIH, VIN = VIH or VIL, II/O = 0mA /CS1 = VIL, CS2 = VIH, VIN = VIH or VIL, Cycle Time = Min, 100% Duty, II/O = 0mA /CS1 < 0.2V, CS2 > Vcc-0.2V, VIN < 0.2V or VIN > Vcc-0.2V, Cycle Time = 1us, 100% Duty, II/O = 0mA /CS1 = VIH or CS2 = VIL or /UB, /LB = VIH VIN = VIH or VIL /CS1 > Vcc - 0.2V or SL CS2 < Vss + 0.2V or /UB, /LB > Vcc - 0.2V VIN > Vcc - 0.2V or LL VIN < Vss + 0.2V IOL = 2.1mA IOH = -1.0mA Min -1 -1 Typ1. Max 1 1 Unit uA uA
Icc
Operating Power Supply Current
5 50
mA mA
ICC1
Average Operating Current
5
mA
ISB
Standby Current (TTL Input)
0.5 0.2 6
mA uA
ISB1
Standby Current (CMOS Input)
0.2 2.4 -
15 0.4 -
uA V V
VOL VOH
Output Low Output High
Note 1. Typical values are at Vcc = 3.0V TA = 25C 2. Typical values are not 100% tested
CAPACITANCE
(Temp = 25C, f= 1.0MHz) Symbol Parameter CIN Input Capacitance (Add, /CS1,CS2,/LB,/UB, /WE, /OE) COUT Output Capacitance (I/O) Note : These parameters are sampled and not 100% tested Condition VIN = 0V VI/O = 0V Max. 8 10 Unit pF pF
Rev.02 / Jun.01
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HY62UF16406C Series
AC CHARACTERISTICS
TA = -40C to 85C, unless otherwise specified # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Symbol Parameter 55ns Min. Max. 55 10 5 10 0 0 0 10 55 50 50 50 0 45 0 0 25 0 5 55 55 30 55 30 30 30 20 70ns Min. Max. 70 10 5 10 0 0 0 10 70 60 60 60 0 50 0 0 30 0 5 70 70 35 70 30 30 30 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
READ CYCLE tRC Read Cycle Time tAA Address Access Time tACS Chip Select Access Time tOE Output Enable to Output Valid tBA /LB, /UB Access Time tCLZ Chip Select to Output in Low Z tOLZ Output Enable to Output in Low Z tBLZ /LB, /UB Enable to Output in Low Z tCHZ Chip Deselection to Output in High Z tOHZ Out Disable to Output in High Z tBHZ /LB, /UB Disable to Output in High Z tOH Output Hold from Address Change WRITE CYCLE tWC Write Cycle Time tCW Chip Selection to End of Write tAW Address Valid to End of Write tBW /LB, /UB Valid to End of Write tAS Address Set-up Time tWP Write Pulse Width tWR Write Recovery Time tWHZ Write to Output in High Z tDW Data to Write Time Overlap tDH Data Hold from Write Time tOW Output Active from End of Write
AC TEST CONDITIONS
TA = -40C to 85C, unless otherwise specified Parameter Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Level Output Load tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW Others Value 0.4V to 2.2V 5ns 1.5V CL = 5pF + 1TTL Load CL = 30pF + 1TTL Load
AC TEST LOADS
VTM=2.8V
1029 Ohm DOUT CL(1) 1728 Ohm
Note 1. Including jig and scope capacitance:
Rev.02 / Jun.01
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HY62UF16406C Series
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
tRC ADDR tAA tACS /CS1 tOH
CS2 tCHZ(3) tBA /UB ,/ LB tBHZ(3) /OE tOLZ(3) tBLZ(3) Data Valid tOE
tOHZ(3)
Data Out
High-Z
tCLZ(3)
READ CYCLE 2(Note 1,2,4)
tRC ADDR tAA tOH Data Out Previous Data Data Valid tOH
READ CYCLE 3(Note 1,2,4)
/CS1 /UB, /LB
CS2 tACS tCLZ(3) Data Out Data Valid tCHZ(3)
Notes: 1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1 and CS2 are in active status. 2. /OE = VIL 3. Transition is measured + 200mV from steady state voltage. This parameter is sampled and not 100% tested. 4. /CS1 in high for the standby, low for active CS2 in low for the standby, high for active. /UB and /LB in high for the standby, low for active
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HY62UF16406C Series
WRITE CYCLE 1 (1,4,8) (/WE Controlled)
tWC ADDR tWR(2) tCW /CS1
CS2
tAW tBW
/UB,/LB tWP /WE tAS Data In High-Z tWHZ(3,7) Data Out tDW Data Valid tOW (5) (6) tDH
WRITE CYCLE 2 (Note 1,4,8) (/CS1, CS2 Controlled)
tWC ADDR tAS /CS1 tAW CS2 tBW /UB,/LB tWP /WE tDW Data In High-Z Data Valid tDH tCW tWR(2)
Data Out
High-Z
Rev.02 / Jun.01
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HY62UF16406C Series
Notes: 1. A write occurs during the overlap of a low /WE, a low /CS1, a high CS2 and a low /UB and/or /LB . 2. tWR is measured from the earlier of /CS1, /LB, /UB, or /WE going high or CS2 going low to the end of write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied. 4. If the /CS1, /LB and /UB low transition and CS2 high transition occur simultaneously with the /WE low transition or after the /WE transition, outputs remain in a high impedance state. 5. Q(data out) is the same phase with the write data of this write cycle. 6. Q(data out) is the read data of the next address. 7. Transition is measured + 200mV from steady state. This parameter is sampled and not 100% tested. 8. /CS1 in high for the standby, low for active CS2 in low for the standby, high for active. /UB and /LB in high for the standby, low for active
DATA RETENTION ELECTRIC CHARACTERISTIC
TA= -40C to 85C Symbol Parameter Test Condition /CS1 > Vcc - 0.2V or CS2 < Vss + 0.2V or /UB, /LB > Vcc - 0.2V, VIN > Vcc - 0.2V or VIN < Vss + 0.2V Vcc=1.5V, /CS1 > Vcc - 0.2V or CS2 < Vss + 0.2V or /UB, /LB > Vcc - 0.2V VIN > Vcc - 0.2V or VIN < Vss + 0.2V Min Typ1. Max Unit
VDR
Vcc for Data Retention
1.2
-
3.3
V
uA SL 0.1 3 uA LL 0 tRC 0.1 10 ns ns
Iccdr
Data Retention Current
tCDR tR
Chip Deselect to Data Retention Time Operating Recovery Time
See Data Retention Timing Diagram
Notes: 1. Typical values are under the condition of TA = 25C. 2. Typical value are sampled and not 100% tested
Rev.02 / Jun.01
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HY62UF16406C Series
DATA RETENTION TIMING DIAGRAM 1
VCC 2.7V tCDR DATA RETENTION MODE tR
VIH VDR CS1>VCC-0.2V /CS1 VSS
DATA RETENTION TIMING DIAGRAM 2
DATA RETENTION MODE tCDR CS2 VDR tR
VCC 2.7V
0.4V VSS CS2<0.2V
Rev.02 / Jun.01
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HY62UF16406C Series
PACKAGE INFORMATION
48ball Micro Ball Grid Array Package(M)
BOTTOM VIEW
B A A1 CORNER INDEX AREA 6 A A B C D C E F G H C1/2 3.0 X 5.0 MIN FLAT AREA 5 4 3 2 1
TOP VIEW
C1
B1/2
B1
SIDE VIEW
5
C
E1 E2 E SEATING PLANE A 4
r
3 D(DIAMETER)
Symbol A B B1 C C1 D E E1 E2 r
Min. 6.7 8.3 0.3 0.85 0.6 0.2 -
Typ. 0.75 3.75 6.8 5.25 8.4 0.35 0.9 0.65 0.25 -
Max. 6.9 8.5 0.4 0.95 0.7 0.3 0.08
Note 1. DIMENSIONING AND TOLERANCING PER ASME Y14. 5M-1994. 2. ALL DIMENSIONS ARE MILLIMETERS. 3. DIMENSION "D" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE CROWN OF THE SOLDER BALLS. 5. THIS IS A CONTROLLING DIMENSION.
Rev.02 / Jun.01
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HY62UF16406C Series
MARKING INFORMATION
Package
H Y
Marking Example
U F 6 4 0 6 C
uBGA
c
s
s
t
y
w
w
p
x
x
x
x
x
K
O
R
Index
* HYUF6406C *c : Part Name : Power Consumption -D -S : Speed - 55 - 70 *t : Temperature -I : 55ns : 70ns : Industrial ( -40 ~ 85 C )
: Low Low Power : Super Low Power
* ss
*y * ww *p * xxxxx * KOR Note - Capital Letter - Small Letter
: Year (ex : 0 = year 2000, 1= year 2001) : Work Week ( ex : 12 = work week 12 ) : Process Code : Lot No. : Origin Country
: Fixed Item : Non-fixed Item
Rev.02 / Jun.01
10

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