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KM62256C Family
32Kx8 bit Low Power CMOS Static RAM
FEATURES
U U
PRELIMINARY CMOS SRAM
GENERAL DESCRIPTION
The KM62256C family is fabricated by SAMSUNG's advanced CMOS process technology. The family can support various operating temperature ranges and has various package types for user flexibility of system design. The family also support low data retention voltage for battery back-up operation with low data retention current.
U
U
U
U
Process Technology : 0.7- CMOS Organization : 32Kx8 Power Supply Voltage : Single 5V 3/4 10% Low Data Retention Voltage : 2V(Min) Three state output and TTL Compatible Package Type : JEDEC Standard 28-DIP, 28-SOP, 28-TSOP I -Forward/Reverse
PRODUCT FAMILY
Power Dissipation Product Family KM62256CL KM62256CL-L KM62256CLE KM62256CLE-L KM62256CLI KM62256CLI-L
* The parameter is measured with 30pF test load.
Operating Temperature.
Speed (ns)
PKG Type
Standby (ISB1, Max) 100E 20E 100E 50E 100E 50E
Operating (Icc2)
Commercial (0~70E) Extended (-25~85E) Industrial (-40~85E)
45*/55/70ns 70/100ns 70/100ns
28-DIP, 28-SOP 28-TSOP I R/F 28-SOP 28-TSOP I R/F 28-SOP 28-TSOP I R/F
70mA
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
A0~A2, A9~11
OE A11 A9 A8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24
A10 CS I/O8 I/O7
Y-Decoder
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
VCC WE A13 A8 A9 A11 OE A10 CS I/O8 I/O7 I/O6 I/O5 I/O4
X-Decoder
A13 WE VCC A14 A12 A7 A6 A5 A4 A3
I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2
28-TSOP Type I - Forward
23 22 21 20 19 18 17 16 15
A3~A8, A12~14
Cell Array
Control Logic
CS
WE,OE
28-DIP 28-SOP
22 21 20 19 18 17 16 15
I/O1~8
A3 A4 A5 A6 A7 A12 A14 VCC WE A13 A8 A9 A11 OE
14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 16 17 18 19 20
I/O Buffer
A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS A10
28-TSOP Type I - Reverse
NameName
A0~A14 WE CS OE I/O1~I/O8 Vcc Vss
Function
Address Inputs Write Enable Input Chip Select Input Output Enable Input Data Inputs/Outputs Power(5V) Ground
21 22 23 24 25 26 27 28
Revision 3.0 April 1996
KM62256C Family
PRODUCT LIST & ORDERING INFORMATION
PRODUCT LIST
Commercial Temp Product (0~70E) Part Name
KM62256CLP-4 KM62256CLP-4L KM62256CLP-5 KM62256CLP-5L KM62256CLP-7 KM62256CLP-7L KM62256CLG-4 KM62256CLG-4L KM62256CLG-5 KM62256CLG-5L KM62256CLG-7 KM62256CLG-7L KM62256CLTG-4 KM62256CLTG-5 KM62256CLTG-7 KM62256CLRG-4 KM62256CLRG-5 KM62256CLRG-7
PRELIMINARY CMOS SRAM
Extended Temp Products (-25~85E) Part Name
KM62256CLGE-7 KM62256CLGE-7L KM62256CLGE-10 KM62256CLGE-10L KM62256CLTGE-7 KM62256CLTGE-7L KM62256CLTGE-10 KM62256CLRGE-7 KM62256CLRGE-7L KM62256CLRGE-10
Industrial Temp Products (-40~85E) Part Name
KM62256CLGI-7 KM62256CLGI-7L KM62256CLGI-10 KM62256CLGI-10L KM62256CLTGI-7 KM62256CLTGI-7L KM62256CLTGI-10 KM62256CLRGI-7 KM62256CLRGI-7L KM62256CLRGI-10
Function
28-DIP, 45ns, L-pwr 28-DIP, 45ns, LL-pwr 28-DIP, 55ns, L-pwr 28-DIP, 55ns, LL-pwr 28-DIP, 70ns, L-pwr 28-DIP, 70ns, LL-pwr 28-SOP, 45ns, L-pwr 28-SOP, 45ns, LL-pwr 28-SOP, 50ns, L-pwr 28-SOP, 50ns, LL-pwr 28-SOP, 70ns, L-pwr 28-SOP, 70ns, LL-pwr 28-TSOP F, 45ns, L-pwr 28-TSOP F, 55ns, L-pwr 28-TSOP F, 70ns, L-pwr 28-TSOP R, 45ns, L-pwr 28-TSOP R, 55ns, L-pwr 28-TSOP R, 70ns, L-pwr
Function
28-SOP, 70ns, L-pwr 28-SOP, 70ns, LL-pwr 28-SOP, 100ns, L-pwr 28-SOP, 100ns, LL-pwr 28-TSOP F, 70ns, L-pwr 28-TSOP F, 70ns, LL-pwr 28-TSOP F, 100ns, L-pwr 28-TSOP R, 70ns, L-pwr 28-TSOP R, 70ns, LL-pwr 28-TSOP R, 100ns, L-pwr
Function
28-SOP, 70ns, L-pwr 28-SOP, 70ns, LL-pwr 28-SOP, 100ns, L-pwr 28-SOP, 100ns, LL-pwr 28-TSOP F, 70ns, L-pwr 28-TSOP F, 70ns, LL-pwr 28-TSOP F, 100ns, L-pwr 28-TSOP F, 100ns, LL-pwr 28-TSOP R, 70ns, L-pwr 28-TSOP R, 70ns, LL-pwr 28-TSOP R, 100ns, L-pwr 28-TSOP R, 100ns, LL-pwr
KM62256CLTGE-10L 28-TSOP F, 100ns, LL-pwr KM62256CLTGI-10L
KM62256CLRGE-10L 28-TSOP R, 100ns, LL-pwr KM62256CLRGI-10L
KM62256CLTG-4L 28-TSOP F, 45ns, LL-pwr KM62256CLTG-5L 28-TSOP F, 55ns, LL-pwr KM62256CLTG-7L 28-TSOP F, 70ns, LL-pwr KM62256CLRG-4L 28-TSOP R, 45ns, LL-pwr KM62256CLRG-5L 28-TSOP R, 55ns, LL-pwr KM62256CLRG-7L 28-TSOP R, 70ns, LL-pwr
ORDERING INFORMATION
KM6 2 X 256 C X X X - XX X L-Low Low Power, Blank-Low Power or High Power Access Time : 4=45ns, 5=55ns, 7=70ns, 10=100ns Operating temperature : Blank=Commercial, I=Industrial, E=Extended Package Type : G=SOP, P=DIP, TG=TSOP Forward, RG=TSOP Reverse L-Low Power or Low Low Power, Blank-High Power Die Version : C=4th generation Density : 256=256K bit Blank=5V, V=3.0~3.6V, U=2.7~3.3V Organization : 2=x8 SEC Standard SRAM
Revision 3.0 April 1996
KM62256C Family
ABSOLUTE MAXIMUM RATINGS*
Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Symbol VIN,VOUT VCC PD TSTG TA Operating Temperature Ratings -0.5 to VCC+0.5 -0.5 to 7.0 1.0 -65 to 150 0 to 70 -25 to 85 -40 to 85 Soldering temperature and time TSOLDER 260E, 10sec (Lead Only) Unit V V W E E E E -
PRELIMINARY CMOS SRAM
Remark KM62256CL/L-L KM62256CLE/LE-L KM62256CLI/LI-L -
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stres s rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not impl ied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS *
Item Supply voltage Ground Input high voltage Input low voltage Symbol Vcc Vss VIH VIL Min 4.5 0 2.2 -0.5*** Typ** 5.0 0 Max 5.5 0 Vcc+0.5V 0.8 Unit V V V V
* 1) Commercial Product : TA=0 to 70E, unless otherwise specified 2) Extended Product : TA=-25 to 85E, unless otherwise specified 3) Industrial Product : TA=-40 to 85E, unless otherwise specified ** TA=25E *** VIL(min)=-3.0V for A 50ns pulse width
CAPACITANCE* (f=1MHz, TA=25E)
Item Input capacitance Input/Output capacitance
* Capacitance is sampled not 100% tested
Symbol CIN CIO
Test Condition VIN=0V VIO=0V
Min -
Max 6 8
Unit pF pF
Revision 3.0 April 1996
KM62256C Family
DC AND OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Operating power supply current Symbol ILI ILO ICC Test Conditions* Min -1 -1 -
PRELIMINARY CMOS SRAM
Typ** 7 Max 1 1 15*** Unit
VIN=Vss to Vcc
CS=VIH or WE=VIL VIO=Vss to Vcc CS=VIL, VIN=VIH or VIL, IIO=0mA Cycle time=1A 100% duty CSA 0.2V, VILA 0.2V VIN AVcc -0.2V, IIO=0mA Min cycle, 100% duty CS=VIL, IIO=0mA IOL=2.1mA IOH=-1.0mA CS=VIH L(Low Power) LL(L Low Power)
E E
mA
ICC1 Average operating current ICC2 Output low voltage Output high voltage Standby Current(TTL) KM62256CL KM62256CL-L Standby Current (CMOS) KM62256CLE KM62256CLE-L KM62256CLI KM62256CLI-L ISB1 VOL VOH ISB
-
-
7****
mA
2.4 -
2 1 -
70 0.4 1***** 100 20 100 50 100 50
mA V V mA
E E E E E E
CS AVcc-0.2V VINA 0.2V or VIN AVCC-0.2V
L(Low Power) LL(L Low Power) L(Low Power) LL(L Low Power)
* 1) Commercial Product : TA=0 to 70E, Vcc=5V3/410% unless otherwise specified 2) Extended Product : TA=-25 to 85E, Vcc=5V3/410% nless otherwise specified 3) Industrial Product : TA=-40 to 85E, Vcc=5V3/410% unless otherwise specified ** TA=25E *** 20mA for Extended and Industrial Products ****10mA for Extended and Industrial Products *****2mA for Extended and Industrial Products
A.C CHARACTERISTICS
TEST CONDITIONS(1.Test Load and Test Input/Output Reference)*
Item Input pulse level Input rising & falling time input and output reference voltage Output load (See right)
* See DC Operating conditions ** Test load for 45ns commercial products
Value 0.8 to 2.4V 5ns 1.5V CL=100pF+1TTL **CL=30pF+1TTL
Remark * Including scope and jig capacitance
CL*
Revision 3.0 April 1996
KM62256C Family
TEST CONDITIONS(2. Temperature and Vcc Conditions)
Product Family KM62256CL/L-L KM62256CLE/LE-L KM62256CLI/LI-L Temperature 0~70E -25~85E -40~85E Power Supply(Vcc) 5V 3/4 10% 5V 3/4 10% 5V 3/4 10% Speed Bin 45*/55/70ns 70/100ns 70/100ns
PRELIMINARY CMOS SRAM
Comments Commercial Extended Industrial
* The parameter is measured with 30pF test load
PARAMETER LIST FOR EACH SPEED BIN
Speed Bins Parameter List Symbol 45ns* Min Read Read cycle time Address access time Chip select to output Output enable to valid output Chip select to low-Z output Output enable to low-Z output Chip disable to high-Z output Output disable to high-Z output Output hold from address change Write Write cycle time Chip select to end of write Address set-up time Address valid to end of write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z
* The parameter is measured with 30pF test load
55ns Min 55 10 5 0 0 5 55 45 0 45 40 0 0 25 0 5 Max 55 55 25 20 20 20 -
70ns Min 70 10 5 0 0 5 70 60 0 60 50 0 0 30 0 5 Max 70 70 35 30 30 25 -
100ns Min 100 10 5 0 0 5 100 80 0 80 60 0 0 50 0 5 Max 100 100 50 35 35 35 -
Units
Max 45 45 25 20 20 20 -
tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW
45 10 5 0 0 5 45 45 0 45 40 0 0 25 0 5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Revision 3.0 April 1996
KM62256C Family
DATA RETENTION CHARACTERISTICS
Item Vcc for data retention VDR KM62256CL KM62256CL-L Data retention current IDR KM62256CLE KM62256CLE-L KM62256CLI KM62256CLI-L Data retention set-up time Recovery time Vcc=3.0V CSAVcc-0.2V Symbol Test Condition* CSAVcc-0.2V L-Ver LL-Ver L-Ver LL-Ver L-Ver LL-Ver See data retention waveform Min 2.0 0 5
PRELIMINARY CMOS SRAM
Typ** 1 0.5 Max 5.5 50 10 50 25 50 25 ms Unit V
E
tSDR tRDR
* 1) Commercial Product : Ta=0 to 70E, unless otherwise specified 2) Extended Product : TA=-25 to 85E, nless otherwise specified 3) Industrial Product : Ta=-40 to 85E, unless otherwise specified ** TA=25E
DATA RETENTION WAVE FORM
1) CS Controlled
VCC 4.5V
tSDR
Data Retention Mode
tRDR
2.2V VDR CSA VCC - 0.2V CS GND
FUNCTIONAL DESCRIPTION
CS H L L L
* X means don't care
WE X H H L
OE X H L X
Mode Power Down Output Disable Read Write
I/O Pin High-Z High-Z Dout Din
Current Mode ISB ISB1 ICC ICC ICC
Revision 3.0 April 1996
KM62256C Family
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE (1) (Address Controlled)
( CS=OE=VIL, WE=VIH)
PRELIMINARY CMOS SRAM
tRC
Address
tAA tOH
Data Out
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
tRC
Address
tOH tAA tCO
CS
tHZ tOE
OE
tOLZ tOHZ
Data out
High-Z
tLZ
Data Valid
NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to 2. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and from device
output voltage levels. to device.
Revision 3.0 April 1996
KM62256C Family
TIMING WAVEFORM OF WRITE CYCLE(1) Controlled) (WE
tWC
PRELIMINARY CMOS SRAM
Address
tWR(4) tCW(2)
CS
tAW
WE
tAS(3)
tWP(1)
tDW
tDH
Data in
Data Valid
tWHZ
tOW
Data out
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) Controlled) (CS
tWC
Address
tWR(4) tAS(3) tCW(2)
CS
tAW tWP(1)
WE
tDW
tDH
Data in
Data Valid
Data out NOTES (WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins at the latest transition among CS goes low and WE going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
Revision 3.0 April 1996
KM62256C Family
PACKAGE DIMENSIONS
28 PIN DUAL INLINE PACKAGE(600mil)
PRELIMINARY CMOS SRAM
Units :Millimeters(Inches )
+0.10 -0.05 +0.004 0.010-0.002
0.25
#28
#15
13.60 3/4 0.20 0.535 3/4 0.008
#1 36.72 MAX 1.446 36.32 3/4 0.20 1.430 3/4 0.008
#14 3.81 3/4 0.20 0.150 3/4 0.008 5.08 0.200 MAX
15.24 0.600
0~15E
( 1.65 ) 0.065
0.46 3/4 0.10 0.018 3/4 0.004 1.52 3/4 0.10 0.060 3/4 0.004
3.30 3/4 0.30 0.130 3/4 0.012 2.54 0.100 0.38 0.015 MIN
28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil)
0~8E #28 #15
8.38 3/4 0.20 11.81 3/4 0.30 0.465 3/4 0.012 0.330 3/4 0.008
#1 18.69 0.736 MAX 18.29 3/4 0.20 0.720 3/4 0.008
#14 2.59 3/4 0.20 0.102 3/4 0.008 3.00 0.118MAX
11.43 0.450
0.15
+0.10 -0.05 0.006+0.004 -0.05
1.02 3/4 0.20 0.040 3/4 0.008
0.10 MAX 0.004 MAX
(
0.89 ) 0.035
0.41 3/4 0.10 0.016 3/4 0.004
1.27 0.050
0.05 MIN 0.002
Revision 3.0 April 1996
KM62256C Family
PACKAGE DIMENSIONS
28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)
PRELIMINARY CMOS SRAM
Units :Millimeters(Inches )
+0.10 -0.05 +0.004 0.008-0.002
0.20
13.40 3/4 0.20 0.528 3/4 0.008 #28 ( 8.40 0.331 MAX 8.00 0.315 0.425 ) 0.017
#1
0.55 0.0217
#14
#15 1.00 3/4 0.10 0.039 3/4 0.004 1.20 0.047 MAX 0.05 0.002 MIN
28 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0813.4R)
1.10 MAX 0.004 MAX
+0.10 -0.05 +0.004 0.008-0.002
0.20
13.40 3/4 0.20 0.528 3/4 0.008 #15 ( 8.40 0.331 MAX 8.00 0.315 0.425 ) 0.017
#14
0.55 0.0217
#1 0.25 0.010 TYP 11.80 3/4 0.10 0.465 3/4 0.004
#28
+0.10 -0.05 0.006+0.004 -0.002
0.15
1.00 3/4 0.10 0.039 3/4 0.004 1.20 0.047 MAX
0~8E
0.45 ~0.75 0.018 ~0.030
(
0.50 ) 0.020
1.10 MAX 0.004 MAX 0.05 0.002 MIN
Revision 3.0 April 1996

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