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TDA2593
SYNCHRO AND HORIZONTAL DEFLECTION CONTROL FOR COLOR TV SET
. . . . . . . . . . . .
LINE OSCILLATOR (two levels switching) PHASE COMPARISON BETWEEN SYNCHRO-PULSE AND OSCILLATOR VOLTAGE O 1, ENABLED BY AN INTERNAL PULSE, (better parasitic immunity) PHASE COMPARISON BETWEEN THE FLYBACK PULSES AND THE OSCILLATOR VOLTAGE O 2 COINCIDENCE DETECTOR PROVIDING A LARGE HOLD-IN-RANGE FILTER CHARACTERISTICS AND GATE SWITCHING FOR VIDEO RECORDER APPLICATION NOISE GATED SYNCHRO SEPARATOR FRAME PULSE SEPARATOR BLANKING AND SAND CASTLE OUTPUT PULSES HORIZONTAL POWER STAGE PHASE LAGGING CIRCUIT SWITCHING OF CONTROL OUTPUT PULSE WIDTH SEPARATED SUPPLY VOLTAGE OUTPUT STAGE ALLOWING DIRECT DRIVE OF SCR'S CIRCUIT SECURITY CIRCUIT MAKES THE OUTPUT PULSE SUPPRESSED WHEN LOW SUPPLY VOLTAGE
DESCRIPTION The TDA2593 is a circuit intended for the horizontal deflectionof color TV sets, suppliedwith transistors or SCR'S.
DIP16 (Plastic Package) ORDER CODE : TDA2593
PIN CONNECTIONS
SUPPLY VOLTAGE OUTPUT STAGE SUPPLY VOLTAGE OUTPUT PULSE SELECTION OF OUTPUT PULSE DURATION DECOUPLING REFERENCE PULSE (flyback) FOR THE 2nd PHASE COMPARATOR SAND CASTLE PULSE VERTICAL SYNCHRO OUTPUT
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
GROUND ADJUSTMENT OF THE CHARGE CURRENT RAMP OSCILLATOR CAPACITANCE FIRST PHASE COMPARATOR OUTPUT TIME CONSTANT SWITCHING V.C.R. SWITCHING NOISE SEPARATOR INPUT
2593-01.EPS
SYNCHRO SEPARATOR INPUT
September 1993
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TDA2593
MAIN CHARACTERISTICS
Symbol V(1-16) I(1) INPUT SIGNALS V(9-16) (pp) V(10-16) (pp) V(4-16) V(4-16) V(4-16) Synchro Separator Input Voltage Noise Separators Input Voltage Control Voltage of the Output Pulse Switching Circuit t = 7 s (thyristor) t = 14 s + td (transistor) t = 0 (V(3-16) = 0) 3 to 4 3 to 4 9.4 to V(1-16) 0 to 3.5 5.4 to 5.6 V V V V V Supply Voltage Supply Current Parameter Typ. 12 30 Unit V mA
OUTPUT SIGNALS V(7-16) (pp) V(3-16) (pp) Sandcastle Pulse Horizontal Driver Stage Control Pulse 11 10.5 V V
2593-01.TBL 2593-03.TBL 2593-02.TBL
V(8-16) (pp)
Frame Synchro Pulse
11
V
ABSOLUTE MAXIMUM RATINGS (Maximum Ratings according to CEI 134 Datasheet)
Symbol V(1-16) V(2-16) V(4-16) V(9-16) V(10-16) V(11-16) I2M = -I3M I2M = I3M I(4) I(6) I(7) I(11) Ptot Toper Tstg Supply Voltage to Pin 1 Supply Voltage to Pin 2 Voltage to Pin 4 Voltage to Pin 9 Voltage to Pin 10 Voltage to Pin 11 Current ai Pins 2 and 3 (with thyristor) Current ai Pins 2 and 3 (with transistor) Current to Pin 4 Current to Pin 6 Current to Pin 7 Current to Pin 11 Power Dissipation Operating Ambient Temperature Storage Temperature Parameter Value 13.2 18 13.2 6 6 13.2 650 400 1 10 -10 2 800 -20, +70 -25, +125 Unit V V V V V V mA mA mA mA mA mA mW
o o
C C
ELECTRICAL OPERATING CHARACTERISTICS (Tamb = 25oC, V1-V16 = 12V , unless otherwise specified)
Symbol Parameter Input Signals Synchro Separator (Pin 9) Input Threshold Voltage Input Threshold Current On-state Input Current Disconnect Input Current Off-state Input Current (V9-16 = - 5V) Video Input Signal (positive synchro pulses) (note 1) Noise Separator (Pin 10) Input Threshold Voltage Min. Typ. Max. Unit
V9-16 I9 I9 I9 I9 V9 V10-16
0.8 5 100 5 to 100 150 -1 3 to 4 1.4
V A A A A VPP V
Note : 1. Allowed range 1 to 7V
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TDA2593
ELECTRICAL OPERATING CHARACTERISTICS (Tamb = 25oC, V1-V16 = 12V , unless otherwise specified)
Symbol I10 I10 I10 V10 V10 V6-16 V6 I6 V4-16 Parameter Input Threshold Current Input Current Off-state Input Current (V10-16 = - 5V) Video Input Signal (positive synchro pulses) (note 1) Allowed superimposed parasitic signal Fly-back Pulse (Pin 6) Input Threshold Voltage Input Limitation Level Input Current Output Pulse Width Control Switch (Pin 4) Input Voltage t = 7 s (thyristor) t = 14 s + td (transistor) t = 0 (V3-16 = 0) (note 2) Input Current t = 7 s (thyristor) t = 14 s + tj (transistor) t = 0 (V3-16 = 0) Video Recorder Switch (Pin 11) Input Voltage (Pin 11 low level) (Pin 11 to + VCC) Input Current (Pin 11 low level) (Pin 11 to + VCC) Output Signals Frame Synchro Pulses (positive) (Pin 8) Output Voltage (peak value) Output Impedance Delay Between Leading Edge of Input Signal and Leading Edge of Output Signal Delay Between Trailing Edge of Input Signal and Trailing Edge of Output Signal Output Voltage (peak valve) Output Impedance Output Current During Trailing Edge Sandcastle Pulse Width (V7 = 7 V) Phase Between Middle Input Synchro Pulse and Leading Edge of Sandcastle Pulse (V7 = 7 V) Output Voltage (peak value) Output Impedance Output Current During Trailing Edge Output Voltage (peak value) Output Impedance (leading edge) (trailing edge) Control Pulse Width V4 = 9.4 to V1-16 V4 = 0 to 4V (note 3) Control pulse is disabled for Min. 100 Typ. 150 5 to 100 3 to 4 7 1.4 -0.7 and +1.4 1 9.4 to V1-16 0 to 3.5 5.4 to 6.6 200 200 0 0 to 2.5 9 to V1-16 200 2 Max. Unit A A A VPP V V V mA V V V A A A V V A mA
-1
0.01
2
I(4)
V11-16 I11
V8-16 R8 ton toff
10
11 2 15 15
V k s s
SANDCASTLE PULSE (POSITIVE) (PIN 7) V7-16 R7 I7 t7 t 10 11 70 2 4.3 3.15 V mA s s
3.7 2.15
FLY-BACK BLANKING PULSE (PIN 7) V7-16 R7 I7 V3-16 R3 t3 t3 V1-16 4 70 2 10.5 2.5 20 5.5 14 + tc 4 8.5 5 V mA V s s V
CONTROL PULSE FOR HORIZONTAL DRIVER (POSITIVE) (PIN 3)
Notes : 1. Allowed range 1 to 7V 2. Or Pin 4 not connected. 3. With tr = 12s
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2593-04.TBL
TDA2593
ELECTRICAL OPERATING CHARACTERISTICS (contined) (Tamb = 25oC, V1-V16 = 12V , unless otherwise specified)
Symbol OVERALL PHASE RELATION SHIP tz I/t V14-16 I14 f f f/15 f f/f V/V nom. f T V13-16 I13 I13 R13 Phrase Between Middle Synchro Pulse and Middle Fly-back Pulse (tr = 12 s, note 4 Sensitivity to Current Adjust Threshold Voltage (low level) (high level) 1.9 30 4.4 7.6 0.47 15625 5 31 10 0.05 10 10 3.8 to 8.2 1.9 to 2.3 -1 High Low 2 780 10 5.4 to 7.6 1 -5 High 8 15 0.2 0.5 to 6 0.1 - 0.5 6 1 100 60 7.5
-4
Parameter
Min.
Typ.
Max. 3.3
Unit s A/s V V mA Hz % Hz/A % % % Hz/C V mA A
OSCILLATOR (PINS 14 AND 15)
Current Generator Free Running Frequency (Cosc = 4700pF, Rosc = 12k) Tolerance on Frequency (note 5) Frequence Control Sensitivity Spread of Frequency nfluence of Supply Voltage on Frequency (note 5) Frequency change when decreasing the supply down to 5 V (V1-16 = 5V, note 5) Frequency Temperature Coefficient (note 5) Control Voltage Range Control Current (peak value) Off-state Current (V 13-16 = 4 to 8 V) Output Impedance (V13-16 = 4 to 8 V, note 6) (V13-16 < 3.8 V cr > 8.2 V, note 7) Control Sensibility Catching and Holding Range Catching and Holding Range Tolerance (note 5) Control Voltage Range Control Current (peak value) Off-state Output Current (V 5-16 = 5.4 to 7.6 V) Output Impedance (V5-16 = 5.4 to 7.6 V, note 6) (V5-16 < 5.4 V or > 7.6 V) Max. delay Between Output Pulse Leading Edge and Fly-back Pulse Trailing Edge (tr = 12 s) Static Control Error Output Voltage Output Current
PHASE COMPARATOR o 1 (PIN 13)
f f/f V5-16 I5 I5 R5 td t/td V11-16 I11
kHz/s Hz % V mA A k s % V mA mA V mA k s
2593-05.TBL
PHASE COMPARATOR 2 AND PHASE-SHIFT (PIN 5)
COINCIDENCE DETECTOR (PIN 11) (without coincidence) (with coincidence)
TIME CONSTANT SWITCH (PIN 12) V12-16 I12 R12 Output Voltage Output Current Output Impedance
(V11-16 = 2.5 to 7 V) (V11-16 < 1.5 or > 9 V)
PULSE GENERATOR (INTERNAL) t Pulse Width
Notes : 4. The adjustement of overall phase relation (and output pulse leading edge position) is automatically performed by phase comparator O 2. If additional adjustement is needed, a current have to be imposed at pin 5. 5. Tolerance of peripheral components not included. 6. Current generator. 7. Emitter-follower
4/6
Frame Synchro Output Pulse 11V
Blanking and Sandcastle Output Pulse 10V
Flyback Pulse
Pulse width
A Tc Line Driver 6V +12V PLL1 : Phase locked loop 1 PLL2 : Phase locked loop 2 (with power stage)
7s
50V
0 14s 12 (15 )
4V 0
0.22F
47k
+td A 5 4 3 2 1 7 6
10
8
PLL2
PHASE COMPARATOR 2 PHASE ADVANCING
OUTPUT FRAME PULSE
BURST AND BLANKING GENERATOR STAGE OUTPUT STAGE
OUTPUT PULSE DURATION SELECTOR
INHIBIT FOR V1 4V
BLOCK DIAGRAM AND TYPICAL APPLICATION
V
OUTPUT PULSE GENERATOR
H PLL1
NOISE SEPARATOR COINCIDENCE DETECTOR TIME CONSTANT SWITCH PHASE COMPARATOR 1 VOLTAGE LIMITE GATE OSCILLATOR
VIDEO
SYNCHRO SEPARATOR
INPUT
9 1.2k or 1.8M 3.3k 0.68 F 47F
10
11
12
13
14
15
16
82k
120k
6.8nF
33k
0.1F
1.5k A
0.47F
2.2M
V CR
4.7nF 10nF 2% Stiroflex
12k 2%
100pF
47k
0.47F
100F
SYNCHRO-GATE PULSE GENERATOR
FRAME SEPARATOR GATE (SH-SV) GATE (SH-SV-G)
SYNCHRO MODE SWITCH
G
TDA2593
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2593-02.EPS
TDA2593
PACKAGE MECHANICAL DATA 16 PINS - PLASTIC DIP
a1
I
b Z
B e3
e
L
b1
E
D
16
9
F
1
8
Dimensions a1 B b b1 D E e e3 F i L Z
Min. 0.51 0.77
Millimeters Typ.
Max. 1.65
Min. 0.020 0.030
Inches Typ.
Max. 0.065
0.5 0.25 20 8.5 2.54 17.78 7.1 5.1 3.3 1.27
0.020 0.010 0.787 0.335 0.100 0.700 0.280 0.201 0.130 0.050
DIP16.TBL
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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PM-DIP16.EPS

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