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L3M Device
Level 3 Mapper TXC-03452B DATA SHEET DESCRIPTION
The L3M maps a DS3 line signal into an STM-1 TUG-3 or STS-3/ STS-1 SPE or STS-1 SPE SDH/SONET signal. An E3 line signal is mapped into an STM-1 TUG-3 signal only. The L3M provides a TUG-3 formatted signal for STM-1 operation, or an STS SPE for STS-3 or STS-1 operation. The SDH/SONET signal is transmitted via an add bus with timing derived from the drop side, add side or from external timing (STS-1 only). An option is provided to generate the A1, A2 framing pattern, C1 byte and H1, H2 pointer towards the add bus when external timing mode is selected.
APPLICATIONS
* Add/drop multiplexers
* Digital cross-connect systems * Broadband switching systems * Transmission equipment
SDH/SONET SIDE
"O"-Bits I/O
Ext Alarms
Control
Microprocessor Interface
LINE SIDE
Add Bus
L3M
Level 3 Mapper TXC-03452B
Drop Bus
POH I/O
VCXO Boundary Alarm Port I/O Scan
U.S. Patents No.: 4,967,405; 5,040,170; 5,157,655; 5,265,096 U.S. and/or foreign patents issued or pending Copyright 2001 TranSwitch Corporation TranSwitch and TXC are registered trademarks of TranSwitch Corporation
TranSwitch Corporation * 3 Enterprise Drive * Shelton, Connecticut 06484 Tel: 203-929-8810 * Fax: 203-926-9453 * www.transwitch.com
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NRZ, Rail Input NRZ Clock, Data (Monitor) NRZ, Rail Output
Document Number: TXC-03452B-MB Ed. 6, April 2001
*
USA
Proprietary TranSwitch Corporation Information for use Solely by its Customers
* Maps DS3 (44.736 Mbit/s) or E3 (34.368 Mbit/s) line formats into SDH/SONET formats as follows: - DS3 to/from STM-1/TUG-3 - DS3 to/from STS-3/STS-1 SPE or STS-1 SPE - E3 to/from STM-1/TUG-3 only * SDH/SONET bus access: - Drop/add data byte access (with clock, C1J1, SPE, and parity) - Add bus interface timing derived from drop bus, add bus, or external timing * Path overhead byte processing: - Microprocessor or external interface - B3 generation and detection with test mask - B3 performance counter (16-bit) and block error counter (8-bit) - C2 mismatch and unequipped detection - G1 processing - FEBE count by block or bits (16-bit counter) * Microprocessor access: - Motorola or Intel compatible (selected via a lead) - Hardware/software interrupt capability * Line Interface - Transmit and receive NRZ or rail operation with split operation capability * Testing functions: - SONET, facility, or line loopback - Transmit and receive 215-1 or 223-1 generators and shared analyzer - Boundary scan capability (IEEE 1149.1) * 144-lead plastic quad flat package (PQFP) or 208-lead plastic ball grid array package (PBGA)
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Individual POH bytes for the transmitted SDH/SONET signal are mapped from the L3M memory map or an external interface. An option is provided to generate an unequipped status or TUG-3 path AIS signal. External accesses are provided for the communications channel "O"-bits and alarms for ring operation. The received signal is desynchronized from drop bus STM-1/TUG-3, STS-3/STS-1 SPE, or STS-1 signals. Internal pointer processing is performed for the TUG-3 signal. All POH bytes are provided for the microprocessor.
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
TABLE OF CONTENTS
Section
L3M TXC-03452B
Page
List of Figures ....................................................................................................... 3 Block Diagram ..................................................................................................... 5 Block Diagram Description .................................................................................. 6 Lead Diagrams .................................................................................................. 11 Lead Descriptions ............................................................................................. 13 Absolute Maximum Ratings and Environmental Limitations ............................. 24 Thermal Characteristics .................................................................................... 24 Power Requirements ......................................................................................... 24 Input, Output and Input/Output Parameters ...................................................... 25 Timing Characteristics ....................................................................................... 27 Operation .......................................................................................................... 49 L3M Power-Up Reset Sequence ................................................................ 49 PLL Filter Connection to VCXO .................................................................. 51 Testing ........................................................................................................ 53 Boundary Scan ........................................................................................... 55 Memory Map ..................................................................................................... 61 Memory Map Descriptions ................................................................................ 63 Package Information ......................................................................................... 86 Ordering Information ......................................................................................... 88 Related Products ............................................................................................... 88 Standards Documentation Sources .................................................................. 89 List of Data Sheet Changes .............................................................................. 91 Documentation Update Registration Form* ................................................. 95
* Please note that TranSwitch provides documentation for all of its products. Current editions of many documents are available from the Products page of the TranSwitch Website at www.transwitch.com. Customers who are using a TranSwitch Product, or planning to do so, should register with the TranSwitch Marketing Department to receive relevant updated and supplemental documentation as it is issued. They should also contact the Applications Engineering Department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product.
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DATA SHEET
LIST OF FIGURES
Figure
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38.
L3M TXC-03452B
Page
L3M TXC-03452B Block Diagram .......................................................... 5 L3M Multiplexing Structure ..................................................................... 6 ITU-TSS TUG-3 Build Format ................................................................ 8 SONET AU-3/STS-1 SPE Build Format ................................................. 9 Lead Diagram for L3M TXC-03452B 144-Lead Plastic Quad Flat Package .............................................................................. 11 Lead Diagram foe L3M TXC-03452B 208-Lead Plastic Ball Grid Array Package ....................................................................... 12 Line Side Transmit Timing ................................................................... 27 Line Side Receive Timing .................................................................... 28 STM-1 Add Bus Derived Interface Timing ............................................ 29 STS-3 Add Bus Derived Interface Timing ............................................ 30 STS-1 Add Bus Derived Interface Timing ............................................ 31 STM-1 Drop Bus Interface Timing ........................................................ 32 STS-3 Drop Bus Interface Timing ........................................................ 33 STS-1 Drop Bus Interface Timing ........................................................ 34 STS-1 Add Bus Interface Timing Using an External Clock .................. 35 STM-1 Add/Drop Bus Interface Timing ................................................ 36 STS-3 Add/Drop Bus Interface Timing ................................................. 37 STS-1 Add/Drop Bus Interface Timing ................................................. 38 Transmit Path Overhead Timing .......................................................... 39 Receive Path Overhead Timing ........................................................... 40 Transmit Alarm Indication Port Timing ................................................. 41 Receive Alarm Indication Port Timing .................................................. 42 Transmit Overhead Communications Channel Timing ........................ 42 Receive Overhead Communications Channel Interface Timing .......... 43 Intel Microprocessor Read Cycle Timing ............................................. 44 Intel Microprocessor Write Cycle Timing .............................................. 45 Motorola Microprocessor Read Cycle Timing ...................................... 46 Motorola Microprocessor Write Cycle Timing ...................................... 47 Boundary Scan Timing ......................................................................... 48 L3M Power-Up Reset Sequence .......................................................... 49 Physical Design For Analog Power Distribution ................................... 50 PLL Connection to External VCXO ...................................................... 51 Jitter Results for STS-3/DS3 and TUG-3/E3 Mappings ....................... 52 Loopbacks, Test Generators and Analyzer .......................................... 54 External Circuit to Maintain Clock Input to TX PRBS Generator .......... 54 Boundary Scan Schematic ................................................................... 56 L3M TXC-03452B 144-Lead Plastic Quad Flat Package ..................... 86 L3M TXC-03452B 208-Lead Small Outline Plastic Ball Grid Array Package ........................................................... 87
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DATA SHEET
L3M TXC-03452B
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DATA SHEET
BLOCK DIAGRAM
L3M TXC-03452B
SDH/SONET SIDE
XC1 XCLKE XCLKI ACLK AC1J1 ASPE ADD ADATA(7-0) APAR
LINE SIDE
TRANSMIT
INPUT BLOCK RNRZD RNRZC TPOS TNEG/LOS TCLK
8 8
ADD BLOCK
8
BUILD BLOCK
STUFF/ SYNC BLOCK
INTEL D7 - D0 A7 - A0 SEL RD WR RDY RESET INT MOTO RAMCI AISCLK RAIPD TAIPD TAIPC TAIPF
MOTOROLA D7 - D0 A7 - A0 SEL RD/WR DTACK RESET IRQ
TOCHC TOCHD ROCHC ROCHD TPOHC TPOHD TPOHF RPOHC RPOHD RPOHF STAI ISTAT PAIS TRI DCLK DC1J1 DSPE DDATA(7-0) DPAR DC1
OVERHEAD COMM CHANNEL I/O RAM PATH OVERHEAD I/O
P
I/O DS3/E3 AIS GEN
ALARM INTERFACE PORT
RECEIVE
DECODE BLOCK DESTUFF BLOCK DESYNC BLOCK OUTPUT BLOCK RPOS RNEG RCLK
8
DROP BLOCK
INTERNAL AMPLIFIER
(FOR VCXO)
BOUNDARY SCAN
TCK TMS TDI TRS TDO CTRL XOSCI FIFOERR
AMPINN AMPINP AMPOUT
Figure 1. L3M TXC-03452B Block Diagram
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DATA SHEET
BLOCK DIAGRAM DESCRIPTION
Transmit And Receive Paths, Overhead Communications, Alarms And Control
L3M TXC-03452B
A simplified block diagram of the L3M device is shown in Figure 1. The portion of the ITU-T SDH multiplexing structure implemented by the L3M device is shown in Figure 2. In the Transmit direction, positive/negative (P/N) rail data and clock input signals, or NRZ data and clock input signals, operating at 44.736 Mbit/s (DS3) or 34.368 Mbit/s (E3), are connected to the Input Block. The transmit line input consists of positive rail/NRZ signal lead (TPOS), negative rail signal lead (TNEG), and input clock (TCLK). A control bit is provided in software that inverts the clock signal if required. The Input Block performs either an HDB3 or B3ZS decoder function if the input line termination is a rail signal. Separate NRZ data (RNRZD) and clock (RNRZC) output signals are provided for external performance monitoring circuits. Illegal coding violations are counted in a 16-bit performance counter. When the line termination is NRZ, the negative rail signal lead (TNEG) can be used to clock in an external loss of signal indication. The transmit signal and clock are both monitored for operation, and alarms are reported for failure conditions. Control bits are provided that enable the L3M device to send a line AIS when either signal or clock failure is detected. The Input Block also monitors the line signal for an E3 AIS and it has a 215-1 or 223-1 pseudo-random binary sequence (PRBS) test generator for testing.
XN STM-N AUG
X1 AU-4 VC-4
ITU-T SDH multiplexing structure C-4 L3M Portion X3 X3 X1 TUG-3 X7 AU-3 VC-3 VC-4 TU-3 VC-3
139264 kbit/s (Note 1) L3M
Same as STS-3
44736 kbit/s or 34368 kbit/s (Note 1) C-3
X7 TUG-2 Pointer processing Multiplexing Aligning Mapping
X1 TU-2 X3 X4 TU-12 VC-12 C-12 VC-2 C-2
6312 kbit/s (Note 1)
2048 kbit/s (Note 1)
TU-11
VC-11
C-11
1544 kbit/s (Note 1)
Note 1: G.702 tributaries associated with containers C-x are shown. Other signals (e.g., ATM) can also be accommodated.
Figure 2. L3M Multiplexing Structure
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DATA SHEET
L3M TXC-03452B
The Stuff/Sync Block and Build Blocks work together for mapping a DS3 signal into a TUG-3 or STS-1 SPE or an E3 signal into a TUG-3. The mapped formats are shown in Figures 3 and 4. The stuffing algorithm for the DS3 signal format uses one set of five control bits (C-bits) with one stuff opportunity bit (S-bit) for frequency justification, per subframe (9 subframes). The E3 format uses five pairs of control bits (C1, C2 bits) to control two stuff opportunity bits (S1 and S2) per subframe (one subframe per three rows for a total of three subframes per frame). A read clock and timing indications are given by the Build Block for reading the transmit FIFO. A FIFO overflow or underflow alarm indication is provided. Should an underflow/overflow condition occur, the FIFO is immediately reset to the start-up preset value. The transmit FIFO also tracks the incoming line signal that can have an average frequency error as high as +/- 20 ppm, and simultaneously accepts this signal with up to 5 UI Peak-to-Peak jitter (where UI = 1/f). The Build Block, with signals exchanged between itself and the Stuff/Sync Block, constructs one of two 87 column by 9 row formats: an ITU-TSS TUG-3 signal (Figure 3) or a SONET STS-1 (for STS-3) signal (Figure 4). The L3M generates a stuff byte in column 0 when control bit NOPOH is set to 0, to fill out the 87 columns of the SPE such that three L3M devices will provide inputs for a VC-4 of 261 columns, as shown in Figure 2. This column position is overwritten with the VC-4 POH when the device is mapped into the first TUG-3, while fixed stuff is used for the second and third TUG-3s. A fixed pointer value of 6800H is used as the initial value when building a TUG-3 format. There are two levels of pointer movements in TUG-3 mapping. When the TUG-3 mode is selected in drop timing mode, the transmit TUG-3 pointer value will change when there is a receive STM-1 AU-4 pointer increment or decrement. However, this feature may be disabled. Pointer movements on the STM-1 bus, which are detected using the C1J1 and SPE bus signals, are compensated by creating a TUG-3 pointer movement in the opposite direction. An "O"-bit serial interface, or two bits in RAM, are used for mapping the two "O"-bits into the DS3 SONET format subframes. The "O"-bit interface consists of an output clock (TOCHC) and an input data lead (TOCHD). The nine Path Overhead bytes are mapped individually into the SONET format from either the POH interface (except the B3 byte), from microprocessor-written RAM positions, or from internal logic (such as the path RDI state in bit 5 of G1). The POH interface consists of an output clock (TPOHC), a framing pulse (TPOHF) and an input data lead (TPOHD). A control bit enables the POH interface bytes to be written into RAM when transmitted. Enable bits are provided for controlling the FEBE and path RDI states as a result of local alarms or remote status information received during ring operation. A B3 test mask or fixed byte can also be transmitted. Control bits are provided for generating a TUG-3 path AIS, or an unequipped status condition (payload and POH bytes are equal to zero). An alarm interface provides FEBE and path RDI (FERF) input indications from a mate L3M device for ring operation. The alarm interface leads consist of input data (TAIPD), framing pulse (TAIPF), and clock signal (TAIPC). The Add Block uses an external byte rate clock signal (XCLKI), or the Add or Drop bus clock and the SPE and C1J1 timing signals, for building and adding a TUG-3, STS-3/STS-1 SPE, or STS-1 SPE to the Add bus. The Add Block supports the STM-1/STS-3 bus signaling rate of 19.44 MHz and the STS-1 signaling rate of 6.48 MHz. The external clock is enabled by placing a high on the external clock enable lead (XCLKE), and is intended for STS-1 operation. The external clock generates the Add bus clock (ACLK), C1J1 indication (AC1J1), and SPE indication (ASPE). The output data to the bus is 3-state, active true. A software control bit enables the transport overhead A1, A2, C1, and H1/H2 bytes to be generated. The H1 and H2 bytes will carry the value of 6000H and the C1 byte carries the value of 01H. An optional C1 signal (XC1 signal lead) can be applied to the L3M device to align the start of the frame (A1, A2 bytes).
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DATA SHEET
L3M TXC-03452B
DS3 44.736 Mbit/s Subframe Format (1 of 9) POH 8R 8R RRC 5I 200I 8R CCRRRRRR 208I 8R CCRROORS 208I 0 1 2 3 4 31 32 59 60 86
E3 34.368 Mbit/s Subframe Format (1 of 3) RRRRRRC1C2 RRRROOC1C2
P O H 01 2
C C C 41
C C A
24I 24I B 8I 86
RRRROORR RRRRRRRR
A B RRRRRRRS1 S2IIIIIII
24I 0 123 R
24I 11
24I 15
24I
24I 24
24I 28
24I 32
24I 36
24I
C 40 41
19 20
24I 45
24I 49
24I
24I 53 57
24I
24I 61 62
24I 66 70
24I 74
24I 78
24I 82 86
0
1 H1 K3 H2 N1 H3 J1 B3 C2 G1 F2 H4 F3 TUG-3 Format (86 x 9)
86 1
9
Figure 3. ITU-TSS TUG-3 Build Format
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DATA SHEET
L3M TXC-03452B
DS3 44.736 Mbit/s Subframe Format (1 of 9) POH 8R 8R RRC 5I 200I 8R 8R CCRRRRRR 208I 8R 8R CCRROORS 208I 1 2 3 30 31 32 59 60 61 87
1 30 59 87 1 J1 B3 C2 G1 F2 H4 Z3 Z4 Z5 9 AU-3/STS-1 SPE Format (87 x 9)
Figure 4. SONET AU-3/STS-1 SPE Build Format When Add bus timing is selected, the clock (ACLK), C1J1 indication (AC1J1), and SPE indication (ASPE) become input signals from the Add bus. When Drop timing is selected, the L3M device supports DC1J1 pointer movements on the Drop bus, and adjusts the pointer value in the TUG-3s accordingly. An active low Add indicator (ADD) is also provided to indicate the location of all time slots that are added to the bus by the L3M device (e.g., TUG-3 A, B or C). In TUG-3 mode, the VC-4 path overhead bytes are optionally sent as output to the bus when control bit NOPOH (Address CA, Bit 5) is set to 0. The selected clock is monitored for operation, and an odd parity signal (APAR) is calculated for the bus data, including the SPE and C1J1 signals when these signals are outputs (i.e., in external timing mode). The Drop Block supports the STM-1/STS-3 bus signaling rate of 19.44 MHz and the STS-1 signaling rate of 6.48 MHz. The Drop Block uses the clock (DCLK), C1J1 indication (DC1J1) and a separate DC1 signal if required, and SPE indication (DSPE) from a Drop bus for determining the location of the Path Overhead J1 byte in the VC-4, the three J1 bytes in the three STS-1 SPEs in the STS-3 signal, and the single SPE for STS-1 operation. The C1 pulse is required, and is synchronous with the first C1 byte in the STM-1 Section Overhead bytes, or in the STS-3 or STS-1 Transport Overhead Bytes. The C1 pulse provides a framing indication for determining the location of the bytes corresponding to the TUG-3 or STS-1 selected, and is also used by the desynchronizer as a frame reference. The C1 pulse can be present in the DC1J1 signal or provided as a separate signal (DC1). The Drop SPE (DSPE) is active during the POH and payload byte times. The Drop Bus clock and composite C1J1 signal are monitored for operation, and odd parity is calculated and compared against the incoming parity bit. The Decode Block contains the logic for performing pointer interpretation and tracking for the selected TUG-3 signal, removing the Path Overhead bytes and Overhead Communication bits, and detecting the E1 byte for an upstream AIS detection. The E1 byte carries an AIS indication from an associated TranSwitch SOT-3 or SOT-1 device. The SOT-3 or SOT-1 generates an AIS signal in one E1 byte for TUG-3 mode, or in each of the three E1 bytes for the three STS-1s, when a loss of frame, loss of pointer, loss of signal, or line AIS is detected. This indication is used by the L3M device to generate a Path RDI indication, and for generating a received DS3 or E3 AIS. In place of the E1 byte AIS, the L3M device also supports an alarm indication provided on the ISTAT and PAIS signal leads. The TUG-3 pointer is monitored for loss of pointer, New Data Flag, and Path AIS. Performance counters are provided for monitoring pointer movements. All POH bytes are written into RAM locations and are also provided at the POH interface. The POH interface consists of an output data lead (RPOHD),
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DATA SHEET
L3M TXC-03452B
framing pulse (RPOHF), and clock signal (RPOHC). The L3M device also provides a microprocessor-written location for performing C2 mismatch detection, and unequipped detection based on ANSI and ITU-TSS standards. The received "O"-bits are available at an external interface and a 2-bit RAM location for these bits is updated each frame. The "O"-bit interface consists of a data lead (ROCHD) and clock signal (ROCHC). An alarm indication port is provided for ring operation. The alarm indication port consists of a data lead (RAIPD), which is used with the POH interface framing pulse (RPOHF) and clock signal (RPOHC). The signal on the data lead (RAIPD) consists of the FEBE count and a path RDI (FERF) status indication. The Desynchronize Block removes the effect on the output DS3 or E3 signals of systemic jitter due to signal mapping and pointer movements. The output has an average frequency equal to the source frequency, and has jitter characteristics that meet ITU-TSS and ANSI standards. The Desynchronize Block consists of two circuits, a Pointer Leak circuit and a Phase-Locked Loop circuit. The function of the Pointer Leak circuit is to absorb the immediate effect of up to eight consecutive pointer movements (any combination of SPE or TUG-3 pointer movements) in either direction, and filter them out in time. A single pointer adjustment is an 8 Unit Interval (UI) phase step. The Pointer Leak circuit turns the phase step into eight 1-UI steps, widely spaced in time, allowing the Phase-Locked Loop circuit to track. In normal operation, the output is one data bit and one clock cycle for each input bit. When a negative stuff occurs 8 extra bits are pulled from the signal and absorbed. Following this operation, the normal operation of one bit in for one bit out continues except that one extra bit is pulled from the FIFO every n frames. In this way, the pointer step is leaked out in 8 x n frames. The value of n is programmed via the microprocessor. The Phase-Locked Loop (PLL) circuit of the Desynchronize Block is externally connected to a line-frequency voltage controlled crystal oscillator (VCXO) via a filter. Details of the external circuit for the PLL are provided in the Operation section of this Data Sheet under the heading "PLL Filter Connection to VCXO". In the Receive direction, the Output Block provides either a positive (RPOS) and negative (RNEG) rail line signal or a NRZ line signal (RPOS), and a clock signal (RCLK). The HDB3/B3ZS coder operates independently of the transmitter. For interface flexibility, a control bit is provided for inverting the output clock. The receive data and clock outputs can be forced to a high impedance state for the purpose of tying two L3M devices together for ring operation or redundancy. An additional 215-1 or 223-1 pseudo-random test generator is provided. The Output Block and the Input Block share a 215-1 or 223-1 analyzer that can compare the desynchronizer output or transmit data against a fixed pattern. An alarm is provided when the analyzer and incoming data are not synchronous. Errors are counted in the 16-bit coding violation counter. Loopbacks between the Input and Output Blocks facilitate board and network debugging. All of the control registers and performance counters, and the status and alarm indications, are accessible through the L3M device's compatible microprocessor bus interface in the Microprocessor I/O Block. The L3M device supports both Intel and Motorola microprocessor bus interfaces, with both hardware and software interrupt capability. The Motorola compatible microprocessor interface is selected by placing a high on the MOTO signal lead. The Boundary Scan Block provides a mechanism for external access to the input and output leads of the device, so that they may be observed and tested. The structure and operation of this Block are described in the Operation section.
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DATA SHEET
LEAD DIAGRAMS
L3M TXC-03452B
100
94
90
86
80
108
106
104
102
98
96
92
88
84
82
78
10
12
14
16
18
20
22
24
26
28
30
32
34
Note: See Figure 37 for package information.
Figure 5. Lead Diagram for L3M TXC-03452B 144-Lead Plastic Quad Flat Package
AISCLK XOSCI CTRL GND AMPINN AMPINP AMPOUT NC AGND APWR FIFOERR NC GND APWR AGND RCAP AGND2 APWR2 NC GND NC NC VDD GND ROCHD ROCHC GND RAIPD GND RPOHD RPOHF RPOHC GND VDD NC NC
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36
2
4
6
8
TPOS TNEG/LOS TCLK GND A0 A1 A2 A3 A4 A5 A6 A7 GND WR RD or RD/WR SEL GND VDD GND RDY/DTACK INT/IRQ RAMCI MOTO GND D0 D1 D2 D3 D4 D5 D6 D7 VDD RCLK RPOS RNEG
76
74
VDD TRI TRS TMS TCK TDI TDO APWR AGND TCAP APWR2 AGND2 ISTAT PAIS STAI RNRZC RNRZD TOCHD TOCHC GND VDD GND RESET TAIPD TAIPF TAIPC NC TPOHD TPOHF TPOHC GND XCLKE XC1 XCLKI GND VDD 72 70 112 68 114 66 116 64 118 62 120 60 122 58 124 126 128 130 50 132 48 134 46 136 44 138 42 140 40 142 38 144 110
L3M (Top View) TXC-03452B
56 54 52
VDD GND ADATA0 ADATA1 ADATA2 ADATA3 ADATA4 ADATA5 ADATA6 ADATA7 GND ACLK ADD AC1J1 ASPE APAR GND VDD GND DSPE DC1J1 DCLK DPAR DC1 GND DDATA0 DDATA1 DDATA2 DDATA3 DDATA4 DDATA5 DDATA6 DDATA7 GND VDD GND
TXC-03452B-MB Ed. 6, April 2001
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
L3M TXC-03452B
VDD 16 NC 15
NC
51
NC
54
GND
58
XCLKE TPOHD TAIPD GND
61 65 69 73
STAI APWR2 APWR
76 80 84
NC
87
TRI
91
VDD
95
NC
98
NC
101
NC
49
NC
53
NC
55
XC1
59
TPOHF TAIPF
64 68
VDD
72
PAIS
77
TCAP
81
NC
85
TCK
88
TRS
93
NC
97
NC
99
TNEG
103
ADATA0 GND
NC
50
VDD
52
GND
56
NC
63
RESET TOCHC RNRZC AGND2
66 71 78 82
NC
86
TDI
90
TMS
96
TPOS
100
NC
102
TCLK
107
14 NC 13
ADATA3
45
ADATA1 ADATA2 XCLKI TPOHC TAIPC 42 46 ADATA4 41 47 NC 43 ADDATA7 35 37 48 57
GND TOCHD RNRZD ISTAT AGND
62 67 75 79 89
TDO
94
A1
104
GND
105
NC
106
A0
110
NC
38
A4
83 108
A3
109
A2
111
NC
114
12
ADATA6 ADATA5
NC
36
A7
115
A6
117
A5
116
NC
118
11 ADD 10
34
ACLK
30
NC
32
AC1J1
31
GND
GND
GND
GND
SEL
123
RD
121
NC
120
WR
122
APAR ASPE 9
26
GND
28
NC
27
GND
GND
GND
GND
128
NC
127
VDD
125
NC
124
GND
126
GND DSPE 8 DPAR 7
22
NC
23
VDD
20 19
GND
GND
GND
GND
131
GND
133
RDY
132
INT
129
NC
130
DC1
18
DCLK DC1J1
17 16 DDATA0 9
GND
GND
GND
GND
NC
137
RAMCI MOTO
136 135
NC
134
DDATA1 DDATA2
NC
12
D0
144
D1
143
D3
140
D2
138
6
DDATA4
14
NC DDATA3
10 7
NC
5 DDATA5 2 163
NC
155
D4
147
D6
145
D5
142
5
DDATA6
DDATA7 6
NC
4
GND ROCHD NC
197 191 186
APWR2
182
NC
174
AGND
170
NC
166
AGND AMPINN
162 156
D7
152
VDD
148
NC
146
4 GND 3 VDD 2 NC 1 T
NC
3
NC
1
GND RPOHD ROCHC VDD
198 194 190 185
NC
181
AGND2
175
NC
171
FIFO
167
NC
164
CTRL
159
NC
153
RCLK
150
NC
149
NC
200
NC
199
NC
195
RPOHC RAIPD
192 188
NC
184
NC
180
RCAP
176
GND
172
NC
168
AMPINP XOSCI AISCLK
165 161 157
NC
154
RPOS
151
NC
NC
VDD RPOHF
GND
NC
GND
NC
APWR APWR AMOUT GND
NC
NC
RNEG
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Note:
This is the bottom view. The leads are solder balls. See Figure 38 for package information. Some signal Symbols have been abbreviated to fit the space available. The Symbols are shown in full in the Lead Descriptions section.
Figure 6. Lead Diagram for L3M TXC-03452B 208-Lead Plastic Ball Grid Array Package
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DATA SHEET
LEAD DESCRIPTIONS
POWER SUPPLY, GROUND AND NO CONNECTS 144-Lead QFP Lead No. 23,34,38,55, 72,73,88, 108,126,141 10,14,101 18,98 208-Lead BGA I/O/P* Lead No. B4, C9, C16, K3, J15, N1, N8, N14, T2, T16 F1, F16, G1, G16, J4 P
L3M TXC-03452B
Symbol VDD
Type**
Name/Function VDD: +5 volts, 5% power supply.
APWR APWR2 GND
P P P
Analog VDD: +5 volts, 5% power supply. Analog VDD2: +5 volts, 5% power supply. Ground: 0 volts reference.
4,13,20,24, A9, C13, D1, 27,29,33,37, D8, G2, G7, 39,48,54,56, G8, G9, G10, 62,71,74,78, H7, H8, H9, 87,89,112, H10, J1, J7, J8, J9, J10, J16, 121,125, K7, K8, K9, 127,132 K10, K13, L1, M4, M14, N3, N16, P9, R14, T3, T8 9,15,100 17,97 8,12,19 21,22,35 36,82 E4, F13, G4 G14, H3 A3, A4, A7, A8, A11, A12, A16, B1, B2, B9, B10, B13, B14, B15, B16, C1, C3, C15, D5, D7, D9, E3, E16, F2, F4, F14, F15, G3, H1, H4, J2, J3, K1, K2, K4, L14, N2, N5, N9, N12, N15, P1, P2, P3, P4, P6, P8, P10, P11, P14, P15, P16, R1, R2, R3, R5, R12, R15, R16, T1, T13, T15
AGND AGND2 NC
P P
Analog Ground: 0 volts reference. Analog Ground2: 0 volts reference. No Connect: NC leads are not to be connected, not even to another NC lead, but must be left floating. Connection of these leads may impair performance or cause damage to the device.
*Note: I = Input; O = Output; P = Power; T = Tri-State **Note: See Input, Output and Input/Output Parameters section below for the Type definitions.
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DATA SHEET
LINE INTERFACE 144-Lead 208-Lead QFP BGA I/O/P Lead No. Lead No. 92 H13 O
L3M TXC-03452B
Symbol RNRZD
Type CMOS 4mA
Name/Function Receive Line NRZ Data: Output provided for an optional external performance monitoring circuit. This serial NRZ output is provided after the decoder (transmit direction), independent of whether the input is NRZ or rail. Data is always clocked out on positive transitions of clock (RNRZC). This lead goes to a high impedance state when control bit L3Z is set to 1. Receive Line Clock: NRZ data on lead RNRZD is clocked out of the L3M device on positive transitions of this clock. This lead goes to a high impedance state when control bit L3Z is set to 1. Transmit NRZ Line Data/Positive Rail Data: Serial NRZ input for the 44.736 or 34.368 Mbit/s asynchronous line data. This lead also provides the positive rail data input for an internal decoder. Transmit Negative Rail Data: When operating in the P/N rail mode, this lead provides a negative rail input for the internal decoder. When operating in the NRZ mode, a high on this lead instead indicates an external loss of signal alarm, so that the lead must be tied to ground if it is not used for input of an external loss of signal indication. Transmit Line Clock: NRZ or rail data is clocked into the L3M device using the TPOS/TNEG signal leads on positive transitions of this clock when control bit INVCI is set to 0. NRZ or rail data is clocked in on negative transitions when control bit INVCI is set to 1. TCLK is used as the input clock for the transmit PRBS generator and it must be present to generate a test pattern. Receive Line Clock: Line data present on the RPOS/ RNEG signal leads (44.736 or 34.368 Mbit/s) is clocked out of the L3M device on negative transitions of this clock when control bit INVCO is set to 0. NRZ or rail data is clocked out on positive transitions of this clock when control bit INVCO is set to 1. This lead goes to a high impedance state when control bit L3Z is set to 1. Receive Line NRZ Data/Positive Rail Data: Serial NRZ output for the 44.736 or 34.368 Mbit/s asynchronous line data. This lead also provides the positive rail output when the rail interface is selected. This lead goes to a high impedance state when control bit L3Z is set to 1. Receive Negative Rail Data: This lead provides a negative rail interface from the internal coder. This lead goes to a high impedance state when control bit L3Z is set to 1. When the NRZ interface is selected, this lead outputs a 0.
RNRZC
93
H14
O
CMOS 4mA
TPOS
109
C14
I
CMOS
TNEG/ LOS
110
A15
I
CMOS
TCLK
111
A14
I
CMOS
RCLK
142
B3
O
CMOS 4mA
RPOS
143
A2
O
CMOS 4mA
RNEG
144
A1
O
CMOS 4mA
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DATA SHEET
MICROPROCESSOR INTERFACE Symbol A(7-0) 144-Lead QFP Lead No. 208-Lead BGA I/O/P Lead No. I Type TTL Name/Function
L3M TXC-03452B
120 - 113 D11, C11, B11, D12, C12, B12, D13, A13 122 A10
Address Bus: These are address line inputs that are used by the microprocessor for accessing the L3M RAM for a read/write cycle. A0 is defined as the least significant bit. High is logic 1. Write (I mode): Intel Mode - An active low signal generated by the microprocessor for writing to the L3M RAM locations. Motorola Mode - Not used. Read (I mode) or Read/Write (M mode): Intel Mode - An active low signal generated by the microprocessor for reading the L3M RAM locations. Motorola Mode - A high signal generated by the microprocessor for reading the L3M RAM locations. A low signal is used for writing to L3M RAM locations. Select: A low enables data transfers between the microprocessor and the L3M device during a read/write cycle.
WR
I
TTL
RD RD/WR
123
C10
I
TTL
SEL RDY/ DTACK
124 128
D10 C8
I
TTLp
O(T) TTL8mA Ready (I mode) or Data Transfer Acknowledge (M mode): Intel Mode - A high is an acknowledgment from the addressed RAM location that the transfer can be completed. A low indicates that the L3M has not completed the transfer cycle, and the microprocessor must wait before latching read data or completing the write cycle. Motorola Mode - During a read bus cycle, a low signal indicates the information on the data bus is valid. During a write bus cycle, a low signal acknowledges the acceptance of data. O(T) TTL4mA Interrupt: Intel Mode - A high on this output lead signals an interrupt request to the microprocessor. The off state is low when control bit INTZ (bit 2, register C2) is 0, and 3-state when INTZ is 1. Motorola Mode - A low on this lead signals an interrupt request to the microprocessor. The off state is high when INTZ is 0, and 3-state when INTZ is 1. I CMOS RAM Clock Input: Clock input for the internal RAM. This clock allows an outside clock to provide an arbitrator function for accessing the internal RAM structure. This clock must operate between 12 and 25 MHz with a duty cycle of 50 +/- 10 percent. This clock and the microprocessor timing signals may operate asynchronously with respect to each other. Motorola/Intel Microprocessor Select: A high selects the Motorola microprocessor compatible bus interface. A low selects the Intel microprocessor compatible bus interface. - 15 of 96 TXC-03452B-MB Ed. 6, April 2001
INT/IRQ
129
B8
RAMCI
130
C7
MOTO
131
B7
I
TTL
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DATA SHEET
144-Lead QFP Lead No. 208-Lead BGA I/O/P Lead No. I/O
L3M TXC-03452B
Symbol D(7-0)
Type
Name/Function
140 - 133 C4, B5, A5, C5, B6, A6, C6, D6
TTL8mA Data Bus: Bi-directional data lines used for transferring data between the L3M device and an external microprocessor. D0 is defined as the least significant bit. High is logic 1.
DROP BUS INTERFACE 144-Lead QFP Lead No. 40 - 47 208-Lead BGA I/O/P Lead No. R4, T4, N4, T5, P5, R6, T6, N6 R7 I
Symbol DDATA (7-0) DC1
Type TTL
Name/Function Drop Data Byte: Byte data that corresponds to the STM-1/ STS-3/STS-1 signal from the drop bus. The first bit received corresponds to bit 7. Drop C1 Pulse: External positive C1 pulse that may be provided on this lead instead of in the DC1J1 signal. This signal is ORed internally with the DC1J1 signal to form a composite C1J1 signal. If this lead is not used it must be grounded. This lead is used for special applications. Drop Bus Parity Bit: This is an odd parity input for each data byte, the DSPE signal, and the composite DC1J1 pulses. The status bit BUSERR (bit 5 in registers B0 and B1) indicates when this input differs from an internally-generated odd parity for these signals, but no other action is taken upon occurrence of this drop bus parity error. Drop Bus Clock: This clock operates at 19.44 MHz for STM-1/STS-3 operation, and at 6.48 MHz for STS-1 bus operation. Drop bus byte-wide data (DDATA7-0), parity (DPAR), payload indicator (DSPE), and C1/J1 (DC1J1 and DC1) are clocked into the L3M device on negative transitions of this clock. Drop Bus C1 and J1 Indicator: The C1 pulse is an active high, one clock cycle wide timing pulse that indicates the location of the first C1 time slot in the STM-1 or STS-3 frame. If the C1 pulse is not present in this signal, it must be provided at the DC1 lead. A J1 pulse, also one clock cycle wide, identifies the location of the J1 byte. Drop Bus SPE Indicator: A signal that is high during the STM-1 VC-4, and the STS-3/STS-1 SPE period.
49
I
TTL
DPAR
50
T7
I
TTL
DCLK
51
P7
I
TTL
DC1J1
52
N7
I
TTL
DSPE
53
R8
I
TTL
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DATA SHEET
ADD BUS INTERFACE 144-Lead 208-Lead QFP BGA I/O/P Lead No. Lead No. 57
L3M TXC-03452B
Symbol APAR
Type
Name/Function
T9
O(T)
TTL4mA Add Bus Parity Bit: This output bit represents the odd parity calculation for each data byte in the add timing and drop timing modes. In the external timing mode, the parity calculation also includes the ASPE and AC1J1 signals which become outputs. This lead is forced to a high impedance state when the control bit ADDZ is set to 1, or when ADD is inactive (high).
ASPE
58
R9
I/O(T) TTL4mA Add Bus SPE Indicator: An input signal that is high during the STM-1 VC-4 period, and STS-3/STS-1 SPE period. When enabled by the external clock enable (XCLKE) control lead, this signal becomes an output. This lead is forced to a high impedance state when the control bit ADDZ is set to 1, or when the drop timing mode is selected. I/O(T) TTL4mA Add Bus C1 and J1 Indicator: The C1 pulse is an active high, one clock cycle wide input timing pulse that identifies the location of the first C1 time slot in the STM-1 or STS-3 frame. A J1 pulse, also one clock cycle wide, identifies the location of the J1 byte. When enabled by the external clock enable (XCLKE) control lead, this signal becomes an output. This lead goes to a high impedance state when control bit ADDZ is set to 1, or when the drop timing mode is selected. O TTL4mA Add Indicator: An active low signal that identifies the position of the data time slots being mapped onto the add bus. This signal will be high when - Data is not present - Reset is present - Add bus loss of clock occurs - When control bit ADDZ is set to 1. - Until the first two C1 pulses are received in either the add bus or drop bus timing mode. This avoids bus contention during start up. This signal will be a high impedance when the TRI lead is low. TTL4mA Add Bus Clock: This clock operates at 19.44 MHz for STM-1/STS-3 operation, and at 6.48 MHz for STS-1 bus operation. The add clock is used for Build Block timing and for sourcing the add bus byte-wide data (ADATA(7-0)), parity (APAR), and add indicator (ADD). When enabled by the external clock enable (XCLKE) control lead, this signal becomes an output. This lead goes to a high impedance state when control bit ADDZ is set to 1.
AC1J1
59
N10
ADD
60
T10
ACLK
61
R10
I/O
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DATA SHEET
144-Lead 208-Lead QFP BGA I/O/P Lead No. Lead No. 63 - 70
L3M TXC-03452B
Symbol ADATA (7-0)
Type
Name/Function
O(T) TTL4mA Add Data Byte: Byte-wide data that corresponds to the N11, STM-1/STS-3/STS-1 time slots that are placed on the add T11, bus. Bit 7 corresponds to bit 1 in the STM-1/SONET transR11, mission format. This bus is forced to a high impedance P12, state when the control bit ADDZ is set to 1, or when ADD is T12, inactive (high). P13, R13, T14
OVERHEAD COMMUNICATIONS CHANNEL INTERFACE 144-Lead 208-Lead QFP BGA I/O/P Lead No. Lead No. 25
Symbol ROCHD
Type
Name/Function
L4
O
TTL4mA Receive Overhead Comm Channel Data: Unaligned data output for the overhead communications channel "O"-bits from the DS3 or E3 formats. The "O"-bits are clocked out of the L3M device on negative transitions of the ROCHC clock signal. TTL4mA Receive Overhead Comm Channel Clock: A gapped 720 kHz output clock with an average frequency of 144 kHz for clocking out the transmit overhead communications channel bits to external circuitry. TTL4mA Transmit Overhead Comm Channel Clock: A gapped 720 kHz output clock with an average frequency of 144 kHz for sourcing the transmit overhead communications channel bits from external circuitry. TTL Transmit Overhead Comm Channel Data: Data input for the overhead communications channel in the DS3 or E3 formats. Data is clocked into the L3M device on positive transitions of the TOCHC clock signal. The bits are multiplexed into the "O"-bit positions unaligned regarding bit position and subframe number. This input is enabled by the EXOO control bit. When enabled, the lead must be grounded if it is desired to insert zeroes in the corresponding fixed stuff locations.
ROCHC
26
L3
O
TOCHC
90
J14
O
TOCHD
91
J13
I
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DATA SHEET
PATH OVERHEAD INTERFACE 144-Lead 208-Lead QFP BGA I/O/P Lead No. Lead No. 30
L3M TXC-03452B
Symbol RPOHD
Type
Name/Function
M3
O
TTL4mA Receive Path Overhead Data: The serial output for the nine path overhead bytes. The POH bytes are clocked out on negative transitions of the clock signal (RPOHC). TTL4mA Receive Path Overhead Framing: A positive one clock cycle (RPOHC) wide output framing pulse that is synchronous with the J1 data of RPOHD. This signal is also used as the framing pulse for the receive alarm indication port data (RAIPD). TTL4mA Receive Path Overhead Clock: A gapped clock used for clocking out the path overhead bytes, and receive alarm indication port data (RAIPD). TTL4mA Transmit Path Overhead Clock: A gapped clock used for clocking the path overhead bytes from an external circuit into the L3M device. TTL4mA Transmit Path Overhead Framing: A positive one clock cycle (TPOHC) wide output framing pulse that determines the start of the J1 byte in TPOHD. TTL Transmit Path Overhead Data: A serial input for the following path overhead bytes: J1, C2, G1, F2, H4, Z3, Z4, and Z5 bytes. The POH bytes are clocked into the L3M device on positive transitions of the TPOHC clock signal. Eight bits are clocked in during the B3 byte time, but they are ignored by the L3M device.
RPOHF
31
M1
O
RPOHC
32
M2
O
TPOHC
79
M13
O
TPOHF
80
L15
O
TPOHD
81
L16
I
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DATA SHEET
ALARM INDICATION PORT 144-Lead 208-Lead QFP BGA I/O/P Lead No. Lead No. 28
L3M TXC-03452B
Symbol RAIPD
Type
Name/Function
L2
O
TTL4mA Receive Alarm Indication Port Data: A serial output that provides the 4-bit FEBE count (B3 error count) and Path RDI alarm indication to a mate L3M device for ring operation. This lead is normally connected to the TAIPD lead at the mate L3M device. The RPOHC signal is used to clock this signal out of the L3M device. The RPOHF signal provides the frame reference signal. The bits are sent in the following format: Bits 1 2 3 4 5 RDI 6 0 7 0 8 1
B3 Count
Bit 1 is the MSB and is sent first in the bit stream. TAIPC 83
L13
I
TTL
Transmit Alarm Indication Port Clock: This clock input is normally connected to the RPOHC clock lead at the mate L3M device for ring operation. Transmit alarm data (TAIPD) is clocked into the L3M device on positive transitions of the RPOHC clock. Transmit Alarm Indication Port Framing Pulse: Normally connected to RPOHF lead at the mate L3M device for ring operation. Used to indicate the first bit in the first byte for the external alarm indications. Transmit Alarm Indication Port Data: This serial input lead is normally connected to the RAIPD lead at the mate L3M device for ring operation. Provides an input for the four bit FEBE count (B3 error count), and Path RDI alarm indication (as shown above for RAIPD).
TAIPF
84
K15
I
TTL
TAIPD
85
K16
I
TTL
ADDITIONAL SIGNALS 144-Lead 208-Lead QFP BGA I/O/P Lead No. Lead No. 1
Symbol AISCLK
Type CMOS
Name/Function AIS Clock Input: Clock input for the L3M device's AIS generator. This clock must be present for the AIS generator to function. The clock must have the operating line rate of either 44.736 or 34.368 MHz, and have a frequency stability of +/- 20 ppm. External Clock Input: Used to derive output timing and data for the add bus. Enabled by placing a high on the lead labeled XCLKE. A byte clock frequency of 6.48 MHz is required for STS-1 operation. This clock is monitored for loss of clock when the external timing mode is selected.
C2
I
XCLKI
75
N13
I
TTL
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DATA SHEET
144-Lead 208-Lead QFP BGA I/O/P Lead No. Lead No. 76
L3M TXC-03452B
Symbol XC1
Type TTL
Name/Function External C1 Input: Optional C1 input signal used to synchronize the frame start when the external timing mode is selected for the add bus. This lead must be held low when the external timing mode is not used. External Clock Enable: A high on this lead enables add bus timing to be derived from the XCKLI lead (external clock signal). The ASPE, AC1J1, and ACLK signal leads become output leads. Hardware Reset: A low clears all counters and initiates reframing in the transmit direction upon its release. This lead is provided with an internal pull-up resistor. The reset signal must be low for a minimum of 200 nanoseconds. The bus clocks, line clocks, microprocessor clock and VCXO clock must be present during the reset signal. The add bus outputs are held in a high impedance state during the reset period. The add bus high impedance state is released on the occurrence of the C1 pulse.
M15
I
XCLKE
77
M16
I
TTL
RESET
86
K14
I
TTLp
FIFOERR
11
F3
O
TTL8mA FIFO Reset Indication: This lead requires an external 4.7 k pull-up resistor to +5V. A high on this lead indicates that OD the receive side FIFOs have been reset. The reset condition occurs after a hardware reset (RESET, lead 86 or K14) or a software reset (control bit RXRST), or after a FIFO error (underflow or overflow). After the hardware or software reset, or the FIFO error, clears, FIFOERR stays high for a minimum of 125 microseconds and a maximum of 250 microseconds before returning to its normal low level. TTL STS Network Alarm Indication: A high on this lead will generate a count of 9 in bits 1 through 4 of G1 when control bit FEBE9EN is equal to 1. An indication is also provided as the XSTAI status bit. The lead is normally grounded. External Path AIS Indication: A high on this lead may be used to indicate an external Path AIS has occurred. It causes the XPAIS status bit to be set to 1. This lead is enabled when control bit XALM2AIS is a 1. When enabled, the in-band upstream AIS indication provided via the TOH E1 byte is disabled. External STS-1 Alarm Indication: A high on this lead may be used to indicate an external SONET/SDH alarm has occurred. It causes the XISTAT status bit to be set to 1. High Impedance Enable: A low causes all L3M device digital outputs and bi-directional leads to be set to a high impedance state for test purposes. This lead is provided with an internal pull-up resistor.
STAI
94
H16
I
PAIS
95
H15
I
TTL
ISTAT
96
G13
I
TTL
TRI
107
D16
I
TTLp
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DATA SHEET
RECEIVE AND TRANSMIT PHASE LOCKED LOOPS 144-Lead 208-Lead QFP BGA I/O/P Lead No. Lead No. 16
L3M TXC-03452B
Symbol RCAP
Type
Name/Function
H2
I
Analog Receiver Internal Phase Locked Loop Capacitor: Optional capacitor used for an internal receive phase locked loop. This lead must be left floating. Analog Transmitter Internal Phase Locked Loop Capacitor: Optional capacitor used for an internal transmit phase locked loop. This lead must be left floating.
TCAP
99
G15
I
RECEIVE DESYNCHRONIZER 144-Lead 208-Lead QFP BGA I/O/P Lead No. Lead No. 2 D2 I
Symbol XOSCI
Type CMOS
Name/Function External Oscillator Input: This input is connected to the output of the external VCXO, as shown in the PLL connections diagram (Figure 32). Phase Detector Output: Normally connected to the external low pass filter consisting of external components and the internal amplifier.
CTRL
3
D3
O
CMOS 4mA
AMPINN
5
D4
I
Analog Internal Amplifier - Negative Port Input: Negative port of an internal amplifier which can be used in the desynchronizer loop filter. Analog Internal Amplifier - Positive Port Input: Positive port of an internal amplifier which can be used in the desynchronizer loop filter. Analog Internal Amplifier - Output: Output of an internal amplifier which can be used in the desynchronizer loop filter.
AMPINP
6
E2
I
AMPOUT
7
E1
O
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DATA SHEET
BOUNDARY SCAN TESTING 144-Lead 208-Lead QFP BGA I/O/P Lead No. Lead No. 102 103 104 E13 E14 E15 O(T) I I
L3M TXC-03452B
Symbol TDO TDI TCK
Type
Name/Function
TTL4mA Boundary Scan Test Data Output: Serial data clocked out on negative transitions of TCK. TTL TTL Boundary Scan Test Data Input: Serial data input for boundary scan test messages. Boundary Scan Test Clock: The input clock for boundary scan testing. The TDI and TMS states are clocked in on positive transitions. Boundary Scan Test Mode Select: The signal present on this lead is used to control test operations. Boundary Scan Test Reset: To asynchronously reset the Test Access Port (TAP) controller, this lead must either be held low or asserted low for at least 200 ns and then held high (i.e., pulsed low). The TAP controller may also be reset by holding the TMS signal lead high for at least five clock cycles of TCK. Failure to perform this reset may cause the TAP controller to take control of the output leads. In applications which will not be using the boundary scan feature, this lead must be tied low, thereby holding the TAP controller reset.
TMS TRS
105 106
D14
I I
TTLp TTLp
D15
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DATA SHEET
ABSOLUTE MAXIMUM RATINGS AND ENVIRONMENTAL LIMITATIONS
Parameter Supply voltage DC input voltage Storage temperature range Ambient Operating Temperature Component Temperature x Time Moisture Exposure Level Relative Humidity, during assembly Relative Humidity, in-circuit ESD Classification
Notes: 1. 2. 3. 4. 5.
L3M TXC-03452B
Symbol VDD VIN TS TA TI ME RH RH ESD
Min -0.3 -0.5 -55 -40 5 30 0
Max +7.0 VDD + 0.5 150 85 270 x 5
Unit V V
oC o oC
Conditions Note 1 Notes 1, 3 Note 1 0 ft/min linear airflow Note 1 per EIA/JEDEC JESD22-A112-A Note 2 non-condensing Notes 4, 5
C xs
Level 60 100 % % V
absolute value 2000
Conditions exceeding the Min or Max values may cause permanent failure. Exposure to conditions near the Min or Max values for extended periods may impair device reliability. Pre-assembly storage in non-drypack conditions is not recommended. Please refer to the instructions on the "CAUTION" label on the drypack bag in which devices are supplied. VIN may not exceed the actual operating supply voltage (VDD) by more than 0.5 volt. Test method for ESD per MIL-STD-883D, Method 3015.7. This note applies to product TXC-03452CIOG only. AGND leads F13 and G4 have shown an ESD sensitivity at absolute levels of 1500 volts and above. APWR lead F16, APWR lead G1 and APWR2 lead G16 have shown an ESD sensitivity at absolute levels of 1500 volts and above.
THERMAL CHARACTERISTICS
Parameter 144-lead QFP thermal resistance: junction to ambient 208-lead BGA thermal resistance: junction to ambient Min Typ Max 34 29.0 Unit
oC/W oC/W
Test Conditions 0 ft/min linear airflow 0 ft/min linear airflow
POWER REQUIREMENTS
Parameter VDD IDD Analog VDD Analog IDD Analog VDD2 Analog IDD2 PDD 4.75 5.00 4.75 5.00 Min 4.75 Typ 5.00 Max 5.25 220 5.25 30 5.25 1 1320 Unit V mA V mA V mA mW Inputs switching Test Conditions
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DATA SHEET
INPUT, OUTPUT AND INPUT/OUTPUT PARAMETERS
INPUT PARAMETERS FOR CMOS Parameter VIH VIL Input leakage current Input capacitance 3.5 Min 3.15 1.65 -10 Typ Max Unit V V A pF
L3M TXC-03452B
Test Conditions 4.75 < VDD < 5.25 4.75 < VDD < 5.25 VDD = 5.25; VIN = 0
INPUT PARAMETERS FOR TTL Parameter VIH VIL Input leakage current Input capacitance 3.5 Min 2.0 0.8 -10 Typ Max Unit V V A pF Test Conditions 4.75 INPUT PARAMETERS FOR TTLp Parameter VIH VIL Input leakage current Input capacitance -0.5 3.5 Min 2.0 0.8 -1.4 Typ Max Unit V V mA pF Test Conditions 4.75 < VDD < 5.25 4.75 < VDD < 5.25 VDD = 5.25; VIN = 0
OUTPUT PARAMETERS FOR CMOS 4mA Parameter VOH VOL IOL IOH tRISE tFALL 1.2 0.9 2.8 2.0 Min VDD(MIN) - 0.7 0.4 4.0 -4.0 5.0 4.1 Typ Max Unit V V mA mA ns ns CLOAD = 15pF CLOAD = 15pF Test Conditions VDD = 4.75; IOH = -4.0 VDD = 4.75; IOL = 4.0
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DATA SHEET
OUTPUT PARAMETERS FOR CMOS 8mA Parameter VOH VOL IOL IOH tRISE tFALL 1.2 0.9 2.8 2.0 Min VDD(MIN) - 0.7 0.4 8.0 -8.0 5.0 4.1 Typ Max Unit V V mA mA ns ns
L3M TXC-03452B
Test Conditions VDD = 4.75; IOH = -8.0 VDD = 4.75; IOL = 8.0
CLOAD = 15pF CLOAD = 15pF
INPUT/OUTPUT PARAMETERS FOR TTL 4mA Parameter VIH VIL Input leakage current Input capacitance VOH VOL IOL IOH tRISE tFALL 2.5 1.0 5.5 2.0 2.4V 0.4 4.0 -4.0 10.0 4.0 3.5 Min 2.0 0.8 -10 Typ Max Unit V V A pF V V mA mA ns ns CLOAD = 15pF CLOAD = 15pF VDD = 4.75; IOH = -4.0 (Note 1) VDD = 4.75; IOL = 4.0 (Note 1) Test Conditions 4.75 < VDD < 5.25 4.75 < VDD < 5.25 VDD = 5.25; VIN = 0
INPUT/OUTPUT PARAMETERS FOR TTL 8mA AND TTL 8mA OD (OPEN DRAIN) Parameter VIH VIL Input leakage current Input capacitance VOH VOL (Note 2) IOL (Note 2) IOH tRISE tFALL (Note 2)
Notes: 1. 2.
Min 2.0
Typ
Max
Unit V
Test Conditions 4.75 < VDD < 5.25 4.75 < VDD < 5.25 VDD = 5.25; VIN = 0 VDD = 4.75; IOH = -8.0 (Note 1) VDD = 4.75; IOL = 8.0 (Note 1)
0.8 -10 3.5 2.4V 0.4 8.0 -8.0 1.9 0.8 4.5 1.5 8.0 3.1
V A pF V V mA mA ns ns
CLOAD = 25pF CLOAD = 25pF
Output drivers will output CMOS logic levels into CMOS loads. VOL, IOL and tFALL are the only parameters applicable to TTL 8mA OD.
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DATA SHEET
TIMING CHARACTERISTICS
L3M TXC-03452B
Detailed timing diagrams for the L3M device are illustrated in Figures 7 through 29, with values of the timing intervals tabulated below the diagrams. All output times are measured with a maximum 25 pF load capacitance. Timing parameters are measured at voltage levels of (VIH + VIL)/2 for input signals or (VOH + VOL)/2 for output signals. Figure 7. Line Side Transmit Timing tCYC(1) TCLK (INPUT) tSU TPOS (INPUT) tSU TNEG(LOS Indication) (INPUT) tSU TPOS/TNEG (INPUT) tCYC(2) RNRZC (OUPUT) tOD RNRZD (OUTPUT)
Note: Shown for INVCI equal to 0; data is clocked in on the negative edge when INVCI equals 1. RNRZD is always clocked out on the positive transitions of RNRZC. The delay between the input clock TCLK and output clock RNRZC is not specified.
tPWH(1) tH NRZ Interface
tH
tH
LOS Indication (NRZ mode)
Rail Interface
tPWH(2)
Parameter TCLK clock period TCLK duty cycle, tPWH(1)/tCYC(1) TPOS/TNEG input set-up time to TCLK TPOS/TNEG input hold time after TCLK RNRZC clock period RNRZC duty cycle, tPWH(2)/tCYC(2) RNRZD output delay after RNRZC * 22.35 ns (DS3) or 29.10 ns (E3).
Symbol tCYC(1) -tSU tH tCYC(2) -tOD
Min
Typ *
Max
Unit ns
40 4.0 2.0
50
60
% ns ns
* 40 -2.0 50 60 5.0
ns % ns
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Figure 8. Line Side Receive Timing tCYC RCLK (OUTPUT) tPWL tOD NRZ Interface tOD RPOS/RNEG (OUTPUT) Rail Interface tPWH
L3M TXC-03452B
RPOS (OUTPUT)
Note:
Shown for INVCO equal to 0; data is clocked out on the positive edge when INVCO equals 1. The three signals are forced to a high impedance state when control bit L3Z is set to 1.
Parameter RCLK clock period RCLK high time RCLK low time RCLK duty cycle, tPWH/tCYC (See Note 2) RPOS/RNEG data output delay after RCLK
Notes:
Symbol tCYC tPWH tPWL --tOD
Min
Typ See Note 1 tCYC/2 tCYC/2
Max
Unit ns ns ns
45 -2.0
50
55 5.0
% ns
1. 22.35 ns (DS3) or 29.10 ns (E3). 2. The RCLK output is derived from the XOSCI input from the external VCXO.
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Figure 9. STM-1 Add Bus Derived Interface Timing
tCYC tPWH ACLK (INPUT) tSU(2) ASPE (INPUT) tH(1) AC1J1 (INPUT) ADATA (7-0) APAR (OUTPUTS) ADD (OUTPUT) tSU(1)
C1(1) J1
L3M TXC-03452B
tH(2) tOD(1) tOD(3)
DATA
STUFF BYTE FOR J1
H1 TUG-3
t tOD(4) OD(2)
Note:
The relationship between J1 and the SPE signal is shown for illustration purposes only. For the STM-1 format, there will be one J1 pulse which indicates the start of the VC-4 that carries the three TUG-3s. The TUG-3 added to the bus is shown for the TUG-3 designated as A. TUG-3 B will occur one clock cycle later. There is always a one byte delay between the output ADATA and AC1J1/ASPE inputs.
Parameter ACLK clock period ACLK duty cycle, tPWH/tCYC AC1J1 set-up time to ACLK AC1J1 hold time after ACLK ASPE set-up time to ACLK ASPE hold time after ACLK ADATA(7-0) data and APAR output delay from ACLK ADD low output delay from ACLK ADATA(7-0) and APAR tri-state delay from ACLK ADD high output delay from ACLK
Symbol tCYC -tSU(1) tH(1) tSU(2) tH(2) tOD(1) tOD(2) tOD(3) tOD(4)
Min
Typ 51.44
Max
Unit ns
40 7.0 3.0 10.0 5.0 3.0 3.0 12 12
50
60
% ns ns ns ns
30 25 25 25
ns ns ns ns
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Figure 10. STS-3 Add Bus Derived Interface Timing
tCYC tPWH ACLK (INPUT) tSU(2) ASPE (INPUT) tH(1) AC1J1 (INPUT) ADATA(7-0) APAR (OUTPUTS) ADD (OUTPUT) tSU(1)
C1(1) J1 for STS-1 #1
DATA STS-1#1
L3M TXC-03452B
tH(2) tOD(1) tOD(3)
J1 STS1#1
DATA STS-1#1
tOD(4) tOD(2)
Note:
The relationship between J1 and the SPE signal is shown for illustration purposes only. For the STS-3 format, there will be three J1 pulses which indicate the start of each of the STS-1 SPEs. The STS-1 SPE added to the bus is shown for STS-1 number 1. STS-1 number 2 will occur one clock cycle later. There is always a one byte delay between the output ADATA and AC1J1/ASPE inputs.
Parameter ACLK clock period ACLK duty cycle, tPWH/tCYC AC1J1 set-up time to ACLK AC1J1 hold time after ACLK ASPE set-up time to ACLK ASPE hold time after ACLK ADATA(7-0) data and APAR output delay from ACLK ADD low output delay from ACLK ADATA(7-0) and APAR tri-state delay from ACLK ADD high output delay from ACLK
Symbol tCYC -tSU(1) tH(1) tSU(2) tH(2) tOD(1) tOD(2) tOD(3) tOD(4)
Min
Typ 51.44
Max
Unit ns
40 7.0 3.0 10.0 5.0 3.0 3.0 12 12
50
60
% ns ns ns ns
30 25 25 25
ns ns ns ns
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Figure 11. STS-1 Add Bus Derived Interface Timing
tCYC tPWH ACLK (INPUT) ASPE (INPUT) AC1J1 (INPUT) ADATA(7-0) APAR (OUTPUTS) ADD (OUTPUT) Note: The relationship between J1 and the SPE signal is shown for illustration purposes only. There is always a one byte delay between the output ADATA and AC1J1/ASPE inputs. tSU(1)
C1
L3M TXC-03452B
tH(2) tSU(2) tH(1)
J1
tOD(1)
DATA J1 DATA DATA
tOD(3)
tOD(2) tOD(4)
Parameter ACLK clock period ACLK duty cycle, tPWH/tCYC AC1J1 set-up time to ACLK AC1J1 hold time after ACLK ASPE set-up time to ACLK ASPE hold time after ACLK ADATA(7-0) data and APAR output delay from ACLK ADD low output delay from ACLK ADATA(7-0) and APAR tri-state delay from ACLK ADD high delay from ACLK
Symbol tCYC -tSU(1) tH(1) tSU(2) tH(2) tOD(1) tOD(2) tOD(3) tOD(4)
Min
Typ 154.32
Max
Unit ns
40 7.0 3.0 10.0 5.0 3.0 3.0 12 12
50
60
% ns ns ns ns
30 25 25 25
ns ns ns ns
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Figure 12. STM-1 Drop Bus Interface Timing
tCYC tPWH DCLK (INPUT) tSU DDATA(7-0) DPAR (INPUTS) DSPE (INPUT) DC1J1 (INPUT)
C1(1) C1(2)
L3M TXC-03452B
tH
C1(3) J1 FIXED STUFF FIXED STUFF H1(1) TUG-3 H1(2) TUG-3
tSU
tH
C1(1) J1
Note:
The relationship between J1 and the SPE signals is shown for illustration purposes only, and will be a function of the pointer offset. For the STM-1 format, there will be one J1 pulse which indicates the start of the VC-4 that carries the three TUG-3s. The C1 pulse is shown dotted because the C1 pulse may be provided on the DC1 signal lead. If the DC1 signal lead is not used, it must be grounded.
Parameter DCLK clock period DCLK duty cycle, tPWH/tCYC DDATA(7-0) data/DPAR/DC1J1 set-up time to DCLK DDATA(7-0) data/DPAR/DC1J1 hold time after DCLK
Symbol tCYC -tSU tH
Min
Typ 51.44
Max
Unit ns
40 7.0 3.0
50
60
% ns ns
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Figure 13. STS-3 Drop Bus Interface Timing
tCYC tPWH DCLK (INPUT) tSU DDATA(7-0) DPAR (INPUTS) DSPE (INPUT) DC1J1 (INPUT)
C1(1) C1(2)
L3M TXC-03452B
tH
C1(3) J1 STS-1 #1 SPE STS-1 #2 SPE STS-1 #3 DATA STS-1 #1
tSU
tH
C1(1) J1 for STS-1#1
Note:
The relationship between J1 and the SPE signals is shown for illustration purposes only, and will be a function of the pointer offset. For the STS-3 format, there will be three J1 pulses which indicate the start of each of the STS-1 SPEs. The C1 pulse is shown dotted because the C1 pulse may be provided on the DC1 signal lead. If the DC1 signal lead is not used, it must be grounded.
Parameter DCLK clock period DCLK duty cycle, tPWH/tCYC DDATA(7-0) data/DPAR/DC1J1 set-up time to DCLK DDATA(7-0) data/DPAR/DC1J1 hold time after DCLK
Symbol tCYC -tSU tH
Min
Typ 51.44
Max
Unit ns
40 7.0 3.0
50
60
% ns ns
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Figure 14. STS-1 Drop Bus Interface Timing
tCYC tPWH DCLK (INPUT) tSU DDATA(7-0) DPAR (INPUTS) DSPE (INPUT) tSU DC1J1 (INPUT) tH
C1 J1
C1 DATA
L3M TXC-03452B
tH
DATA J1 DATA DATA DATA
Note:
The relationship between J1 and the SPE signals is shown for illustration purposes only, and will be a function of the pointer offset. For the STS-1 format, there will be one J1 pulse which indicates the start of the STS-1 SPE. The C1 pulse is shown dotted because the C1 pulse may be provided on the DC1 signal lead. If the DC1 signal lead is not used, it must be grounded.
Parameter DCLK clock period DCLK duty cycle, tPWH/tCYC DDATA(7-0) data/DPAR/DC1J1 set-up time to DCLK DDATA(7-0) data/DPAR/DC1J1 hold time after DCLK
Symbol tCYC -tSU tH
Min
Typ 154.32
Max
Unit ns
40 7.0 3.0
50
60
% ns ns
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Figure 15. STS-1 Add Bus Interface Timing Using an External Clock
tH min = 3 ns
L3M TXC-03452B
tSU XC1 (INPUT) tPWH(1) XCLKI (INPUT) tOD(3)
min = 7 ns
tOD min = 7 ns
max = 25 ns
tCYC(1)
tCYC(2) tPWH(2)
ACLK (OUTPUT) tOD(1) ASPE (OUTPUT) tOD(1)
AC1J1 (OUTPUT) ADATA(7-0) APAR (OUTPUTS) ADD (OUTPUT) Note:
C1
J1
tOD(2)
DATA A1 A2 C1 = 01 DATA h1 h2 h3 J1 R=00 R=00
(LOW)
Timing is shown for STS-1 signal. Pointer value is transmitted with a value equal to 0. When the TOHOUT bit is set to 1, the A1, A2, C1, H1, and H2 bytes are generated. Different from add/drop mode, output AC1J1/ASPE and ADATA are synchronous in the external clock mode.
Parameter XCLKI clock period XCLKI duty cycle, tPWH(1)/tCYC(2) ACLK clock period ACLK duty cycle, tPWH(2)/tCYC(2) AC1J1/ASPE delay after ACLK ADATA(7-0) data and APAR delay after ACLK ACLK clock delay after XCLKI
Symbol tCYC(1) -tCYC(2) -tOD(1) tOD(2) tOD(3)
Min
Typ 154.32
Max
Unit ns
40
50 154.32
60
% ns
40 0.0 0.0 3.0
50
60 5.0 12 25
% ns ns ns
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Figure 16. STM-1 Add/Drop Bus Interface Timing
tCYC tPWH
L3M TXC-03452B
DCLK (INPUT)
tSU(1) tH(1)
C1(3) DATA DATA DATA J1
FIXED STUFF FIXED STUFF
DDATA(7-0) DPAR (INPUTS) DSPE (INPUT)
tSU(1)
C1(1)
C1(2)
H1(1) TUG-3
H1(2) TUG-3
tH(2) tSU(2)
tH(1)
C1(1) J1
DC1J1 (INPUT) ADATA(7-0) APAR (OUTPUTS) ADD (OUTPUT) Note:
tOD(1)
DATA
FIXED STUFF FOR J1
tOD(2)
tOD(3)
tOD(4)
The relationship between J1 and the SPE signals is shown for illustration purposes only, and will be a function of the pointer offset. For the STM-1 format, there will be one J1 pulse which indicates the start of the VC-4 that carries the three TUG-3s. The C1 pulse is shown dotted because the C1 pulse may be provided on the DC1 signal lead. If the DC1 signal lead is not used, it must be grounded. Shown is TUG-3 A being added to the Add bus.
Parameter DCLK clock period DCLK duty cycle, tPWH/tCYC DDATA(7-0) data/DPAR/DC1J1 set-up time to DCLK DDATA(7-0) data/DPAR/DC1J1 hold time after DCLK DSPE set-up time to DCLK DSPE hold time after DCLK ADATA(7-0) data and APAR delay after DCLK ADD indicator delayed after DCLK ADATA(7-0) data and APAR tri-state after DCLK ADD high after DCLK
Symbol tCYC -tSU(1) tH(1) tSU(2) tH(2) tOD(1) tOD(2) tOD(3) tOD(4)
Min
Typ 51.44
Max
Unit ns
40 7.0 3.0 10.0 5.0 3.0 3.0 12 12
50
60
% ns ns ns ns
30 25 25 25
ns ns ns ns
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Figure 17. STS-3 Add/Drop Bus Interface Timing
tCYC tPWH DCLK (INPUT) tSU(1) DDATA(7-0) DPAR (INPUTS) DSPE (INPUT) tSU(1) DC1J1 (INPUT) ADATA(7-0) APAR (OUTPUTS) ADD (OUTPUT) Note:
C1(1)
C1(1) C1(2)
L3M TXC-03452B
tH(1)
C1(3) DATA DATA DATA J1
FIXED STUFF FIXED STUFF
tSU(2) tH(1)
tH(2)
J1
tOD(1)
DATA
J1 DATA
tOD(3)
tOD(2) tOD(4) The relationship between J1 and the SPE signals is shown for illustration purposes only, and will be a function of the pointer offset. For the STS-3 format, there will be three J1 pulses with each J1 pulse indicating the start of an STS-1. The C1 pulse is shown dotted because the C1 pulse may be provided on the DC1 signal lead. If the DC1 signal lead is not used, it must be grounded. Shown is STS-1 number 1 being added to the Add bus.
Parameter DCLK clock period DCLK duty cycle, tPWH/tCYC DDATA(7-0) data/DPAR/DC1J1 set-up time to DCLK DDATA(7-0) data/DPAR/DC1J1 hold time after DCLK DSPE set-up time to DCLK DSPE hold time after DCLK ADATA(7-0) data and APAR delay after DCLK ADD indicator delayed after DCLK ADATA(7-0) data and APAR tri-state after DCLK ADD indicator high after DCLK
Symbol tCYC -tSU(1) tH(1) tSU(2) tH(2) tOD(1) tOD(2) tOD(3) tOD(4)
Min
Typ 51.44
Max
Unit ns
40 7.0 3.0 10.0 5.0 3.0 3.0 12 12
50
60
% ns ns ns ns
30 25 25 25
ns ns ns ns
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Figure 18. STS-1 Add/Drop Bus Interface Timing
tCYC tPWH DCLK (INPUT) tSU(1) DDATA(7-0) DPAR (INPUTS) DSPE (INPUT) tSU(1) DC1J1 (INPUT) ADATA(7-0) APAR (OUTPUTS)
C1(3)
C1 SPE
L3M TXC-03452B
tH(1)
J1 SPE SPE
tSU(2)
tH(2)
tH(1)
J1
tOD(1)
SPE J1 SPE SPE
tOD(3)
tOD(2) ADD (OUTPUT) Note:
tOD(4)
The relationship between J1 and the SPE signals is shown for illustration purposes only, and will be a function of the pointer offset. For the STS-1 format, there will be one J1 pulse which indicates the start of the STS-1. The C1 pulse is shown dotted because the C1 pulse may be provided on the DC1 signal lead. If the DC1 signal lead is not used, it must be grounded.
Parameter DCLK clock period DCLK duty cycle, tPWH/tCYC DDATA(7-0) data/DPAR/DC1J1 set-up time to DCLK DDATA(7-0) data/DPAR/DC1J1 hold time after DCLK DSPE set-up time to DCLK DSPE hold time after DCLK ADATA(7-0) data and APAR delay after DCLK ADD indicator delayed after DCLK ADATA(7-0) data and APAR tri-state after DCLK ADD indicator high after DCLK
Symbol tCYC -tSU(1) tH(1) tSU(2) tH(2) tOD(1) tOD(2) tOD(3) tOD(4) - 38 of 96 -
Min
Typ 154.32
Max
Unit ns
40 7.0 3.0 10.0 5.0 3.0 3.0 12 12
50
60
% ns ns ns ns
30 25 25 25
ns ns ns ns
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Figure 19. Transmit Path Overhead Timing
L3M TXC-03452B
tPWL tPWH TPOHC (OUTPUT) TPOHF (OUTPUT) tSU TPOHD (INPUT)
Bit 1 J1 Bit 2 J1 Bit 3 J1 Bit 4 J1 Bit 5 J1 Bit 6 J1 Bit 7 J1
tPWH
tD tPW tH
Bit 8 J1
Bit 1 B3
Note: The clock cycle that corresponds to bit 8 in each overhead byte is stretched.
Parameter TPOHC high time TPOHC low time TPOHF output delay after TPOHC TPOHD set-up time to TPOHC TPOHD data hold time after TPOHC TPOHF pulse width
Symbol tPWH tPWL tD tSU tH tPW
Min 617
Typ
Max 3395
Unit ns ns
771.7 -2.0 7.0 3.0 1388.9 5.0
ns ns ns ns
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Figure 20. Receive Path Overhead Timing
L3M TXC-03452B
tPWL tPWH RPOHC (OUTPUT) RPOHF (OUTPUT) RPOHD (OUTPUT) tD(1) tPW tD(2)
Bit 8 Z5 Bit 1 J1 Bit 2 J1 Bit 3 J1 Bit 4 J1 Bit 5 J1 Bit 6 J1 Bit 7 J1
tPWL
Bit 8 J1
Bit 1 B3
Note: The clock cycle that corresponds to bit 8 in each overhead byte is stretched.
Parameter RPOHC low time RPOHC high time RPOHF output delay after RPOHC RPOHD output delay after RPOHC RPOHF pulse width
Symbol tPWL tPWH tD(1) tD(2) tPW
Min 617
Typ
Max 3395
Unit ns ns
771.7 -2.0 -2.0 1388.9 5.0 5.0
ns ns ns
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Figure 21. Transmit Alarm Indication Port Timing
L3M TXC-03452B
tPWL tPWH TAIPC (INPUT) tSU(1) TAIPF (INPUT) tSU(2) TAIPD (INPUT)
Bit 1 Byte1 Bit 2 Byte 1 Bit 3 Byte 1 Bit 4 Byte 1 Bit 5 Byte 1 Bit 6 Byte 1 Bit 7 Byte 1
tPWL
tH(1)
tH(2)
Bit 8 Byte 1
Bit 1 Byte 2
Note:
Alarm indication byte consists of eight bits and is repeated nine times. Bit 8 in each byte is stretched. The first four bits correspond to the FEBE count (bits 1 through 4 in G1), bit 5 is the path RDI value, and bits 6 and 7 are set to 0, while bit 8 is set to 1.
Parameter TAIPC low time TAIPC high time TAIPF set-up time to TAIPC TAIPF hold time after TAIPC TAIPD set-up time to TAIPC TAIPD set-up time after TAIPC
Symbol tPWL tPWH tSU(1) tH(1) tSU(2) tH(2)
Min 617
Typ
Max 3395
Unit ns ns ns ns ns ns
771.7 7.0 3.0 7.0 3.0
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Figure 22. Receive Alarm Indication Port Timing tPWL tPWH RPOHC (OUTPUT) RPOHF (OUTPUT) tD(1) tPW tD(2)
Bit 1 Byte 1 Bit 2 Byte 1 Bit 3 Byte 1 Bit 4 Byte 1 Bit 5 Byte 1 Bit 6 Byte 1 Bit 7 Byte 1 Bit 8 Byte 1
L3M TXC-03452B
tPWL
RAIPD Bit 8 Byte 9 (OUTPUT)
Note:
Bit 1 Byte 2
Alarm indication byte consists of eight bits and is repeated nine times. Bit 8 in each byte is stretched. The first four bits correspond to the FEBE count (bits1 through 4 in G1), bit 5 is the path RDI value, and bits 6 and 7 are set to 0, while bit 8 is set to 1.
Parameter RPOHC low time RPOHC high time RPOHF output delay after RPOHC RAIPD output delay after RPOHC RPOHF pulse width
Symbol tPWL tPWH tD(1) tD(2) tPW
Min 617
Typ
Max 3395
Unit ns ns
771.7 -2.0 -2.0 1388.9 5.0 5.0
ns ns ns
Figure 23. Transmit Overhead Communications Channel Timing tPWH TOCHC (OUTPUT) tPWL tH tSU TOCHD (INPUT)
Parameter TOCHC high time TOCHC low time TOCHD set-up time to TOCHC TOCHD hold time after TOCHC
Symbol tPWH tPWL tSU tH - 42 of 96 -
Min 617
Typ
Max 11729
Unit ns ns ns ns
TXC-03452B-MB Ed. 6, April 2001
771.2 7.0 3.0
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Figure 24. Receive Overhead Communications Channel Interface Timing
L3M TXC-03452B
tPWH ROCHC (OUTPUT) tD ROCHD (OUTPUT) tPWL
Parameter ROCHC high time ROCHC low time ROCHD output delay after ROCHC
Symbol tPWH tPWL tD
Min 617
Typ
Max 11729
Unit ns ns
771.2 -2.0 5.0
ns
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Figure 25. Intel Microprocessor Read Cycle Timing
L3M TXC-03452B
A (7-0)
tH(1)
D(7-0)
tD(1) tSU(1)
tF(1)
SEL
tSU(2)
RD
tH(2) tPW(1)
tF(2)
tD(2)
RDY
tD(3) tPW(2)
Parameter A(7-0) address hold time after RD A(7-0) address set-up time to SEL D(7-0) data valid delay after RDY D(7-0) data float time after RD RD pulse width SEL set-up time to RD SEL hold time after RD RDY delay after SEL RDY delay after RD RDY pulse width * RDY float time after SEL
Symbol tH(1) tSU(1) tD(1) tF(1) tPW(1) tSU(2) tH(2) tD(2) tD(3) tPW(2) tF(2)
Min 3.0 0.0
Typ
Max
Unit ns ns
7.0 6.0 40.0 10.0 0.0 10.0 16.0 0.0 48 * Rcyc 10.0
ns ns ns ns ns ns ns s ns
* Note: RDY goes low when the address being read corresponds to a RAM location but remains high during status or control register access. Rcyc is the period, in nanoseconds, of the RAM clock (RAMCI) (e.g., RAMCI @ 25MHz yields tPW(2) = 1.92s max)
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Figure 26. Intel Microprocessor Write Cycle Timing
tH(1)
L3M TXC-03452B
A(7-0)
tH(2)
D(7-0)
tSU(2) tSU(1)
SEL
tSU(4)
tSU(3)
WR
tPW(1) tD(1) tD(2)
tF
RDY
tPW(2)
Parameter A(7-0) address hold time after WR A(7-0) address set-up time to SEL D(7-0) data valid set-up time to WR D(7-0) data hold time after WR SEL set-up time to WR WR pulse width RDY delay after SEL RDY delay after WR RDY pulse width * RDY float time after SEL RAM cycle D(7-0) valid set-up time to WR
Symbol tH(1) tSU(1) tSU(2) tH(2) tSU(3) tPW(1) tD(1) tD(2) tPW(2) tF tSU(4)
Min 3.0 0.0 8.0 6.0 10.0 40.0
Typ
Max
Unit ns ns ns ns ns ns
10.0 16.0 0.0 48 * Rcyc 10.0 -2 * Rcyc
ns ns ns ns ns
* Note: RDY goes low when the address being written to corresponds to a RAM location but remains high during status or control register access. Rcyc is the period, in nanoseconds, of the RAM clock (RAMCI) (e.g., RAMCI @ 25MHz yields: tSU(4)=-80ns min, tPW(2) = 1.92s max)
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Figure 27. Motorola Microprocessor Read Cycle Timing
tH(1)
A(7-0)
L3M TXC-03452B
D(7-0)
tSU(1)
tF(1) tPW(1) tSU(2) tH(3)
SEL
RD/WR
tD(1)
tPW(2)
DTACK
tF(2)
tD(2)
Parameter A(7-0) address hold time after SEL A(7-0) address valid set-up time to SEL D(7-0) data valid delay after DTACK D(7-0) data float time after SEL SEL pulse width RD/WR set-up time to SEL RD/WR hold time after SEL DTACK delay after SEL DTACK pulse width DTACK float time after SEL
Note:
Symbol tH(1) tSU(1) tD(1) tF(1) tPW(1) tSU(2) tH(3) tD(2) tPW(2) tF(2)
Min 3.0 10.0
Typ
Max
Unit ns ns
5.0 6.0 40.0 5.0 3.0 16.0 0.0 48 * Rcyc 10.0
ns ns ns ns ns ns s ns
Rcyc is the period, in nanoseconds, of the RAM clock (RAMCI) (e.g., RAMCI @ 25 MHz yields tPW(2) = 1.92s max).
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Figure 28. Motorola Microprocessor Write Cycle Timing tH(1)
A(7-0)
L3M TXC-03452B
tH(2)
D(7-0)
tSU(2) tSU(4)
SEL
tSU(1) tSU(3)
RD/WR
tPW(1)
tH(3)
tPW(2)
DTACK
tF
tD
Parameter A(7-0) address hold time after SEL A(7-0) address valid set-up time to SEL D(7-0) data valid set-up time to SEL D(7-0) data hold time after SEL SEL pulse width RD/WR set-up time to SEL RD/WR hold time after SEL DTACK delay after SEL DTACK pulse width DTACK float time after SEL RAM cycle D(7-0) valid set-up time to SEL
Note:
Symbol tH(1) tSU(1) tSU(2) tH(2) tPW(1) tSU(3) tH(3) tD tPW(2) tF tSU(4)
Min 3.0 10.0 8.0 6.0 40.0 5.0 3.0
Typ
Max
Unit ns ns ns ns ns ns ns
15.0 0.0 48 * Rcyc 10.0 -2 * Rcyc
ns ns ns ns
Rcyc is the period, in nanoseconds, of the RAM clock (RAMCI) (e.g., RAMCI @ 25MHz yields: tSU(4)=-80ns min, tPW(2) = 1.92s max).
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Figure 29. Boundary Scan Timing
L3M TXC-03452B
tPWL tPWH
TCK (Input)
tH(1) tSU(1)
TMS (Input)
tH(2) tSU(2)
TDI (Input)
tD
TDO (Output)
Parameter TCK clock high time TCK clock low time TMS setup time to TCK TMS hold time after TCK TDI setup time to TCK TDI hold time after TCK TDO output delay after TCK
Symbol tPWH tPWL tSU(1) tH(1) tSU(2) tH(2) tD
Min 50 50 3.0 5.0 6.0 5.0 -
Max
Unit ns ns
10
ns ns ns ns ns
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OPERATION
L3M POWER-UP RESET SEQUENCE
L3M TXC-03452B
The L3M requires that the clocks are valid and stable for a minimum of 200 nanoseconds in order for a reset to take effect (refer to Hardware Reset function, RESET, lead 86 or K14). The sequence shown in Figure 30 is recommended on L3M power-up: 1. When a system reset is initiated, the L3M input leads RESET and TRI are set low at the same time. 2. The L3M RESET lead is held low for a minimum of 200 nanoseconds after the system reset has been completed and all of the L3M clocks have become stable. 3. The L3M TRI lead then remains low to hold the L3M outputs with tri-state capability in the tri-state condition until the TUG-3 position in register C0H has been programmed. 4. Once the L3M is programmed for the assigned TUG-3 in register C0H, the TRI lead is set high and the L3M will lock to the C1 pulse and map data to and from the positions selected by the DPOSn and APOSn settings.
System reset 200 ns (Min.) Sys Reset
L3M configuration reg. C0H should be programmed during this time.
L3M RESET
L3M TRI
Figure 30. L3M Power-Up Reset Sequence
For application circuit boards that require the capability for hot insertion, a suitable circuit must be included to ensure that the L3M RESET and TRI input leads are forced low until the L3M power supply leads have all reached the normal operating voltage range. It is important to remember that, when reading the latched registers in the L3M, the contents should be read a second time before determining the current status.
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Figure 31. Physical Design For Analog Power Distribution
L3M TXC-03452B
0.01F 0.01F APWR Leads 10,14,101 APWR2 Leads 18,98
108 109
*
101
*
98
73 72
L3M PQFP
Top View
EMI 25-120 MHz Digi-Key Part No. P9809
144
1 10
14
18
36
37
+ 5V
*
10 F 0.01 F (3 places)
*
*
* *
10 F EMI 25-120 MHz Digi-Key Part No. P9809
+ 5V
Note: The 10 F capacitors may be polarized types.
Separate power islands should be used for APWR and APWR2, as shown in Figure 31. Traces should be kept as short as possible when connecting the EMI filter to the analog power planes. Place the 0.01 microfarad decoupling capacitors as close as possible to the associated device lead and on the same board side as the L3M. Place the 10 microfarad capacitors close to the EMI filters. Leads 1, 36, 37, 72, 73, 108, 109 and 144 are shown for reference only, they are not connected to the APWR or APWR2 power islands. Similar design considerations apply to the PBGA package.
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PLL FILTER CONNECTION TO VCXO
L3M TXC-03452B
The Desynchronize Block in the receive line side path contains a phase-locked loop (PLL) circuit, which must be connected to an external voltage-controlled crystal oscillator (VCXO) via an external filter. This arrangement is designed to meet limits for jitter on the asynchronous line output signal, which is due to signal mapping and pointer movements. Figure 32 shows the external filter circuit that is recommended for connecting the L3M PLL circuit to the VCXO. Figure 33 shows the jitter results obtained with the circuit shown in Figure 32. Figure 32. PLL Connection to External VCXO
R1 806k C2 0.01 C3 3.2
R2 3M
Inverter Internal Op Amp
(See Notes 6, 9) CTRL 3, D3 U1
AMPINN 5, D4 AMPINP 6, E2 C1 0.1 GND 13, G2 XOSCI 2, D2
+
AMPOUT 7, E1 R3
L3M Device TXC-03452B
(See Note 7) R4 X1
1k
VCXO
Termination (See Note 5)
Notes: 1. The VCXO PLL filter design is a 2-pole integrator that is designed to supply reliable jitter performance and capture range with good margins for implementation in high volume production applications. Due to the characteristics of the filter network the signal at AMPOUT will go to a rail in the absence of a DS3/E3 signal in the SONET/ SDH payload. In systems that experience extended Loss of Signal in the TUG-3/STS payload, this characteristic can cause long capture times, which can exceed 30 seconds. 2. This filter arrangement can be used for TUG-3/DS3, TUG-3/E3, STS-1/DS3 and STS-3/STS-1/DS3 mapping modes. It provides a bandwidth of 0.3 Hz for DS3 and 0.23 Hz for E3. 3. All resistance () and capacitance (F) values must be within 5% and 10%, respectively, of the values shown to meet the requirements of Figure 33. Two components in series or parallel may be used, where needed. 4. All capacitors must be high quality, non-polarized ceramic types. 5. Termination resistor R4 must be chosen to suit the physical design adopted (e.g., 75 or 50 ohms). 6. Inverter U1 is a Signetics 74HCT04 or equivalent. 7. VCXO X1 is a Fordahl DFV 14-MHR 44.736 MHz V14112 or DFV 14-KHR 34.368 MHz V14111 or equivalent, depending on the application signal rate. 8. Setting the DIV4 bit (bit 4 in register C7) controls the gain of the phase detector. This bit must be set to 1. 9. Setting the INVCTRL bit (bit 3 in register C7) controls the polarity of the CTRL signal on lead 3 or D3. This bit must be set to 0 for the circuit shown, which provides the results tabulated in Figure 33. Control bit INVCTRL allows the use of an external circuit that does not include the inverter U1, if INVCTRL is set to 1. 10. Please contact the TranSwitch Applications Engineering Department if questions arise concerning the PLL filter design and characteristics.
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L3M TXC-03452B
L3M Jitter Results for STS-3/DS3 Mapping Bellcore, GR-253-CORE, Rev. 2, Jan 1999 Mapping Jitter Single Pointer Adjustment Pointer Adjustment Burst Phase Transient Pointer Adjustment Burst Periodic Pointer Adjustments without added or canceled pointer adjustments Periodic Pointer Adjustments with added or canceled pointer adjustments Periodic Pointer Adjustments Continuous Pattern Periodic Pointer Adjustments Continuous Pattern with added or canceled pointer adjustment Maximum Measured Jitter (UI P-P) 0.16 0.12 0.38 0.19 0.47 (T = 34 ms) 0.13 (T = 10 s) 0.54 (T = 34 ms) 0.16 (T = 10 s) 0.08 (T = 34 ms) 0.14 (T = 10 s) 0.17 (T = 34 ms) 0.24 (T = 10 s) 1.3 1.0 1.3 Maximum Jitter Specified by GR-253-CORE (UI P-P) 0.4 A0 + 0.3 1.3 1.2 1.0
L3M Jitter Results for TUG-3/E3 Mapping PA Sequence specified by ETSI document ETS-DE/TM-1015-1:Nov-93 A B C D E Maximum Measured Jitter (UI P-P) HP1/LP 0.021 0.024 0.028 0.026 0.026 HP2/LP 0.012 0.016 0.016 0.016 0.016 0.4 0.75 0.4 0.4 Maximum Allowed Jitter (UI P-P) Specified by ETS-DE/TM-1015-1:Nov-93 HP1/LP HP2/LP 0.075 0.75 0.75 0.75 0.75
Figure 33. Jitter Results for STS-3/DS3 and TUG-3/E3 Mappings
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TESTING Loopbacks
L3M TXC-03452B
Three loopback capabilities are provided: facility, line and SDH/SONET. Diagrams illustrating the three types of loopback are provided in the Memory Map Descriptions Section, Address C1, Bits 2-0. Writing a 1 to control bit FLBK enables facility loopback. Facility loopback and line loopback operations are shown in Figure 34. When facility loopback is enabled, the internal DS3/E3 transmit signal becomes the internal receive signal. Either interface may be used, P/N rail or NRZ. Line loopback is enabled by writing a 1 to control bit L3LBK. The DS3/E3 receive output becomes the transmit line input. The receive output may be P/N rail or NRZ. Writing a 1 to control bit SLBK enables a SDH/SONET loopback. SDH/SONET loopback disables the STM-1/ STS-3/STS-1 signal input on the drop bus, and enables the add signals to become the drop bus signals. The add signals are provided at the add bus. Test Generators and Analyzers Two pseudo-random binary sequence (PRBS) test generators are provided, as shown in Figure 34. Each generator can provide a 215-1 or 223-1 pseudo-random pattern. The test sequence of 223-1 is selected when a 1 is written into control bit PAT23. When PAT23 is 0, the pattern is 215-1. The transmit test generator is enabled by writing a 1 to control bit TPRBS. When enabled, the transmit test generator transmits the pseudo-random pattern in place of transmit NRZ data. The transmit test generator must have a clock signal provided at the Transmit Line Clock (TCLK) input lead in order to generate a test pattern. For applications where no transmit line clock is present and the system is required to generate a transmit PRBS signal, a Loss of Clock detection circuit and a circuit to multiplex the transmit line clock and the AISCLK should be used externally to maintain a valid clock, as shown in Figure 34. The receive test generator is enabled by writing a 1 to control bit RPRBS. When enabled, the receive test generator inserts the pseudo-random test pattern in place of the received desynchronized NRZ data. The test analyzer is enabled by writing a 1 to control bit ENANA. The test sequence of 223-1 is selected when a 1 is written into control bit PAT23. Receive NRZ data is analyzed when a 0 is written to control bit TXANA. When a 1 is written to control bit TXANA, the transmit NRZ data path is monitored. The selection of the test analyzer disables the decoder CV output to the 16-bit counter. The 16-bit counter now counts received errors from the test analyzer, when the analyzer is in lock.
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Figure 34. Loopbacks, Test Generators and Analyzer
L3M TXC-03452B
AISCLK LOS DET TPRBS 1 0 HDB3/ B3ZS Decoder TX PRBS Generator TCLK 0 1 L3LBK Line In (TX DS3/E3)
TLAISGN To Synchronizer 1 0 AIS Generator
CVs Errors
0 1 Counter
Facility Loopback AISCLK
1 0 TXANA
PRBS Analyzer
ENANA
AIS Generator
RAISGN 1 RPRBS 0 1 FLBK 0 1 HDB3/ B3ZS Coder Line Out (RX DS3/E3) Line Loopback
from desynchronizer
0
1 RX PRBS Generator XOSCI (VCXO) 0 RAISGN
Figure 35. External Circuit to Maintain Clock Input to TX PRBS Generator TCLK Input Lead TX PRBS Generator TCLK Detect
AISCLK
TCLK
L3M
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BOUNDARY SCAN Introduction
L3M TXC-03452B
The IEEE 1149.1 standard defines the requirements of a boundary scan architecture that has been specified by the IEEE Joint Test Action Group (JTAG). Boundary scan is a specialized scan architecture that provides observability and controllability for the interface leads of the device. As shown in Figure 36, one cell of a boundary scan register is assigned to each input or output lead to be observed or tested (bidirectional leads may have two cells). The boundary scan capability is based on a Test Access Port (TAP) controller, instruction and bypass registers, and a boundary scan register bordering the input and output leads. The boundary scan test bus interface consists of four input signals (Test Clock (TCK), Test Mode Select (TMS), Test Data Input (TDI) and Test Reset (TRS)) and a Test Data Output (TDO) output signal. Boundary scan signal timing is shown in Figure 29. The TAP controller receives external control information via a Test Clock (TCK) signal and a Test Mode Select (TMS) signal, and sends control signals to the internal scan paths. The TAP controller is reset by asserting the TRS lead low for a minimum of 5 nanoseconds. Detailed information on the operation of this state machine can be found in the IEEE 1149.1 standard. The serial scan path architecture consists of an instruction register, a boundary scan register and a bypass register. These three serial registers are connected in parallel between the Test Data Input (TDI) and Test Data Output (TDO) signals, as shown in Figure 36. The boundary scan function will be reset and disabled by holding lead TRS low. When boundary scan testing is not being performed the boundary scan register is transparent, allowing the input and output signals to pass to and from the L3M device's internal logic. During boundary scan testing, the boundary scan register may disable the normal flow of input and output signals to allow the device to be controlled and observed via scan operations. Boundary Scan Operation The maximum frequency the L3M device will support for boundary scan is 10 MHz. The timing diagrams for the boundary scan interface leads are shown in Figure 29. The instruction register contains three bits. The L3M device performs the following three boundary scan test instructions: The EXTEST test instruction (000) provides the ability to test the connectivity of the L3M device to external circuitry. The SAMPLE test instruction (010) provides the ability to examine the boundary scan register contents without interfering with device operation. The BYPASS test instruction (111) provides the ability to bypass the L3M boundary scan and instruction registers. During the Capture - IR state, a fixed value (101) is loaded into the instruction register.
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Figure 36. Boundary Scan Schematic
L3M TXC-03452B
Boundary Scan Register
CORE LOGIC OF L3M DEVICE
Signal input and output leads (solder balls on bottom surface of PBGA package)
Instruction Register Bypass Register TAP Controller
TDI
3 Controls IN OUT Boundary Scan Serial Test Data
TDO
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Boundary Scan Chain
L3M TXC-03452B
There are 104 scan cells in the L3M boundary scan chain. Bidirectional signals require two scan cells. Additional scan cells are used for direction control as needed. A boundary scan description language (BSDL) source file for each package type is available via the Products page of the TranSwitch World Wide Web site (www.transwitch.com). The following table shows the listed order of the scan cells and their function. Scan Cell No. 103 102 Input/Output Input --PQFP (PBGA) Lead No. 107 (D16) --Symbol TRI (L3 out ctrl) Comments See Note 1 (at end of table). When low, leads 92 (H13), 93 (H14), 142 (B3), 143 (A2) and 144 (A1) are set to a high impedance state. See Note 1.
101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84
Input Input Input Input Input Input Input Input Input Input Input Input Input --Input Output (3-state) Output (3-state) ---
109 (C14) 110 (A15) 111 (A14) 113 (A13) 114 (D13) 115 (B12) 116 (C12) 117 (D12) 118 (B11) 119 (C11) 120 (D11) 122 (A10) 123 (C10) --124 (D10) 128 (C8) 129 (B8) ---
TPOS TNEG TCLK A0 A1 A2 A3 A4 A5 A6 A7 WR RD or RD/WR (Rdy Ctrl) SEL RDY/DTACK INT/IRQ (P D(7-0) Ctrl) When low, leads 133 thru 140 (C4, B5, A5, C5, B6, A6, C6 and D6) are set to a high impedance state. See Note 1. When low, lead 128 (C8) is set to a high impedance state. See Note 1.
83 82
Input ---
130 (C7) ---
RAMCI (INT/IRQ Ctrl) When low, lead 129 (B8) is set to a high impedance state. See Note 1.
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Scan Cell No. 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 PQFP (PBGA) Lead No. 131 (B7) 133 (D6) 133 (D6) 134 (C6) 134 (C6) 135 (A6) 135 (A6) 136 (B6) 136 (B6) 137 (C5) 137 (C5) 138 (A5) 138 (A5) 139 (B5) 139 (B5) 140 (C4) 140 (C4) 143 (A2) 144 (A1) 1 (C2) 2 (D2) 3 (D3) 8 (E3) 11 (F3) 21 (J2) 22 (K4) 25 (L4) 26 (L3) 28 (L2) 30 (M3)
L3M TXC-03452B
Input/Output Input Output (3-state) Input Output (3-state) Input Output (3-state) Input Output (3-state) Input Output (3-state) Input Output (3-state) Input Output (3-state) Input Output (3-state) Input Output (3-state) Output (3-state) Input Input Output (2-state) Output (2-state) Output (2-state) Output (2-state) Output (2-state) Output (2-state) Output (2-state) Output (2-state) Output (2-state)
Symbol MOTO D0 (out) D0 (in) D1 (out) D1 (in) D2 (out) D2 (in) D3 (out) D3 (in) D4 (out) D4 (in) D5 (out) D5 (in) D6 (out) D6 (in) D7 (out) D7 (in) RPOS RNEG AISCLK XOSCI CTRL NC FIFOERR NC NC ROCHD ROCHC RAIPD RPOHD
Comments
Not used
Not used Not used
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Scan Cell No. 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 PQFP (PBGA) Lead No. 31 (M1) 32 (M2) 35 (N2) 36 (P1) 40 (R4) 41 (T4) 42 (N4) 43 (T5) 44 (P5) 45 (R6) 46 (T6) 47 (N6) 49 (R7) 50 (T7) 51 (P7) 52 (N7) 53 (R8) 57 (T9) 58 (R9) 58 (R9) 59 (N10) 59 (N10) 60 (T10) 61 (R10) 61 (R10) 63 (N11) 64 (T11) 65 (R11) 66 (P12) 67 (T12)
L3M TXC-03452B
Input/Output Output (2-state) Output (2-state) Output (2-state) Output (2-state) Input Input Input Input Input Input Input Input Input Input Input Input Input Output (3-state) Output (3-state) Input Output (3-state) Input Output (2-state) Output (3-state) Input Output (3-state) Output (3-state) Output (3-state) Output (3-state) Output (3-state)
Symbol RPOHF RPOHC NC NC DDATA7 DDATA6 DDATA5 DDATA4 DDATA3 DDATA2 DDATA1 DDATA0 DC1 DPAR DCLK DC1J1 DSPE APAR ASPE ASPE AC1J1 AC1J1 ADD ACLK ACLK ADATA7 ADATA6 ADATA5 ADATA4 ADATA3
Comments
Not used Not used
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Scan Cell No. 21 20 19 18 PQFP (PBGA) Lead No. 68 (P13) 69 (R13) 70 (T14) ---
L3M TXC-03452B
Input/Output Output (3-state) Output (3-state) Output (3-state) ---
Symbol ADATA2 ADATA1 ADATA0 (APAR, ADATA(7-0) Ctrl)
Comments
When low, leads 57 (T9), 63 thru 70 (N11, T11, R11, P12, T12, P13, R13 and T14) are set to a high impedance state. See Note 1.
17 16
Input ---
75 (N13) ---
XCLKI (SPE Ctrl) When low, leads 58 (R9), 59 (N10), and 61 (R10) are set to a high impedance state. See Note 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Input Input Output (2-state) Output (2-state) Input Input Input Input Input Output (2-state) Input Output (3-state) Output (3-state) Input Input Input
76 (M15) 77 (M16) 79 (M13) 80 (L15) 81 (L16) 83 (L13) 84 (K15) 85 (K16) 86 (K14) 90 (J14) 91 (J13) 92 (H13) 93 (H14) 94 (H16) 95 (H15) 96 (G13)
XC1 XCLKE TPOHC TPOHF TPOHD TAIPC TAIPF TAIPD RESET TOCHC TOCHD RNRZD RNRZC STAI PAIS ISTAT
Note 1: All outputs are disabled when the High Impedance Enable input (TRI, lead 107 (D16)) is low, except during EXTEST, when the direction control Scan Cells (numbers 16 (H2), 18 (J4), 82 (L14), 84 (K15), 88 (J15), 102 (E13) and 103 (E14)) take precedence.
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MEMORY MAP
L3M TXC-03452B
Please note that all control registers (C0H to CAH) and the FIFO Leak Rate Register (A0H) must be initialized to 00H value unless otherwise specified below or required by the application. CONTROL BITS Address (Hex)
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA
Mode*
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7
TUG3 DECODE ALM2AIS EXZ5 EXOO COR FASTPTR TESTB3
Bit 6
STS3 CODE ALM2FB9 EXZ4 FEBE9EN TEST TOHOUT FIXPTR
Bit 5
DPOS1 INVCI TLAISGN EXZ3 RAMRDI DROPT H4CTR TEST
Bit 4
DPOS0 INVCO TPAISGN EXH4 FEBEEN POH2RAM PAT23 DIV4
Bit 3
APOS1 RING TPAIS00 EXF2 XALM2AIS RAISGN ENANA INVCTRL
Bit 2
APOS0 FLBK INTZ EXG1 TEST RAISEN TXANA TXRST
Bit 1
TEST L3LBK ADDZ EXC2
Bit 0
DS3 SLBK L3Z EXJ1
TLOC2AIS TLOS2AIS WGDEC TPRBS RXRST PSL2AIS RPRBS RESETC
C2 Compare TEST TEST NOPOH TEST RDI5 FEBEBLK
STATUS BITS Address (Hex)**
B0 B1 B2 B3 B4 B5 B6 B7
Mode
R R/W(L) R R/W(L) R R/W(L) R R/W(L)
Bit 7
DLOC DLOC RDI RDI SINT Reserved L3ERR L3ERR
Bit 6
DLOJ1 DLOJ1 L3LOS L3LOS FEBE9 FEBE9 LOVFL LOVFL
Bit 5
BUSERR BUSERR L3LOC L3LOC NEW NEW RFRST RFRST
Bit 4
E1AIS E1AIS TOVFL TOVFL TUG3NEW TUG3NEW TFRST TFRST
Bit 3
LOP LOP L3AIS L3AIS ROVFL ROVFL VCXOLOC VCXOLOC
Bit 2
PAIS PAIS RAMLOC RAMLOC XSTAI XSTAI TPLOC TPLOC
Bit 1
PSLERR PSLERR ALOC ALOC XISTAT XISTAT RPLOC RPLOC
Bit 0
C2EQ0 C2EQ0 ALOJ1 ALOJ1 XPAIS XPAIS OOL OOL
*R/W: Read/write; R: Read only; R/W(L): Read/Write - latched register. **Even addresses contain unlatched status bits. Odd addresses contain latched status bits.
INTERRUPT MASK BITS Address (Hex)
BA BB BC BD
Mode
R/W R/W R/W R/W
Bit 7
DLOC RDI HINT L3ERR
Bit 6
DLOJ1 L3LOS FEBE9 LOVFL
Bit 5
BUSERR L3LOC NEW RFRST
Bit 4
E1AIS TOVFL TUG3NEW TFRST
Bit 3
LOP L3AIS ROVFL VCXOLOC
Bit 2
PAIS RAMLOC XSTAI TPLOC
Bit 1
PSLERR ALOC XISTAT RPLOC
Bit 0
C2EQ0 ALOJ1 XPAIS OOL
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DATA SHEET
TRANSMIT POH BYTES & "O"-BITS J1
00-3F
L3M TXC-03452B
B3 Error Mask and Test
40
C2
41
G1
42
F2
43
H4
44
Z3 (F3)
45
Z4 (K3)
46
Z5 (N1)
47
Not "O"-bits used
48 49 Bits 1-0
RECEIVE POH BYTES, TUG-3 H1/H2 BYTES & "O"-BITS J1
50-8F
B3
90
C2
91
G1
92
F2
93
H4
94
Z3 (F3)
95
Z4 (K3)
96
Z5 (N1)
97
H1
98
H2
99
"O"-bits
9A Bits 1-0
PERFORMANCE COUNTERS & FIFO LEAK RATE RCV Frame Count
A0
Not used
A1
FIFO Leak Rate
A2
INC Count
A3
DEC Count NDF Count
A4 A5
TUG-3 INC Count
A6
TUG-3 DEC Count
A7
TUG-3 New Data Flag Count
A8
B3 Block Error Count
A9
FEBE Count
AA
B3 Error Count
AC
Line CV/PRBS Error Count
AE
Common High Byte (FEBE, B3, CVs)
FF
DEVICE IDENTIFICATION The device identification (ID) is based on the manufacturer identity, part-number and version codes described in IEEE standard 1149.1 on Boundary Scan, using the manufacturer code assigned by the Joint Electron Device Engineering Council (JEDEC). The serial format for this ID is shown below: MSB Version (TBD) 4 bits Part-Number 0000 1101 0111 1100 16 bits Manufacturer Identity 000 0110 1011 11 bits LSB Fixed Bit 1 1 bit
The device identification is not currently provided as a boundary scan message. However, the manufacturer identity and part-number are implemented with read-only capability for microprocessor read access. The manufacturer identity for TranSwitch devices is 107 (06B hex.). The part-number of the L3M device is 03452 (0D7C hex.). In addition, the read-only segment is expanded to include a 4-bit mask level field and a 4-bit future growth field, as shown below: Address (Hex) F4 F3 F2 F1 F0 Mode R R R R R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mask Level - Content TBD Revision (Version) Level - Content TBD PN11=1 PN3=1 MI6=1 PN10=1 PN2=1 MI5=1 PN9=0 PN1=0 MI4=0 PN8=1 PN0=0 MI3=1 PN15=0 PN7=0 MI10=0 MI2=0
Growth - Content TBD PN14=0 PN6=1 MI9=0 MI1=1 PN13=0 PN5=1 MI8=0 MI0=1 PN12=0 PN4=1 MI7=0 1
TXC-03452B-MB Ed. 6, April 2001
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DATA SHEET
MEMORY MAP DESCRIPTIONS
CONTROL BITS
L3M TXC-03452B
On power-up, the control bits will not be automatically initialized to a fixed default pattern. The microprocessor must write the control bits to the required system status. The control bits are not affected by either hardware or software resets. Address C0 Bit 7, 6 Symbol TUG3, STS3 Description Bus Format Control Bits: Determine the bus format according to the table given below: TUG3 0 0 1 1 5, 4 DPOS1,0 STS3 0 1 0 1 Mapping STS-1 STS-3 Future Use TUG-3
Drop Positions 1 and 0: Determine the locations of the TUG-3s and AU-3/STS-1 SPEs dropped from the STM-1/STS-3 according to the table given below: DPOS1 0 0 1 1 DPOS0 0 1 0 1 Mapping TUG-3 position A (or STS-1 #1) TUG-3 position B (or STS-1 #2) TUG-3 position C (or STS-1 #3) Idle state. RX front end held in reset.
3, 2
APOS1,0
Add Positions 1 and 0: Determine the locations of the TUG-3s and AU-3/STS-1 SPEs to be added to the STM-1/STS-3 according to the table given below: APOS1 0 0 1 1 APOS0 0 1 0 1 Mapping TUG-3 position A (or STS-1 #1) TUG-3 position B (or STS-1 #2) TUG-3 position C (or STS-1 #3) Undefined
1 0
TEST DS3
TEST: A 0 must be written into this location. DS3 Mode: Determines the mapping mode according to the table given below: DS3 0 1 Mapping Mode E3 (34.368 Mbit/s) DS3 (44.736 Mbit/s)
C1
7 6 5
DECODE CODE INVCI
Transmit Decoder Enabled: A 1 enables the transmit HDB3/ B3ZS decoder (for rail operation). A 0 disables the decoder (for NRZ operation). Receive Coder Enabled: A 1 enables the receive HDB3/B3ZS coder (for rail operation). A 0 disables the coder (for NRZ operation). Invert Transmit Line Clock Input: When set to 0, the DS3 or E3 line signals are clocked into the L3M device on positive transitions of the clock (TCLK). A 1 enables the line signal to be clocked out of the L3M device on negative transitions of the clock.
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Address C1 (cont.) Bit 4 Symbol INVCO Description
L3M TXC-03452B
Invert Receive Line Clock Output: When set to 0, the DS3 or E3 line signals are clocked out of the L3M device on negative transitions of the clock (RCLK). A 1 enables the line signal to be clocked out on positive transitions of the clock. Ring Operating Mode: A 1 enables the external alarm interface FEBE count and RDI alarm indication from another L3M device to be transmitted in the G1 byte. The outgoing G1 byte comes from the POH port if the external POH G1 byte is selected. The alarm conditions at the other L3M device that may cause RDI are shown below. The + symbol represents an OR function, while & represents an AND function. Control bit states are given by the = sign. LOP (TUG-3) PAIS (TUG-3) TUG3=1 DLOJ1 (Alarm) E1AIS (Alarm) & XALM2AIS=0 ISTAT lead high + PAIS lead high XALM2AIS=1 PSLERR (Alarm) C2EQ0 (Alarm) PSL2AIS=1 + & + Send RDI
3
RING
&
+
&
2
FLBK
Facility Loopback: A 1 enables the transmit line data and clock signals to be looped back as the receive line data and clock signals. A SDH/SONET BUS D TX
L3M
DS3/E3 RX
Facility Loopback 1 L3LBK Line E3/DS3 Loopback: A 1 enables the receive line signal to be looped back as the transmit line signal. The receive data and clock are provided at the receive line interface. A SDH/SONET BUS D TX
L3M
DS3/E3 RX
Line Loopback
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Address C1 (cont.) Bit 0 Symbol SLBK Description
L3M TXC-03452B
SDH/SONET Loopback: A 1 enables the add SDH/SONET signal to be looped back as the drop signal. The drop signals from the bus are disabled. Add data and clock are provided at the bus interface. A SDH/SONET BUS D
TX
L3M
DS3/E3 RX
SDH/SONET Loopback C2 7 ALM2AIS External Alarm Enable AIS: A 1 enables an AIS detected in an E1 byte (when control bit XALM2AIS = 0) or a high on either the ISTAT or PAIS leads (when control bit XALM2AIS = 1) to generate a line AIS in the receive direction when control bit RAISEN is a 1. See logic diagram for Address C5, bit 2. External Alarm Enable FEBE9: A 1 enables an AIS detected in an E1 byte (when control bit XALM2AIS = 0) or a high on either the ISTAT or PAIS leads (when control bit XALM2AIS = 1) to generate a count of 9 in bits 1 through 4 of the transmitted G1 byte when control bit FEBE9EN is a 1. See logic diagram for Address C4, bit 6. Transmit Line AIS: A 1 written into this position generates and transmits a DS3 or E3 AIS towards the SDH/SONET bus, independent of the state of control bit FLBK (bit 2 in register C1H). See Note 1 below. Transmit Zeros or Path AIS Enable: A 1 enables the L3M device to transmit an SPE with zeros (and valid pointer) or a TUG-3 path AIS towards the SDH/SONET bus, depending on the state of TPAIS00. The logic diagram for sending path AIS is given below. The + symbol represents an OR function, while & represents an AND function. Control bit states are given by the = sign. UNEQUIP is sent instead if TPAIS00 = 1. TUG3=1 TPAISGN=1 TPAIS00=0 TUG3=1 TPAISGN=1 TPAIS00=1 3 TPAIS00 Transmit SPE with Zeros (Unequipped payload): When enabled by writing a 1 to control bit TPAISGN, a 1 written into this location causes the SPE (POH bytes and payload) to be transmitted with zeros, but with a valid pointer. A 0 causes a TUG-3 AIS to be transmitted towards the SDH/ SONET bus. & SEND UNEQUIP & SEND TUG-3 PATH AIS
6
ALM2FB9
5
TLAISGN
4
TPAISGN
Note 1: DS3 AIS is defined as a valid M-frame with proper subframe structure. The data payload is a 1010... sequence starting with a 1 after each overhead bit. Overhead bits are as follows: F0=0, F1=1, M0=0, M1=1; C-bits are set to 0; X-bits are set to 1; and P-bits are set for valid parity. E3 AIS is an all ones pattern.
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Address C2 (cont.) Bit 2 Symbol INTZ Description
L3M TXC-03452B
Interrupt High Impedance Enable: A 0 enables the interrupt INT/IRQ (lead 129 or B8) to be either high (Intel mode) with the off state low, or to be low (Motorola mode), with the off state high. A 1 enables the off state to be high impedance. Add Bus High Impedance Enable: A 1 sets Add bus data (ADATA(7-0)) and Add Parity (APAR) leads to a high impedance state, and ADD high. If the external timing mode is selected, the clock (ACLK), SPE (ASPE), and C1J1 (AC1J1) signals are also forced to a high impedance state. Receive Output High Impedance Enable: A 1 forces the receive interface clock (RCLK) and data signals (RPOS and RNEG), and NRZ outputs (RNRZC and RNRZD) to a high impedance state. Transmit External Interface Z5 byte: A 1 enables the Z5 byte from the POH I/O to be transmitted. A 0 enables the corresponding RAM location to be transmitted. Transmit External Interface Z4 byte: A 1 enables the Z4 byte from the POH I/O to be transmitted. A 0 enables the corresponding RAM location to be transmitted. Transmit External Interface Z3 byte: A 1 enables the Z3 byte from the POH I/O to be transmitted. A 0 enables the corresponding RAM location to be transmitted. Transmit External Interface H4 byte: A 1 enables the H4 byte from the POH I/O to be transmitted. A 0 enables the corresponding RAM location to be transmitted. Transmit External Interface F2 byte: A 1 enables the F2 byte from the POH I/O to be transmitted. A 0 enables the corresponding RAM location to be transmitted. Transmit External Interface G1 Byte: A 1 enables bits 1 through 8 in the G1 byte from the POH I/O to be transmitted. A 0 enables the corresponding RAM location or internal logic/alarms to control the transmitted state of FEBE, RDI, and the unassigned bits. Transmit External Interface C2 Byte: A 1 enables the C2 byte from the POH I/O to be transmitted. A 0 enables the corresponding RAM location to be transmitted. Transmit External Interface J1 Bytes: A 1 enables the J1 bytes from the POH I/O to be transmitted. A 0 enables the corresponding RAM segment (64 locations) to be transmitted.
1
ADDZ
0
L3Z
C3
7
EXZ5
6
EXZ4
5
EXZ3
4
EXH4
3
EXF2
2
EXG1
1
EXC2
0
EXJ1
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Address C4 Bit 7 Symbol EXOO Description
L3M TXC-03452B
External "O"-Bit Select: A 1 selects the two Overhead Communication Bits ("O"-bits) from the external interface (lead TOCHD) as the two "O"-bits transmitted in each of the nine subframes of the DS3 format or each of the three subframes of the E3 format. A 0 enables the two "O"-bits from the corresponding RAM location to be transmitted (TO2, TO1 at Address 49H). FEBE9 Enable: Enable bit for generating a FEBE count of 9 (this is a proprietary non-standard feature and lead FEBE9EN should be disabled for standard compliance by holding it low). When EXG1 is a 0 and FEBE9EN is high, a FEBE count of 9 is generated when: - Either the ISTAT or PAIS input lead is high, and the external alarm enable control bit XALM2AIS is a 1 and ALM2FB9 is 1; - An AIS is detected in the E1 byte, and XALM2AIS is 0 and ALM2FB9 is 1; - Either the TUG-3 PAIS or LOP alarms occur; - The STAI lead is high. The logic diagram for sending FEBE9 is given below. The + symbol represents an OR function, while & represents an AND function. Control bit states are given by the = sign. E1AIS (Alarm) & XALM2AIS=0 ISTAT lead high + PAIS lead high XALM2AIS=1 ALM2FB9=1 LOP (TUG-3) + PAIS (TUG-3) TUG3=1 STAI lead high FEBE9EN lead high EXG1=0
6
FEBE9EN
&
+
&
&
+
&
SEND FEBE9 (Count of 9 in bits 1-4 of G1)
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Address C4 (cont.) Bit 5 Symbol RAMRDI Description
L3M TXC-03452B
Remote Defect Indication (Yellow alarm) Enabled: Enable bit for controlling the generation of Path RDI (bit 5 in G1 byte). When control bits RING and EXG1 are 0, and RAMRDI is a 0, RDI is generated when the following alarms or conditions occur: - Drop bus loss of J1 (DLOJ1) - Drop bus loss of clock (DLOC) - Loss of pointer (LOP) (TUG-3 operation) - Path AIS detected (PAIS) (TUG-3 operation) - Received E1 byte has a majority of 1s and control bit XALM2AIS is 0 - Either the ISTAT or PAIS input lead is high and control bit XALM2AIS is a1 - PSLERR or C2EQ0 alarm, and control bit PSL2AIS is a 1 When control bit RING is a 1, EXG1 is a 0, and RAMRDI is a 0, the RDI state is controlled via the external alarm indication port. The microprocessor controls the RDI state when RAMRDI is a 1 and EXG1 is a 0. Note: writing a 1 to the RAMRDI bit will disable the local alarms and the alarm indication port RDI in the ring mode from controlling the state of the transmitted RDI bit. The logic diagram for sending Path RDI is given below. The + symbol represents an OR function, while & represents an AND function. Control bit states are given by the = sign. bit 5 of G1 from port EXG1=1 RING=0 PSLERR (Alarm) + C2EQ0 (Alarm) PSL2AIS=1 + LOP (TUG-3) PAIS (TUG-3) TUG3=1 DLOJ1 (Alarm) DLOC (Alarm) & E1AIS (Alarm) XALM2AIS=0 ISTAT lead high + PAIS lead high XALM2AIS=1 REMOTE ALM I/O RING=1 RAMRDI=0 RAMRDI=1 & RAM RDI VALUE EXG1=0 & & & + & + & + & +
SEND PATH RDI/FERF/ YELLOW ALARM (Bit 5 in G1 Byte)
& &
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Address C4 (cont.) Bit 4 Symbol FEBEEN Description
L3M TXC-03452B
FEBE Enable: A 1 enables the local B3 count or remote B3 count to be inserted as the FEBE count. A 0 written into this position permits the microprocessor to control the FEBE count. The logic diagram for sending FEBE for all conditions is given below. The + symbol represents an OR function, while & represents an AND function. Control bit states are given by the = sign. EXG1=1 Port G1 FEBE Value & RX B3 count & + RING=0 REMOTE ALM FEBE count & RING=1 FEBEEN=1 SEND FEBE9=0 (internal) FEBEEN=0 & RAM FEBE count EXG1=0
&
+
&
+
SEND FEBE Count
3
XALM2AIS
External Alarm AIS Lead Enable: A 1 enables the external alarm leads (ISTAT and PAIS) to affect alarm generation instead of AIS in the E1 byte. A 0 causes alarm generation to be based on E1AIS from the drop bus. TranSwitch Test Mode: A 0 must be written into this location. Transmit Loss Of Clock (TLCK) AIS Enable: A 1 enables the L3M device to send SONET/SDH DS3 AIS or E3 AIS automatically when a transmit line clock failure is detected. The logic diagram for transmitting a line AIS is given below. The + symbol represents an or function, while & represents an and function. Control bit states are given by the = sign. L3LOC (Alarm) TLOC2AIS=1 L3LOS (Alarm) TLOS2AIS=1 TLAISGN=1 & & +
SEND DS3 or E3 AIS
2 1
TEST TLOC2AIS
0
TLOS2AIS
Transmit Loss Of Signal (TPOS/TNEG) AIS Enable: A 1 enables the L3M device to send DS3 or E3 AIS automatically when a transmit line signal failure is detected.
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DATA SHEET
Address C5 Bit 7 Symbol COR Description
L3M TXC-03452B
Clear On Read: A 0 enables all performance counters to become nonsaturating with roll over capability. The contents of the counter are not affected by a read cycle. A 1 causes the performance counters to become saturating counters, which clear on read. TEST: A 1 must be written into this location. Drop Bus Timing: Drop timing can only be selected when the L3M lead XCLKE is low. A 1 selects drop bus timing for the add bus. A 0 selects timing signals from the add bus.
6 5
TEST DROPT
4
POH2RAM Path Overhead Bytes to RAM: Works in conjunction with the EXbn control bits (e.g., EXF2). The following table summarizes the action taken by this bit and an EXbn bit: POH2RAM
1 0
EXbn (e.g., EXF2)
1 1
Action POH bn interface byte transmitted and written to RAM location. POH bn interface byte transmitted, RAM location holds microprocessor-written value. POH bn value written to RAM location by the microprocessor is transmitted.
X
0
3
RAISGN
Generate Receive Line AIS: A 1 written into this position generates a DS3/E3 AIS towards the line (RPOS, RNEG) independent of the state of the receive AIS enable bit (RAISEN). See Note below.
Note:
DS3 AIS is defined as a valid M-frame with proper subframe structure. The data payload is a 1010... sequence starting with a 1 after each overhead bit. Overhead bits are as follows: F0=0, F1=1, M0=0, M1=1; C-bits are set to 0; X-bits are set to 1; and P-bits are set for valid parity. E3 AIS is an all ones pattern.
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Address C5 (cont.) Bit 2 Symbol RAISEN Description
L3M TXC-03452B
Receive AIS Enable: A 1 enables receive AIS to be generated when the following alarms/conditions occur: - Loss of drop bus clock (DLOC) - Loss of drop bus J1 (DLOJ1) - E1 AIS (E1AIS) and XALM2AIS are 0, and ALM2AIS is a 1 - ISTAT or PAIS (lead) and XALM2AIS are 1, and ALM2AIS is a 1 - Loss of pointer (LOP) (TUG-3) - Path AIS (PAIS) (TUG-3) - PSLERR or C2EQ0 occurs, and Path Signal Label Error Enable AIS control bit (PSL2AIS) is a 1 The logic diagram for generating receive line AIS is given below. The + symbol represents an OR function, while & represents an AND function. Control bit states are given by the = sign. TUG3=1 LOP (TUG-3) PAIS (TUG-3) + DLOJ1 (Alarm) DLOC (Alarm) E1AIS (Alarm) & XALM2AIS=0 ISTAT lead high + & PAIS lead high XALM2AIS=1 ALM2AIS=1 PSLERR (Alarm) + C2EQ0 (Alarm) PSL2AIS=1 RAISEN=1 RAISGN=1
& + & +
SEND RECEIVE AIS
+
&
&
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Address C5 (cont.) Bit 1 Symbol WGDEC Description
L3M TXC-03452B
Test Equipment BPV Selection: A 1 enables the decoder to detect coding violations as found in `Type 1' test equipment. A 0 enables the decoder to detect coding violations as found in `Type 0' test equipment. The following tables summarize the two decoding procedures of coding violations:
BPV For B3ZS
BPV ++ or -0BV or 000V BB0V after odd B00V after even
"Type 1" Equipment 000 (preceding bit(s) changed) 0000 1000 1000
BPV For HDB3
"Type 0" Equipment 11 011 or 0001 1101 1001
BPV ++ or -0BV or 0000V BB00V after odd B000V after even
"Type 1" Equipment 0000 (preceding bit(s) changed) 00000 10000 10000
"Type 0" Equipment 11 011 or 00001 11001 10001
0
PSL2AIS
Path Signal Label Error Enable AIS: A 1 enables the L3M device to send DS3 or E3 AIS automatically towards the receive line, and path RDI (FERF) when a PSLERR or C2EQ0 alarm occurs. (See RAMRDI and RAISEN for diagrams.) Fast Pointer Enabled: A 1 allows the L3M device to track pointer movements every frame instead of every other frame for TUG-3 operation. Transport Overhead Bytes Out: A 1 enables the L3M device to generate the A1, A2, C1, and the H1, H2 bytes, in the external timing mode (STS-1 mode) only. The H1 and H2 bytes are transmitted with a fixed pointer value of 6000H. H4 Counter Enable: Normally set to 0. A 1 enables the H4 byte to be transmitted with a count generated by an internal 8-bit frame counter. 223-1 Test Pattern Enable: A 0 selects the test pattern generators' and analyzer's pattern to be 215-1. A 1 selects the pattern generators' and analyzer's pattern to be 223-1. Enable Analyzer: A 1 enables the 215-1or 223-1 analyzer. PRBS errors are counted in a 16-bit counter in locations AEH and AFH. Transmit Analyzer Enable: A 1 enables the analyzer to sample the transmit NRZ line (DS3/E3) signal after the Decoder. A 0 causes the analyzer to sample the receive NRZ line data prior to the coder function. A 1 must be written into ENANA for this bit to function (see Figure 34). Transmit Test Pattern Generator Enable: A 1 enables the transmit test pattern generator and disables the NRZ decoder output. Receive Test Pattern Generator Enable: A 1 enables the receive test pattern generator and disables the NRZ coder input.
C6
7 6
FASTPTR TOHOUT
5 4
H4CTR PAT23
3 2
ENANA TXANA
1 0
TPRBS RPRBS
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Address C7 Bit 7 Symbol TESTB3 Description
L3M TXC-03452B
Test B3 Byte: A 1 transmits a B3 value written by the microprocessor in location 40H. A 0 enables the test byte to become a test mask. When configured as a test mask, a 1 in one or more bit positions causes those bits in the transmitted B3 byte to be inverted. TUG-3 Fixed Pointer Generation: A 1 forces a fixed pointer of 0 to be generated in the transmitted TUG-3 regardless of any pointer movements (J1 in DC1J1) that may occur on the Drop side when the Drop timing mode is selected, or if a pointer movement (J1 in AC1J1) takes place when Add bus timing is selected. When this bit is written with a 0, a pointer movement on the Add or Drop bus is compensated with an outgoing TUG-3 pointer movement in the opposite direction. Test Bit Position: This bit must be set to 1. Phase Detector Gain: This control bit governs the gain of the phase detector, and it should be set as indicated in the Operation section entitled "PLL Filter Connection to VCXO". Invert Control: Inverts the CTRL output lead (lead 3 or D3). When set to 0, the external loop filter must be non-inverting, which requires the use of an inverter in the loop (U1 in Figure 32). When set to 1, an external inverting loop filter is necessary, and U1 is not required. Transmit Reset: A 1 written into this position resets the transmit section (Line to SDH/SONET) of the L3M device. This includes the transmit FIFOs and internal counters. The L3M device's transmitter will remain reset until the microprocessor writes a 0 into this location. Receive Reset: A 1 written into this position resets the receive section (SDH/SONET to Line) of the L3M device. This includes the receive FIFOs and internal counters. The L3M device's receiver will remain reset until the microprocessor writes a 0 into this location. Reset Performance Counters: A 1 written into this position resets all performance counters to 0. This bit is self clearing, and does not require the microprocessor to write a 0 into this location.
6
FIXPTR
5 4
TEST DIV4
3
INVCTRL
2
TXRST
1
RXRST
0
RESETC
C8
7-0
C2 Compare Path Signal Label Compare: The bits in this location are written by the microprocessor, and are compared against the C2 byte received (register 91H) for a signal label mismatch condition. TEST RDI5 Test Bit Positions: Zeros must be written into these bits. RDI 5 Consecutive Enable: A 1 enables the detection/recovery of RDI (bit 5 in the G1 byte) to 5 consecutive matches/mismatches. A 0 enables the detection/recovery of RDI to 10 consecutive matches/mismatches. FEBE Counter Block Count Enable: A 1 configures the FEBE counter (register locations AA and AB) to count one or more FEBE errors per received G1 byte as one error (block). A 0 configures the FEBE counter to count the number of errors detected (1 to 8).
C9
7-2 1
0
FEBEBLK
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DATA SHEET
Address CA Bit 7-6 5 Symbol TEST NOPOH Description Test Bit Positions: These bits must be set 0.
L3M TXC-03452B
No Path Overhead: When this bit is set to 1, the VC-4 path overhead time slots of the Add bus data signals ADATA(7-0) are set to a high impedance and the ADD signal is high during these time slots. When this bit is set to 0, ADATA(7-0) and ADD are active during these time slots. The ADATA (7-0) byte values are set to 00H during these time slots. Test Bit Positions: These bits must be set 0.
4-0
TEST
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L3M TXC-03452B
STATUS BITS Status bits report the condition of alarms. Unlatched bit positions (even addresses) respond to transient alarm conditions. Latched bit positions (odd addresses) are set upon occurrence of an alarm condition and then stay high until they are cleared by a read cycle. It is important to remember that, when reading the latched registers in the L3M, the contents should be read a second time before determining the current status. Address B0 & B1 Bit 7 Symbol DLOC Description Drop Bus Loss Of Clock Alarm: A loss of clock alarm occurs when the input Drop clock is stuck high or low for 1000 500 nanoseconds. Recovery occurs on the first clock transition. Drop Bus Loss of J1: A loss of J1 alarm occurs when: - 8 consecutive new J1 positions have been detected or - J1 is stuck low for 8 consecutive frames or - J1 is stuck high for 8 consecutive bytes or - 8 J1 pulses are received in one frame. Recovery occurs when the J1 pulse is detected in the same location for 8 consecutive frames. Bus Parity Error: A 1 indicates a parity error has been detected on the drop bus. Odd parity is calculated over the DDATA, DSPE, DC1J1 or DC1, and DPAR leads. Other than providing this alarm, no other action is taken. E1 Byte AIS Detected: A 1 indicates that AIS has been detected in the E1 byte corresponding to AU-3/STS-3 STS-1. For TUG-3 operation, the E1 in slot 0 is monitored. Majority logic (5 out of 8 1s) is used for detection. The following alarms in the TranSwitch SOT-3/SOT-1 devices generate an E1 byte having an AIS indication: loss of frame, loss of signal, loss of pointer, and line AIS detected. Internal pointer processing is performed for the TUG3 signal according to ETSI draft document pr ETS 300 417-1, July 1994. Loss Of Pointer Alarm: Valid for TUG-3 pointer processing only. A loss of pointer alarm occurs when a New Data Flag (NDF) or an invalid pointer is detected for eight consecutive frames. Recovery occurs when a valid pointer is received for three consecutive frames. Path AIS Alarm: Valid for TUG-3 pointer processing only. A Path Alarm Indication Signal (AIS) is detected when all ones are detected in the 16 bit pointer word (H1 and H2) for three consecutive frames. Recovery occurs when a valid NDF is received, or a valid pointer is detected, for three consecutive frames. Path Signal Label Error: A 1 indicates that the comparison between the received C2 byte and the microprocessor-written C2 byte or certain fixed values did not match 5 times consecutively (i.e., the two mismatch test conditions are C2 value in register C8H and-gated with C2 01H, or C2 = 00H). Recovery to 0 occurs when the comparison matches five times consecutively. Unequipped Alarm: An unequipped alarm is detected (C2EQ0 = 1) when the C2 byte is equal to 00H 5 times consecutively. Alarm recovery to C2EQ0 = 0 occurs when the C2 byte is not equal to 00H five times consecutively.
6
DLOJ1
5
BUSERR
4
E1AIS
3
LOP
2
PAIS
1
PSLERR
0
C2EQ0
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Address B2 & B3 Bit 7 Symbol RDI Description
L3M TXC-03452B
Receive RDI (Yellow) Alarm: When RDI5 is set to 0, a 1 in RDI indicates that bit 5 in the G1 byte has been detected as a one for 10 consecutive frames. When RDI5 is set to 0, RDI recovers to 0 when a 0 has been detected for 10 consecutive frames. When RDI5 is a 1, detection and recovery of RDI occurs after 5 consecutive events instead of 10. Mapper Transmit Loss Of Signal: For an E3 signal, a loss of signal alarm occurs when the positive/negative rail is stuck low for 256 bit times. Recovery occurs when there are at least 32 transitions (both positive and negative rail) in a count of 256 clock cycles. For a DS3 signal, a loss of signal alarm occurs when either the positive or negative rail is stuck low for 200 bit times. Recovery occurs on the first transition (both positive and negative rail). When the interface is configured for NRZ operation, an active high on the TNEG will be an external loss of signal indication and will cause a L3LOS indication. Mapper Transmit Loss of Clock: A 1 indicates the incoming line clock (TCLK) signal has been stuck high or low for 1000 500 nanoseconds. Recovery occurs on the first clock transition. Transmit FIFO Overflow/Underflow: A 1 indicates that the transmit FIFO has either underflowed or overflowed. When this happens, the FIFO automatically resets to a preset position. Mapper E3 Transmit AIS Detected: For an E3 signal, AIS is detected when four or fewer zeros are detected in 1536 bits, twice in a row. Recovery occurs when there are five or more zeros detected in 1536 bits two consecutive times. Loss Of Microprocessor RAM Clock: A 1 indicates that the RAM clock (RAMCI) has been stuck high or low for 1000 500 nanoseconds. Recovery occurs on the first clock transition. Add Bus Loss Of Clock: A loss of clock alarm occurs when the input add clock (ACLK) is stuck high or low for 1000 500 nanoseconds. Recovery occurs on the first clock transition. When the add bus clock is an output, the external byte clock (XCLKI) is monitored for loss of clock instead, and its loss is reported by this alarm. Add Bus Loss of J1: A loss of J1 alarm occurs when: - 8 consecutive new J1 positions have been detected or - J1 is stuck low for 8 consecutive frames or - J1 is stuck high for 8 consecutive bytes or - 8 J1 pulses are received in one frame. Recovery occurs when the J1 pulse is detected in the same location for 8 consecutive frames.
6
L3LOS
5
L3LOC
4
TOVFL
3
L3AIS
2
RAMLOC
1
ALOC
0
ALOJ1
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Address B4 & B5 Bit 7 Symbol SINT (B4 only) Description
L3M TXC-03452B
Software Interrupt: A software interrupt indication occurs when one or more bit locations in the interrupt mask locations is set to 1, and the corresponding latched alarm is active. The SINT state is exited when the latched alarm causing the interrupt clears or its corresponding bit in the interrupt mask is cleared. FEBE Count of 9 Indication: An STS FEBE9 indication occurs when the code 1001 (count of 9) in bits 1-4 in the received G1 byte is detected for five consecutive frames. The alarm is terminated when any code other than the 1001 is detected in bits 1-4 for five consecutive frames. New Alarm: An indication that a new J1 location, other than those resulting from INC or DEC, has been detected.
6
FEBE9
5 4
NEW
TUG3NEW TUG-3 New Alarm: A TUG-3 new indication occurs when three consecutive new pointers, or an NDF and a match of the SS bits and the pointer offset value is in range, has been detected. ROVFL Receive FIFO Overflow/Underflow: A 1 indicates an underflow or overflow condition in the receive direction (SDH/SONET to line). When this happens, the FIFO will automatically reset to a preset position and the FIFOERR output (lead 11 or F3) will pulse high. SDH/SONET Network Alarm Indication: A 1 indicates that the input on the lead labeled STAI is high. External STS-1 Alarm: A 1 indicates that the input on the lead labeled ISTAT is a high. A 1 is equal to an external alarm condition (e.g., LOP). External Path AIS: A 1 indicates that the input on the lead labeled PAIS is a high. A 1 is equal to an external alarm condition (i.e., Path AIS).
3
2 1 0
XSTAI XISTAT XPAIS
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Address B6 & B7 Bit 7 Symbol L3ERR Description
L3M TXC-03452B
Analyzer Error Indication: A 1 indicates that the 215-1 or 223-1 analyzer has detected an error when enabled. A 1 written to ENANA (bit 3, location C6) enables the analyzer. This indication will be disabled during operation when control bit ENANA is a 0. Leak FIFO Overflow/Underflow Alarm: A 1 indicates that the leak FIFO has underflowed or overflowed. When this occurs, the FIFO will automatically reset to a preset position and the FIFOERR output (lead 11 or F3) will pulse high. Receive FIFO Reset Indication: A 1 indicates that either of the receive FIFOs has been reset. This may occur because of a FIFO overflow/underflow alarm, or when the receive section has been reset by writing a 1 to control bit RXRST, or upon hardware reset. Transmit FIFO Reset Indication: A 1 indicates that the transmit FIFO has been reset. This may occur because of a FIFO overflow/underflow alarm, or when the transmit section has been reset by writing a 1 to control bit TXRST, or upon hardware reset.
6
LOVFL
5
RFRST
4
TFRST
3
VCXOLOC Loss of VCXO Clock: A 1 indicates that the external VCXO clock has been stuck high or low for 1000 500 nanoseconds. Recovery occurs on the first clock transition. TPLOC Loss of Transmit PLL Clock: A 1 indicates that the internal PLL clock has been stuck high or low for 1000 500 nanoseconds. Recovery occurs on the first clock transition. Loss of Receive PLL Clock: A 1 indicates that the internal PLL clock has been stuck high or low for 1000 500 nanoseconds. Recovery occurs on the first clock transition. Analyzer Out of Lock: A 1 indicates that the analyzer, when enabled, is out of lock.
2
1
RPLOC
0
OOL
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Interrupt Mask Bits
L3M TXC-03452B
A 1 written to any of the bits in the interrupt mask (except HINT), and the occurrence of the corresponding alarm, causes a software interrupt (SINT) to occur. If the hardware interrupt bit (HINT) is also written with a 1, then a hardware interrupt also occurs. Address BA Bit 7 6 5 4 3 2 1 0 BB 7 6 5 4 3 2 1 0 BC 7 6 5 4 3 2 1 0 BD 7 6 5 4 3 2 1 0 Symbol DLOC DLOJ1 BUSERR E1AIS LOP PAIS PSLERR C2EQ0 RDI L3LOS L3LOC TOVFL L3AIS RAMLOC ALOC ALOJ1 HINT FEBE9 NEW ROVFL XSTAI XISTAT XPAIS L3ERR LOVFL RFRST TFRST VCXOLOC TPLOC RPLOC OOL Drop Bus Loss Of Clock Drop Bus Loss of J1 Bus Parity Error E1 Byte AIS detected Loss Of Pointer (TUG-3 operation) Path AIS (TUG-3 operation) Path Signal Label Error C2 Equal to 0 alarm (unequipped) Receive RDI (yellow) detected. Transmit Line Loss Of Signal Transmit Line Loss Of Clock Transmit FIFO Error (underflowed or overflowed) E3 Transmit Line AIS Detected Loss Of Microprocessor RAM Clock (RAMCI signal, lead 130 or C7) Add Bus Loss Of Clock Add Bus Loss of J1 Hardware Interrupt Enable FEBE Count of 9 indication New Alarm - NDF and 3x new pointer events (TUG-3 operation) Receive FIFO Overflow/Underflow SDH/SONET Network Alarm Indication External STS-1 Alarm (ISTAT) signal detected as a 1 (if enabled) External Path AIS (PAIS) signal detected as a 1 (if enabled) Internal Analyzer bit error detected. Leak FIFO Overflow/Underflow Receive FIFO Reset Indication Transmit FIFO Reset Indication VCXO Loss Of Clock Transmit PLL loss of clock Receive PLL loss of clock Analyzer out of lock. Description
TUG3NEW TUG-3 New Alarm - Three new pointer events
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Transmit Path Overhead Bytes And "O"-bits
L3M TXC-03452B
The Transmit Path Overhead bytes consist of the J1, B3, C2, G1, F2, H4, Z3 (F3), Z4 (K3), and Z5 (N1) bytes, where Z3, Z4 and Z5 are ANSI designations. The POH bytes may be individually transmitted from the POH interface, or from RAM locations written by the microprocessor. When POH2RAM is a 1, the POH interface byte selected for transmission is written into the common RAM location as transmitted. For example, if EXC2 is set to 1, the transmit POH interface C2 byte is written into the assigned RAM location, in addition to being transmitted. If EXC2 is set to 0, the transmitted byte is the value written into the corresponding RAM location by the microprocessor. When a 0 is written into the POH2RAM control bit, the L3M device disables the capability of writing any of the selected POH interface bytes into their RAM locations. However, individual bytes may still be transmitted from either the POH interface or the microprocessor-written RAM location. This feature permits switching back and forth between a selected POH interface byte or a RAM location for transmission, without having to re-initialize the RAM location. The following table is a summary of this operation:
POH2RAM 1 0 X
* e.g., bn = C2.
EXbn* 1 1 0
Action POH interface byte bn written into RAM, and also transmitted. POH interface byte bn transmitted, but not written into RAM. Microprocessor writes RAM value as required. POH RAM value of bn byte transmitted.
The relationship between a transmitted Path Overhead byte and the corresponding RAM location is as follows: Bits of RAM Location 7 6 5 4 3 2 1 0
Bits of Transmitted POH Byte 1 2 3 4 5 6 7 8
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L3M TXC-03452B
The "O"-bits consists of two overhead communication bits per subframe, for nine subframes, in the DS3 format, or for 3 subframes in the E3 format. The selection of the two bits per subframe, either from the "O"-bit interface or from RAM, operates in the same way as the Path Overhead bytes, but "O"-bits from the transmit "O"-bit port are not written into RAM. When sourced from the RAM, the same "O"-bit pair will be sent throughout the entire SONET frame (i.e., the "O"-bit value from RAM is accessed only once per frame).
Address 00 to 3F 40
Bit 7-0
Symbol J1
Description Path Trace: The bytes written into this location provide a repetitive 64 byte fixed length message for transmission. The bytes written into these positions are either from the microprocessor or from the external POH I/O. B3 Error Mask: When control bit TESTB3 is a 0, the bit columns written with a one represent the columns in the B3 byte in which errors are generated. The B3 errors are sent until this position is rewritten with a 00H. When control bit TESTB3 is a 1, the value written into this location is the transmitted B3 byte. Path Signal Label (microprocessor): The bits written into this position indicate the construction of the AU-3, TUG-3, or SPE. Transmit Byte G1: This byte is used for sending the microprocessor-controlled states for FEBE, RDI, and the unassigned bits, according to states given in the tables below: Transmit G1 Bit RAM Bit 1 7 2 6 3 5 4 4 5 3 TRDI 6 2 7 1 8 0
7-0
B3 Error Mask
41 42
7-0 7-0
C2 G1
TFEBE TFEBE EXG1 0 0 1 FEBEEN 0 1 X
Unassigned
Action Microprocessor-written value sent Internal or mate (ring mode) value sent External POH value sent TRDI
EXG1 0 0 1
RAMRDI 0 1 X
Action Internal or mate (ring mode) value sent Microprocessor-written value sent External POH value sent Unassigned Bits
EXG1 0 1
Action Microprocessor-written value sent External POH value sent
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Address 43 44 Bit 7-0 7-0 Symbol F2 H4 Description
L3M TXC-03452B
User Channel: This location provides microprocessor- or I/O- written information between elements. H4 Channel: This byte is not used in this mapping, and should be set to 00H by the microprocessor or I/O. Writing a one to the H4CTR bit inserts an 8-bit counter into this byte. Z3 (F3), Z4 (K3), Z5 (N1) Bytes: The processing of these bytes is not supported in the L3M. However, the microprocessor may write the transmit values of these bytes in these registers. Not used. Not used.
45 46 47 48 49
7-0 7-0 7-0 7-0 7-2 1 0
Z3 (F3) Z4 (K3) Z5 (N1)
TO2 TO1
Transmit "O"-Bits: These two bits correspond to the two "O"-bits found in each of the nine subframes in the DS3 format or the three subframes in the E3 format. The "O"-bits are read once per frame and inserted into each of the subframes.
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Receive Path Overhead Bytes, Tug-3 H1/h2 Bytes And "O"-bits
L3M TXC-03452B
The received bytes are written into the locations given below, and are also provided at the receive Path Overhead byte interface. The relationship between a received Path Overhead byte and the corresponding RAM location is as follows: Bits of RAM Location: 7 6 5 4 3 2 1 0
Bits of Received POH Byte: 1 2 3 Bit 7-0 4 5 6 7 8 Description Path Trace: The received J1 bytes are written in the 64 byte segment in a rotating fashion. There is no specific starting point. Path B3: The value in this location is the received B3 parity byte. Path Signal Label: These bits indicate the construction of the AU-3, TUG-3, or SPE (e.g., unequipped). Receive Byte G1: This location provides the receive status of the FEBE bits, Path RDI, and unassigned bits in the G1 byte. Receive G1 Bit RAM Bit 1 7 2 6 3 5 4 4 5 3 RRDI 6 2 7 1 8 0
Address 50 to 8F 90 91 92
Symbol J1
7-0 7-0 7-0
B3 C2 G1
RFEBE 93 94 95 96 97 98 99 7-0 7-0 7-0 7-0 7-0 7-0 F2 H4 Z3 (F3) Z4 (K3) Z5 (N1) H1 H2
Unassigned
User Channel: This location provides user information between elements. H4 Byte: This byte is not specified for use in this application. It is provided for future use as required. Path Growth: The Z3, Z4 and Z5 bytes are designated for future growth. The Z5 byte has been assigned for Tandem Connection application. Received H1 and H2 Pointer: The contents of the H1 and H2 pointer for a TUG-3 are provided in the following bit order for a microprocessor read cycle. H1 H2 Bit 7 6 5 4 3 2 1 0 76543210 NNNNSS ID I DI DI DI D Receive "O"-Bits: The received states of the two Overhead Communication channel bits found in the nine subframes in the DS3 format or the three subframes in the E3 format. The two bits are updated once a frame from one of the subframes in the frame.
9A
1 0
RO2 RO1
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Performance Counters And Fifo Leak Rate
L3M TXC-03452B
All 16-bit performance counters allow uninterrupted access, without the danger of one byte changing while the other byte is read. To perform a 16-bit read, the low order byte is read first. This causes the high order byte of the counter to be transferred to a common high order byte at location FFH. The common high order byte should be read next to complete the count transfer; if another performance counter low order byte is read first, the contents of the common high order byte will change to reflect the performance counter just read. Counts that occur during the read cycle are held for the counter to be updated afterwards. All the performance counters can also be configured to be either saturating or non-saturating. When a 1 is written to control bit COR (clear on read), the performance counters are configured to be saturating, with the counters stopping at their maximum count. An 8-bit or 16-bit counter is reset on a microprocessor read cycle. When a 0 is written to control bit COR, the performance counters are configured to be non-saturating, and roll over to zero after the maximum count in the counter is reached. The counters are then not cleared on a read cycle. All the performance counters can be reset simultaneously by writing a 1 to control bit RESETC. This bit is self clearing, and does not require writing a 0 into this location. All drop bus related performance counters are inhibited (i.e., will not increment) when one or more of the following alarms occurs: - Loss of Drop bus clock (DLOC) - Loss of Drop bus J1 (DLOJ1) - AIS detected in the E1 byte (when XALM2AIS = 0) - When either ISTAT or PAIS lead is high (when XALM2AIS = 1) - Loss of pointer (TUG-3) - Path AIS (TUG-3) The performance counters can also be written by the microprocessor. However, when writing to a 16-bit counter (at locations n, n+1) it is recommended that the low order byte at location n should be written first. The high order byte can be written by addressing location n + 1. Since the writes occur in separate cycles, care must be taken to prevent the low byte from carrying-out to the high byte before the high byte is initialized. Writing a low byte equal to 00H will provide the maximum time for the microprocessor to update the high byte.
Address A0 A1 A2
Bit 7-0 7-0 7-0
Symbol Rcv Frame Cnt FIFO Leak Rate
Description Receive SDH/SONET Frame Count: Counts the number of received SDH/SONET frames. Not used. FIFO Leak Rate Register: The number written into this location represents the number of frames between consecutive leaked bits, in multiples of four frames (i.e., a value of x means that there are 4x frames between bit leaks). The recommended value of zero causes a bit to be leaked every other frame. Positive Justification Counter: Counts the number of positive (increment) pointer movements in the AUG/VC-4 or STS-3/STS-1 based on J1 movements.
A3
7-0
INC Count
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Address A4 Bit 7-0 Symbol Description
L3M TXC-03452B
DEC Count Negative Justification Counter: Counts the number of negative (decrement) pointer movements in the AUG/VC-4 or STS-3/STS-1 based on J1 movements. New Count New Data Flag (NDF) Counter: Counts the number of J1 movements for the AUG/VC-4 or STS-3/STS-1. TUG-3 INC Count TUG-3 Positive Justification Counter: Counts the number of positive (increment) pointer movements in the TUG-3, based on interpretation of H1 and H2.
A5 A6
7-0 7-0
A7
7-0
TUG-3 Negative Justification Counter: Counts the number of negative TUG-3 DEC Count (decrement) pointer movements in the TUG-3, based on interpretation of H1 and H2. TUG-3 NDF TUG-3 New Data Flag (NDF) Counter: Counts the number of New Data Flags (NDFs) or new pointers in the TUG-3 pointer (H1/H2). Note: The Count TUG-3 NDF counter will not register a count when the pointer is changed between certain sets of values (i.e., 192 to 194 or 193 to 195). The TUG-3 NDF counter will register two counts for the inverse case, (i.e., 194 to 192 or 195 to 193). B3 Block Count B3 Blocks (in error) Counter: Counts the number of B3 blocks which are received in error.
A8
7-0
A9 AA
7-0 7-0
FEBE Count Far End Block Error Counter: Counts the FEBE error count indication received in bits 1 through 4 of G1 when control bit FEBEBLK is a 0. When FEBEBLK is a 1, one or more errors per received G1 byte are counted as 1 error (block). Location AAH is the low order byte, while location ABH is the high order byte of the 16-bit counter. After reading the low order byte from AAH the corresponding high order byte (ABH) should be read from FFH. B3 Counter B3 Error Counter: Counts the number of B3 errors that occur between the incoming value and calculated value. Location ACH is the low order byte, while location ADH is the high order byte of the 16-bit counter. After reading the low order byte from ACH the corresponding high order byte (ADH) should be read from FFH. Coding Errors HDB3/B3ZS Coding Error Counter: Counts the number of internal coding violation errors detected when in P/N rail mode. Location AEH is the low order byte while location AFH is the high order byte of the 16-bit counter. When control bit ENANA is set to 1, PRBS errors are counted when the internal analyzer is in lock (no OOL alarm). After reading the low order byte from AEH the corresponding high order byte (AFH) should be read from FFH. Common High Order Byte: This location contains a copy of the high order byte that was associated with the low order byte of the 16-bit counter most recently read.
AC
7-0
AE
7-0
FF
7-0
Common High Byte Count
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PACKAGE INFORMATION
L3M TXC-03452B
The L3M device is available in two package formats. One is a 144-lead plastic quad flat package suitable for surface mounting, as shown in Figure 37. The other is a 208-lead small outline plastic ball grid array package suitable for surface mounting, as illustrated in Figure 38.
108
73
109
72
0.65 TYP
TRANSWITCH TXC-03452BIPQ or TXC-03452CIPQ
0.30 TYP
144
37
1 INDEX LEAD #1 22.75 SQ 28.00 SQ 31.90 0.25 SQ
36
0.18 TYP SEE DETAIL "A"
4.07(MAX)
3.42 0.25 (MIN)
0 -7 DEGREE TYP
0.80 TYP DETAIL "A"
Note: All linear dimension values are shown in millimeters and are nominal unless otherwise indicated.
Figure 37. L3M TXC-03452B 144-Lead Plastic Quad Flat Package
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L3M TXC-03452B
E E2 Bottom View -E1-
TRANSWITCH
TXC-03452CIOG
D D2 E1/4 Note 2
D1/4
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TRPNMLKJHGFEDCBA
-D1-
(A3)
A2
A A1
e
b
Dimension (Note 1) Notes: 1. All dimensions are in millimeters. Values shown are for reference only. 2. Identification of the solder ball A1 corner is contained within this shaded zone. This package corner may be a 90 angle, or chamfered for A1 identification. 3. Size of array: 16 x 16, JEDEC code MO-151-AAF-1 A A1 A2 A3 (Ref.) b D D1 (BSC) D2 E E1 (BSC) E2 e (BSC)
Min 1.35 0.30 0.75 0.36 0.40 17.00 15.00 15.00 17.00 15.00 15.00 1.00
Max 1.75 0.50 0.85 0.60
15.70
15.70
Figure 38. L3M TXC-03452B 208-Lead Small Outline Plastic Ball Grid Array Package
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ORDERING INFORMATION
Part Number: TXC-03452BIPQ (not recommended for new designs) TXC-03452CIPQ TXC-03452CIOG
L3M TXC-03452B
144-Lead Plastic Quad Flat Package
144-Lead Plastic Quad Flat Package 208-Lead Small Outline Plastic Ball Grid Array Package
RELATED PRODUCTS
TXC-02030, DART VLSI Device (Advanced E3/DS3 Receiver/Transmitter). DART performs the transmit and receive line interface functions required for transmission of E3 (34.368 Mbit/s) and DS3 (44.736 Mbit/s) signals across a coaxial interface. TXC-02302B, SYN155C VLSI Device (155-Mbit/s Synchronizer, Clock and Data Output). Transmits and receives at STS-3/STM-1 rates. Provides the complete STS-3/STM-1 frame synchronization function. Connects directly to optical fiber interface components. TXC-03001/TXC-03001B, SOT-1 VLSI Device (SONET STS-1 Overhead Terminator). This device performs section, line and path overhead processing for STS-1 SONET signals. Has programmable STS-1 or STS-N modes. TXC-03003/TXC-03003B, SOT-3 VLSI Device (STM-1/STS-3/STS-3c Overhead Terminator). This device performs section, line and path overhead processing for STM-1/STS-3/STS-3c signals. Compliant with ANSI and ITU-TSS standards. TXC-03303, M13E VLSI Device. Extended feature version of the TXC-03301 (M13). TXC-03305, M13X VLSI Device (DS3/DS1 Mux/Demux). This single-chip device provides the functions needed to multiplex and demultiplex 28 independent DS1 signals to and from a DS3 signal with either an M13 or C-bit frame format. It includes some enhanced features relative to the M13E device. TXC-06103, PHAST-3N VLSI Device (SONET/SDH STM-1, STS-3 or STS-3c Overhead Terminator) This PHAST-3N VLSI device provides a COMBUS interface for downstream devices and operates from a power supply of 3.3 volts. TXC-06125, XBERT VLSI Device (Bit Error Rate Generator Receiver). Programmable multi-rate test pattern generator and receiver in a single chip with serial, nibble, or byte interface capability.
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STANDARDS DOCUMENTATION SOURCES
L3M TXC-03452B
Telecommunication technical standards and reference documentation may be obtained from the following organizations:
ANSI (U.S.A.): American National Standards Institute 11 West 42nd Street New York, New York 10036 The ATM Forum (U.S.A., Europe, Asia): 2570 West El Camino Real Suite 304 Mountain View, CA 94040 ATM Forum Europe Office Av. De Tervueren 402 1150 Brussels Belgium ATM Forum Asia-Pacific Office Hamamatsu-cho Suzuki Building 3F 1-2-11, Hamamatsu-cho, Minato-ku Tokyo 105-0013, Japan Bellcore (See Telcordia) CCITT (See ITU-T) EIA (U.S.A.): Electronic Industries Association Global Engineering Documents 7730 Carondelet Avenue, Suite 407 Clayton, MO 63105-3329 ETSI (Europe): European Telecommunications Standards Institute 650 route des Lucioles 06921 Sophia Antipolis Cedex France Tel: 4 92 94 42 22 Fax: 4 92 94 43 33 Web: www.etsi.org Tel: (800) 854-7179 (within U.S.A.) Tel: (314) 726-0444 (outside U.S.A.) Fax: (314) 726-6418 Web: www.global.ihs.com Tel: 3 3438 3694 Fax: 3 3438 3698 Tel: 2 761 66 77 Fax: 2 761 66 79 Tel: (650) 949-6700 Fax: (650) 949-6705 Web: www.atmforum.com Tel: (212) 642-4900 Fax: (212) 302-1286 Web: www.ansi.org
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DATA SHEET
L3M TXC-03452B
GO-MVIP (U.S.A.): The Global Organization for Multi-Vendor Integration Protocol (GO-MVIP) 3220 N Street NW, Suite 360 Washington, DC 20007 ITU-T (International): Publication Services of International Telecommunication Tel: 22 730 5111 Union Telecommunication Standardization Sector Fax: 22 733 7256 Place des Nations, CH 1211 Web: www.itu.int Geneve 20, Switzerland MIL-STD (U.S.A.): DODSSP Standardization Documents Ordering Desk Building 4 / Section D 700 Robbins Avenue Philadelphia, PA 19111-5094 PCI SIG (U.S.A.): PCI Special Interest Group 2575 NE Kathryn Street #17 Hillsboro, OR 97124 Tel: (800) 433-5177 (within U.S.A.) Tel: (503) 693-6232 (outside U.S.A.) Fax: (503) 693-8344 Web: www.pcisig.com Tel: (215) 697-2179 Fax: (215) 697-1462 Web: www.dodssp.daps.mil Tel: (800) 669-6857 (within U.S.A.) Tel: (903) 769-3717 (outside U.S.A.) Fax: (508) 650-1375 Web: www.mvip.org
Telcordia (U.S.A.): Telcordia Technologies, Inc. Attention - Customer Service 8 Corporate Place Piscataway, NJ 08854 TTC (Japan): TTC Standard Publishing Group of the Telecommunications Technology Committee 2nd Floor, Hamamatsu-cho Suzuki Building, 1 2-11, Hamamatsu-cho, Minato-ku, Tokyo Tel: 3 3432 1551 Fax: 3 3432 1553 Web: www.ttc.or.jp Tel: (800) 521-CORE (within U.S.A.) Tel: (908) 699-5800 (outside U.S.A.) Fax: (908) 336-2559 Web: www.telcordia.com
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Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
LIST OF DATA SHEET CHANGES
L3M TXC-03452B
This change list identifies those areas within this updated L3M TXC-03452B Data Sheet that have significant differences relative to the previous and now superseded Data Sheet: Updated L3M TXC-03452B Data Sheet: Previous L3M TXC-03452B Data Sheet: Edition 6, April 2001 Edition 5A, February 2000
The page numbers indicated below of this updated data sheet include changes relative to the previous data sheet. Page Number of Updated Data Sheet All 2 -3 12 22 23 24
Summary of the Change Changed edition number and date. Updated the Table of Contents and List of Figures. Changed the PBGA Lead Diagram labels for leads K15 and K16 to Symbols TAIPF, TAIPD respectively. In the Receive Desynchronizer table changed the lead Type for symbol CTRL. In the Boundary Scan Testing Table, changed text of the Name/Function column for symbol TRS. Added Note 5 below the Absolute Maximum Ratings and Environmental Limitations table. In the Power Requirements Table changed the values in the Max column for IDD and PDD. Added Note 2 for the RCLK duty cycle, below the table of Figure 8. In the table below Figure 29, changed Boundary Scan Timing Min values for Symbols tH(1), tSU(2), and tH(2). Changed the value in the Max column for Symbol tD. Changed title of Figure 34, added clock input for Rx PRBS Generator, and added the note. Added "Unequipped payload" to description of Symbol TPA1S00 (C2, Bit 3). In the Related Products Section removed the fifth and last paragraphs. Updated List of Data Sheet Changes.
28 48
54 65 88 91
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Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET - NOTES -
L3M TXC-03452B
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Proprietary TranSwitch Corporation Information for use Solely by its Customers
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L3M TXC-03452B
TranSwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. No liability is assumed as a result of their use or application. TranSwitch assumes no liability for TranSwitch applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TranSwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TranSwitch covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.
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TranSwitch Corporation
*
3 Enterprise Drive
*
Shelton, CT 06484 USA
*
Tel: 203-929-8810
*
Fax: 203-926-9453
*
www.transwitch.com
Proprietary TranSwitch Corporation Information for use Solely by its Customers
DATA SHEET
DOCUMENTATION UPDATE REGISTRATION FORM
L3M TXC-03452B
If you would like to receive updated documentation for selected devices as it becomes available, please provide the information requested below (print clearly or type) then tear out this page, fold and mail it to the Marketing Communications Department at TranSwitch. Marketing Communications will ensure that the relevant Product Information Sheets, Data Sheets, Application Notes, Technical Bulletins and other publications are sent to you. You may also choose to provide the same information by fax (203.926.9453), or by e-mail (info@txc.com), or by telephone (203.929.8810). Most of these documents will also be made immediately available for direct download as Adobe PDF files from the TranSwitch World Wide Web Site (www.transwitch.com). Name: ________________________________________________________________________________ Company: ___________________________________________ Title: ______________________________ Dept./Mailstop: __________________________________________________________________________ Street: ________________________________________________________________________________ City/State/Zip: __________________________________________________________________________ If located outside U.S.A., please add - Country: _______________ Telephone: ________________________ Postal Code: ___________________
Ext.: _____________ Fax: __________________________
E-mail: ________________________________________________ Please provide the following details for the managers in charge of the following departments at your company location. Department Company/Division Engineering Marketing Title __________________ __________________ __________________ Name __________________ __________________ __________________
Please describe briefly your intended application(s) and indicate whether you would like to have a TranSwitch applications engineer contact you to provide further assistance: _____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ ____________________________________________________________________________________________ If you are also interested in receiving updated documentation for other TranSwitch device types, please list them below rather than submitting separate registration forms: __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________ __________
Please fold, tape and mail this page (see other side) or fax it to Marketing Communications at 203.926.9453.
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(Fold back on this line second, then tape closed, stamp and mail.)
3 Enterprise Drive Shelton, CT 06484-4694 U.S.A.
First Class Postage Required
TranSwitch Corporation
Attention: Marketing Communications Dept. 3 Enterprise Drive Shelton, CT 06484-4694 U.S.A.
(Fold back on this line first.)
Please complete the registration form on this back cover sheet, and fax or mail it, if you wish to receive updated documentation on this TranSwitch product as it becomes available.
TranSwitch Corporation
*
3 Enterprise Drive
*
Shelton, CT 06484 USA
*
Tel: 203-929-8810
*
Fax: 203-926-9453
*
www.transwitch.com

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