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Integrated Circuit Systems, Inc.
ICS9DB202
PCI EXPRESSTM JITTER ATTENUATOR
Features
* Two 0.7V current mode differential HCSL output pairs * 1 differential clock input * CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL * Maximum output frequency: 140MHz * Output skew: 110ps (maximum) * Cycle-to-cycle jitter: 110ps (maximum) * RMS phase jitter @ 100MHz, (1.5MHz - 22MHz): 2.42ps (typical) * 3.3V operating supply * 0C to 70C ambient operating temperature * Lead-Free package available * Industrial temperature information available upon request
GENERAL DESCRIPTION
The ICS9DB202 is a high perfromance 1-to-2 Differential-to-HCSL Jitter Attenuator designed for use HiPerClockSTM in PCI ExpressTM systems. In some PCI ExpressTM systems, such as those found in desktop PCs, the PCI ExpressTM clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter-attenuating device may be necessary in order to reduce high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS9DB202 has two PLL bandwidth modes. In low bandwidth mode, the PLL loop bandwidth is 500kHz. This setting offers the best jitter attenuation and is still high enough to pass a triangular input spread spectrum profile. In high bandwidth mode, the PLL bandwidth is at 1MHz and allows the PLL to pass more spread spectrum modulation.
ICS
For serdes which have x10 reference multipliers instead of x12.5 multipliers, each of the two PCI ExpressTM outputs (PCIEX0:1) can be set for 125MHz instead of 100MHz by configuring the appropriate frequency select pins (FS0:1).
PIN ASSIGNMENT
PLL_BW CLK nCLK FS0 VDD GND PCIEXT0 PCIEXC0 VDD nOE0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDDA BYPASS IREF FS1 VDD GND PCIEXT1 PCIEXC1 VDD nOE1
BLOCK DIAGRAM
IREF
+
Current Set 1 HiZ 0 Enabled
nOE0
ICS9DB202
nCLK CLK
Phase Detector
Loop Filter
0
VCO
0 /4 1 /5
1
20-Lead TSSOP 6.50mm x 4.40mm x 0.92 package body PCIEXT0 G Package nPCIEXC0 Top View
ICS9DB202
/5 Internal Feedback
0
FS0
20-Lead, 209-MIL SSOP 5.30mm x 7.20mm x 1.75mm body package F Package Top View
PCIEXT1 nPCIEXC1
0 /5 1 /4
1
FS1
BYPASS
nOE1
1 HiZ 0 Enabled
9DB202CG
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REV. A OCTOBER 6, 2004
Integrated Circuit Systems, Inc.
ICS9DB202
PCI EXPRESSTM JITTER ATTENUATOR
Type Input Input Input Input Pullup Description Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5, 9, 12, 16 6, 15 7, 8 10, 11 13, 14 17 18 19 20 Name PLL_BW CLK nCLK FS0 VDD GND PCIEXT0, PCIEXC0 nOE0, nOE1 PCIEXC1, PCIEXT1 FS1 IREF BYPASS VDDA
Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. Pulldown Pullup Frequency select pin. LVCMOS/LVTTL interface levels. Core supply pins. Power supply ground. Differential output pairs. HCSL interface levels. Pulldown Output enable. When HIGH, forces outputs to HiZ state. When LOW, enables outputs. LVCMOS/LVTTL interface levels. Differential output pairs. HCSL interface levels. Pulldown Frequency select pin. LVCMOS/LVTTL interface levels. A fixed precision resistor (475) from this pin to ground provides a reference current used for differential current-mode PCIEX clock outputs. BYPASS pin. When HIGH. bypass mode, when LOW, PLL mode. Pulldown LVCMOS/LVTTL interface levels. Analog supply pin. Requires 24 series resistor.
Power Power Output Input Output Input Input Power Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K
TABLE 3A. RATIO OF OUTPUT FREQUENCY INPUT FREQUENCY FUNCTION TABLE, FS0
Inputs FS0 0 1 Outputs PCIEX0 5/4 1
TO
TABLE 3B. RATIO OF OUTPUT FREQUENCY INPUT FREQUENCY FUNCTION TABLE, FS1
Inputs FS1 0 1 Outputs PCIEX1 1 5/4
TO
TABLE 3C. BYPASS TABLE
Inputs BYPASS 0 1 Mode PLL Mode Bypass Mode (output = inputs)
TABLE 3D. OUTPUT ENABLE FUNCTION TABLE, NOE0
Inputs nOE0 0 1 Outputs PCIEX0 Enabled HiZ
TABLE 3E. OUTPUT ENABLE FUNCTION TABLE, NOE1
Inputs nOE1 0 1 Outputs PCIEX1 Enabled HiZ
TABLE 3F. PLL BANDWIDTH TABLE
Inputs PLL_BW 0 1 Bandwidth 500kHz 1MHz
9DB202CG
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2
REV. A OCTOBER 6, 2004
Integrated Circuit Systems, Inc.
ICS9DB202
PCI EXPRESSTM JITTER ATTENUATOR
4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 73.2C/W (0 lfpm) 80.8C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA 20 Lead TSSOP 20 Lead SSOP Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C, RREF = 475
Symbol VDD VDDA IDD IDDA Parameter Core Supply Voltage Analog Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 112 22 Units V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current BYPASS, nOE0, nOE1, FS1 FS0, PLL_BW BYPASS, nOE0, nOE1, FS1 FS0, PLL_BW VDD = VIN = 3.465V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 5 VDD = 3.465V, VIN = 0V A Units mV mV A
IIL
Input Low Current
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C, RREF = 475
Symbol IIH IIL V PP Parameter Input High Current Input Low Current CLK, nCLK CLK, nCLK Test Conditions VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V 0.15 Minimum Typical Maximum 150 150 1.3 VDD - 0.85 Units A A V V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
9DB202CG
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REV. A OCTOBER 6, 2004
Integrated Circuit Systems, Inc.
ICS9DB202
PCI EXPRESSTM JITTER ATTENUATOR
Test Conditions Minimum 12 680 65 -10 250 10 550 Typical 14 Maximum 16 Units mA V V A mV
TABLE 4D. HCSL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C, RREF = 475
Symbol IOH VOH VOL IOZ VOX Parameter Output Current Output High Voltage Output Low Voltage High Impedance Leakage Current Output Crossover Voltage
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = 0C TO 70C, RREF = 475
Symbol fMAX Parameter Output Frequency Output Skew; NOTE 1, 2 Cycle-to-Cycle Jitter RMS Phase Jitter (Random); NOTE 3 Output Rise/Fall Time Outputs @ Different Frequencies Outputs @ Same Frequencies Integration Range: 1.5MHz - 22MHz 20% to 80% 300 2.42 1100 52 50 Test Conditions Minimum Typical Maximum 140 110 110 50 Units MHz ps ps ps ps ps %
tsk(o) tjit(cc) tjit(O)
tR / tF
o dc Output Duty Cycle 48 NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. NOTE 3: Please refer to the Phase Noise Plot following this section.
9DB202CG
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REV. A OCTOBER 6, 2004
Integrated Circuit Systems, Inc.
ICS9DB202
PCI EXPRESSTM JITTER ATTENUATOR
TYPICAL PHASE NOISE AT 100MHZ
0 -10 -20 -30 -40 -50 -60
PCI ExpressTM Filter 100MHz
RMS Phase Jitter (Random) 1.5MHz to 22MHz = 2.42ps (typical)
NOISE POWER dBc Hz
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
Raw Phase Noise Data
The illustrated phase noise plot was taken using a low phase noise signal generator, the noise floor of the signal generator is less than that of the device under test. Using this configuration allows one to see the true spectral purity or phase noise performance of the PLL in the device under test.
Phase Noise Result by adding PCI ExpressTM Filter to raw data OFFSET FREQUENCY (HZ)
Due to the tracking ability of a PLL, it will track the input signal up to its loop bandwidth. Therefore, if the input phase noise is greater than that of the PLL, it will increase the output phase noise performance of the device. It is recommended that the phase noise performance of the input is verified in order to achieve the above phase noise performance.
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9DB202CG
REV. A OCTOBER 6, 2004
Integrated Circuit Systems, Inc.
ICS9DB202
PCI EXPRESSTM JITTER ATTENUATOR
PARAMETER MEASUREMENT INFORMATION
3.3V5%
VDD
VDD, VDDA
SCOPE
Qx
nCLK
V
PP
Cross Points
V
CMR
CLK
HCSL
GND
GND
0V
3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PCIEXCx
PCIEXC0, PCIEXC1 PCIEXT0, PCIEXT1
PCIEXTy PCIEXCx PCIEXTy
tcycle
n
tjit(cc) = tcycle n -tcycle n+1
tsk(o)
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
PCIEXC0, PCIEXC1
80% Clock Outputs
80% VSW I N G
PCIEXT0, PCIEXT1
Pulse Width t
PERIOD
20%
20% tR tF
odc =
t PW t PERIOD
HCSL OUTPUT RISE/FALL TIME
9DB202CG
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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6
REV. A OCTOBER 6, 2004
tcycle n+1
Integrated Circuit Systems, Inc.
ICS9DB202
PCI EXPRESSTM JITTER ATTENUATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS9DB202 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 24 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin.
3.3V VDD .01F V DDA .01F 10F 24
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
9DB202CG
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REV. A OCTOBER 6, 2004
Integrated Circuit Systems, Inc.
ICS9DB202
PCI EXPRESSTM JITTER ATTENUATOR
here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V
3.3V
LVDS_Driv er
Zo = 50 Ohm
CLK
R1 100
nCLK
Receiv er
Zo = 50 Ohm
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
9DB202CG
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8
REV. A OCTOBER 6, 2004
Integrated Circuit Systems, Inc.
ICS9DB202
PCI EXPRESSTM JITTER ATTENUATOR RELIABILITY INFORMATION
TABLE 6A.
JAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP PACKAGE
JA by Velocity (Linear Feet per Minute)
0 200
98C/W 66.6C/W
500
88C/W 63.5C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
114.5C/W 73.2C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6B.
JAVS. AIR FLOW TABLE FOR 20 LEAD SSOP PACKAGE
JA by Velocity (Linear Feet per Minute)
0 200
73.2C/W
500
69.2C/W
Multi-Layer PCB, JEDEC Standard Test Boards
80.8C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS9DB202 is: 2471
9DB202CG
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REV. A OCTOBER 6, 2004
Integrated Circuit Systems, Inc.
ICS9DB202
PCI EXPRESSTM JITTER ATTENUATOR
20 LEAD TSSOP PACKAGE OUTLINE - F SUFFIX
FOR
PACKAGE OUTLINE - G SUFFIX
FOR
20 LEAD SSOP
TABLE 6A. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 Millimeters Minimum 20 1.20 0.15 1.05 0.30 0.20 6.60 Maximum
TABLE 6B. PACKAGE DIMENSIONS
Millimeters SYMBOL Minimum N A A1 A2 b c D E E1 e L 0.55 0 -0.05 1.65 0.22 0.09 6.90 7.40 5.0 0.65 BASIC 0.95 8 20 2.0 -1.85 0.38 0.25 7.50 8.20 5.60 Maximum
Reference Document: JEDEC Publication 95, MO-153
Reference Document: JEDEC Publication 95, MO-150
9DB202CG
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10
REV. A OCTOBER 6, 2004
Integrated Circuit Systems, Inc.
ICS9DB202
PCI EXPRESSTM JITTER ATTENUATOR
TABLE 7. ORDERING INFORMATION
Part/Order Number ICS9DB202CG ICS9DB202CGT ICS9DB202CGLF ICS9DB202CGLFT ICS9DB202CF ICS9DB202CFT ICS9DB202CFLF ICS9DB202CFLFT Marking ICS9DB202CG ICS9DB202CG ICS9DB202CGL ICS9DB202CGL ICS9DB202CF ICS9DB202CF ICS9DB202CFLF ICS9DB202CFLF Package 20 Lead TSSOP 20 Lead TSSOP on Tape and Reel 20 Lead "Lead-Free" TSSOP 20 Lead "Lead-Free" TSSOP on Tape and Reel 20 Lead SSOP 20 Lead SSOP on Tape and Reel 20 Lead "Lead-Free" SSOP 20 Lead "Lead-Free" SSOP on Tape and Reel Count 72 per Tube 2500 72 per Tube 2500 64 per Tube 1000 64 per Tube 1000 Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C
The aforementioned trademarks, HiPerClockSTM and PCI ExpressTM iare trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 9DB202CG
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REV. A OCTOBER 6, 2004

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