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S3C7295/P7295
PRODUCT OVERVIEW
1
OVERVIEW
PRODUCT OVERVIEW
The S3C7295 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers). With an up-to-704-dot LCD direct drive capability, and flexible 8-bit timer/counter, the S3C7295 offers an excellent design solution for a mid-end LCD game. Up to 8 pins of the 80-pin QFP package can be dedicated to I/O. Six vectored interrupts provide fast response to internal and external events. In addition, the S3C7295's advanced CMOS technology provides for low power consumption.
OTP
The S3C7295 microcontroller is also available in OTP (One Time Programmable) version, S3P7295. S3P7295 microcontroller has an on-chip 16K-byte one-time-programable EPROM instead of masked ROM. The S3P7295 is comparable to S3C7295, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW
S3C7295/P7295
FEATURES
Memory * * 256 x 4-bit RAM (excluding LCD display RAM) 16,384 x 8-bit ROM Memory-Mapped I/O Structure * Data memory bank 15
Power-Down Modes * * * Idle mode (only CPU clock stops) Stop mode (main system oscillation stops) Sub system clock stop mode
8 I/O Pins * I/O: 8 pins
LCD Controller/Driver * * * * 44 segments and 16 common terminals (8, 12 and 16 common selectable) Internal resistor circuit for LCD bias Voltage doubler All dot can be switched on/off * 8-bit Basic Timer * * 4 interval timer functions Watch-dog timer Instruction Execution Times * 8-bit Timer/Counter * * * Programmable 8-bit timer Arbitrary clock output (TCLO0) Inverted clock output (TCLO0) Operating Temperature * - 40 C to 85 C * 0.95, 1.91, 15.3 s at 4.19 MHz (main) 122 s at 32.768 kHz (subsystem) * Oscillation Sources * * * Crystal, ceramic, or RC for main system clock Crystal oscillator for subsystem clock Main system clock frequency: 4.19 MHz (typical) Subsystem clock frequency: 32.768 kHz CPU clock divider circuit (by 4, 8, or 64)
Watch Timer * * * Time interval generation: 0.5 s, 3.9 ms at 32768 Hz Four frequency outputs to BUZ pin and BUZ pin Clock source generation for LCD
Operating Voltage Range * 2.2 V to 3.4 V (0.4 MHz to 4.19 MHz)
Package Type * 80-pin QFP or pellet
Interrupts * * * Two internal vectored interrupts Four external vectored interrupts Two quasi-interrupts
1-2
S3C7295/P7295
PRODUCT OVERVIEW
BLOCK DIAGRAM
RESET
Xin XTin
Xout XTout
P0.3/BUZ/K3 P0.2/CLO/ BUZ/K2 P0.1/TCLO0/K1 P0.0/TCLO0/K0 P1.3/INT P1.2/INT2 P1.1/INT1 P1.0/INT0 I/O PORT 1 I/O PORT 0
INTERRUPT CONTROL BLOCK
CLOCK
INSTRUCTION REGISTER
BASIC TIMER
WATCH-DOG TIMER
INTERNAL INTERRUPT INSTRUCTION DECODER ARITHMETIC AND LOGIC UNIT
PROGRAM COUNTER PROGRAM STATUS WORD STACK POINTER
WATCH TIMER BIAS CA CB
VOLTAGE DOUBLER
8-BIT TIMER/ COUNTER
LCD DRIVER/ CONTROLLER
SEG0-SEG43 COM0-COM15 VLC0
256 x 4-BIT DATA MEMORY
16K BYTES PROGRAM MEMORY
Figure 1-1. S3C7295 Simplified Block Diagram
1-3
PRODUCT OVERVIEW
S3C7295/P7295
PIN ASSIGNMENTS
SEG41 SEG42 SEG43 P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P0.3/BUZ/K3 P0.2/CLO/ BUZ/K2 P0.1/TCLO0/K1 P0.0/TCLO0/K0 VDD VSS Xout Xin TEST XTin XTout RESET CA CB VLC0 BIAS COM15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25
S3C7295
(TOP VIEW)
SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
Figure 1-2. S3C7295 80-QFP Pin Assignment Diagram
1-4
COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEG0
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
S3C7295/P7295
PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C7295 Pin Descriptions Pin Name P0.0 P0.1 P0.2 P0.3 Pin Type I/O Description 4-bit I/O port. 1-bit and 4-bit read/write and test are possible. Individual pins are software configurable as input or output. Individual pins are software configurable as opendrain or push-pull output. Individual pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. Same as port 0. Circuit Number Type E-1 11 10 9 8 Share Pin TCLO0/K0 TCLO0/K1 CLO/BUZ/K2 BUZ/K3
P1.0 P1.1 P1.2 P1.3 INT0, INT1 INT2 INT4 BUZ BUZ CLO TCLO0 TCLO0 COM0-COM15 SEG0-SEG43
I/O
E-1
7 6 5 4 7, 6 5 4 8 9 9 10 11
INT0 INT1 INT2 INT4 P1.0, P1.1 P1.2 P1.3 P0.3/K3 P0.2/CLO/K2 P0.2/BUZ/K2 P0.1/K1 P0.0/K0 - -
I/O I/O I/O I/O I/O I/O I/O I/O O O
External interrupts. The triggering edge for INT0 and INT1 is selectable. Quasi-interrupt with detection of rising or falling edges External interrupt with detection of rising or falling edges. 2 kHz, 4 kHz, 8 kHz or 16 kHz frequency output for buzzer sound. Inverted BUZ signal Clock output Inverted Timer/counter 0 clock output Timer/counter 0 clock output LCD common signal output LCD segment signal output H-6 H-6
39-24 40-80, 1-3
1-5
PRODUCT OVERVIEW
S3C7295/P7295
Table 1-1. S3C7295 Pin Descriptions (Continued) Pin Name K0-K3 VDD VSS RESET CA, CB VCL0 BIAS Xin, Xout XTin, XTout TEST Pin Type I/O - - I - - O - - I Power supply Ground Reset input (active low) Capacitor terminal for voltage doubling LCD power supply input Doubling voltage level output Crystal, ceramic or RC oscillator pins for system clock Crystal oscillator pins for subsystem clock Test input (must be connected to VSS) Description External interrupt (triggering edge is selectable) Circuit Number Share Pin Type E-1 - - B - - - - - - 11-8 12 13 19 20, 21 22 23 15, 14 17, 18 16 P0.0-P0.3 - - - - - - - - -
NOTE: Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.
1-6
S3C7295/P7295
PRODUCT OVERVIEW
PIN CIRCUIT DIAGRAMS
VDD VDD
PNE PULL-UP RESISTOR
VDD
RESISTOR ENABLE I/O N-CH
P-CH
P-CHANNEL IN N-CHANNEL
DATA
OUTPUT DISABLE
SCHMITT TRIGGER
Figure 1-3. Pin Circuit Type A
Figure 1-5. Pin Circuit Type E-1
VLC0
VLC1
VDD
VLC2 PULL-UP RESISTOR SEG/COM DATA IN SCHMITT TRIGGER VLC3 OUT
VLC4 VSS
Figure 1-4. Pin Circuit Type B
Figure 1-6. Pin Circuit Type H-6
1-7
S3C7295/P7295
ELECTRICAL DATA
13
OVERVIEW
ELECTRICAL DATA
In this section, information on S3C7295 electrical characteristics is presented as tables and graphics. The information is arranged in the following order: Standard Electrical Characteristics -- Absolute maximum ratings -- D.C. electrical characteristics -- Main system clock oscillator characteristics -- Subsystem clock oscillator characteristics -- I/O capacitance -- A.C. electrical characteristics -- Operating voltage range Miscellaneous Timing Waveforms -- A.C timing measurement point -- Clock timing measurement at Xin -- Clock timing measurement at XTin -- TCL timing -- Input timing for RESET -- Input timing for external interrupts -- Serial data transfer timing Stop Mode Characteristics and Timing Waveforms -- RAM data retention supply voltage in stop mode -- Stop mode release timing when initiated by RESET -- Stop mode release timing when initiated by an interrupt request
13-1
ELECTRICAL DATA
S3C7295/P7295
Table 13-1. Absolute Maximum Ratings (TA = 25 C) Parameter Supply Voltage Input Voltage Output Voltage Output Current High Symbol VDD VI VO IOH IOL Ports 0, 1 - One I/O pin active All I/O pins active Output Current Low One I/O pin active Conditions - Rating - 0.3 to + 4.5 - 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 15 - 30 + 30 (Peak value) + 15(note) Total for pins 0, 1 Operating Temperature Storage Temperature TA Tstg - - + 100 (Peak value) + 60(note) - 40 to + 85 - 65 to + 150
Duty . C C
Units V V V mA
mA
NOTE: The values for Output Current Low ( IOL ) are calculated as Peak Value x
Table 13-2. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.2 V to 3.4 V) Parameter Input High Voltage Symbol VIH1 VIH2 Input Low Voltage Output High Voltage Output Low Voltage VIL1 VIL2 VOH Conditions Ports 0, 1, and RESET Xin, Xout, and XTin Ports 0, 1, and RESET Xin, Xout, and XTin VDD = 2.2 V to 3.4 V IOH = - 1 mA Ports 0, 1 VDD = 2.2 V to 3.4 V IOL = 5 mA Ports 0, 1 VDD - 1.0 - Min 0.8VDD VDD - 0.1 - - Typ - Max VDD VDD 0.2VDD 0.1 - V V Units V
VOL
-
-
1.0
V
13-2
S3C7295/P7295
ELECTRICAL DATA
Table 13-2. D.C. Electrical Characteristics (Continued) (TA = - 40 C to + 85 C, VDD = 2.2 V to 3.4 V) Parameter Input High Leakage Current Symbol ILIH1 Conditions VI = VDD All input pins except those specified below for ILIH2 VI = VDD Xin, Xout and XTin VI = 0 V All input pins except RESET Xin, Xout and XTin ILIL2 Output High Leakage Current Output Low Leakage Current Pull-Up Resistor ILOH VI = 0 V RESET, Xin, Xout and XTin VO = VDD All output pins VO = 0 V All output pins VI = 0 V; VDD = 3V Ports 0, 1 RL2 LCD Voltage Dividing Resistor (1) VDD-COMi Voltage Drop (i = 0-15) VLCDSEGx Voltage Drop (x = 0-43) Middle Output Voltage (2) RLCD1 VI = 0 V; VDD = 3V; RESET Ta = + 25 C 200 50 450 100 800 150 k - - 3 A - 20 - - Min - Typ - Max 3 Units A
ILIH2 Input Low Leakage Current ILIL1
20 -3 A
ILOL
-
-
-3
A
RL1
50
100
200
k
RLCD2 VDC
Ta = + 25 C VLCD = 3.0 V - 15 A per common pin VLCD = 3.0 V - 15 A per common pin
25 -
50 -
75 120 mV
VDS
-
-
120
VLC0 VLC1 VLC2 VLC3 VLC4
VLC0 = 5.0 V
VLC0-0.2 0.8VLC0-0.2 0.6VLC0-0.2 0.4VLC0-0.2 0.2VLC0-0.2
VLC0 0.8VLC0 0.6VLC0 0.4VLC0 0.2VLC0
VLC0+0.2 0.8VLC0+0.2 0.6VLC0+0.2 0.4VLC0+0.2 0.2VLC0+0.2
V
NOTES: 1. RLCD1 is LCD voltage dividing resistor when LCON.2 = "0", and RLCD2 when LCON.2 = "1". 2. It is middle output voltage when 1/16 duty and 1/5 bias.
13-3
ELECTRICAL DATA
S3C7295/P7295
Table 13-2. D.C. Electrical Characteristics (Concluded) (TA = - 40 C to + 85 C, VDD = 2.2 V to 3.4 V) Parameter Supply Current (1) Symbol IDD1 Conditions VDD = 3V 10% 4.19 MHz (PCON=3H) crystal oscillator C1 = C2 = 22 pF Idle mode; VDD = 3 V 10% 4.19 MHz (PCON=3H) crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10% 32 kHz crystal oscillator Idle mode; VDD = 3 V 10% 32 kHz crystal oscillator Stop mode; VDD = 3 V 10% Stop mode; VDD = 3 V 10%
NOTES: 1. 2. 3. Current in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, voltage doubler, and output port drive currents. Data includes power consumption for subsystem clock oscillation. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the subsystem clock is used.
Min -
Typ 1.3
Max 3.0
Units mA
IDD2
0.4
1.0
IDD3 (2) IDD4 (2) IDD5
-
15 5
30 15 3 2
A
SCMOD=0000B, XTin=0V SCMOD=0100B
0.5 0.2
13-4
S3C7295/P7295
ELECTRICAL DATA
Table 13-3. Main System Clock Oscillator Characteristics (TA = - 40 C to + 85 C, VDD = 2.2 V to 3.4 V) Oscillator Ceramic Oscillator Clock Configuration
Xin Xout (1)
Parameter Oscillation frequency
Test Condition -
Min 0.4
Typ -
Max 4.19
Units MHz
C1
C2
Stabilization time (2)
Stabilization occurs when VDD is equal to the minimum oscillator voltage range; VDD = 3.0 V -
-
-
4
ms
Crystal Oscillator
Xin
Xout
Oscillation frequency
(1)
0.4
-
4.19
MHz
C1
C2
Stabilization time (2) External Clock
Xin Xout
VDD = 3.0 V -
- 0.4
- -
10 4.19
ms MHz
Xin input frequency (1)
Xin input high and low level width (tXH, tXL) RC Oscillator
Xin R Xout
- VDD = 3 V
83.3 0.4
- -
1250 1.5
ns MHz
Frequency
NOTES: 1. Oscillation frequency and Xin input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillator stabilization after a power-on occurs, or when stop mode is terminated.
13-5
ELECTRICAL DATA
S3C7295/P7295
Table 13-4. Recommended Oscillator Constants (TA = - 40 C to + 85 C, VDD = 2.2 V to 3.4 V) Manufacturer Series Number (1) FCR FCR CCR M5 MC5 MC3 Frequency Range Load Cap (pF) C1 TDK 3.58 MHz-4.2 MHz 3.58 MHz-4.2 MHz 3.58 MHz-4.2 MHz 33
(2)
Oscillator Voltage Range (V) MIN 2.2 2.2 2.2 MAX 3.4 3.4 3.4
Remarks
C2 33
(2)
Leaded Type On-chip C Leaded Type On-chip C SMD Type
(3)
(3)
NOTES: 1. Please specify normal oscillator frequency. 2. On-chip C: 30pF built in. 3. On-chip C: 38pF built in.
Table 13-5. Subsystem Clock Oscillator Characteristics (TA = - 40 C to + 85 C, VDD = 2.2 V to 3.4 V) Oscillator Crystal Oscillator Clock Configuration
XTin XTout
Parameter Oscillation frequency (1)
Test Condition -
Min 32
Typ 32.768
Max 35
Units kHz
C1
C2
Stabilization time (2) External Clock
XTin XTout
VDD = 2.2 V to 3.4 V -
- 32
1.0 -
3 100
s kHz
XTin input frequency (1)
XTin input high and low level width (tXTL, tXTH)
-
5
-
15
s
NOTES: 1. Oscillation frequency and XTin input frequency data are for oscillator characteristics only. 2. Stabilization time is the interval required for oscillating stabilization after a power-on occurs.
13-6
S3C7295/P7295
ELECTRICAL DATA
Table 13-6. Input/Output Capacitance (TA = 25 C, VDD = 0 V ) Parameter Input Capacitance Output Capacitance I/O Capacitance Symbol CIN COUT CIO Condition f = 1 MHz; Unmeasured pins are returned to VSS Min - - - Typ - - - Max 15 15 15 Units pF pF pF
Table 13-7. Voltage Doubler Output (TA = -40 C to + 85 C, VDD = 2.2 V to 3.4 V) Parameter Voltage Doubler Output Symbol Vbias Condition VDD = 2.2 V to 3.4 V Min - Typ 2 VDD Max - Units V
Table 13-8. A.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.2 V to 3.4 V) Parameter Instruction Cycle Time (note) Interrupt Input High, Low Width RESET Input Low Width Symbol tCY Conditions VDD = 2.2 V to 3.4 V With subsystem clock (fxt) f INTH, f INTL tRSL INT0-INT2, INT4 K0-K3 Input Min 0.95 114 10 10 Typ - 122 - - Max 64 125 - - Units s
NOTE: Unless otherwise specified, Instruction Cycle Time condition values assume a main system clock ( fx ) source.
13-7
ELECTRICAL DATA
S3C7295/P7295
CPU CLOCK 1.05 MHz
Main OSC frequency (Divided by 4) 4.2 MHz
15.6 kHz 1 2 3 4 5 6 7
2.2V SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
Figure 13-1. Standard Operating Voltage Range
Table 13-9. RAM Data Retention Supply Voltage in Stop Mode (TA = - 40 C to + 85 C) Parameter Data retention supply voltage Data retention supply current Release signal set time Oscillator stabilization wait time (1) Symbol VDDDR IDDDR tSREL tWAIT Conditions - VDDDR = 2.2 V - Released by RESET Released by interrupt Min 2.2 - 0 - - Typ - 0.1 - 217 / fx
(2)
Max 3.4 10 - - -
Unit V A s ms
NOTES: 1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator start-up. 2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.
13-8
S3C7295/P7295
ELECTRICAL DATA
TIMING WAVEFORMS
INTERNAL RESET OPERATION STOP MODE DATA RETENTION MODE IDLE MODE NORMAL MODE
~ ~ ~ ~
VDD
VDDDR
EXECUTION OF STOP INSTRUCTION RESET
tWAIT tSREL
Figure 13-2. Stop Mode Release Timing When Initiated by RESET
IDLE MODE
~ ~
STOP MODE DATA RETENTION MODE
NORMAL MODE
VDD
EXECUTION OF STOP INSTRUCTION
POWER-DOWN MODE TERMINATING SIGNAL (INTERRUPT REQUEST)
Figure 13-3. Stop Mode Release Timing When Initiated by Interrupt Request
~ ~
VDDDR tSREL t WAIT
13-9
ELECTRICAL DATA
S3C7295/P7295
0.8 VDD 0.2 VDD
MEASUREMENT POINTS
0.8 VDD 0.2 VDD
Figure 13-4. A.C. Timing Measurement Points (Except for Xin and XTin)
1 / fx
tXL
tXH
Xin
VDD-0.5 V 0.4 V
Figure 13-5. Clock Timing Measurement at Xin
1 / f xt
t XTL
t XTH
XTin
VDD - 0.5 V 0.4 V
Figure 13-6. Clock Timing Measurement at XT in
13-10
S3C7295/P7295
ELECTRICAL DATA
tRSL
RESET 0.2 VDD
Figure 13-7. Input Timing for RESET Signal
tINTL
t INTH
INT0, 1, 2, 4, K0 to K3
0.8 VDD 0.2 VDD
Figure 13-8. Input Timing for External Interrupts
13-11
ELECTRICAL DATA
S3C7295/P7295
NOTES
13-12
S3C7295/P7295
ELECTRICAL DATA
CHARACTERISTIC CURVES
NOTE The characteristic values shown in the following graphs are based on actual test measurements. They do not, however, represent guaranteed operating values.
(TA = 25 C, fx = 4.2 MHz)
5.0 4.5 IDD1, CPU Clock = fx/4 4.0 3.5 3.0 2.5 2.0 IDD1, CPU Clock = fx/64 1.5 1.0 0.5 IDD2
IDD1, IDD2 (mA)
0
2.7
4.0
4.5
6.0
VDD (V) Figure 13-11. IDD1, IDD2 VS. VDD
13-13
ELECTRICAL DATA
S3C7295/P7295
(T A = 25 C, fx = 32.768 kHz)
50 45 I DD3 40 35
IDD3, 4, 5 (A)
30 25 20 15 10 5 I DD5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 I DD4
VDD (V) Figure 13-12. IDD3, IDD4, IDD5 VS. VDD
13-14
S3C7295/P7295
ELECTRICAL DATA
(TA = 25 C, CPU CLOCK = fx/4)
4.5 VDD = 6.0 V 4.0 3.5
IDD1 (mA)
3.0 2.5 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VDD = 4.5 V
4.5
Main System Clock Frequency (MHz) Figure 13-13. IDD1 VS. Main System Clock Frequency
(TA = 25 C)
1.6 1.4 1.2 VDD = 6.0 V
I DD2 (mA)
1.0 0.8 0.6 0.4 0.2 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VDD = 4.5 V
4.5
Main System Clock Frequency (MHz) Figure 13-13. IDD2 VS. Main System Clock Frequency
13-15
ELECTRICAL DATA
S3C7295/P7295
(TA = 25 C, Ports 0, 2, 3, 4, 5, 6, 7)
-25.0 -22.5 -20.0 -17.5
IOH (mA)
-15.0 -12.5 -10.0 -7.5 -5.0 -2.5 VDD = 4.5 V 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD = 6.0 V
VOH (V) Figure 13-15. IOH VS. VOH (P0, 2, 3, 4, 5, 6, 7)
13-16
S3C7295/P7295
ELECTRICAL DATA
(TA = 25 C, Ports 8, 9)
-25.0 -22.5 -20.0 -17.5
IOH (mA)
-15.0 -12.5 -10.0 -7.5 -5.0 -2.5 VDD = 4.5 V 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD = 6.0 V
VOH (V) Figure 13-16. IOH VS. VOH (P8, 9)
13-17
ELECTRICAL DATA
S3C7295/P7295
(TA = 25 C, Ports 0, 2, 3, 4, 5, 6, 7)
55.0 50.0 45.0 40.0 VDD = 6.0 V
IOL (mA)
35.0 30.0 25.0 20.0 15.0 10.0 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VDD = 4.5 V
5.0
5.5
6.0
VOL (V) Figure 13-17. IOL VS. VOL (P0, 2, 3, 4, 5, 6, 7)
13-18
S3C7295/P7295
ELECTRICAL DATA
(TA = 25 C, Ports 8, 9)
55.0 50.0 45.0 40.0 VDD = 6.0 V
IOL (mA)
35.0 30.0 25.0 20.0 15.0 10.0 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VDD = 4.5 V
5.0
5.5
6.0
VOL (V) Figure 13-18. IOL VS. VOL (P8, 9)
13-19
S3C7295/P7295
MECHANICAL DATA
14
OVERVIEW
MECHANICAL DATA
The S3C7295/P7295 is available in a 80-QFP-1420 package.
23.90 0.30 20.00 0.20 0-8
+ 0.10
0.15 - 0.05
17.90 0.30
14.00 0.20
80-QFP-1420C
0.80 0.20 #1 0.80 0.35 + 0.10 0.15 MAX
0.10 MAX
#80
0.05 MIN (0.80) 2.65 0.10 3.00 MAX
0.80 0.20
NOTE: Dimensions are in millimeters.
Figure 14-1. 80-QFP-1420C Package Dimensions
14-1
S3C7295/P7295
S3P7295 OTP
15
OVERVIEW
S3P7295 OTP
The S3P7295 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C7295 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. The S3P7295 is fully compatible with the S3C7295, both in function and in pin configuration. Because of its simple programming requirements, the S3P7295 is ideal for use as an evaluation chip for the S3C7295.
15-1
S3P7295 OTP
S3C7295/P7295
SEG41 SEG42 SEG43 P1.3/INT4 P1.2/INT2 P1.1/INT1 P1.0/INT0 P0.3/BUZ/K3 P0.2/CLO/ BUZ/K2 SDAT / P0.1/ TCLO0/K1 SCLK /P0.0/TCLO0/K0 VDD /VDD VSS/VSS Xout Xin VPP/TEST XTin XTout RESET / RESET CA CB VLC0 BIAS COM15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25
S3P7295
(TOP VIEW)
SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
Figure 15-1. S3P7295 Pin Assignments (80-QFP Package)
15-2
COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEG0
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
S3C7295/P7295
S3P7295 OTP
Table 15-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip Pin Name P0.1 Pin Name SDAT Pin No. 10 During Programming I/O I/O Function Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. Serial clock pin. Input only pin. Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.5 V is applied, OTP is in writing mode and when 5 V is applied, OTP is in reading mode. (Option) Chip initialization Logic power supply pin. VDD should be tied to +5 V during programming.
P0.0 TEST
SCLK VPP(TEST)
11 16
I/O I
RESET VDD/VSS
RESET VDD/VSS
19 12/13
I I
Table 15-2. Comparison of S3P7295 and S3C7295 Features Characteristic Program Memory Operating Voltage (VDD) OTP Programming Mode Pin Configuration EPROM Programmability 2.2 V to 3.4 V VDD = 5 V, VPP(TEST)=12.5V 80 QFP User Program 1 time 80 QFP Programmed at the factory S3P7295 16 Kbyte EPROM S3C7295 16 Kbyte mask ROM 2.2 V to 3.4 V
OPERATING MODE CHARACTERISTICS When 12.5 V is supplied to the VPP(TEST) pin of the S3P7295, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 15-3 below. Table 15-3. Operating Mode Selection Criteria VDD 5V VPP (TEST) 5V 12.5 V 12.5 V 12.5 V REG/MEM 0 0 0 1 Address (A15-A0) 0000H 0000H 0000H 0E3FH R/W 1 0 1 0 EPROM read EPROM program EPROM verify EPROM read protection Mode
NOTE: "0" means Low level; "1" means High level.
15-3
S3P7295 OTP
S3C7295/P7295
Table 15-4. D.C. Electrical Characteristics (TA = - 40 C to + 85 C, VDD = 2.2 V to 3.4 V) Parameter Supply Current (1) Symbol IDD1 Conditions VDD = 3V 10% 4.19 MHz (PCON=3H) crystal oscillator C1 = C2 = 22 pF Idle mode; VDD = 3 V 10% 4.19 MHz (PCON=3H) crystal oscillator C1 = C2 = 22 pF VDD = 3 V 10% 32 kHz crystal oscillator Idle mode; VDD = 3 V 10% 32 kHz crystal oscillator Stop mode; VDD = 3 V 10% Stop mode; VDD = 3 V 10% SCMOD=0000B, XTin=0V SCMOD=0100B - Min - Typ 1.3 Max 3.0 Units mA
IDD2
0.4
1.0
IDD3 (2) IDD4 (2) IDD5
15 5 0.5 0.2
30 15 3 2
A
NOTES: 1. Data includes power consumption for subsystem clock oscillation. 2. When the system clock control register, SCMOD, is set to 1001B, main system clock oscillation stops and the subsystem clock is used. 3. Current in the following circuits are not included; on-chip pull-up resistors, internal LCD voltage dividing resistors, voltage doubler, and output port drive currents.
CPU CLOCK 1.05 MHz
Main OSC frequency (Divided by 4) 4.2 MHz
15.6 kHz 1 2 3 4 5 6 7
2.2V SUPPLY VOLTAGE (V) CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
Figure 15-2. Standard Operating Voltage Range
15-4

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