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LH77790B
Embedded Microcontroller
Thermal & Electrical Specification
Version 1.0
(R)
SHARP reserves the right to make changes in specifications described herein at any time and without notice in order to improve design or reliability. SHARP does not assume any responsibility for the use of any circuitry described; no circuit patent licenses are implied. SHARP assumes no responsibility for damage caused by misuse or improper use of devices.
LIFE SUPPORT POLICY
SHARP components should not be used in medical devices with life support functions, safety equipment (or similar applications where component failure would result in loss of life or physical harm), aerospace equipment, telecommunication equipment (trunk lines) or nuclear power control equipment. Contact a SHARP representative or sales office before using SHARP devices for any applications other than those recommended by SHARP.
LIMITED WARRANTY
Sharp warrants to its Customer that the Products will be free from defects in material and workmanship under normal use and service for a period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that Sharp will either (i) repair or replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the failure to Sharp in writing) or, (ii) if Sharp is unable to repair or replace, refund the purchase price of the Product upon its return to Sharp. This warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or which has been altered or modified in design or construction, or which has been serviced or repaired by anyone other than Sharp. The warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will Sharp be liable, or in any way responsible, for any incidental or consequential economic or property damage. The above warranty is also extended to Customers of Sharp authorized distributors with the following exception: reports of failures of Products during the warranty period and return of Products that were purchased from an authorized distributor must be made through the distributor. In case Sharp is unable to repair or replace such Products, refunds will be issued to the distributor in the amount of distributor cost. Trademark Advanced RISC Machines, United Kingdom. LH77790B Embedded Microcontroller Preliminary User's Guide Version 1.0 (c) 1999 Copyright SHARP Microelectronics of the Americas. Printed and Bound in USA.
Reference No. SMA99104
Thermal & Electrical Specification
Overview
Portable devices are becoming more and more prevalent in our daily life. They are used as personal information managers, communication devices, digital cameras, handheld games, bar-code scanners, medical equipment, electronic instrumentation, and navigation systems. There are significant design challenges for portable devices. Low cost is a top priority for high volume products. Low power is a must for long battery life. High performance is critical for computationally-intensive applications such as PDAs, GPS, and 2-D scanners. Communication capabilities and effective user interface are integral parts of any portable device. Last, but not least, superior product development support tools are crucial to reducing time-to-market. The Sytem On Chip team at SHARP has designed the LH77790B Embedded Microcontroller (a.k.a. 790B) to meet the above challenges in portable design. The LH77790B, powered by an ARM7DITM, is a complete system on chip with a high level of integration to satisfy a wide range of customer requirements and expectations. The 790B combines a 32-bit ARM7DI RISC engine, a number of essential peripherals (UARTs, Counter/Timers, PIOs, PWMs, etc...), LCD controller, cache, and on-chip SRAM. This high level of integration lowers overall system cost, reduces development cycle time and accelerates product introduction. The 790B's fully static design, power management unit, dual voltage operation (3.3 V/5 V), fast interrupt response time, on-chip cache and SRAM, powerful instruction set, and very low power RISC core provide high performance at low current draw. The on-chip LCD controller, UARTs, IrDA/DASK, and the programmable peripheral interface (PPI) are well suited for wireless, cable, and visual communication requirements. Other features like, watchdog timer, programmable memory interface, onchip SRAM/DRAM controllers and debug support provides a high level of flexibility. Please check our website at www.sharpsma.com or with your local SHARP sales office for the latest Thermal and Electrical Specifications and/or errata sheets. These documents will contain the latest parameters for the LH77790B.
Thermal & Electrical Specification
1
LH77790B
Features
* Highly Integrated Single Chip * 32-Bit ARM7DI RISC Core - Built-In Debug and ICE Support - Fast Interrupt Response - Powerful Instruction Set * 26-bit External Address Bus - 512MB Addressable Space * 16-bit External Data Bus * 2KB Data/Instruction Cache - 4 Way Set Associative - Write Back Policy - Flexible Modes of Operation * 2KB Static RAM - Expandable to 4KB without Cache * Low Power * High Performance * Programmable Clock and Power Management * Programmable Monochrome LCD Controller - 1024 (V) x 2048 (H) - Four Gray Shades - Frame buffer in Main Memory * On-Chip Interrupt Controller - Six External Interrupts - Seven Internal Interrupts - ARM7DI Wake-Up * Three UARTs - 16C450-class - Full Modem Support on UART0 - Partial Modem Support on UART1 - IrDA-1.0/DASK Support on UART2 * IrDA/DASK IR Interface - IrDA-1.0 (2.4 kbps to 115.2 kbps) - DASK (2.4 kbps to 57.6 kbps) * Three Pulse Width Modulator Channels - PWM0 and PWM1 have 8-Bit Resolution - PWM2 has 16-Bit Resolution
2
Thermal & Electrical Specification
LH77790B * Flexible Memory Interface - Six Multiplexeled Chip Enables/CAS pins - Two RAS pins - Fully Programmable - Six SRAM Banks (64MB each) - Two DRAM Banks (128MB each) - Access Privileges (System/User) * On-Chip DRAM Controller - Fast Page Mode - Normal Mode - CAS before RAS Refresh * Programmable Peripheral Interface (PPI) - 24 Programmable I/O Signals - Three Modes of Operation * Three 16-Bit Counter/Timer Channels - Six Modes of Operation - Binary or BCD Counting * Hardware Watchdog Timer - Eight Time-out Intervals - Protection Mechanism - Three Time-out Actions * Little Endian * JTAG Interface * Dual Supply Voltage - 5 V TTL - 25 MHz - 3.3 V LVTTL - 16.7 MHz
Development Environment
The 790B Evaluation Board (part number LU7790AH2A) and the ARM Software Development ToolKit (part number LU7V211H1) give users full access to the power and features of the 790B and provide a complete integrated environment for development. Users will be able to develop, benchmark, and profile both hardware and software easily and quickly.
Thermal & Electrical Specification
3
LH77790B
Block Diagram
CLOCK(S) JTAG INTERRUPTS RESET LCD DISPLAY
CLOCK/POWER MANAGEMENT
ARM7DI TAP CONTROLLER
INT/RESET CONTROLLER
LCD CONTROLLER
ARM7DI CPU AND CACHE 32-BIT INTERNAL BUS
2K BYTES SCRATCH PAD SRAM EXTERNAL MEMORY INTERFACE
BUS CONTROLLER
PWM
82C55 PROGRAMMABLE PERIPHERAL INTERFACE
16C450 UARTS
82C54 COUNTER/ TIMERS
WATCH DOG TIMER
IrDA/ DASK
3 CHANNELS
24 BITS
CH 0/CH 1
CH 2
CH 0 CH 1 CH 2
ARM-8
Figure 1. LH77790B Block Diagram
4
Thermal & Electrical Specification
LH77790B
Pin Description
Table 1. Pin Descriptions
PINS NAME DIRECTION EXTERNAL BUS INTERFACE 36 - 31, 28 - 21, 18 - 11, 8 - 5 60 - 55, 52 - 47, 42 - 41, 38 - 37 72 A[25:0] D[15:0] O I/O External Address bus. The 790B will provide a 26-bit address to external memories and peripherals. External 16-Bit data bus. Output Enable for external memory and peripherals. OE allows external memory and peripherals to drive the data bus and is asserted LOW during a read access and HIGH during a write access. Write Enable for external memory and peripherals. During a write access, this pin is driven LOW. During a read access, this pin is driven HIGH. These pins provide the Chip Enable/Column Address Select signals allowing direct connection to standard external memory/peripheral devices. The pins act as CAS when interfacing to DRAMs and as CE otherwise. They are fully programmable by the system designer and can support byte enables. Row Address Select pins for DRAM Bank 0 and Bank 1. External Memory Wait. Allows the use of slow memories. The 790B generates external WAIT cycles (EWC) in response to activating WAIT. WAIT is sampled on the HIGH to LOW transition on XCLK. To add one EWC, WAIT must be active prior to sampling in the last cycle (beginning of the last cycle) of a memory transfer. If WAIT continues to be active (when sampled) in subsequent cycles, more EWC will be added. Once WAIT is deactivated, the 790B will complete the memory transfer. Byte Wide Access. BW is LOW when the ARM7DI executes a store/ load byte instruction. BW is HIGH when the ARM7DI Core executes a store/load word instruction or an instruction fetch. BW does not depend on the bus size of the external memory/peripheral device. BW is valid during an external memory access. It can be used by an external address decoder to generate extra chip/byte enables. BW is a don't care during DRAM refresh. Byte Boot selects between x8 or x16 for the boot memory. The 790B samples and captures the state of BB on the rising edge of RESETI allowing BB to change state after Reset. If BB is LOW the 790B will boot from a x8 memory. If BB is HIGH, the 790B will boot from a x16 memory. This pin is normally tied LOW for x8 boot memory or HIGH for x16 boot memory. Counter/Timer control gate input signals. Counter/Timer output signals. INTERRUPT INTERFACE 107 - 102 INT[5:0] I External interrupt input signals. DESCRIPTION
OE
O
71
WE
O
70 - 65
CE[5:0]/ CAS[5:0]
O
62 - 61
RAS[1:0]
O
74
WAIT
I
73
BW
O
169
BB
I
COUNTERS/TIMERS INTERFACE 123, 121, 117 124, 122, 118 CTGATE[2:0] CTOUT[2:0] I O
Thermal & Electrical Specification
5
LH77790B Table 1. Pin Descriptions
PINS NAME DIRECTION LCD CONTROLLER INTERFACE 91 92 93 94 95 84 - 77 CP2 CP1 MCLK S LCDCNTL VD[7:0] O O O O O O Shift/Pixel Clock. Line Pulse/HSYNC. AC Modulation Signal. Frame Pulse/VSYNC. LCD Control Signal. Video Data. Parallel ports A, B, and C signals. Signals have programmable access and can function as Input, Output or Controls (port C only). PB[7:2] and PC[2:0] are multiplexed with UARTs modem signals. PWM INTERFACE 98 - 96 PWM[2:0] O Pulse Width Modulator output signals. UARTs INTERFACE 114, 112, 108 115, 113, 111 150, 151 145, 146 142, 147 152 149 148 RxD[2:0] TxD[2:0] RTS[1:0] CTS[1:0] RI[1:0] DTR0 DSR0 DCD0 I O O I I O I I UART serial data input signals. RxD2 also doubles as the digital input for the IR interface. UART serial data output signals. TxD2 also doubles as the digital output for the IR interface. Request To Send for UART0 and UART1. Multiplexed with PC0 and PC1 respectively. Clear To Send for UART0 and UART1. Multiplexed with PB3 and PB4 respectively. Ring Indicator for UART0 and UART1. Multiplexed with PB2 and PB5 respectively. Data Terminal Ready for UART0 only. Multiplexed with PC2. Data Set Ready for UART0 only. Multiplexed with PB7. Data Carrier Detect for UART0 only. Multiplexed with PB6. Chip and JTAG TAP Controller Reset Input. RESETI has a built-in glitch detector. RESETO will be driven LOW after a valid reset is detected for as long as RESETI is driven LOW. JTAG reset, TRST, is internally connected to RESETI. Chip Reset Output. It will be driven LOW during: 1. Chip Reset 2. WDT Timeout Reset 3. Software Controlled Reset The 790B External Clock Input pin. Duty cycle is 50%. XCLKDIS is an active HIGH output pin that can be used to disable external clock circuitry and will result in reducing current consumption to micro-amperes. XCLKDIS is HIGH in Sleep and Stop modes. Connecting this pin to the external clock circuitry, allows the 790B to go into Stop mode by disabling the external clock. UART/DASK Demodulator External clock input signal. Duty cycle is 50%. Counter/Timer External clock input signal. Duty cycle is 50%. DESCRIPTION
PROGRAMMABLE PERIPHERAL INTERFACE 139 - 135, 128 - 126 149 - 145, 142 - 140 159 - 155, 152 - 150 PA[7:0] PB[7:0] PC[7:0]
I/O
RESET AND EXTERNAL CLOCKS
101
RESETI**
I
119
RESETO
O
3
XCLK
I
162
XCLKDIS
O
116 125
UCLK CTCLK
I I
6
Thermal & Electrical Specification
LH77790B Table 1. Pin Descriptions
PINS NAME DIRECTION JTAG INTERFACE* 160 TCK I JTAG Test/EmbeddedICETM clock input signal. Must be pulled-up for normal operation (56 k is recommended for compatibility with ARM's EmbeddedICE) JTAG Test/EmbeddedICE mode select input signal. Must be pulled-up for normal operation (56 k is recommended for compatibility with ARM's EmbeddedICE) JTAG Test/EmbeddedICE data input signal. Must be pulled-up for normal operation (56 k is recommended for compatibility with ARM's EmbeddedICE) JTAG Test/EmbeddedICE data output signal. RESERVED INTERFACE 170 167 168 171 172 9, 19, 29, 39, 53, 63, 75, 85, 99, 109, 129, 143, 153, 163, 173 4, 10, 20, 30, 40, 54, 64, 76, 86, 100, 110, 120, 130, 144, 154, 164, 174 1, 2, 43, 44, 45, 46, 87, 88, 89, 90, 131, 132, 133, 134, 175, 176 ADBE TEST0 TEST1 TEST2 TEST3 I I O I O Reserved. Must be tied HIGH for normal operation. Reserved. Must be tied LOW for normal operation. Reserved. No Connect. Reserved. Must be tied LOW for normal operation Reserved. No Connect POWER SIGNALS VCC I Power. All LH77790B are 5 V/3.3 V. DESCRIPTION
161
TMS
I
165 166
TDI TDO
I O
VSS
I
Ground. All ground pins must be used.
NO CONNECT
NC
--
No connection.
NOTE: *JTAG Reset, TRST, is internally connected to RESETI. IEEE 1149.1 - 1990 Standard requires JTAG Inputs to be pulled up to a good logic level to achieve normal operations.
Thermal & Electrical Specification
7
LH77790B Table 2. Pinout
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 SIGNAL NC NC XCLK VSS A0 A1 A2 A3 VCC VSS A4 A5 A6 A7 A8 A9 A10 A11 VCC VSS A12 A13 A14 A15 A16 A17 A18 A19 VCC VSS A20 A21 A22 A23 A24 A25 D0 D1 VCC VSS D2 D3 NC NC PIN 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 SIGNAL NC NC D4 D5 D6 D7 D8 D9 VCC VSS D10 D11 D12 D13 D14 D15 RAS0 RAS1 VCC VSS CE0/CAS0 CE1/CAS1 CE2/CAS2 CE3/CAS3 CE4/CAS4 CE5/CAS5 WE OE BW WAIT VCC VSS VD0 VD1 VD2 VD3 VD4 VD5 VD6 VD7 VCC VSS NC NC PIN 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 SIGNAL NC NC CP2 CP1 MCLK S LCDCNTL PWM0 PWM1 PWM2 VCC VSS RESETI INT0 INT1 INT2 INT3 INT4 INT5 RxD0 VCC VSS TxD0 RxD1 TxD1 RxD2 TxD2 UCLK CTGATE0 CTOUT0 RESETO VSS CTGATE1 CTOUT1 CTGATE2 CTOUT2 CTCLK PA0 PA1 PA2 VCC VSS NC NC PIN 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 SIGNAL NC NC PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2/RI1 VCC VSS PB3/CTS1 PB4/CTS0 PB5/RI0 PB6/DCD0 PB7/DSR0 PC0/RTS1 PC1/RTS0 PC2/DTR0 VCC VSS PC3 PC4 PC5 PC6 PC7 TCK TMS XCLKDIS VCC VSS TDI TDO TEST0 TEST1 BB ADBE TEST2 TEST3 VCC VSS NC NC
8
Thermal & Electrical Specification
LH77790B
Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings
PARAMETER Supply Voltage Input Voltage Output Voltage Storage Temperature Power Dissipation (Package Limit) SYMBOL VCC VIN VOUT TSTG PDPKG RATING -0.3 to 6.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -40 to +125 1 UNIT V V V C W
NOTE: These are stress ratings for transient conditions only. Operation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the device.
Recommended Operating Conditions
Table 4. LH77790B (5 V Operation) Recommended Operating Conditions
PARAMETER Supply Voltage Supply Voltage Clock Frequency Operating Temperature SYMBOL VCC VSS FXCLK TOPR MIN. 4.5 0 0 0 TYP. 5.0 0 -- -- MAX. 5.5 0 25 70 UNIT V V MHz C
NOTE: Unused input pins should be pulled LOW or HIGH to their inactive state.
Table 5. LH77790B (3.3 V Operation) Recommended Operating Conditions
PARAMETER Supply Voltage Supply Voltage Clock Frequency Operating Temperature SYMBOL VCC VSS FXCLK TOPR MIN. 3.0 0 0 0 TYP. 3.3 0 -- -- MAX. 3.6 0 16.7 70 UNIT V V MHz C
NOTE: Unused input pins should be pulled LOW or HIGH to their inactive state.
Thermal & Electrical Specification
9
LH77790B
DC Specifications
Over recommended operating voltage and temperature conditions, unless otherwise specified. Table 6. LH77790B DC Specifications
PARAMETER Input LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Input Leakage Current HIGH Impedance (OFF-State) Output Leakage Current Operating Current (Active Mode) Operating Current (Standby Mode) Operating Current (Sleep Mode) Operating Current (Stop Mode) SYMBOL VIL VIH VIL VIH VOL VOH VOL VOH ILI IOZ ICCAT VOLTAGE RANGE 3.3 V/5 V 3.3 V/5 V 3.3 V/5 V 3.3 V/5 V 3.3 V 5V 3.3 V 5V 3.3 V 5V 3.3 V 5V 3.3 V/5 V 3.3 V/5 V 3.3 V 5V ICCSB ICCSL ICCST 3.3 V 5V 3.3 V 5V 3.3 V 5V Operating temperature 0C to 50C IOL = 1 mA, VCC = 3 V IOL = 2 mA, VCC = 4.5 V IOH = -1 mA, VCC = 3 V IOH = -2 mA, VCC = 4.5 V IOL = 100 A, VCC = 3 V IOL = 200 A, VCC = 4.5 V IOH = -100 A, VCC = 3 V IOH = -200 A, VCC = 4.5 V VIN = 0 V to VCCMAX VIN = 0 V to VCCMAX TEST CONDITION MIN. 0 2.0 0 VCC - 0.2 -- -- 2.4 2.4 -- -- VCC - 0.2 VCC - 0.2 -5 -5 -- -- -- -- -- -- -- -- MAX. UNIT NOTES 0.8 VCC 0.2 VCC 0.4 0.4 -- -- 0.2 0.2 -- -- 5 5 60 115 2 4 1 2 40 200 V V V V V V V V V V V V A A mA mA mA mA mA mA A A 3 3 4 4 5 5 6 6 1 1 2 2 1 1 1 1 2 2 2 2
NOTES: 1. TTL 2. CMOS 3. Condition 1: CMOS input levels (Note 2), for recommended operating conditions see Table 4. XCLK Frequency = 25 MHz (5 V) or 16 MHz (3.3 V) 4. Condition 2: Same as Condition 1 with core and peripherals halted. DRAM Refresh is active. 5. Condition 3: Same as Condition 2 with DRAM Refresh disabled. 6. Condition 4: Same as Condition 3 with XCLK stopped.
10
Thermal & Electrical Specification
LH77790B
AC Test Conditions
Table 7. AC Test Conditions1
PARAMETER Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load NOTE: 1. Applies to LH77790B (3.3 V and 5.0 V ranges). 2. Includes scope and jig capacitance. RATING VSS to VCC 5 1.5 50 UNIT V ns V pF 2 NOTE
Pin Capacitance
Table 8. Pin Capacitance1
PARAMETER Input Capacitance Output Capacitance I/O Capacitance SYMBOL CIN COUT CIO MAX. 10 20 20 UNIT pF pF pF NOTE 2 2 2
NOTE: 1. Applies to LH77790B (3.3 V and 5.0 V ranges). 2. Measurement Condition: All pins are set to 0 V except measured pin.
AC Specifications
Over Recommended operating voltage, temperature and AC test conditions.
External Clocks
tXCLK tXCLKL tXCLKH
ARM2-99
Figure 2. System Clock AC Timing
Thermal & Electrical Specification
11
LH77790B
tCTCLK tCTCLKH tCTCLKL
ARM2-100
Figure 3. External Counters/Timers Clocks AC Timing
tUCLK tUCLKH tUCLKL
ARM2-101
Figure 4. External UARTs/DASK Clock AC Timing Table 9. External Clocks AC Specifications
PARAMETER tXCLK tXCLKH tXCLKL tCTCLK tCTCLKH tCTCLKL tUCLK* tUCLKH* tUCLKL* DESCRIPTION XCLK (System Clock) Period XCLK HIGH Time XCLK LOW Time CTCLK (Counters/Timers External Clock) Period CTCLK HIGH Time CTCLK LOW Time UCLK (UARTs/DASK External Clock) Period UCLK HIGH Time UCLK LOW Time 3.3 V RANGE MIN. 60 1/2 1/2 2 1 1 2 1 1 MAX. -- -- -- -- -- -- -- -- -- 5.0 V RANGE MIN. 40 1/2 1/2 2 1 1 2 1 1 MAX. -- -- -- -- -- -- -- -- -- UNIT ns tXCLK tXCLK tXCLK tXCLK tXCLK tXCLK tXCLK tXCLK
NOTE: *When UCLK is used as a DASK Demodulator Clock, use a 14.318 MHz Oscillator (50% Duty).
12
Thermal & Electrical Specification
CYCLE 1* CYCLE 2** CYCLE 3
Thermal & Electrical Specification
tXA tXAH
XCLK
***
VALID VALID VALID
SRAM/DRAM Interface
A25 - A0
D15 - D0 tXCE tDS
VALID tDH
VALID tXCEH
CE tXOE tXOEH
OE
WE tXBW
tXBWH
Figure 5. SRAM Read Access AC Timing
tWTS1 tWTH1
BW
WAIT
NOTES: 1. WAIT = 0 790B will extend the memory access by adding an extra wait cycle. WAIT = 1 790B will not extend the memory access. Memory access will complete as shown. 2. * 790B inserts an address setup cycle at the beginning of every non-sequential access (CYCLE1). ** Sequential accesses do not have an address setup cycle. Memory access starts with CYCLE2. *** Sequential accesses only.
LH77790B
13
ARM2-102
14
CYCLE 1* CYCLE 2** CYCLE 3
tXA tXAH
LH77790B
XCLK
***
VALID
tXD
A25 - A0
VALID
VALID
tACEH tDCEH
D15 - D0 VALID
tXCE
VALID
tXDH tXCEH
CE
tXWE tXWEH tDWEH
WE
tAWEH tXBW
OE
Figure 6. SRAM Write Access AC Timing
tWTS1 tWTH1
tXBWH
BW
WAIT
NOTES: 1. WAIT = 0 790B will extend the memory access by adding an extra wait cycle. WAIT = 1 790B will not extend the memory access. Memory access will complete as shown. 2. * 790B inserts an address setup cycle at the beginning of every non-sequential access (CYCLE1). ** Sequential accesses do not have an address setup cycle. Memory access starts with CYCLE2. *** Sequential accesses only.
ARM2-103
Thermal & Electrical Specification
CYCLE 1*
CYCLE 2**
CYCLE 3
CYCLE 4
XCLK
tXA tXAH
Thermal & Electrical Specification
A25 - A0 DRAM ROW COLUMN
tDS tDH
D15 - D0
tXRAS
VALID
tXRASH
RAS
tASR tXCAS tXCASH
CAS
tASC tXOE tXOEH
OE
Figure 7. DRAM Read Access AC Timing
WE
tXBW
tXBWH
BW
WAIT NOTES: 1. WAIT = 0 790B will extend the memory access by adding an extra wait cycle. WAIT = 1 790B will not extend the memory access. Memory access will complete as shown. 2. * 790B inserts an address setup cycle at the beginning of every non-sequential access (CYCLE1). ** Sequential accesses do not have an address setup cycle. Memory access starts with CYCLE2.
tWTS1 tWTH1
LH77790B
ARM2-104
15
16
CYCLE 1* CYCLE 2** CYCLE 3 CYCLE 4
LH77790B
XCLK
tXA tXAH
A25 - A0 DRAM
tXD
ROW
COLUMN
tXDH
***
VALID VALID
D15 - D0
tXRAS
tXRASH
RAS
tASR tXCAS tDSC tXCASH
CAS
tXWE tASC tXWEH
WE
Figure 8. DRAM Write Access Timing
OE
tXBW
tXBWH
BW
WAIT
tWTS1 tWTH1
Thermal & Electrical Specification
NOTES: 1. WAIT = 0 790B will extend the memory access by adding an extra wait cycle. WAIT = 1 790B will not extend the memory access. Memory access will complete as shown. 2. * 790B inserts an address setup cycle at the beginning of every non-sequential access (CYCLE1). ** Sequential accesses do not have an address setup cycle. Memory access starts with CYCLE2. *** Only for Burst CAS cycles in page mode (not shown).
ARM2-105
LH77790B Table 10. SRAM/DRAM AC Specifications
PARAMETER tXA tXAH tXCE tXCEH tXWE (SRAM) tXWE (DRAM) tXWEH tWTS tWTH tXD tXDH tXOE tXOEH tDS tDH tXBW tXBWH tAWEH tDWEH tACEH tDCEH tXRAS tXRASH tXCAS tXCASH tASR tASC tDSC DESCRIPTION XCLK to Address Valid Address Hold relative to XCLK XCLK to CE Active CE Hold relative to XCLK XCLK to WE Active (SRAM) XCLK to WE Active (DRAM) WE Hold relative to XCLK WAIT Setup relative to XCLK WAIT Hold relative to XCLK XCLK to Write Data Valid Write Data Hold relative to XCLK XCLK to OE Active OE Hold relative to XCLK Read Data Setup relative to XCLK Read Data Hold relative to XCLK XCLK to BW Valid BW Hold relative to XCLK Address Hold relative to WE Inactive Data Hold relative to WE Inactive Address Hold relative to CE Inactive Data Hold relative to CE Inactive XCLK to RAS Valid RAS Hold relative to XCLK XCLK to CAS Valid CAS Hold relative to XCLK DRAM Row Address Setup relative to RAS DRAM Column Address Setup relative to CAS DRAM Write Data Setup relative to CAS 3.3 V RANGE MIN. -- 4 -- 4 -- -- 4 10 6 -- 4 -- 4 13 21 -- 4 0 0 0 0 -- 2 -- 4 10 10 10 MAX. 41 -- 41 -- 35 40 -- -- -- 44 -- 31 -- -- -- 35 -- -- -- -- -- 26 -- 32 -- -- -- -- 5.0 V RANGE MIN. -- 4 -- 4 -- -- 4 10 6 -- 4 -- 4 9 19 -- 4 0 0 0 0 -- 2 -- 4 4 5 5 MAX. 33 -- 27 -- 30 35 -- -- --32 -- 25 -- -- -- 28 -- -- -- -- -- 21 -- 26 -- -- -- -- UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 1, 3, 4 1 NOTE
NOTES: 1. Measures hold time on data bus until data changes. The change could either be a state change or HIGH Impedance change. 2. This parameter is the setup time when both data and CAS become valid in the same cycle (Burst CAS cycles in Page Mode). 3. Minimum Data Hold Time with respect to CE, OE, and address invalid is 0 ns (SRAM). 4. Minimum Data Hold Time with respect to CAS and OE invalid is 0 ns (DRAM).
Thermal & Electrical Specification
17
LH77790B
Programmable Peripheral Interface, PPI
The PPI has three different modes of operation shown in Figure 9 through Figure 13. Modes 1 and 2 assign alias names to port C when used as control signals depending on the mode of operation. Table 11 shows a cross reference between the alias names which are used in the AC timing diagrams for modes 1 and 2 and the 790B external I/O names.
ARM2-108
tXAH
INTERNAL PPI ADDRESS REFLECTED ON 790B EXTERNAL ADDRESS BUS
tXPO
VALID DATA OUT FROM 790
A25 - A0
PWE *
PPI Port (A, B, or C)
XCLK
Figure 9. Programmable Peripheral Interface (MODE 0, Output) AC Timing
18
Thermal & Electrical Specification
NOTE:
* = 790B Internal signals shown for reference (790B Internal Peripheral Write Enable)
tXA
Thermal & Electrical Specification
XCLK
tXA tXAH
A25 - A0
INTERNAL PPI ADDRESS REFLECTED ON 790B EXTERNAL ADDRESS BUS
POE
*
PORT INPUT SAMPLED
tP0IS
tP0IH
Figure 10. Programmable Peripheral Interface (MODE 0, Input) AC Timing
PPI PORT (A, B, or C)
VALID DATA IN FROM PERIPHERAL
NOTE:
LH77790B
* = 790B Internal signals shown for reference (790B Internal Peripheral Output Enable)
19
ARM2-109
20
tXA tXAH
INTERNAL PPI ADDRESS REFLECTED ON 790B EXTERNAL BUS
LH77790B
XCLK
A25 - A0
POE *
tSTB
790 READS CAPTURED DATA
STB **
tSTIB tXIBF
IBF **
tSTIN tXINT1
INTR **
tPIS tPIH
Figure 11. Programmable Peripheral Interface (Mode 1, Input) AC Timing
VALID DATA IN FROM PERIPHERAL
PPI PORT (A or B)
Thermal & Electrical Specification
NOTES: 1. * = Internal signal shown for reference (790B Internal Peripheral Output Enable) 2. ** = Asynchronous signals
ARM2-110
XCLK
tXAH
Thermal & Electrical Specification
INTERNAL PPI ADDRESS REFLECTED ON 790B EXTERNAL ADDRESS BUS
A25 - A0
PWE *
tXOBF
OBF **
tACOB tACK
ACK **
tXINT2
INTR **
tXPO tACIN
Figure 12. Programmable Peripheral Interface (Mode 1, Output) AC Timing
VALID DATA OUT FROM 790B
PPI PORT (A or B)
LH77790B
ARM2-111
NOTES: 1. * = 790B Internal signal shown for reference (790 Internal Peripheral Write Enable) 2. ** = Asynchronous signals
21
22
tXAH tXA
INTERNAL PPI ADDRESS REFLECTED ON 790B EXTERNAL ADDRESS BUS
LH77790B
XCLK
A25 - A0 INTERNAL PPI ADDRESS REFLECTED ON 790B EXTERNAL ADDRESS BUS
PWE *
tXOBF tACOB
OBF **
tACK
ACK **
tXNT2
tSTIN
INTR **
tSTIB tXIBF
IBF **
tSTB
STB **
POE *
tPIS tPIH tACD tACDH
Figure 13. Programmable Peripheral Interface (Mode 2, Bi-directional) AC Timing
VALID DATA IN FROM PERIPHERAL VALID DATA OUT FROM 790B
PPI PORT (A ONLY)
Thermal & Electrical Specification
NOTES: 1. * = 790B Internal signals shown for reference 2. ** = Asynchronous signals
ARM2-112
LH77790B Table 11. PPI Cross Reference
ALIAS STB IBF INTR OBF ACK MODE 1 (INPUT) PORT A PC4 PC5 PC3 -- -- PORT B PC2 PC1 PC0 -- -- MODE 1 (OUTPUT) Port A -- -- PC3 PC7 PC6 Port B -- -- PC0 PC1 PC2 MODE 2 (BI-DIRECTIONAL) Port A PC4 PC5 PC3 PC7 PC6
Table 12. PPI AC Specification
PARAMETER tXPO tP0IS tSTIB tPIS tP0IH tPIH tSTIN tXINT1 tXIBF tSTB tXINT2 (Bit A) tXOBF tACK tACIN tACOB tACD tACDH DESCRIPTION XCLK to Data Out Valid Port Input Setup relative to XCLK (MODE 0) STB to IBF Port Input Setup relative to STB (MODES 1 & 2) Port Input Hold relative to XCLK (MODE 0) Port Input Hold relative to STB (MODES 1 & 2) STB to INTR XCLK to INTR (MODE 1 Input) XCLK to IBF STB Pulse Width XCLK to INTR (MODE 1 Output & MODE 2) XCLK to OBF ACK Pulse Width ACK to INTR ACK to OBF ACK to Data Out Valid Data Out Hold relative to ACK 3.3 V RANGE MIN. -- 40 -- 12 10 10 -- -- -- 17 -- -- -- 15 -- -- -- 6 MAX. 54 -- 34 -- -- -- 32 78 52 -- 86 57 57 -- 34 44 39 -- 5.0 V RANGE MIN. -- 41 -- 12 7 7 -- -- -- 14 -- -- -- 12 -- -- -- 6 MAX. 41 -- 27 -- -- -- 25 57 40 -- 56 44 44 -- 27 28 27 -- UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tXINT2 (Port B) XCLK to INTR (MODE 1 Output & MODE 2)
Thermal & Electrical Specification
23
LH77790B
External Reset
1 2 3 4 5 6 7 8 9 10 11
XCLK
tRSTIW
RESETI*
tRSTOV tRSTOH
RESETO
NOTE: * = RESETI is an asynchronous input, it is sampled on the rising edge of XCLK clock.
ARM2-120
Figure 14. LH77790B External Reset AC Timing Table 13. External Reset AC Specifications
PARAMETER tRSTIW tRSTOV tRSTOH DESCRIPTION RESETI Pulse Width (Once Sampled Low) RESETO Valid (Once RESETI Sampled Low) RESETO Hold (Once RESETI Sampled High) (3.3 V RANGE) MIN. 8.5 -- -- TYP. -- 3.5 1 MAX. -- -- -- (5.0 V RANGE) MIN. 8.5 -- -- TYP. -- 3.5 1 MAX. -- -- -- UNIT XCLK XCLK XCLK
24
Thermal & Electrical Specification
LH77790B
LCD Controller
The LCD controller signals (VD[7:0], CP1, CP2, S, MCLK, LCDCNTL) are fully programmable to drive most common passive LCD panels. The `Basic Timing' section of Chapter 10 in the LH77790B User Guide, best describes the relationship between the output signals and the control registers in the LCD controller. The following tables and equations are repeated here for convenience. Table 14. LCD Controller Parameter Description
PARAMETER DUTY BC CP1W CLKDIV tLCD_in_CLK tLCDCLK tS tCP1 tCP2 tPXFR tCP1W t12 t12F t21 tDS tDH tSS tSH t1M DESCRIPTION Number of CP1 Pulses per Frame (LCD_DUTY) Number of Memory Bytes in a Horizontal Line (LCD_BC) Line Pulse High Width (LCD_CP1W) Clock Frequency Divider (LCD_CLKDIV) LCD Input Clock from Power Management Unit LCD Reference Clock (Output of Clock Divider) Frame Pulse Period Line Pulse Period Shift Clock Period Pixels Transfer Time per Line Line Pulse High Width Time Current Frame CP1 to Current Frame CP2 Current Frame CP1 to next frame CP2 CP2 to CP1 Data Setup time Data Hold time S signal Setup time S signal Hold time CP1 to MCLK Inverting NOTE 1 1 1 1
NOTE: Decimal `equivalent' values, as defined in the corresponding parameters tables, must be used in timing equations.
The following equations (see above note) and parameters describe the relationship between LCD input Clock, S, CP1, CP2, and MCLK.
tLCDCLK = CLKDIV x tLCD_in_CLK (tLCD_in_CLK = XCLK period) tS = tCP1 x DUTY tCP1 = tPXFR + tCP1W + t12 tPXFR, tCP1W, and tCP2 vary from one display mode to another. Their typical values are shown in Table 15.
Thermal & Electrical Specification
25
LH77790B Table 15. Typical AC Timing for LCD Controller (3.3 V and 5.5 V Ranges)
DISPLAY MODE 1a (4-bit) 1b (8-bit) 2 3a (4-bit) 3b (8-bit) 4 5 6 tPXFR 2 x BC x tCP2 BC x tCP2 BC x tCP2 2 x BC x tCP2 BC x tCP2 BC x tCP2 2 x BC x tCP2 BC x tCP2 tCP1W (CP1W+1/2) x tCP2 (CP1W+1/2) x tCP2 (CP1W+1/2) x tCP2 (CP1W-1/2) x tCP2 (CP1W) x tCP2 (CP1W+1/2) x tCP2 (CP1W-1/2) x tCP2 (CP1W+1/2) x tCP2 tCP2 2 x tlcdclk 4 x tlcdclk 4 x tlcdclk 4 x tlcdclk 8 x tlcdclk 8 x tlcdclk 4 x tlcdclk 8 x tlcdclk
Other timing parameters are shown in Table 16. Table 16. Other Typical LCD Timing Parameters (3.3 V and 5.5 V Ranges)
VARIABLE tDS tDH t12 t12F t21 tSH tSS t1M VALUE 1/2 x tCP1 1/2 x tCP1 1/2 x tCP1 Variable 1/2 x tCP1 3.5 x tCP1 tPXFR + tCP1W - tSH 0 2 1 NOTES
NOTES: 1. Since this delay happens once a frame, its effect on the frame rate is small, t12 will be used in the timing equations. 2. MCLK clock changes on a falling edge of CP1 clock as programmed by LCD_MCLKW register. 3. Actual timing may vary from those calculated depending on current instruction executed, memory speed, DRAM Refresh Rate, etc.
26
Thermal & Electrical Specification
LAST ROW
ROW 1 INVALID DATA DATA DATA DATA INVALID DATA DATA DATA
VD[7:0] tDS tDH tPXFR
DATA
Thermal & Electrical Specification
CP2 tCP1W t12F tCP2 t21 t12 CP1 tSS tSH S MCLK VD[7:0]
ROW 1 ROW 2
INVALID DATA INVALID DATA INVALID DATA
LAST ROW
INVALID DATA
ROW 1
INVALID DATA
Figure 15. LCD Controller AC Timing
tCP1 CP1 S
NEW FRAME
NEW FRAME
tS t1M
MCLK
LH77790B
ARM2-86
27
LH77790B
Package Specifications
NC NC VSS VCC TEST3 TEST2 ADBE BB TEST1 TEST0 TDO TDI VSS VCC XCLKDIS TMS TCK PC7 PC6 PC5 PC4 PC3 VSS VCC PC2/DTR0 PC1/RTS0 PC0/RTS1 PB7/DSR0 PB6/DCD0 PB5/RI0 PB4/CTS0 PB3/CTS1 VSS VCC PB2/RI1 PB1 PB0 PA7
176-PIN TQFP
TOP VIEW
PA6 PA5 PA4 PA3 NC NC
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
NC NC XCLK VSS A0 A1 A2 A3 VCC VSS A4 A5 A6 A7 A8 A9 A10 A11 VCC VSS A12 A13 A14 A15 A16 A17 A18 A19 VCC VSS A20 A21 A22 A23 A24 A25 D0 D1 VCC VSS D2 D3 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
LH77790B Embedded Microcontroller
NC NC VSS VCC PA2 PA1 PA0 CTCLK CTOUT2 CTGATE2 CTOUT1 CTGATE1 VSS RESETO CTOUT0 CTGATE0 UCLK TxD2 RxD2 TxD1 RxD1 TxD0 VSS VCC RxD0 INT5 INT4 INT3 INT2 INT1 INT0 RESETI VSS VCC PWM2 PWM1 PWM0 LCDCNTL S MCLK CP1 CP2 NC NC
NC NC D4 D5 D6 D7 D8 D9 VCC VSS D10 D11 D12 D13 D14 D15 RAS0 RAS1 VCC VSS CE0/CAS0 CE1/CAS1 CE2/CAS2 CE3/CAS3 CE4/CAS4 CE5/CAS5 WE OE BW WAIT VCC VSS VD0 VD1 VD2 VD3 VD4 VD5 VD6 VD7 VCC VSS NC NC
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
77790-3
Figure 16. LH77790B 176-Pin TQFP (Thin Quad Flat Pack) Pin Assignment
28
Thermal & Electrical Specification
LH77790B
176TQFP (TQFP-176-P-2424)
26.30 25.70 24.20 23.80 0.10 1.00 REF. 1.00 REF.
24.20 23.80 26.30 25.70
25.2 24.8
0.175 0.075 1.70 MAX.
DETAIL
0.50 TYP.
0.28 0.12
0.65 0.35
0.20 0.00 DIMENSIONS IN MM
176TQFP
Figure 17. LH77790B Package Specification
Thermal & Electrical Specification
29
(R)
NORTH AMERICA
EUROPE
ASIA
SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (360) 834-2500 Facsimile: (360) 834-8903 http://www.sharpsma.com
SHARP Electronics (Europe) GmbH Microelectronics Division Sonninstrae 3 20097 Hamburg, Germany Phone: (49) 40 2376-2286 Facsimile: (49) 40 2376-2232 http://www.sharpmed.com
SHARP Corporation Integrated Circuits Group 2613-1 Ichinomoto-Cho Tenri-City, Nara, 632, Japan Phone: (07436) 5-1321 Facsimile: (07436) 5-1532 http://www.sharp.co.jp

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