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| CDCVF2505 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER SCAS640C - JULY 2000 - REVISED JUNE 2002 D D D D D D D D D D D D Phase-Lock Loop Clock Driver for Synchronous DRAM and General-Purpose Applications Spread Spectrum Clock Compatible Operating Frequency: 24 MHz to 200 MHz Low Jitter (Cycle-cycle): <|150 ps| Over the Range 66 MHz-200 MHz Distributes One Clock Input to One Bank of Five Outputs (CLKOUT Is Used to Tune the Input-Output Delay) Three-States Outputs When There Is no Input Clock Operates From Single 3.3-V Supply Available in 8-Pin TSSOP and 8-Pin SOIC Packages Consumes Less Than 100-A (Typically) in Power Down Mode Internal Feedback Loop Is Used to Synchronize the Outputs to the Input Clock 25- On-Chip Series Damping Resistors Integrated RC PLL Loop Filter Eliminates the Need for External Components D OR PW PACKAGE (TOP VIEW) CLKIN 1Y1 1Y0 GND 1 2 3 4 8 7 6 5 CLKOUT 1Y3 VDD 3.3 V 1Y2 description The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks (1Y[0-3] and CLKOUT) to the input clock signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input signal is applied to CLKIN. Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop filter for the PLLs is included on-chip, minimizing component count, space, and cost. Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference. The CDCVF2505 is characterized for operation from -40C to 85C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 CDCVF2505 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER SCAS640C - JULY 2000 - REVISED JUNE 2002 FUNCTION TABLE INPUT CLKIN L H <10 MHz L H Z OUTPUTS 1Y (0:3) CLKOUT L H Z Typically, below 2 MHz the device goes in power-down mode in which the PLL is turned off and the outputs enter into Hi-Z mode. If a >10 MHz signal is applied at CLKIN the PLL turns on, reacquires lock and stabilizes after approximately 100 s. The outputs will then be enabled. functional block diagram 8 CLKIN 1 PLL 25 CLKOUT 3 25 1Y0 Power Down 25 2 1Y1 5 25 1Y2 7 25 1Y3 Edge Detect Typical < 10 MHz 3-State 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 CDCVF2505 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER SCAS640C - JULY 2000 - REVISED JUNE 2002 Terminal Functions TERMINAL NAME 1Y[0-3] CLKIN NO. 2, 3, 5, 7 1 I/O O I DESCRIPTION Clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated 25- series damping resistor. Clock input. CLKIN provides the clock signal to be distributed by the CDCVF2505 clock driver. CLKIN is used to provide the reference signal to the integrated PLL that generates the clock output signals. CLKIN must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid signal is applied, a stabilization time (100 s) is required for the PLL to phase lock the feedback signal to CLKIN. Feedback output. CLKOUT completes the internal feedback loop of the PLL. This connection is made inside the chip and an external feedback loop should NOT be connected. CLKOUT can be loaded with a capacitor to achieve zero delay between CLKIN and the Y outputs. Ground 3.3-V Supply CLKOUT 8 O GND VDD3.3V 4 6 Power Power absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.3 V Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VDD + 0.5 V Input clamp current, IIK (VI < 0 or VI > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Output clamp current, IOK (VO < 0 or VO > VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous total output current, IO (VO = 0 to VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.5C/W PWR package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230.5C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.3 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions MIN Supply voltage, VDD High-level input voltage, VIH Low-level input voltage, VIL Input voltage, VI High-level output current, IOH Low-level output current, IOL Operating free-air temperature, TA -40 0 3 0.7 VDD 0.3 VDD VDD -12 12 85 NOM 3.3 MAX 3.6 UNIT V V V V mA mA C POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 CDCVF2505 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER SCAS640C - JULY 2000 - REVISED JUNE 2002 timing requirements over recommended ranges of supply voltage and operating free-air temperature MIN fclk Clock frequency Input clock duty cycle Stabilization time (see Note 4) 24 40% 50% NOM MAX 200 60% 100 s UNIT MHz NOTE 4: Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH Input voltage High-level output voltage TEST CONDITIONS II = -18 mA IOH = -100 A IOH = -12 mA IOH = -6 mA IOL = 100 A IOL = 12 mA IOL = 6 mA VO = 1 V VO = 1.65 V VO = 2 V VO = 1.65 V VI = 0 V or VDD VI = 0 V or VDD Yn CLKOUT VI = 0 V or VDD VDD 3V MIN to MAX 3V 3V MIN to MAX 3V 3V 3V 3.3 V 3V 3.3 V 3.3 V 33V 3.3 27 40 5 4.2 2.8 5.2 A pF pF F -27 -36 MIN VDD-0.2 2.1 2.4 0.2 0.8 0.55 V TYP MAX -1.2 UNIT V V VOL Low-level output voltage IOH IOL II Ci Co High level output current High-level Low-level Low level output current Input current Input capacitance Output ca acitance Out ut capacitance All typical values are at respective nominal VDD and 25C. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 25 pF, VDD = 3.3 V 0.3 V (see Note 5) PARAMETER tpd tsk(o) tc(jit_cc) (jit ) odc Propagation delay (normalized (see Figure 3) Output skew (see Note 6) Jitter (cycle to cycle) (see Figure 5) Output duty cycle (see Figure 4) TEST CONDITIOINS CLKIN to Yn, f= 66 MHz to 200 MHz Yn to Yn f = 66 MHz to 200 MHz f = 24 MHz to 50 MHz f = 24 MHz to 200 MHz at 50% VDD 45% 0.5 0.5 70 200 MIN -150 TYP MAX 150 150 150 400 55% 2.0 2.0 ns ns UNIT ps ps ps tr Rise time VO = 0.4 V to 2 V tf Fall time VO = 2 V to 0.4 V All typical values are at respective nominal VDD and 25C. NOTE 5: The tsk(o) specification is only valid for equal loading of all outputs. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 CDCVF2505 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER SCAS640C - JULY 2000 - REVISED JUNE 2002 ESD information ESD MODELS Human Body Model (HBM) Machine Model (MM) Charge Device Model (CDM) LIMIT 2.0 kV 300 V 1.0 kV thermal information CDCVF2505 8 PIN SOIC 8-PIN RJA RJA RJC RJC High K Low K High K Low K 39 42 THERMAL AIR FLOW (CFM) 0 97 165 150 87 126 250 83 113 500 77 97 UNIT C/W C/W C/W C/W CDCVF2505 8-PIN TSSOP 8 PIN RJA RJA RJC RJC High K Low K High K Low K 65 69 THERMAL AIR FLOW (CFM) 0 149 230 150 142 185 250 138 170 500 132 150 UNIT C/W C/W C/W C/W TYPICAL CHARACTERISTICS tpd, PROPAGATION DELAY TIME vs DELTA LOAD (TYPICAL VALUES @ 3.3 V, 25C) 1400 1050 t pd- Propagation Delay Time - ps 700 350 Load: CLKOUT = 12 pF || 500 , Yn = 25 pF || 500 t pd - Propagation Delay Time - ps 400 tpd, PROPAGATION DELAY TIME vs FREQUENCY (TYPICAL VALUES @ 3.3 V, 25C) 500 Load: CLKOUT = 12 pF || 500 , Yn = 25 pF || 500 300 0 -350 -700 -1050 -1400 -30 200 100 -20 -10 0 10 Delta Load - pF 20 30 0 25 50 75 100 125 150 f - Frequency - MHz 175 200 Figure 1 NOTE: Delta Load = CLKOUT Load - Yn Load Figure 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 CDCVF2505 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER SCAS640C - JULY 2000 - REVISED JUNE 2002 TYPICAL CHARACTERISTICS tpd, TYPICAL PROPAGATION DELAY TIME vs FREQUENCY(TUNED FOR MINIMUM DELAY) 150 Load: CLKOUT = 21 pF || 500 , Yn = 25 pF || 500 52.5 50 55 Load: CLKOUT = 12 pF || 500 , Yn = 25 pF || 500 DUTY CYCLE vs FREQUENCY t pd - Propagation Delay Time - ps 100 0 Duty Cycle - % 0 50 100 f - Frequency - MHz 150 200 50 -50 47.5 -100 -150 45 25 50 75 100 125 150 f - Frequency - MHz 175 200 Figure 3 CYCLE-CYCLE JITTER vs FREQUENCY 500 Typical Values @ 3.3 V, TA = 25C t c(jit_CC) - Cycle-Cycle Jitter - ps 400 I CC - Supply Current - mA 100 120 Figure 4 ICC, SUPPLY CURRENT vs FREQUENCY Worst Case @ VCC = 3.6 V, TA = 85C, Load: Y and CLKOUT = 25 pF || 500 80 300 60 200 40 100 20 0 25 50 75 100 125 150 f - Frequency - MHz 175 200 0 0 20 40 60 80 100 120 140 160 180 200 f - Frequency - MHz Figure 5 Figure 6 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 CDCVF2505 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER SCAS640C - JULY 2000 - REVISED JUNE 2002 PARAMETER MEASUREMENT INFORMATION From Output Under Test Yn = 25 pF || 500 CLKOUT = 12 pF || 500 500 Figure 7. Test Load Circuit 3V CLKIN tpd 2V 0.4 V tr 2V 0.4 V VOH VOL 50% VDD 0V 1Y0 - 1Y3 50% VDD tf Figure 8. Voltage Threshold for Measurements, Propagation Delay (tpd) Any Y 50 % VDD tsk(o) Any Y 50 % VDD Figure 9. Output Skew tc1 tc2 tc(jit_CC) = tc1 - tc2 Figure 10. Cycle-to-Cycle Jitter POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 CDCVF2505 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER SCAS640C - JULY 2000 - REVISED JUNE 2002 MECHANICAL DATA D (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.010 (0,25) M Gage Plane 0.010 (0,25) 1 A 7 0- 8 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10) PINS ** DIM A MAX 8 0.197 (5,00) 0.189 (4,80) 14 0.344 (8,75) 0.337 (8,55) 16 0.394 (10,00) 0.386 (9,80) 4040047 / D 10/96 A MIN NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 CDCVF2505 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER SCAS640C - JULY 2000 - REVISED JUNE 2002 MECHANICAL DATA PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,65 14 8 0,30 0,19 0,10 M 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0- 8 0,75 0,50 Seating Plane 1,20 MAX 0,15 0,05 0,10 PINS ** DIM A MAX 8 14 16 20 24 28 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2002, Texas Instruments Incorporated |
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