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APA2030/2031
Stereo 2.6W Audio Amplifier(With Gain Control)
Features
* Low operating current with 6mA * Improved depop circuitry to eliminate turn-on transients in outputs * High PSRR * Internal gain control, eliminate external components. * 2.6W per channel output power into 3 load at 5V, BTL mode * Multiple input modes allowable selected by HP /LINE pin (APA2030) * Two output modes allowable with BTL and SE modes selected by SE/BTL pin (for APA2030 only) * Low current consumption in shutdown mode (50 A) * Short Circuit Protection * TSSOP-24-P (APA2030) and TSSOP-20-P (APA2031) with thermal pad package.
General Description
APA2030/1 is a monolithic integrated circuit, which provides internal gain control, and a stereo bridged audio power amplifiers capable of producing 2.6W (1.9W) into 3 with less than 10% (1.0%) THD+N. By control the two gain setting pins, Gain0 and Gain1, The amplifier can provide 6dB, 10dB, 15.6dB, and 21.6dB gain settings. The advantage of internal gain setting can be less components and PCB area. Both of the depop circuitry and the thermal shutdown protection circuitry are integrated in APA2030/1, that reduces pops and clicks noise during power up or shutdown mode operation. It also improved the power off pop noise and protects the chip from being destroyed by over temperature and short current failure. To simplify the audio system design APA2030 combines a stereo bridge-tied loads (BTL) mode for speaker drive and a stereo single-end (SE) mode for headphone drive into a single chip, where both modes are easily switched by the SE/BTL input control pin signal. Besides the multiple input selections is used for portable audio system. APA2031 eliminates both input selection and single-end (SE) mode function to simplifying the design and save the PCB space.
Applications
* * NoteBook PC LCD Monitor
Ordering and Marking Information
APA2030/1
Lead Free C ode H andling C ode Tem p. R ange P ackage C ode A P A 2030/1 R : A P A 2030/1 XXXXX P ackage C ode R : TS S O P-P * Tem p. R ange I : - 40 to 85 C H andling C ode TU : Tube TR : Tape & R eel TY : Tray Lead Free C ode L : Lead Free D evice B lank : O riginal D evice XXXXX - D ate C ode
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.2 -Apr., 2004 1 www.anpec.com.tw
APA2030/2031
Pin Assignment
GND 1 GA IN0 2 GA IN1 3 LOUT+ 4 LLINEIN 5 LHPIN 6 PV D D 7 RIN+ 8 LOUT- 9 LIN+ 10 BY PA SS 11 GND 12
A P A 2030_P inOut
24 GND 23 RLINEIN 22 SHUTDOWN 21 ROUT+ T OP V ie w (A PA 2030) 20 RHPIN 19 V D D 18 PV D D 17 HP/LINE 16 ROUT15 SE/BTL 14 PCBEEP 13 GND
GND 1 GA IN0 2 GA IN1 3 LOUT+ 4 LIN- 5 PV D D 6 RIN+ 7 LOUT- 8 LIN+ 9 BY PA SS 10
T OP V ie w (A PA 2031)
20 GND 19 SHUTDOWN 18 ROUT+ 17 RIN16 V D D 15 PV D D 14 ROUT13 GND 12 NC 11 GND
Block Diagram
LLINEIN LHPIN
MUX
LOUT+
LIN+ BY PA SS
Vb ias
LOUTGA IN0 GIA N1 RLINEIN RHPIN
MUX G ain select ab le
ROUT+
RIN+ HP/LINE
H P/L IN E Vb ias
SE/BTL
SE /B T L
SHUTDOW N
Sh u t d o w n ckt
ROUT-
PCBEEP
PC - B EEP ckt
A P A 2030_B lock
APA2030
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Block Diagram
LIN-
LOUT+
LIN+ BY PA SS
Vb ias
SHUTDOWN GA IN0 GA IN1 RIN-
Sh u td o w n ckt
LOUT-
G ain select ab le
ROUT+
RIN+
Vb ias
ROUTAPA2031_Block
APA2031
Absolute Maximum Ratings
(Over operating free-air temperature range unless otherwise noted.) Parameter Supply voltage range, VDD, PVDD Input voltage range at SE/BTL, HP/LINE, SHUTDOWN, Operating ambient temperature range, TA Maximum junction temperature, TJ Storage temperature range, TSTG Soldering Temperature, 10 seconds, TS
Electrostatic Discharge, VESD Power dissipation, PD Note: Rating -0.3V to 6V -0.3V to VDD -40C to 85C Internal Limited -65C to 150C 260C -3000 to 3000*1 -200 to 200*2 Internal Limited
*1. Human body model: C=100pF, R=1500, 3 positives pulse plus 3 negative pulses *2. Machine model: C=200pF, L=0.5mH, 3 positive pulses plus 3 negative pulses
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APA2030/2031
Recommended Operating Conditions
Supply Voltage, VDD...................................................................................................4.5V to 5.5V
Thermal Characteristics
Symbol RTHJA Parameter Thermal Resistance from Junction to Ambient in Free Air TSSOP-P24* TSSOP-P20* Value 45 48 Unit C/W
* 5 in2 printed circuit board with 2oz trace and copper pad through 9 25mil diameter vias. The thermal pad on the TSSOP_P package with solder on the printed circuit board.
Electrical Characteristics
(VDD=5V,-20CSymbol VDD IDD ISD VIH VIL II VICM VOS
Parameter Supply Voltage Supply current Supply current in shutdown mode High level threshold Voltage Low level threshold Voltage Input current Common mode Input voltage Output differential voltage PC_beep trigger level
Test Condition SE/BTL = 0V SE/BTL = 5V SHUTDOWN = 0V SHUTDOWN, GAIN0, GAIN1 SE/BTL, HP/LINE SHUTDOWN, GAIN0, GAIN1 SE/BTL, HP/LINE SHUTDOWN, SE/BTL, HP/LINE, GAIN0, GAIN1
Min. 3.3
Typ. 6 4 50
Max. 5.5 12 8 300
Unit V mA mA A V V
2 4 0.8 3 5 VDD-1.0 5 1
V V nA V mV Vp.p
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Electical Characteristics (Cont.)
Operating Characteristics, BTL mode Vdd=5V, TA=25C, Rl=4, Gain=6dB, (Unless otherwise noted)
Symbol
Parameter
Test Condition THD=10%, Fin=1khz, RL=3 THD=10%, Fin=1khz, RL=4 THD=10%, Fin=1khz, RL=8 THD=1%, Fin=1khz, RL=3 THD=1%, Fin=1khz, RL=4 THD=1%, Fin=1khz, RL=8
Min.
Typ. 2.6 2.3 1.5 1.9 1.7
Max.
Unit W W W W W W % % dB dB dB dB
PO
Maximum output power
1
1.1 0.05 0.04 85 95 80 105
THD+N PSRR xtalk S/N
Total harmonic distortion plus noise Power ripple rejection ratio Channel separation HP/LINE input separation Signal to noise ratio
Po=1.1W, RL=4 Fin=1khz Po=0.7W, RL=8, Fin=1khz Vin=0.2Vrms, Rl=8, Cb=0.47f, f=120Hz f=1khz, Cb=0.47f, f=1khz, Cb=0.47f, Po=1.1W, Rl=8 , A_weight
Operating Characteristics, SE mode ( for APA2030 only) Vdd=5V, TA=25C, Rl=32, Gain=4, 1dB, (Unless otherwise noted)
Symbol PO THD+N PSRR
Parameter Maximum output power
Test Condition THD=10%, Fin=1khz, RL=32 THD=1%, Fin=1khz, RL=32
Min.
Typ. 110 90 0.03 55 80 65 80 100
Max. Unit mW mW % dB dB dB dB dB
Total harmonic distortion plus Po=75mW, RL=32 .Fin=1khz noise Vin=0.2Vrms, Rl=32, Power ripple rejection ratio Cb=0.47f, f=120, SE/BTL attenuation Channel separation HP/LINE input separation Signal to noise ratio f=1khz, Cb=0.47f, f=1khz, Cb=0.47f, BTL Po=75mW, Rl=32, A_weight,
xtalk S/N
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Pin Descriptions
APA2030
Pin Config. Function Description no. 1, 12, G ND G round connection, Connected to therm al pad. 13, 24 G AIN0 2 I/P Input signal for internal gain setting G AIN1 3 I/P Input signal for internal gain setting LOUT+ 4 O /P Left channel positive output in BTL m ode and SE m ode LLINEIN 5 I/P Left channel line input term inal, selected when HP/LINE is held low. RLINEIN 23 I/P Right channel line input term inal, selected when HP/LINE is held low. LHPIN 6 O /P Left channel headphone input term inal, selected when HP/LINE is held high. 7, PVDD Supply voltage only for power am plifier 18 RIN+ 8 I/P Right channel positive signal input, when differential signal is accepted. LOUT9 O /P Left channel negative output in BTL m ode and high im pedance in SE m ode LIN+ 10 I/P Left channel positive signal input, when differential signal is accepted. BYPASS 11 Bypass voltage PCBEEP 14 I/P PC-beep signal input O utput m ode control input pin, high for SE output m ode and low for BTL 15 I/P SE/BTL m ode Right channel negative output in BTL m ode and high im pedance in SE ROUT16 O /P m ode Multi-input selection input, headphone m ode when held high, line-in m ode HP/LINE 17 I/P when held low VDD 19 Supply voltage for internal circuit excepting power am plifier. Right channel headphone input term inal, selected when HP/LINE is held RHPIN 20 I/P high. ROUT+ 21 O /P Right channel positive output in BTL m ode and SE m ode 22 I/P SHUTDOW N It will be into shutdown m ode when pull low 23 I/P RLINEIN Right channel line input term inal, selected when HP/LINE is held low Pin name
APA2031
Pin name GND GAIN0 GAIN1 LOUT+ LINPVDD RIN+ LOUTLIN+ BYPASS NC ROUTVDD Pin Config. Function Description no. 1, 11, Ground connection, Connected to thermal pad. 13, 20 2 I/P Input signal for internal gain setting 3 I/P Input signal for internal gain setting 4 O/P Left channel positive output 5 I/P Left channel negative audio signal input 6,15 Supply voltage only for power amplifier 7 I/P Right channel positive audio signal input 8 O/P Left channel negative output 9 I/P Left channel positive audio signal input 10 Bypass voltage 12 No connection 14 O/P Right channel negative output 16 Supply voltage for internal circuit excepting power amplifier
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Pin Description
APA2031
Pin name RIN+ ROUT+ Pin Config. Function Description no. 17 I/P Right channel negative audio signal input 18 O/P Right channel positive output I/P It will be into shutdown mode when pull low
SHUTDOWN 19
Control Input Table ( for APA2030 only)
HP/ LINE X L H L H X SE/BTL X L L H H X SHUTDOWN L H H H H X PCBEEP Disable Disable Disable Disable Disable Enable Operating mode Shutdown mode Line input, BTL out HP input, BTL out Line input, SE out HP input, SE out PCBEEP input, BTL out
Gain Setting Table (for both APA2030 and APA2031)
GAIN0 0 0 1 1 GAIN1 0 1 0 1 Ri 90K 69K 42K 25.7K Rf 90K 111K 138K Av 6dB 10dB 15.6dB
154.3K 21.6dB
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Typical Application Circuit
(for APA2030 using SE input signal)
VDD 0 100F PVDD
(f
0.1F VDD 0.47F L-LINE L-HP 0.47F 0.47F 0.47F LLINEIN LHPIN LIN+ BYPASS GND
MUX
LOUT+ 220F 1k
Vbias
4
Control Pin Ring SE/BTL Signal Sleeve Tip Headphone Jack
GAIN0 GAIN1 0.47F R-LINE R-HP 0.47F 0.47F
Gain selectable
LOUT-
RLINEIN RHPIN RIN+ HP/LINE
MUX
ROUT+ 220F 1k
HP/LINE Control Signal 100k SE/BTL Signal Shutdown Signal BEEP Signal
VDD 100k SE/BTL
HP/LINE
Vbias
SE/BTL
4 ROUT-
SHUTDOWN PCBEEP 0.47F
Shutdown ckt PC-BEEP ckt
APA2030AppCkt
APA 2030
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Typical Application Circuit
(for APA2031 using SE input signal)
V DD 0
0 .1 F
100 F P V DD
V DD L -INP UT 0 .4 7 F
G ND
L IN-
L O UT +
0 .4 7 F
L IN+ BYPASS
Vbias 4
0 .4 7 F
G A IN0 G A IN1 Gain se l e cta b l e
L O UT -
R-INP UT
0 .4 7 F
RIN-
RO UT +
0 .4 7 F
RIN+
Vbias 4 S h u td o wn S ig na l
S HUT DO WN
S h u td o wn ckt
RO UT -
APA 2031
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Typical Characteristics
THD+N vs. Output Power
10
THD+N vs. Output Power
10
VDD=5V AV=6dB f=1kHz BTL
VDD=5V AV=4.1dB f=1kHz COUT=330F SE
THD+N (%)
THD+N (%)
1
RL=8
RL=4
RL=3
1
RL=32
RL=16
0.1
0.1
0.01 0 0.5 1 1.5 2 2.5 3
0.01
0
50
100
150
200
250
Output Power (W)
Output Power (mW)
THD+N vs. Output Power
10
10
THD+N vs. Output Power
VDD=5V AV=6dB RL=3 BTL
f=15kHz f=15kHz
1
THD+N (%)
1
THD+N (%)
f=1kHz
0.1
f=1kHz
0.1
f=30Hz
0.01 10m
0.01
VDD=5V AV=15.6dB RL=3 BTL
100m
f=30Hz
100m
1
5
10m
1
2
5
Output Power (W)
Output Power (W)
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Typical Characteristics (Cont.)
THD+N vs. Output Power
10
THD+N vs. Output Power
10
VDD=5V AV=6dB RL=4 BTL
1
f=15kHz f=15kHz
1
THD+N (%)
THD+N (%)
f=1kHz
0.1
f=1kHz
0.1
f=30Hz
0.0 1 10m
VDD=5V AV=15.6dB RL=4 BTL
1 2 5
0.01 10m 100m
f=30Hz
100m
1
2
5
Output Power (W)
Output Power (W)
THD+N vs. Output Power
10
THD+N vs. Frequency
10
VDD=5V AV=6dB RL=8 BTL f=15kHz
VDD=5V AV=15.6dB RL=8 BTL f=15kHz
1
THD+N (%)
1
THD+N (%)
f=30Hz
0.1
0.1
f=1kHz
f=1kHz f=30Hz
0.01 10m 0.01 10m
100m
1
2
5
100m
1
2
5
Output Power (W)
Output Power (W)
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Typical Characteristics (Cont.)
THD+N vs. Output Power
10 10
THD+N vs. Output Power
VDD=5V AV=4.1dB RL=32 COUT=1000F SE
1
VDD=5V AV=4dB RL=16 COUT=1000F SE
1
f=30Hz f=15kHz
THD+N (%)
THD+N (%)
f=15kHz
0.1
0.1
f=30Hz f=1kHz
0.01 10m 0.01 10m
f=1kHz
200m 300m 50m 100m 200m 300m
50m
100m
Output Power (W)
Output Power (W)
THD+N vs. Frequency
10 10
THD+N vs. Frequency
VDD=5V PO=1.75W RL=3 BTL
1
VDD=5V AV=6dB RL=3 BTL
THD+N (%)
THD+N (%)
1
AV=15.6dB
PO=1.75W
0.1
0.1
AV=6dB
PO=1W
0.01 20
100
1k
10k 20k
0.01 20
100
1k
10k
20k
Frequency (Hz)
Frequency (Hz)
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Typical Characteristics (Cont.)
THD+N vs. Frequency
10 10
THD+N vs. Frequency
VDD=5V PO=1.5W RL=4 BTL
1
VDD=5V AV=6dB RL=4 BTL
1
THD+N (%)
THD+N (%)
AV=15.6dB
PO=1.5W
0.1
0.1
AV=6dB
PO=0.75W
0.01 20 100 1k 10k 20k
0.01 20 100 1k 10k 20k
Frequency (Hz)
Frequency (Hz)
THD+N vs. Frequency
10
THD+N vs. Frequency
10
VDD=5V AV=6dB RL=8 BTL
VDD=5V PO=1W RL=8 BTL
1
THD+N (%)
PO=1W
0.1
THD+N (%)
1
AV=6dB
0.1
PO=0.5W
AV=15.6dB
0.01
20
100
1k
10k
20k
0.01 20 100 1k 10k 20k
Frequency (Hz)
Frequency (Hz)
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Typical Characteristics (Cont.)
THD+N vs. Frequency
10
THD+N vs. Frequency
10
VDD=5V AV=4.1dB RL=16 COUT=1000F SE
VDD=5V AV=4.1dB RL=32 COUT=1000F SE
THD+N (%)
1
0.1
THD+N (%)
PO=75mW
1
0.1
PO=25mW
PO=150mW
0.01 20 100 1k 10k 20k 0.01 20 100
PO=75mW
1k 10k 20k
Frequency (Hz)
Frequency (Hz)
Frequency Response
+6 +240
Frequency Response
+20 +18 +16 +270 +260 +250
+230 +220
+4 +2
Gain
Phase (Degress)
+200
+14
+220 +210 +200 +190 +180
Gain (dB)
-0 +190 -2 +180
Gain (dB)
+12 +10 +8 +6 +4 +2 -0
Phase
-4
+170 +160
-6
-8
VDD=5V RL=4 AV=6dB PO=1W BTL
10 100 1k 10k
Phase VDD=5V RL=4 AV=15.6dB PO=1W BTL
10 100 1k 10k
+170 +160 +150 +140 +130 +120 100k 200k
+150 +140 +130 +120 100k 200k
-10
Frequency (Hz)
Frequency (Hz)
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Phase (Degress)
+210
Gain
+240 +230
APA2030/2031
Typical Characteristics (Cont.)
Frequency Response
+10 +9 +8 +7 +270 +5 +4 +3 +2
Frequency Response
+300 +280 +260 +250 +240 +230 +220 +210 +200 +190 +180
Gain
Gain
+260
Phase (Degress)
Gain (dB)
+6 +5 +4 +3 +2 +1 -0 10 100 1k 10k
Gain (dB)
+1 +0 -1 -2 -3
+220 +200 +180
Phase VDD=5V RL=8 AV=10dB PO=0.5W BTL
+170 +160 +150 +140 +130 +120 100k 200k
Phase VDD=5V RL=32 AV=4.1dB VIN=1V SE
100 1k 10k
+160 +140 +120 +100 100k 200k
-4 -5 10
Frequency (Hz)
Frequency (Hz)
Crosstalk vs. Frequency
+0
Crosstalk vs. Frequency
+0 -10 -20 -30
-20
-40
VDD=5V RL=4 AV=6dB PO=1.5W SE
6
6
Crosstalk (dB)
VDD=5V RL=32 AV=4.1dB VIN=1V COUT=330F SE
Crosstalk (dB)
-60
-40 -50 -60 -70 -80
-80
Left to Right
Left to Right Right to Left
-100
-120
Right to Left
20 100 1k 10k 20k
-90 -100 20
-140
100
1k
10k
20k
Frequency (Hz)
Frequency (Hz)
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Phase (Degress)
+240
APA2030/2031
Typical Characteristics (Cont.)
PSRR vs. Frequency
+0
+0 -10 -20 -30
PSRR vs. Frequency
VDD=5V RL=32 CB=0.47F SE
VDD=5V -10 RL=4 CB=0.47F -20 BTL
-30
PSRR (dB)
-50 -60 -70 -80 -90 -100 20 100 1k 10k 20k
PSRR (dB)
-40
-40 -50 -60 -70 -80 -90 -100 20 100 1k 10k 20k
Frequency (Hz)
Frequency (Hz)
Output Noise Voltage vs. Frequency
100 50 100
Output Noise Voltage vs. Frequency
50
Filter BW < 22kHz
Output Noise Voltage (V)
Filter BW < 22kHz
20
Output Noise Voltage (V)
20
10
10
A-Weight
A-Weight
5
5
VDD=5V RL=4 2 AV=6dB BTL
1 20 100 1k 10k 20k
2
VDD=5V RL=32 AV=4.1dB SE
20 100 1k 10k 20k
1
Frequency (Hz)
Frequency (Hz)
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Typical Characteristics (Cont.)
Supply Current vs. Supply Voltage
7
2.0
Power Dissipation vs. Output Power
VDD=5V BTL RL=3
No Load
6
BTL
1.8 1.6
5
Power Dissipation (W)
Supply Current (mA)
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0
4 3
RL=4
SE
2 1
RL=8
0 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0.0
0.5
1.0
1.5
2.0
2.5
Supply Voltage (V)
Output Power (W)
Power Dissipation vs. Output Power
200 180
VDD=5V SE RL=8
Power Dissipation (mW)
160 140 120 100 80 60 40 20 0 0 50
RL=16
RL=32
100
150
200
250
300
Output Power (mW)
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Application Descriptions
BTL Operation The APA2030/1 has two pairs of operational amplifiers internally, allowed for different amplifier configurations.
IN PU TIN PU T+
Single-Ended Operation (for APA2030 only) Consider the single-supply SE configuration shown Application Circuit. A coupling capacitor is required to block the DC offset voltage from reaching the load. These capacitors can be quite large (approximately 33F to 1000F) so they tend to be expensive, occupy valuable PCB area, and have the additional drawback of limiting low-frequency performance of the system (refer to the Output Coupling Capacitor). The rules described should be following relationship:
DIF F _AM P _CONF IG
Figure 1: APA2030 internal configuration (each channel) The OP1 and OP2 are all differential drive configuration, The differential drive configuration doubling the voltage swing on the load compare to the single-ending configuration, the differential gain for each channel is 2X(Gain of SE mode). By driving the load differentially through outputs OUT+ and OUT-, an amplifier configuration commonly referred to as bridged mode is established. BTL mode operation is different from the classical single-ended SE amplifier configuration where one side of its load is connected to ground. A BTL amplifier design has a few distinct advantages over the SE configuration, as it provides differential drive to the load, thus doubling the output swing for a specified supply voltage. Four times the output power is possible as compared to a SE amplifier under the same conditions. A BTL configuration, such as the one used in APA2030/1, also creates a second advantage over SE amplifiers. Since the differential outputs, ROUT+, ROUT-, LOUT+, and LOUT-, are biased at half-supply, no need DC voltage exists across the load. This eliminates the need for an output coupling capacitor which is required in a single supply, SE configuration.
Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004
+ + -
OP1
OUT+
V bias
OUTOP2
1 Cbypass x125k
R1 i << R 1 iC LCC
(1)
Output SE/BTL Operation (for APA2030 only) The ability of the APA2030 to easily switch between BTL and SE modes is one of its most important costs saving features. This feature eliminates the requirement for an additional headphone amplifier in applications where internal stereo speakers are driven in BTL mode but external headphone or speakers must be accommodated. Internal to the APA2030, two separate amplifiers drive OUT+ and OUT- (see Figure 1). The SE/BTL input controls the operation of the follower amplifier that drives LOUT- and ROUT-. * * When SE/BTL is held low, the OP2 is actived and the APA2030 is in the BTL mode. When SE/BTL is held high, the OP2 is in a high output impedance state, which configures the APA2030 as SE driver from OUT+. IDD is reduced by approximately one-half in SE mode.
Control of the SE/BTL input can be a logic-level TTL source or a resistor divider network or the stereo headphone jack with switch pin as shown in Application Circuit.
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Application Descriptions
Vdd 1K Control Pin Ring
SE/BTL
100K
100K
SE/BTL_Switc h
the HP/LINE pin, enabling the headphone input function. Differential Input Operation
Tip
Sleeve
Headphone Jack
Figure 2: SE/BTL input selection by phonejack plug In Figure 2, input SE/BTL operates as follows: When the phonejack plug is inserted, the 1k resistor is disconnected and the SE/BTL input is pulled high and enables the SE mode. When the input goes high level, the OUT- amplifier is shutdown causing the speaker to mute. The OUT+ amplifier then drives through the output capacitor (CO) into the headphone jack. When there is no headphone plugged into the system, the contact pin of the headphone jack is connected from the signal pin, the voltage divider set up by resistors 100k and 1k. Resistor 1k then pulls low the SE/BTL pin, enabling the BTL function. Input HP/LINE Operation (for APA2030 only) APA2030 amplifier has two separate inputs for each of the left and right stereo channels. An internal multiplexer selects which input will be connected to the amplifier based on the state of the HP/LINE pin on the IC. * * To select the line inputs, set HP/LINE pin tied to low level To enable the headphone inputs, set HP/ LINE pin tied to high level
APA2030/1 can accepted the differential input signal, and it's can improve the CMRR (Common Mode Rejection ratio). For example: when apply differential input signals to APA2031, connect positive input signals to the IN+ (LIN+ and RIN+) of APA2031 and negative input signals to the IN- (LIN- and RIN-) of APA2031. When input signals are single-end, just connect IN+ (LIN+ and RIN+) to ground via a capacitor. Input Resistance, Ri The APA2030/1 provides four gain setting decided by GAIN0 and GAIN1 input ins in Differential mode and it become 4.1dB fixed gain when SE mode is selected (for APA2030). In table 1,internal resistors Ri and Rf according to BTL operation set the gain for each audio input of the APA2030/1.
GAIN0 0 0 1 1 X GAIN1 0 1 0 1 X Ri 90K 69K 42K Rf 90K 111K 138K SE/BTL 0 0 0 0 1 Av 6dB 10dB 15.6dB 21.6dB 4.1dB
25.7K 154.3K 69K 111K
Table 1: The close loop gain setting resistance Ri/Rf BTL mode operation brings about the factor 2 in the gain equation due to the inverting amplifier mirroring the voltage swing across the load. The input resistance has wide variation (+/-10%) caused by manufacture. Input Capacitor, Ci In the typical application an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the minimum input impedance Ri form a high-pass filter with the corner frequency determined in the follow equation:
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Refer to the application circuit, the voltage divider of 100k and 1k sets the voltage at the HP/LINE pin to be approximately 50mV when there are no headphones plugged into the system. This logic low voltage at the HP/LINE pin enables the APA2030 and places it LINE input mode operation. When a set of headphones is plugged into the system, the contact pin of the headphone jack is disconnected from the signal pin, interrupting the voltage divider set up by resistors 100k. Resistor 100k then pulls-up
Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004
APA2030/2031
Application Descriptions
fC (highpass)=
1 2Riminx Ci
(2)
To avoid start-up pop noise occurred, the bypass voltage should be rise slower then the input bias voltage and the relationship shown in equation should be maintained.
1 Cbypass x 125k
The value of Ci is important to consider as it directly affects the low frequency performance of the circuit. Consider the example where Ri is 90k when 6dB gain is setting and the specification calls for a flat bass response down to 40Hz . Equation is reconfigured as follow: Ci=
1 2Rifc
<<
1 Ci x 180k
(4)
(3)
The capacitor is fed from a 125k source inside the amplifier. Bypass capacitor, Cb, values of 3.3F to 10F ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance. The bypass capacitance also effect to the start up time. It is determined in the follow equation: Tstart up =5x(Cbypassx125k) (5)
Consider to input resistance variation, the Ci is 0.04F so one would likely choose a value in the range of 0.1F to 1.0F. A further consideration for this capacitor is the leakage path from the input source through the input network (Ri+Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications as the DC level there is held at VDD/2, which is likely higher that the source DC level. Please note that it is important to confirm the capacitor polarity in the application. Effective Bypass Capacitor, Cbypass As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. The capacitor location on both the bypass and power supply pins should be as close to the device as possible. The effect of a larger half supply bypass capacitor is improved PSRR due to increased halfsupply stability. Typical applications employ a 5V regulator with 1.0F and a 0.1F bypass capacitors which aid in supply filtering. This does not eliminate the need for bypassing the supply nodes of the APA2030/1. The selection of bypass capacitors, especially Cb, is thus dependent upon desired PSRR requirements, click and pop performance.
Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 20
Output Coupling Capacitor, Cc (for APA2030 only) In the typical single-supply SE configuration, an output coupling capacitor (Cc) is required to block the DC bias at the output of the amplifier thus preventing DC currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by equation.
1 2 RLCC
fc(highpass)=
(6)
For example, a 330F capacitor with an 8 speaker would attenuate low frequencies below 60.6Hz. The main disadvantage, from a performance standpoint, is the load impedance is typically small, which drives the low-frequency corner higher degrading the bass response. Large values of CC are required to pass low frequencies into the load. Power Supply Decoupling, Cs The APA2030/1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible.
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APA2030/2031
Application Descriptions
Power supply decoupling also prevents the oscillations causing by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by using two different type capacitors that target on different type of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance(ESR) ceramic capacitor, typically 0.1F placed as close as possible to the device VDD lead works best. For filtering lowerfrequency noise signals, a large aluminum electrolytic capacitor of 10F or greater placed near the audio power amplifier is recommended. Shutdown Function In order to reduce power consumption while not in use, the APA2030/1 contains a shutdown pin to externally turn off the amplifier bias circuitry. This shutdown feature turns the amplifier off when a logic low is placed on the SHUTDOWN pin. The trigger point between a logic high and logic low level is typically 2.0V. It is best to switch between ground and the supply VDD to provide maximum device performance. By switching the SHUTDOWN pin to low, the amplifier enters a low-current state, IDD<50A. APA2030 is in shutdown mode, except PC-BEEP detect circuit. On normal operating, SHUTDOWN pin pull to high level to keeping the IC out of the shutdown mode. The SHUTDOWN pin should be tied to a definite voltage to avoid unwanted state changes. PC-BEEP Detection ( for APA2030 only) APA2030 integrates a PCBEEP detect circuit for NOTEBOOK PC used. When PC-BEEP signal drive to PCBEEP input pin, and PCBEEP mode is active. APA2030 will force to BTL mode and the internal gain fixed as -10dB. The PCBEEP signal becomes the amplifier input signal and play on the speaker without coupling capacitor. If the amplifier in the shutdown mode, it will out of shutdown mode whenever PCBEEP mode enable. The APA2030 will return to previous setting when it is out of PC-BEEP mode. The input impedance is 100k on PCBEEP input pin.
Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 21
Optimizing Depop Circuitry Circuitry has been included in the APA2030/1 to minimize the amount of popping noise at power-up and when coming out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to eliminate clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the device or the shutdown function will cause the click and pop circuitry. The value of Ci will also affect turn-on pops. (Refer to Effective Bypass Capacitance) The bypass voltage rise up should be slower than input bias voltage. Although the bypass pin current source cannot be modified, the size of Cb can be changed to alter the device turn-on time and the amount of clicks and pops. By increasing the value of Cb, turn-on pop can be reduced. However, the tradeoff for using a larger bypass capacitor is to increase the turn-on time for this device. There is a linear relationship between the size of Cb and the turn-on time. In a SE(for APA2030) configuration, the output coupling capacitor, CC, is of particular concern. This capacitor discharges through the internal 10k resistors. Depending on the size of CC, the time constant can be relatively large. To reduce transients in SE mode, an external 1k resistor can be placed in parallel with the internal 10k resistor. The tradeoff for using this resistor is an increase in quiescent current. In the most cases, choosing a small value of Ci in the range of 0.33F to 1F, Cb being equal to 0.47F and an external 1k resistor should be placed in parallel with the internal 10k resistor should produce a virtually clickless and popless turn-on. A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain. So it is advantageous to use low-gain configurations. BTL Amplifier Efficiency An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power delivered to the load. The following equations are the basis for calculating amplifier efficiency.
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APA2030/2031
Application Descriptions
Efficiency = Where: PO =
VOrmsx VOrms RL VP PO PSUP VP x VP 2RL
(7)
=
VOrms =
2
2VP RL
(8)
A final point to remember about linear amplifiers (either SE or BTL) is how to manipulate the terms in the efficiency equation to utmost advantage whenpossible. Note that in equation, VDD is in the dominator. This indicates that as VDD goes down,efficiency goes up. In other words, use the efficiency analysis to choose the correct supply voltage and speaker impedance for the application. Power Dissipation Whether the power amplifier is operated in BTL or SE modes, power dissipation is a major concern. In equation11 states the maximum power dissipation point for a SE mode operating at a given supply voltage and driving a specified load.
Psup = VDD * IDDAVG =
Efficiency of a BTL configuration:
PO PSUP VP x VP 2RL 2VP RL VP 4VDD
=(
) / (VDD x
)=
(10)
SE mode : PD,MAX =
VDD 2 2RL
2
(11)
Table 2 calculates efficiencies for four different output power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a stereo 1W audio system with 8 loads and a 5V supply, the maximum draw on the power supply is almost 3W.
In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus the maximum power dissipation point for a BTL mode operating at the same given conditions is 4 times as in SE mode.
4V DD BTL mode : PD,MAX = 2 2 RL
2
(12)
Po (W) 0.25 0.50 1.00 1.25
Efficiency (%) 31.25 47.62 66.67 78.13
IDD(A) 0.16 0.21 0.30 0.32
VPP(V) 2.00 2.83 4.00 4.47
PD (W) 0.55 0.55 0.5 0.35
Since the APA2030/1 is a dual channel power amplifier, the maximum internal power dissipation is 2 times that both of equations depending on the mode of operation. Even with this substantial increase in power dissipation, the APA2030/1 does not require extra heatsink. The power dissipation from equation12, assuming a 5V-power supply and an 8 load, must not be greater than the power dissipation that results from the equation13: PD,MAX =
TJ.MAX - TA JA
(13)
**High peak voltages cause the THD to increase. Table 2. Efficiency Vs Output Power in 5V/8 BTL Systems
Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 22
For TSSOP-24 (APA2030) and TSSOP-20 (APA2031) package with and without thermal pad, the thermal resistance (JA ) is equal to 45 oC/W and 48oC/W, respectively. Since the maximum junction temperature (TJ,MAX) of APA2030/1 is 150oC and the ambient temperature (TA) is defined by the power system design, the maximum
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APA2030/2031
Application Descriptions
power dissipation which the IC package is able to handle can be obtained from equation13. Once the power dissipation is greater than the maximum limit (P D,MAX ), either the supply voltage (V DD ) must bedecreased, the load impedance (RL) must be increased or the ambient temperature should be reduced. Thermal Pad Considerations The thermal pad must be connected to ground. The package with thermal pad of the APA2030/1 requires special attention on thermal design. If the thermal design issues are not properly addressed, the APA2030/1 4 will go into thermal shutdown when driving a 4 load. The thermal pad on the bottom of the APA2030/1 should be soldered down to a copper pad on the circuit board. Heat can be conducted away from the thermal pad through the copper plane to ambient. If the copper plane is not on the top surface of the circuit board, 8 to 10 vias of 13 mil or smaller in diameter should be used to thermally couple the thermal pad to the bottom plane. For good thermal conduction, the vias must be plated through and solder filled. The copper plane used to conduct heat away from the thermal pad should be as large as practical. If the ambient temperature is higher than 25C, a larger copper plane or forced-air cooling will be required to keep the APA2030/1 junction temperature below the thermal shutdown temperature (150C). In higher ambient temperature, higher airflow rate and/ or larger copper area will be required to keep the IC out of thermal shutdown. Thermal Considerations Linear power amplifiers dissipate a significant amount of heat in the package under normal operating conditions. To calculate maximum ambient temperatures, first consideration is that the numbers from the Power Dissipation vs. Output Power graphs (page17) are per channel values, so the dissipation of the IC heat needs to be doubled for two-channel operation. Given JA, the maximum allowable junction temperature (TJ, ), and the total internal dissipation (PD), the maxiMAX mum ambient temperature can be calculated with the following equation. The maximum recommended junction temperature for the APA2030/1 is 150C. The internal dissipation figures are taken from the Power Dissipation vs. Output Power graphs. (Page17)
TA,Max = TJ,Max -APD 150 - 45(0.8*2) = 78C (TSSOP-P24) 150 - 48(0.8*2) = 73.2C (TSSOP-P20)
(14)
The APA2030/1 is designed with a thermal shutdown protection that turns the device off when the junction temperature surpasses 150C to prevent damaging the IC.
Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004
23
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APA2030/2031
Packaging Information
T S S O P / T S S O P -P ( R eference JE D E C R egistration M O -153)
e N
2x E/2
E1
E
1
2
3
e/2 D
A2 A
b D1
A1 S
(
2)
GAUGE PLANE
EXPOSED THERMAL PAD ONE E2 0.25 L (L1) ( 3) 1
BOTTOM VIEW (THERMALLY ENHANCED VARIATIONDS ONLY)
D im A A1 A2 D D1 e E E1 E2 L L1 R R1 S 1 2 3
M illim eters
Inches
M ax. 1.2 0.00 0.15 0.80 1.05 6.4 (N =20P IN ) 6.6 (N =20P IN ) 7.7 (N =24P IN ) 7.9 (N =24P IN ) 9.6 (N =28P IN ) 9.8 (N =28P IN ) 4.2 B S C (N =20P IN ) 4.7 B S C (N =24P IN ) 3.8 B S C (N =28P IN ) 0.65 B S C 6.40 B S C 4.30 4.50 3.0 B S C (N =20P IN ) 3.2 B S C (N =24P IN ) 2.8 B S C (N =28P IN ) 0.45 0.75 1.0 R E F 0.09 0.09 0.2 0 8 12 R E F 12 R E F
24
M in.
M ax. 0.047 0.000 0.006 0.031 0.041 0.252 (N =20P IN ) 0.260 (N =20P IN ) 0.303 (N =24P IN ) 0.311 (N =24P IN ) 0.378 (N =28P IN ) 0.386 (N =28P IN ) 0.165 B S C (N =20P IN ) 0.188 B S C (N =24P IN ) 0.150 B S C (N =28P IN ) 0.026 B S C 0.252 B S C 0.169 0.177 0.118 B S C (N =20P IN ) 0.127 B S C (N =24P IN ) 0.110 B S C (N =28P IN ) 0.018 0.030 0.039R E F 0.004 0.00 4 0.008 0 8 12 R E F 12 R E F
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M in.
Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004
APA2030/2031
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
(IR/Convection or VPR Reflow)
tp Ram p-up Critical one T L to T P
Reflow Condition
TP
Temperature
TL Tsm ax
tL
Tsm in Ram p-down ts Preheat
25
t 25 C to Peak
Classificatin Reflow Profiles
Profile Feature
Tim e
Sn-Pb Eutectic Assembly Large Body Small Body
Pb-Free Assembly Large Body Small Body 3C/second max. 150C 200C 60-180 seconds 3C/second max 217C 60-150 seconds 245 +0/-5C 250 +0/-5C 10-30 seconds 20-40 seconds
Average ramp-up rate 3C/second max. (TL to TP) Preheat Temperature Min (Tsmin) 100C Temperature Mix (Tsmax) 150C Time (min to max)(ts) 60-120 seconds Tsmax to TL - Ramp-up Rate Tsmax to TL Temperature(TL) 183C Time (tL) 60-150 seconds Peak Temperature(Tp) 225 +0/-5C 240 +0/-5C Time within 5C of actual Peak 10-30 seconds 10-30 seconds Temperature(tp) Ramp-down Rate 6C/second max. 6 minutes max. Time 25C to Peak Temperature
Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004 25
6C/second max. 8 minutes max.
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Note: All temperatures refer to topside of the package. Measured on the body surface.
APA2030/2031
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C, 5 SEC 1000 Hrs Bias 125C 168 Hrs, 100%RH, 121C -65C 150C, 200 Cycles VHBM 2KV, VMM 200V 10ms, 1tr 100mA
Carrier Tape & Reel Dimensions
t E Po P P1 D
W
F
Bo
Ao
D1
Ko
T2
J C A B
T1
Application
A 330 1
B 100 ref D 1.5 +0.1
C 13 0.5 D1 1.5 min
J 2 0.5 Po 4.0 0.1
T1 16.4 0.2 P1 2.0 0.1
T2 2 0.2 Ao 6.9 0.1
W 16 0.3 Bo 8.3 0.1
P 12 0.1 Ko 1.5 0.1
E 1.750.1 t 0.30.05
TSSOP- 24
F 7.5 0.1
(mm)
Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004
26
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APA2030/2031
Cover Tape Dimensions
Application TSSOP- 24 Carrier Width 16 Cover Tape Width 21.3 Devices Per Reel 2000
Customer Service
Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369
Copyright ANPEC Electronics Corp. Rev. A.2 - Apr., 2004
27
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