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19-0317; Rev 1; 3/95
MAX2101 Evaluation Kit
_______________General Description
The MAX2101 evaluation kit (EV kit) simplifies the evaluation of the MAX2101 quadrature digitizer. The board is assembled with a MAX2101, supporting circuitry such as a complete phase-locked loop, filter tuning circuitry, signal and data buffering, and supply conditioning for ease of characterization. This manual provides complete instructions for using the EV kit. Separate sections discuss board interfacing, recommended test equipment, and measurement techniques.
____________________________Features
o ADCs Provide Greater than 5.3 Effective Bits and fS = 60Msps Data Rate, fIN = 15MHz o Integrated Lowpass Filters with Variable Bandwidth (10MHz to 30MHz) o On-Board Phase-Locked Loop for Generation of Quadrature Detection Local Oscillator (450MHz to 650MHz) o Buffered Baseband Signals (both I and Q) for Ease of Demodulator Characterization o Buffered Baseband Data for Ease of ADC Characterization o User Selectable Output Data Format (twos complement or offset binary) o Programmable Counter for Variable Sample Rates
Evaluates: MAX2101
______________Ordering Information
PART MAX2101EVKIT-SO TEMP. RANGE 0C to +70C BOARD TYPE Surface Mount
_____________________________________________________________Component List
DESIGNATION AR3 U21, U22 AR6 U1, U2 U3 U4 U5 U6 C1, C3-C6, C9, C10, C13-C16, C20, C33, C35, C39, C67-C73, C88, C89, C94, C95, C96, C101, C102, C103, C200, C300, C301 C7, C8 C11, C12 C18, C22, C302 C21, C25, C26, C29, C31, C32, C41, C42, C44, C46, C48, C50, C52, C58, C65, C74, C76, C90 C27, C36, C43, C45, C47, C49, C51, C53, C59, C60, C66, C75, C77, C91 C78, C81 C79, C80, C83, C104, C105 C82 C54, C56, C61-C64, C84-C87, C97-C100 QTY 1 2 1 2 1 1 1 1 33 2 2 3 18 14 2 5 1 14 DESCRIPTION Dual single-supply op amp (SO-8). Maxim MAX407CSA. Wideband transconductance amplifiers. Maxim MAX436CSD. OP27, low-noise op amp (SO-8). Maxim OP27GS. Octal 3-state buffers 74ABT541 (SO-20). Texas Instruments 74ABT541DW. Voltage regulator LM337 (TO-220). National Semiconductor LM337T. ECL phase frequency detector MC12040 (PLCC-20). Motorola MC12040FN. ECL triple-line receiver MC10116 (PLCC-20). Motorola MC10116FN. 6-bit quadrature digitizer MAX2101 (MQFP-100). Maxim MAX2101. 0.01F, 20%, 50V ceramic capacitors 180pF, 5%, 50V ceramic capacitors 470pF, 5%, 100V ceramic capacitors 100pF, 10%, 50V ceramic capacitors 0.1F, 10%, 50V ceramic capacitors 1000pF, 10%, 50V ceramic capacitors 33F, 20%, 20V tantalum capacitors. AVX TPSD336M020R0200. 100F, 20%, 10V tantalum capacitors. AVX TPSD107M010R0100. 10F, 20%, 25V aluminum capacitor. Nichicon UWX1E100M. 0.22F, 10%, 25V ceramic capacitors 1
________________________________________________________________ Maxim Integrated Products
Call toll free 1-800-998-8800 for free samples or literature.
MAX2101 Evaluation Kit Evaluates: MAX2101
________________________________________________Component List (continued)
DESIGNATION C92 C2, C93 D_VARI VR100 L1, L2 L3, L4, L6, L8 R12, R13, R16-R23, R60, R69-R85 R1, R3 R4, R5, R6, R36, R58, R59 R7 R8 R25, R27, R37, R47 R11 R14, R15, R24, R26, R33, R34 R28-R31 R32, R65 R35, R61-R64, R66, R67 R48 R49, R50 R53, R54, R68 R55 R200, R201 R56 R301, R302 R38, R39, R41, R42 R40, R43 R44, R51 R45, R46 SW1 P1-P10 J1, J4, J7, J8 J2, J3, J5, J6 None None SH1* QTY 1 2 1 1 2 4 28 2 6 1 1 4 1 6 4 2 7 1 2 3 1 2 1 2 4 2 2 2 1 10 4 4 1 1 1 DESCRIPTION 2.0pF to 10pF, 100V ceramic variable capacitor. Tusonix 513016 A 2.0-10. 1pF, 10%, 25V ceramic capacitors 2.0pF to 10pF, hyper-abrupt varactor diode (SOT-23). Alpha Industries 1204199 dual or M/A-COM MA45436. 12V zener diode (RV021C through-hole). Motorola 1N4742A. 8nH air-core inductors. CoilCraft A03T. 68nH, 10%, Q = 50 ceramic core inductors. CoilCraft 1206CS-680XKBC. 51, 5%, 0.125W resistors 100, 5%, 0.125W resistors 20k, 1%, 0.125W resistors 5.6k, 1%, 0.125W resistor 2.21k, 1%, 0.125W resistor 4.75k, 1%, 0.125W resistors 24.9, 5%, 0.125W resistor 10k, 5%, 0.125W resistors 47.5k, 1%, 0.125W resistors 2.32k, 1%, 0.125W resistors 1k, 5%, 0.125W resistors 10k, 25%, 0.25W variable resistor (single-turn) 2k, 25%, 0.25W variable resistors (multi-turn through-hole) 200, 1%, 0.125W resistors 121, 1%, 0.125W resistor 221, 5%, 0.125W resistors 75, 1%, 0.125W resistor 500, 5%, 0.125W resistors 51.1k, 1%, 0.125W resistors 576, 1%, 0.125W resistors 5.9k, 1%, 0.125W resistors 150, 1%, 0.125W resistors Dip 6 SPST rocker switch SMA RF connectors, 50, female 0.100"/center 1x2 male square pins 0.100"/center 1x6 male square pins MAX2101 PC board. Maxim. MAX2101 data sheet. Maxim. 0.5" x 1.0" x 0.5" brass RF shield (not mounted). Fotofabrication.
* Optional for shielding the LO resonant tank circuit.
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MAX2101 Evaluation Kit
______________Component Suppliers
SUPPLIER Alpha Industries AVX CoilCraft M/A-COM Motorola Nichicon Fotofabrication Tusonix PHONE (617) 935-5150 (207) 282-5111 (800) 282-4975 (708) 639-6400 (617) 564-3100 (602) 655-5058 (708) 843-7500 (312) 463-6211 (602) 744-0400 FAX (617) 935-2359 (207) 283-1941 (708) 639-1469 (617) 564-3050 (602) 655-5020 (708) 843-2798 (312) 463-3387 (602) 744-6155
Signal Connections
1) Connect the input labeled IFIN to a signal generator through a 50 cable. 2) Connect the input labeled EXT'L OSC IN to a signal generator through a 50 cable. 3) Connect the input labeled MASTER CLK IN to a signal generator through a 50 cable. 4) To use external baseband anti-aliasing filters, connect the output labeled MIXOUTI to the input labeled BBINI through a coaxial cable and the intended filter. The filter must provide a DC signal path from MIXOUTI to BBINI. Follow the same procedure for the MIXOUTQ and BBINQ connections. 5) Connect the output labeled PLL TP to a frequency counter, an oscilloscope, or a spectrum analyzer, through a terminated 50 cable. 6) To characterize the time domain characteristics of the analog baseband signals, connect the output labeled BBOUTI to channel 1 of an oscilloscope through a terminated 50 cable, and connect the output labeled BBOUTQ to channel 2 of the same oscilloscope through a terminated 50 cable. This will facilitate analysis of the quadrature detection network. 7) To characterize the frequency domain characteristics of the analog baseband signal, connect the output labeled BBOUTI (or BBOUTQ) to a spectrum analyzer through a terminated 50 cable. 8) Connect the outputs labeled DATA OUT I, DATA CLK OUT, REF CLK OUT, and DATA OUT Q to a logic analyzer through a flexible 3M cable with 2x20, 0.1" center female headers. Note that jumpers J2, J4, J6, and J8 are connected to ground to realize an efficient ground-return connection for the high-speed digital signals. The cable assembly should use alternating signal-ground assignments, connecting the data line's adjacent ground wire to the associated ground pin on the EV board. The cable assembly should be shielded. It is important that the grounded jumpers be connected as part of the logic analyzer interface cable.
Evaluates: MAX2101
__________Test Equipment Required
Signal Generators
Input (IFIN): 400MHz to 700MHz frequency range (two sources necessary for intermodulation measurements) LO Reference Oscillator: 20MHz to 50MHz frequency range Master Sample Clock: Under 1MHz to over 60MHz frequency range
Measurement Equipment
Oscilloscope: Over 200MHz bandwidth, Tektronix TDS 460 Logic Analyzer: Over 100MHz data rate, Tektronix 3001HSM (200 channels @ 200MHz)
____________________Getting Started
The MAX2101 EV kit is fully assembled and tested. To verify board functionality and proceed with evaluation, follow these start-up instructions. Do not turn on the power supply until all connections are completed.
Power-Supply Connections
1) Connect a +15V supply to the pad marked +15V. 2) Connect a -15V supply to the pad marked -15V. 3) Connect a +5V supply to the pad marked +5V. Verify the supply is capable of sourcing 500mA of current, as noted on the board. 4) Connect a -5.2V supply to the pad marked -5.2V. 5) Connect power-supply ground to the pad marked GROUND.
Initial Conditions
The MAX2101 EV kit comes tested and set to certain initial conditions, as stated in Table 1.
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MAX2101 Evaluation Kit Evaluates: MAX2101
Table 1. MAX2101 EV Kit Initial Conditions
PARAMETER External Oscillator In (P8) Automatic Gain Control Filter Cutoff Frequency Filter Temperature-Coefficient Adjustment Programmable Sample Rate Filter Select Offset Correction Enable Data Format Select SETTING 35MHz (LO = 560MHz) Set for IF IN power of -30dBm 20MHz 0TC at 20MHz Maximum Sample Rate Internal Filters Enabled Offset Binary C92 R50 R49 R48 S0, S1, S2 = 0 FLTRSEL = 0 ENOPB = GND BINEN = 1 ADJUSTMENT
Analysis
1) Select all user settings (note that the EV board has been adjusted to the initial conditions found in Table 1): (a) ENOPB should normally be enabled, i.e. set to ground. (b) Determine the sample rate by setting S0, S1, and S2, referring to the Sample-Rate Control table (Table 1) in the MAX2101 data sheet. For maximum sample rate, set all inputs to logic low. (c) Select the baseband signal path (internal or external) by setting the FLTRSEL switch. For internal signal path, set FLTRSEL to logic low. For external signal path, set FLTRSEL to logic high. (d) Select the digitized baseband data format by setting BINEN. For twos-complement format, set BINEN to logic low. For offset binary format, set BINEN to logic high. 2) Establish LO: (a) Choose the desired LO frequency, fLO; for this EV kit, the LO should be between 450MHz and 650MHz. The MAX2101 EV kit has been factory preset for a LO frequency of 560MHz. (b) Divide fLO by 16 to determine the External Reference Oscillator Frequency, fREF: fREF = fLO /16 (c) Apply f REF to the EXT'L OSC IN port, with a power level between -10dBm and 0dBm. 3) Establish the input and output signals: (a) Choose a baseband frequency, fBB; for the MAX2101 EV kit, the frequency should be between 10kHz and 30MHz. (b) Determine the input frequency, fIN, by adding or subtracting fBB from fLO: fIN = fLO fBB (c) Choose a signal power for the input signal, fIN; for the MAX2101, the power should be between -50dBm and -10dBm. (c) Apply fIN to the IFIN port.
4) Apply power to the board. Note the following supply sequence: (a) Turn on the +15V and -15V supplies. (b) Turn on the -5.2V supply. (c) Turn on the +5V supply. (d) Measure the voltage at Test Point 3, VREF; this voltage should be between 1.18V and 1.26V. (e) Adjust the variable capacitor, C92, until the frequency measured at the PLL TP output equals f REF . (f) Verify the phase-locked loop is active by measuring the voltage at the output of the loop filter, at C13; this voltage should be between 0V and +11V. (g) If the loop is not locked, adjust capacitor C92, while periodically shorting the left node of VR100 to ground, until the loop locks. (h) Adjust the filters to ensure they are not attenuating the baseband signal by adjusting the FTUNE ADJUST potentiometer until the voltage measured on the rectangular pad next to R12 is greater than 3V. (i) Verify the correct baseband frequency by measuring the BBOUTI or BBOUTQ signal. (j) Adjust the AGC ADJUST potentiometer until the peak-to-peak amplitude of the signal at BBOUTI or BBOUTQ is 500mVp-p. (k) Adjust the FTUNE ADJUST potentiometer until the signals at BBOUTI and BBOUTQ are attenuated between 0% and 5%. (l) As a final check for proper operation, measure the voltage on OFFI by probing the left node of capacitor C97, and measure the voltage on OFFQ by probing the left node of capacitor C100. The measured voltages should be in the 1.5V to 3.5V range. 5) Acquire signals: (a) Measure all signals associated with DATA CLK OUT, DATA OUT I, and DATA OUT Q to verify proper logic levels. (b) Using the DATA CLK OUT signals as the synchronizing clock, acquire data at DATA OUT I and DATA OUT Q with a logic analyzer. Note the data frequency and edge
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MAX2101 Evaluation Kit
rate require proper high-speed design techniques to ensure proper data transmission. Each data pin has an associated ground pin. The data line should be AC terminated in the cable's characteristic impedance. Analysis may now be performed in the digital domain. 6) The analog quadrature demodulator front end may be analyzed by measuring signals at various ports. The analog baseband signals can be measured at the BBOUTI and BBOUTQ ports. The video amplifiers buffering BBOUTI and BBOUTQ can drive a ground referenced 50 load, such as a high-speed oscilloscope probe. The mixer output signals can be measured at MIXOUTI and MIXOUTQ. Select the external signal path with the FLTRSEL control to measure MIXOUTI and MIXOUTQ. The MAX2101 can drive a back-terminated AC-coupled impedance of 50 at this port. The AGC should be adjusted to provide -22dBm from MIXOUTI and MIXOUTQ, ensuring a full-scale signal at the BBINI and BBINQ ports. Measurements at these ports facilitate analysis of the IF front end and the quadrature demodulation networks, without adding effects due to baseband filters and amplifiers.
Inputs/Outputs
RF Input (P7). Accepts a 400MHz to 700MHz signal, depending on the coarse setting of the resonant-tank variable capacitor. Signal level can be from -50dBm to -10dBm. Signal is DC referenced to ground, and is AC coupled through an impedance matching network to the MAX2101's IFIN input. I and Q Channel Mixer Outputs (MIXOUTI/Q) (P4, P5). Intended to drive a lowpass filter, which drives the appropriate baseband input. Output is capable of driving 100 referenced to 2.4V. I and Q Channel Baseband Inputs (BBINI/Q) (P1, P6). Accepts the filtered, downconverted signal from the appropriate mixer output port. Driving signal must be DC referenced to 2.4V. Signal level should be nominally 18mV, or -22dBm from a 50 source resistance. I and Q Channel Analog Baseband Outputs (BBOUTI/Q) (P2, P3). The analog baseband signals prior to digitizing. The internal baseband signals are buffered, converted from differential to single-ended format, attenuated, and translated to ground reference. This signal is capable of driving 50 for ease of evaluation. LO Reference Oscillator In (P8). This port accepts the external oscillator that determines the LO frequency. The LO frequency will be 16 times the reference signal frequency. To realize a LO frequency range of 400MHz to 700MHz, the external oscillator must supply a frequency range of 25MHz to 43.75MHz. The signal level should be between -7dBm and +5dBm from a 50 source resistance. The source should exhibit extremely low phase noise (better than -90dBc at 10kHz off the carrier) to ensure optimum phase-noise performance of the LO. Phase-Lock-Loop Test Point (P10). Test point for examining the output of the MAX2101 prescaler. Capable of driving a low-impedance load directly (RL = 50). Master Clock In (MCLK) (P9). Port for accepting the master sample-clock signal. Signal level must be between 0dBm and +10dBm. Signal should exhibit low jitter characteristics (<40ps) to ensure proper sample jitter on the digitized data. Reference Clock Out (RCLK) (J7, J8). Buffered output port from the MAX2101 providing a low-jitter replica of the master clock, divided by 6 in frequency. Output clock is in TTL/CMOS format.
Evaluates: MAX2101
Resonator Shield
The MAX2101 EV kit includes a shield to prevent EMI from pulling the resonator frequency or introducing noise into the resonator signal. You may attach the shield over the resonator network after setting the desired LO frequency (by adjusting C92). Attach the shield by (a) forming the shield following the indentations provided, and (b) soldering the shield to the grounded contact surrounding the resonator tank. If further adjustment of C92 is required, simply drill a hole into the shield, placed over the trimmer capacitor, with a diameter just large enough to allow insertion of a tool.
______Board Interface Descriptions
Power Supplies
+5V 5%, 500mA. Provides power for the MAX2101, the data buffers, and the single-supply op amps. -5.2V 5%, 50mA. Provides power for MC10116 line receiver and MC12040 phase frequency detector. Ground 50mV. +15V or -15V 10%, 10mA. Provides power for the phase-locked-loop op amp (AR6).
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MAX2101 Evaluation Kit Evaluates: MAX2101
Data Clock Out (DCLK) (J1, J4). Buffered output port from the MAX2101 providing the sample clock synchronized with the data. Data clock output is in differential TTL/CMOS format. Data Out I/Q (J2, J3, J5, J6). Buffered output port from the MAX2101 providing the baseband digitized data for both I and Q channels. Data is in TTL/CMOS format.
User-Selectable Settings
Programmable Sample Rate (S0, S1, S2). The ADC sample rate is determined by the frequency of the master clock and the programmable sample-rate prescaler. The setting of this prescaler is determined by the logic levels set by toggle switches S0, S1, and S2, according to the Sample-Rate Control table (Table 1) in the MAX2101 data sheet. Filter Select (FLTRSEL). The FLTRSEL logical input selects the signal path of the baseband signal out of the quadrature detection mixers. Logic level 0 (low) enables the internal signal path, through the internal lowpass filters. At this setting, MIXOUTI and MIXOUTQ are disabled. Logic level 1 (high) enables MIXOUTI and MIXOUTQ, and disables the internal signal path. Offset Correction Enable (ENOPB). This input enables the internal op amps in the offset correction networks. ENOPB at 0V enables the op amps, while ENOPB at 5V disables the op amps. Data Format Select (Binary Enable) (BINEN). This input selects the output data format. Logic level 0 (low) selects the twos-complement format, while logic level 1 (high) selects an offset binary format.
Adjustments
Automatic Gain Control (AGC) (R50). A variable resistor sets the gain of the signal path. The variable gain adjusts for the signal level at the input (IFIN) to provide a full-scale signal to the ADCs. FTUNE Adjust (R49). A potentiometer sets the voltage applied to a network to establish the cutoff frequency for the two internal lowpass filters. This adjustment sets both filters. TC Adjust (R48). A variable resistor sets the temperature coefficient of the filter tuning network to compensate for the filters' temperature dependence. The 10k potentiometer is used as a variable resistor. This resistor should be adjusted to 0 for a zero temperature coefficient at 20MHz cutoff frequency. Resonant Tank Trim (C92). A variable capacitor establishes the coarse setting of the LO frequency.
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BBOUTI
C56 0.22F R1 100 R46 150 A C63 0.22F A A
+5V 11 42 1 13 7 A 2 R+ 3 R38 51.1k R40 576 1% PP2 C84 PROBEPT 0.22F PP3 PROBEPT C97 0.22F C100 0.22F 72 INVI A C99 0.22F 71 NONINVI C98 0.22F 70 NONINVQ
69 IN
P2 SMA
1 2 A
U21
MAX436 5 R6
18 0 1 R51 5.9k 1%
C87 0.22F R39 51.1k
C64 0.22F +5V VCC 1m358 3
U6 MAX2101CMQ
AGC ADJUST +5V +5V R301 500 1 R49 2k 3 R302 500 A R5 20k C101 0.01F A C103 A 0.01F R53 200 2 C67 0.01F 74 BBOUTIB 75 BBOUTI 76 OFFI 78 BBINI 77 FTUNEI 81 MIXOUTI 93 AGC 90 IFIN 91 IFINB 86 88 97 100
A
-5.2V C94 0.01F
A
AR3A MAX407
R7 5.6k R8 2.21k 3 2
8 1 4 A R47 4.75k FTUNE ADJUST PP5
PP4 PROBEPT
BBINI P1
SMA
1 2 A 1 2 A R13 51
PP6 PROBEPT C95 0.01F A
1 R50 2k
AR3B
2 R4 20k
MAX407
5 7 6
VREF
TP3 VREF 1 R37 4.75k A R70 51
MIXOUTI P4
SMA A L1 8nH C2 1pF A
R48 10k 1
2 PROBEPT TC ADJUST C90 0.1F +5V
R6 20k
R36 20k
3 R54 200 A IFIN 1 P7
SMA
C1 2 A 0.01F
A C3 R11 0.01F 24.9
A
C102 0.01F
MIXOUTO P5
A SMA
1 2 A 1 2 A R12 51
2R5 VREF VPTAT MIXOUTQ
PP7 PROBEPT C96 0.01F A
BBOUTQ
C54 0.22F R3 100 R45 150
A
11 42 1
A 2 R+ 3
R41 51.1k R43 576 1%
C85 0.22F
PP9 PROBEPT
BBINO P6
SMA
4 FTUNEQ 3 BBINQ 5 6 7 23 24 OFFQ BBOUTQ BBOUTQB VCOPRE VCOPREQ
P3 SMA
1 2 A
13 7 A
U22
MAX436 5 R6
18 0 1 R44 5.9k 1%
C86 0.22F R42 51.1k
PP10 PROBEPT
N.C. 1 9 12 13 18 19 63 67 82 83 89 92 98
C61 0.22F
A -5.2V
C62 0.22F +5V
A
VCCQ
VCC2A
VCCAD
VCCIF
VCCI PP11 PROBEPT +5V PP12 PROBEPT C6 0.01F R26 10k R24 10k C5 0.01F
+5V
PWR 1 C104 100F PWRIN1 +5V C105 100F C42 0.1F C43 1000pF A C16 0.01F L4 C18 68nH 100pF C301 0.01F VGNDQ VCCP PWRIN2 GROUND A D C26 0.1F D C39 0.01F VGND2 VCCO C31 0.1F VGNDO C41 0.1F C33 0.01F C20 0.01F L6 C22 68nH 100pF C300 0.01F VGNDAD VCCD C29 0.1F VGNDD C21 0.1F VGNDIF C88 0.01F L8 68nH C32 0.1F VGNDI VCC C25 0.1F GND C27 1000pF VCC 1m358
VSUBAD A VSUBRF VCCC
GROUND
PWR 1
C36 1000pF
C66 1000pF
C35 0.01F VGNDC D
VGNDP
-5.2V
PWR 1 C79 100F PWRIN3 -5.2V C80 100F C44 0.1F C45 1000pF C50 0.1F C51 1000pF VEE -5.2V
+15V
PWR 1 C52 0.1F VCC1 VCC2 C53 1000pF D C78 33F PWRIN4 +15V C46 0.1F C47 1000pF C58 0.1F C59 1000pF A +15V
-15V
PWR 1 C81 33F PWRIN5 -15V C48 0.1F C49 1000pF C65 0.1F C60 1000pF A -15V
Figure 1. MAX2101 EV Kit Schematic
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+5V C99 0.22F 71 NONINVI C98 0.22F 70 NONINVQ D 69 INVQ 68 ENOP 95 FLTRSEL 56 BINEN 62 S0 58 S1 57 S2 65 MCLK 85 PWRI 54 53 50 49 2 3 4 5 6 7 8 9 1 19 D 2 3 4 5 6 7 8 1 19 D 1 2 3 4 5 6 12 11 10 9 8 7 C74 0.1F D C75 1000pF
A
Evaluates: MAX2101
R61 1k
R62 1k
R63 1k
R64 1k
R67 1k D
U6 MAX2101CMQ
SW1 SW DIP-6
R66 1k C89 MASTER CLK IN 0.01F 1 P9
PP6 PROBEPT C95 0.01F A
46 45 42 DCLK 41 DCLKB
D5I D4I D3I D2I D1I D0I
18 Y1 A1 17 A2 Y2 16 A3 Y3 U1 15 A4 Y4 74ABT541 14 A5 Y5 13 A6 Y6 12 A7 Y7 11 A8 Y8 G1 G2 A1 Y1 Y2 A2 A3 Y3 U2 A4 Y4 74ABT541 A5 Y5 A6 Y6 A7 Y7 G1 Y8 G2 18 17 16 15 14 13 12 11
R71-R78 51
1 2 3 4 5 6 1 2 1 2 1 2 3 4 5 6
J3
1 2 3 4 5 6 1 2 1 2 1 2 3 4 5 6 D 2
J2
R59 20k
1 TP1 C14 PWR I 0.01F A
R60 51 A
2
SMA D
DATA OUT I
M6 J1 M2 J7 M2 J5
M6 J4
DATA CLK OUT
M2 J8
PP7 PROBEPT C96 0.01F A
RCLK D0Q D1Q D2Q D3Q 28 D4Q 27 D5Q
39 36 35 32 31
R79-R85 51
REF CLK OUT
M2 J6
DATA OUT Q
CIRCUITRY WITHIN DASHED LINE TO BE UNDER METAL ENCLOSURE L3 68nH 3 1 C93 1pF 2 C92 2-10pF R34 10k A C13 0.01F D C10 0.01F R32 2.32k +15V 3 7 A R35 1k R33 10k R68 200 +15V C76 0.1F A C77 1000pF PP16 PROBEPT VR100 1N4742A
M6 C15 0.01F
M6 TP2
D_VAR1 1204199 ALPHA
C11 470pF
PWRQ N.C. 9 12 13 18 19 63 67 82 83 89 92 98 99 A
96
TNKB 14 TNKA 17 BGRIN 80 C91 1000pF A C302 100pF
R58 20k
PWR Q
A
U5B MC10116 12 8
13 9 14 R200 221 C200 PLL TP 0.01F 1 P10 R201 221 VEE 2 SMA D
L2 8nH
C12 470pF
P11 OBEPT
C6 0.01F
R26 10k R24 10k
U5A MC10116 5 3
7 R27 4.75k C69 0.01F D R25 4.75k 14 4 R18 51
13
V
U_BAR
4
R28 47.5k
R29 47.5k C7 180pF R31 47.5k C8 180pF
C5 0.01F
R19 51 9 VT R
6 U4 U MC12040 18 D_BAR D 16 R20 51 R21 51 VT D R56 75 C82 10F -5.2V 1 ADJ U3 3 LM337T VOUT VIN 2 R22 51
R30 47.5k R23 51
D
AR6
2 OP27 1 48 -15V
6
C70 0.01F D C4 0.01F
D
P8 SMA
1 2 D R69 51
U5C PP14 MC10116 PROBEPT 15 18
17 19 14 R16 51 R17 51
C72 0.01F
C73 0.01F D C83 100F R55 121
C9 R65 2.32k 0.01F
EXT'L OSC IN
R15 10k D
R14 10k
PP15 VT PROBEPT
C68 0.01F
VT D
C71 0.01F D
-2V
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MAX2101 Evaluation Kit Evaluates: MAX2101
Figure 2. MAX2101 EV Kit Component Placement Guide--Component Side (Positive Image)
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MAX2101 Evaluation Kit Evaluates: MAX2101
Figure 3. MAX2101 EV Kit Component Placement Guide--Solder Side (Positive Image)
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MAX2101 Evaluation Kit Evaluates: MAX2101
Figure 4. MAX2101 EV Kit PC Board Layout--Component Side (Positive Image)
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MAX2101 Evaluation Kit Evaluates: MAX2101
Figure 5. MAX2101 EV Kit PC Board Layout--Supply Plane (Negative Image)
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MAX2101 Evaluation Kit Evaluates: MAX2101
Figure 6. MAX2101 EV Kit PC Board Layout--Ground Plane (Negative Image)
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MAX2101 Evaluation Kit Evaluates: MAX2101
Figure 7. MAX2101 EV Kit PC Board Layout--Solder Side (Positive Image)
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MAX2101 Evaluation Kit
MAX2101 EV DS REV 0
Evaluates: MAX2101
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MAX2101 Evaluation Kit Evaluates: MAX2101
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MAX2101 Evaluation Kit Evaluates: MAX2101
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