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MT88L89
3V Integrated DTMF Transceiver with Adaptive Micro Interface
Features
* * * * * * * * Complete DTMF transmitter/receiver Low voltage operation (2.7-3.6V) Pin for pin compatible with existing MT8880, MT8888 and MT8889 devices Adaptive micro interface enables compatibility with Intel and Motorola processors DTMF transmitter/receiver power-down via register control Adjustable guard time Automatic tone burst mode Call progress tone detection to -30dBm
DS5033 ISSUE 3 January 1999
Ordering Information MT88L89AE 20 Pin Plastic DIP MT88L89AS 20 Pin SOIC MT88L89AN 24 Pin SSOP MT88L89AP 28 Pin PLCC -40C to +85C
Description
The MT88L89 is a monolithic DTMF transceiver with call progress filter. It is fabricated in CMOS technology offering low power consumption and high reliability. The receiver section is based upon the industry standard MT8870 DTMF receiver. The transmitter utilizes a switched capacitor D/A converter for low distortion, high accuracy DTMF signalling. Internal counters provide a burst mode such that tone bursts can be transmitted with precise timing. A call progress filter can be selected allowing a microprocessor to analyze call progress tones. The MT88L89 utilizes an adaptive micro interface, which allows the device to be connected to a number of popular microcontrollers with minimal external logic. The MT88L89 provides enhanced power-down features. The transmitter and receiver may independently be powered down via register control.
Applications
* * * * * * Credit card systems Paging systems Repeater systems/mobile radio Interconnect dialers Pay phones Remote monitor/Control systems
TONE
D/A Converters
Row and Column Counters
Transmit Data Register Status Register
Data Bus Buffer
D0 D1 D2 D3
Tone Burst Gating Cct. IN+ INGS OSC1 OSC2 Oscillator Circuit Bias Circuit VDD VRef VSS + Dial Tone Filter
Control Logic
Interrupt Logic IRQ/CP
High Group Filter Low Group Filter Control Logic
Digital Algorithm and Code Converter
Control Register A Control Register B I/O Control
DS/RD CS R/W/WR RS0
Steering Logic
Receive Data Register
ESt
St/GT
Figure 1 - Functional Block Diagram
4-123
MT88L89
IN+ INGS VRef VSS OSC1 OSC2 TONE R/W/WR CS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD St/GT ESt D3 D2 D1 D0 IRQ/CP DS/RD RS0 IN+ INGS VRef VSS OSC1 OSC2 NC NC TONE R/W/WR CS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD St/GT ESt D3 D2 D1 D0 NC NC IRQ/CP DS/RD RS0
GS NC ININ+ VDD St/GT EST
4 3 2 1 28 27 26
*
20 PIN /PLASTIC DIP/SOIC
24 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin # 20 1 2 3 4 5 6 7 24 1 2 3 4 5 6 7 28 1 2 4 6 7 8 9 Name IN+ INGS VRef VSS OSC1 OSC2 Non-inverting op-amp input. Inverting op-amp input. Gain Select. Gives access to output of front end differential amplifier for connection of feedback resistor. Reference Voltage output (VDD/2). Ground (0V). Oscillator input. This pin can also be driven directly by an external clock. CMOS compatible. Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2 completes the internal oscillator circuit. Leave open circuit when OSC1 is driven externally. Output from internal DTMF transmitter. High impedance when TOUT bit in Control Register A (CRA) is set to low. Requires resistive termination to VSS. (Motorola) Read/Write or (Intel) Write microprocessor input. CMOS compatible. Chip Select input must be gated externally by either address strobe (AS), valid memory address (VMA) or address latch enable (ALE) signal, depending on processor used. See Figure 12. Must not be tied low. CMOS compatible. Register Select input. Refer to Table 3 for bit interpretation. CMOS compatible. Description
8 9 10
10 11 12
12 13 14
TONE R/W (WR) CS
11 12 13
13 14 15
15
RS0
17 DS (RD) (Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this input is only required when the device is being accessed. CMOS compatible. 18 IRQ/CP Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes low when a valid DTMF tone burst has been transmitted or received. In call progress mode, this pin will output a rectangular signal representative of the input signal applied at the input op-amp. The input signal must be within the bandwidth limits of the call progress filter. See Figure 10. D0-D3 ESt Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1 (Intel). CMOS compatible. Early Steering output. Presents a logic high once the digital algorithm has detected a valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low.
14- 18- 1917 21 22 18 22 26
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TONE R/W/WR CS RS0 NC DS/RD IRQ/CP
12 13 14 15 16 17 18
NC VRef VSS OSC1 OSC2 NC NC
5 6 7 8 9 10 11
25 24 23 22 21 20 19
NC NC NC D3 D2 D1 D0
28 PIN PLCC
MT88L89
Pin Description
Pin # 20 19 24 23 28 27 Name St/GT Description Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt detected at St causes the device to register the detected tone pair and update the output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. Positive power supply (3V typ.).
20
24
28
VDD
Functional Description
The MT88L89 Integrated DTMF Transceiver consists of a high performance DTMF receiver with an internal gain setting amplifier and a DTMF generator, which employs a burst counter to synthesize precise tone bursts and pauses. A call progress mode can be selected so that frequencies within the specified passband can be detected. The adaptive micro interface allows various microcontrollers to access the MT88L89 internal registers. Power-Down The MT88L89 provides enhanced power-down functionality to facilitate minimization of supply current consumption. DTMF transmitter and receiver circuit blocks can be independently powered down via register control. When asserted, RxEN control bit powers down all analog and digital circuitry associated solely with the DTMF and Call Progress receiver. The TOUT control bit is used to disable the transmitter and put all circuitry associated only with the DTMF transmitter in power-down mode. With the TOUT control bit is set to zero, the TONE output pin is held in a high impedance (floating) state. When both transmitter and receiver circuits are powered down, circuits utilized by both the DTMF transmitter and receiver are also powered down. This powerdown control disables the crystal oscillator, and the VRef generator. In addition, the IRQ, TONE output and DATA pins are held in a high impedance state. Input Configuration The input arrangement of the MT88L89 provides a differential-input operational amplifier as well as a bias source (VRef), which is used to bias the inputs at VDD/2. Provision is made for connection of a feedback resistor to the op-amp output (GS) for gain adjustment.
For applications which are required to meet a guaranteed RX input level of -29dBm over the full temperature and supply voltage range, a unity gain input configuration as shown in Figures 3 and 4 can be used. For applications which require signal detection lower than -29dBm, the external resistors can be configured to give adequate gain. For example, if the application requires tone detection of -31dBm, the input gain can be set to +2dB with the external resistors (see Figures 13 and 14 for value of resistors). However, when +2dB gain is used, the corresponding maximum input signal level must not exceed -6dBm. Receiver Section Separation of the low and high group tones is achieved by applying the DTMF signal to the inputs of two sixth-order switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies (see Table 1). The filters also incorporate notches at 350 Hz and 440 Hz for exceptional dial tone rejection. Each filter output is followed by a single order switched capacitor filter section, which smooths the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals. The outputs of the comparators provide full rail logic swings at the frequencies of the incoming DTMF signals.
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MT88L89
MT88L89 IN+ IN-
C
RIN
VOLTAGE GAIN (AV) = RF / RIN
RF
GS VRef
Figure 3 - Single-Ended Input Configuration
C1 R1 C2 R4 R5 GS R3 R2 VRef DIFFERENTIAL INPUT AMPLIFIER C1 = C2 R1 = R4 VOLTAGE GAIN R3 = (R2R5)/(R2 + R5) (AV diff) = R5/R1 FOR UNITY GAIN INPUT IMPEDANCE R5=R1 (ZINdiff) = 2 R12 + (1/C)2 MT88L89 IN+ IN-
Following the filter section is a decoder employing digital counting techniques to determine the frequencies of the incoming tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm protects against tone simulation by extraneous signals such as voice while providing tolerance to small frequency deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. When the detector recognizes the presence of two valid tones (this is referred to as the "signal condition" in some industry specifications) the "Early Steering" (ESt) output will go to an active state. Any subsequent loss of signal condition will cause ESt to assume an inactive state. Steering Circuit Before registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as character recognition condition). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes vc (see Figure 5) to rise as the capacitor discharges. Provided that the signal condition is maintained (ESt remains high) for the validation period (tGTP), vc reaches the threshold (VTSt) of the steering logic to register the tone pair, latching its corresponding 4-bit code (see Table 1) into the Receive Data Register. At this point the GT output is activated and drives vc to VDD. GT continues to drive high as long as ESt remains high. Finally, after a short delay to allow the output latch to settle, the delayed steering output flag goes high, signalling that a received tone pair has been registered. The status of the delayed steering flag can be monitored by checking the appropriate bit in the status register. If Interrupt mode has been selected, the IRQ/CP pin will pull low when the delayed steering flag is active. The contents of the output latch are updated on an active delayed steering transition. This data is presented to the four bit bidirectional data bus when the Receive Data Register is read. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (drop out) too short to be considered a valid pause. This facility, together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements.
Figure 4 - Differential Input Configuration
FLOW FHIGH DIGIT D3 D2 D1 D0
697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941
1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633
1 2 3 4 5 6 7 8 9 0 * # A B C D
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0
0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
0= LOGIC LOW, 1= LOGIC HIGH
Table 1 - Functional Encode/Decode Table
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MT88L89
VDD
MT88L89
The value of tDP is a device parameter (see AC Electrical Characteristics) and tREC is the minimum signal duration to be recognized by the receiver. A value for C1 of 0.1 F is recommended for most
C1 Vc R1 St/GT tGTA = (R1C1) In (VDD / VTSt) tGTP = (R1C1) In [VDD / (VDD-VTSt)] tGTP = (RPC1) In [VDD / (VDD-VTSt)] tGTA = (R1C1) In (VDD/VTSt) VDD C1 RP = (R1R2) / (R1 + R2)
VDD
St/GT ESt
R1 ESt
R2 a) decreasing t GTP; (t GTP < t GTA)
Figure 5 - Basic Steering Circuit Guard Time Adjustment
tGTP = (R1C1) In [VDD / (VDD-VTSt)]
The simple steering circuit shown in Figure 5 is adequate for most applications. Component values are chosen according to the following inequalities (see Figure 7): t REC t DPmax + t GTPmax - t DAmin t REC t DPmin + t GTPmin - t DAmax t ID t DAmax + t GTAmax - t DPmin t DO t DAmin + t GTAmin - t DPmax
VDD C1 St/GT
tGTA = (RpC1) In (VDD/VTSt) RP = (R1R2) / (R1 + R2)
R1 ESt
R2 b) decreasing t GTA; (t GTP > t GTA)
Figure 6 - Guard Time Adjustment
Pin Description
Pin # 20 24
8,9 16, 17
28
3,5, 1011 16 2325
Name NC No Connection.
Description
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MT88L89
EVENTS A B C D E F
tREC
Vin
tREC
TONE #n
tID
TONE #n + 1
tDO
TONE #n + 1
tDP
ESt
tDA tGTP tGTA
VTSt
St/GT
tPStRX
RX0-RX3 DECODED TONE # (n-1) #n # (n + 1)
tPStb3
b3
b2
Read Status Register IRQ/CP
Figure 7 - Receiver Timing Diagram
applications, leaving R1 to be selected by the designer. Different steering arrangements may be used to select independent tone present (tGTP) and tone absent (tGTA) guard times. This may be necessary to meet system specifications which place both accept and reject limits on tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor system parameters such as talk-off and noise immunity. Increasing tREC improves talk-off performance since it reduces the probability that tones simulated by speech will maintain a valid signal condition long enough to be registered. Alternatively, a relatively short tREC with a long tDO would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figure 6. The receiver timing is shown in Figure 7 with a description of the events in Figure 8.
input are common, however, call progress tones can only be detected when CP mode has been selected. DTMF signals cannot be detected if CP mode has been selected (see Table 7). Figure 10 indicates the useful detect bandwidth of the call progress filter. Frequencies presented to the input, which are within the `accept' bandwidth limits of the filter, are hardlimited by a high gain comparator with the IRQ/CP pin serving as the output. The square-wave output obtained from the schmitt trigger can be analyzed by a microprocessor or counter arrangement to determine the nature of the call progress tone being detected. Frequencies which are in the `reject' area will not be detected and consequently the IRQ/CP pin will remain low.
DTMF Generator
The DTMF transmitter employed in the MT88L89 is capable of generating all sixteen standard DTMF tone pairs with low distortion and high accuracy. All frequencies are derived from an external 3.579545 MHz crystal. The sinusoidal waveforms for the individual tones are digitally synthesized by using row and column programmable dividers and switched capacitor D/A converters. The row and column tones are mixed and filtered to provide a DTMF signal with low total harmonic distortion and
Call Progress Filter
A call progress mode, using the MT88L89, can be selected to allow the detection of various tones, which identify the progress of a telephone call on the network. The call progress tone input and DTMF
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MT88L89
high accuracy. To specify a DTMF signal, data conforming to the encoding format shown in Table 1 must be written to the transmit Data Register. Note that Table 1 is the same as the receiver output code. The individual tones which are generated (fLOW and fHIGH) are referred to as Low Group and High Group tones. As seen from the table, the low group frequencies are 697, 770, 852 and 941 Hz. The high group frequencies are 1209, 1336, 1477 and 1633 Hz. Typically, the high group to low group amplitude ratio (twist) is 2 dB to compensate for high group attenuation on long loops.
LEVEL (dBm)
is issued and the counter starts again. The number of time segments is fixed at 32, however, by varying the segment length as described above, the frequency can also be varied. The divider output clocks another counter, which addresses the sinewave lookup ROM. The lookup table contains codes which are used by the switched capacitor D/A converter to obtain discrete and highly accurate DC voltage levels. Two identical circuits are employed to produce row and column tones, which are then mixed by using a low noise summing amplifier. A bandwidth limiting filter is incorporated and serves to attenuate distortion products above 8 kHz. Figure 9 shows that the distortion products are very low in amplitude.
-25
Burst Mode
In certain telephony applications it is required that DTMF signals being generated are of a specific duration determined either by the particular application or by any one of the exchange transmitter specifications currently existing. Standard DTMF signal timing can be accomplished by making use of the Burst Mode. The transmitter is capable of issuing symmetric bursts/pauses of predetermined duration. This burst/pause duration is 51 ms1 ms which is a standard interval for autodialer and central office applications. After the burst/pause has been issued, the appropriate bit is set in the Status Register to indicate that the transmitter is ready for more data. The timing described above is available when DTMF mode has been selected. However, when CP mode (Call Progress mode) is selected, the burst/pause duration is doubled to 102 ms 2 ms. Note that when CP mode and Burst mode have been selected, DTMF tones may only be transmitted and not
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0 = Reject = May Accept = Accept
250
500
750
FREQUENCY (Hz)
Figure 10 - Call Progress Response The period of each tone consists of 32 equal time segments. The period of a tone is controlled by varying the length of these time segments. During write operations to the Transmit Data Register the 4 bit data on the bus is latched and converted to 2 of 8 coding for use by the programmable divider circuitry. This code is used to specify a time segment length, which will ultimately determine the frequency of the tone. When the divider reaches the appropriate count, as determined by the input code, a reset pulse
MT88L89
received. In applications where a non-standard burst/pause time is desirable, a software timing loop or external timer can be used to provide the timing pulses when the burst mode is disabled by enabling and disabling the transmitter. group amplitude, respectively and V2IMD is the sum of all the intermodulation components. The internal switched-capacitor filter following the D/A converter keeps distortion products down to a very low level as shown in Figure 9.
Single Tone Generation
A single tone mode is available whereby individual tones from the low group or high group can be generated. This mode can be used for DTMF test equipment applications, acknowledgment tone generation and distortion measurements. Refer to Control Register B (CRB) description for details.
ACTIVE INPUT L1 L2 L3 L4 H1 H2 H3 H4 OUTPUT FREQUENCY (Hz) SPECIFIED ACTUAL %ERROR
V22L + V23L + .... V2nL + V22H + V23H + .. V2nH + V2IMD
THD (%) = 100
V2L + V2H
Equation 2. THD (%) For a Dual Tone
DTMF Clock Circuit
+0.30 -0.49 -0.54 +0.74 +0.57 -0.32 -0.35 Frequency: Frequency Tolerance: Resonance Mode: Load Capacitance: Maximum Series Resistance: Maximum Drive Level: 3.579545 MHz 0.1% Parallel 18 pF 150 ohms 2 mW The internal clock circuit is completed with the additions of a standard television colour burst crystal. The crystal specification is as follows:
697 770 852 941 1209 1336 1477
699.1 766.2 847.4 948.0 1215.9 1331.7 1471.9
1633 1645.0 +0.73 Table 2. Actual Frequencies Versus Standard Requirements
Distortion Calculations
The MT88L89 is capable of producing precise tone bursts with minimal error in frequency (see Table 2). The internal summing amplifier is followed by a firstorder lowpass switched capacitor filter to minimize harmonic components and intermodulation products. The total harmonic distortion for a single tone can be calculated by using Equation 1, which is the ratio of the total power of all the extraneous frequencies to the power of the fundamental frequency expressed as a percentage.
e.g. CTS Knights MP036S Toyocom TQC-203-A-9S A number of MT88L89 devices can be connected as shown in Figure 11 such that only one crystal is required. Alternatively, the OSC1 inputs on all devices can be driven from a CMOS buffer with the OSC2 outputs left unconnected.
MT88L89 OSC1 OSC2
MT88L89 OSC1 OSC2
MT88L89 OSC1 OSC2
V22f + V23f + V24f + .... V2nf
THD (%) = 100
3.579545 MHz
Figure 11 - Common Crystal Connection
V2fundamental
Equation 1. THD (%) For a Single Tone The Fourier components of the tone output correspond to V2f.... Vnf as measured on the output waveform. The total harmonic distortion for a dual tone can be calculated by using Equation 2. VL and VH correspond to the low group amplitude and high
Microprocessor Interface
The MT88L89 design incorporates an adaptive interface, which allows it to be connected to various kinds of microprocessors. Key functions of this interface include the following:
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MT88L89
* * Continuous activity on DS/RD is not necessary to update the internal status registers. Compatible with Motorola and Intel processors. Determines whether input timing is that of an Intel or Motorola controller by monitoring DS/RD, on the CS falling edge. Differentiates between multiplexed and nonmultiplexed microprocessor buses. Address and data are latched in accordingly. details). Transceiver control is accomplished with two control registers (see Tables 6 and 7), CRA and CRB, which have the same address. A write operation to CRB is executed by first setting the most significant bit (b3) in CRA. The following write operation to the same address will then be directed to CRB, and subsequent write cycles will be directed back to CRA. The read-only status register indicates the current transceiver state (see Table 8). A software reset must be included at the beginning of all programs to initialize the control registers upon power-up or power reset (see Figure 15). Refer to Tables 4-7 for bit descriptions of the two control registers. The multiplexed IRQ/CP pin can be programmed to generate an interrupt upon validation of DTMF signals or when the transmitter is ready for more data (burst mode only). Alternatively, this pin can be configured to provide a square-wave output of the call progress signal. The IRQ/CP pin is an open drain output and requires an external pull-up resistor (see Figure 13 and Figure 14).
Motorola RS0 R/W Intel WR RD FUNCTION Write to Transmit Data Register Read from Receive Data Register Write to Control Register Read from Status Register
*
Figure 17 shows the timing diagram for the Motorola microcontrollers. The chip select (CS) input is formed by NANDing address strobe (AS) and address decode output. The MT88L89 examines the state of DS/RD on the falling edge of CS. For Motorola bus timing DS/RD must be low on the falling edge of CS. Figure 12(a) shows the connection of the MC68L11/ MC68B11 Motorola processor to the MT88L89 DTMF transceiver. Figures 18 and 19 are the timing diagrams for the Intel 8xL5x series (12 MHz) micro-controllers with multiplexed address and data buses. The MT88L89 latches in the state of DS/RD on the falling edge of CS. When DS/RD is high, Intel processor operation is selected. By NANDing the address latch enable (ALE) output with the high-byte address (P2) decode output, CS can be generated. Figure 12(b) shows the connection of these Intel processors to the MT88L89 transceiver. NOTE: The adaptive micro interface relies on highto-low transition on CS to recognize the microcontroller interface. This pin must not be tied permanently low. Only one register access is allowed on any CS assertion. The adaptive micro interface provides access to five internal registers. The read-only Receive Data Register contains the decoded output of the last valid DTMF digit received. Data entered into the write-only Transmit Data Register will determine which tone pair is to be generated (see Table 1 for coding
0 0 1 1
0 1 0 1
0 1 0 1
1 0 1 0
Table 3. Internal Register Functions
EXPLANATION OF EVENTS A) TONE BURSTS DETECTED, TONE DURATION INVALID, RX DATA REGISTER NOT UPDATED. B) TONE #n DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. C) END OF TONE #n DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER RETAINED UNTIL NEXT VALID TONE PAIR. D) TONE #n+1 DETECTED, TONE DURATION VALID, TONE DECODED AND LATCHED IN RX DATA REGISTER. E) ACCEPTABLE DROPOUT OF TONE #n+1, TONE ABSENT DURATION INVALID, DATA REMAINS UNCHANGED. F) END OF TONE #n+1 DETECTED, TONE ABSENT DURATION VALID, INFORMATION IN RX DATA REGISTER RETAINED UNTIL NEXT VALID TONE PAIR. EXPLANATION OF SYMBOLS DTMF COMPOSITE INPUT SIGNAL. Vin ESt EARLY STEERING OUTPUT. INDICATES DETECTION OF VALID TONE FREQUENCIES. St/GT STEERING INPUT/GUARD TIME OUTPUT. DRIVES EXTERNAL RC TIMING CIRCUIT. RX 0-RX 3 4-BIT DECODED DATA IN RECEIVE DATA REGISTER 4-131
MT88L89
b3 RSEL b2 IRQ b1 CP/DTMF b0 TOUT
Table 4. CRA Bit Positions
b3 C/R
b2 S/D
b1 RxEN
b0 BURST ENABLE
Table 5. CRB Bit Positions
BIT b0
NAME TOUT
DESCRIPTION Tone Output Control. A logic high enables the tone output; a logic low puts the DTMF transmitter in power-down mode. The TONE output pin is held in high impedance and the transmit register is cleared. See Note 1 below. Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode; a logic low enables DTMF mode. In DTMF mode the device is capable of receiving and transmitting DTMF signals. In CP mode a rectangular wave representation of the received tone signal will be present on the IRQ/CP output pin if IRQ has been enabled (Control Register A, b2=1). In order to be detected, CP signals must be within the bandwidth specified in the AC Electrical Characteristics for Call Progress. Note: DTMF signals cannot be detected when CP mode is selected. Interrupt Enable. A logic high enables the interrupt function; a logic low de-activates the interrupt function. When IRQ is enabled and DTMF mode is selected (Control Register A, b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has been received for a valid guard time duration, or 2) the transmitter is ready for more data (burst mode only). Register Select. A logic high selects Control Register B for the next write cycle to the control register address. After writing to Control Register B, the following control register write cycle will be directed to Control Register A. Table 6. Control Register A Description
b1
CP/DTMF
b2
IRQ
b3
RSEL
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MT88L89
BIT b0 NAME BURST DESCRIPTION Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode. When activated, the digital code representing a DTMF signal (see Table 1) can be written to the transmit register, which will result in a transmit DTMF tone burst and pause of equal durations (typically 51 msec). Following the pause, the status register will be updated (b1 Transmit Data Register Empty), and an interrupt will occur if the interrupt mode has been enabled. When CP mode (Control Register A, b1) is enabled the normal tone burst and pause durations are extended from a typical duration of 51 msec to 102 msec. When BURST is high (de-activated) the transmit tone burst duration is determined by the TOUT bit (Control Register A, b0). b1 RxEN This bit enables the DTMF and Call Progress Tone receivers. A logic low enables both circuits. A logic high deactivates and puts both receiver circuits into power-down mode. See Note 1 below. Single or Dual Tone Generation. A logic high selects the single tone output; a logic low selects the dual tone (DTMF) output. The single tone generation function requires further selection of either the row or column tones (low or high group) through the C/R bit (Control Register B, b3). Column or Row Tone Select. A logic high selects a column tone output; a logic low selects a row tone output. This function is used in conjunction with the S/D bit (Control Register B, b2). Table 7. Control Register B Description
b2
S/D
b3
C/R
Note 1: When both TOUT and RxEN are asserted to power-down, the crystal oscillator and the Vref circuits are powered down.
BIT b0 b1
NAME IRQ TRANSMIT DATA REGISTER EMPTY (BURST MODE ONLY) RECEIVE DATA REGISTER FULL DELAYED STEERING
STATUS FLAG SET Interrupt has occurred. Bit one (b1) or bit two (b2) is set. Pause duration has terminated and transmitter is ready for new data. Valid data is in the Receive Data Register. Set upon the valid detection of the absence of a DTMF signal.
STATUS FLAG CLEARED Interrupt is inactive. Cleared after Status Register is read. Cleared after Status Register is read or when in non-burst mode. Cleared after Status Register is read. Cleared upon the detection of a valid DTMF signal.
b2 b3
Table 8. Status Register Description
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MT88L89
VDD MT88L89 C1 DTMF/CP INPUT R2 R1 IN+ INGS VRef VSS X-tal OSC1 OSC2 NC C4 DTMF OUTPUT C6 RLT NC TONE R/W/WR CS VDD St/GT ESt D3 D2 D1 D0 NC NC IRQ/CP DS/RD RS0 To P or C R6 C5 R7 C3
Notes: Example of External Component Values: R6 = 374 k 1% *Microprocessor based systems can inject undesirable noise into the supply rails. R7 = 3.3 k 10% The performance of the MT88L89 can be optimized by keeping RLT = 10 k (min.) 50 k (max.) noise on the supply rails to a minimum. The decoupling capacitor (C3) should be connected close to the device and ground loops should be avoided. C1 = 100 nF 5% C3 = 100 nF 10% C4 = 0.1 F (to remove the DC component) C5 = 100 nF 5% C6 = 10 nF 10% (to remove any high frequency components) X-tal = 3.579545 MHz
For Unity Gain: R1 = 100 k 1% R2 = 100 k 1% For +2dB Gain: R1 = 100 k 1% R2 = 127 k 1%
Figure 13 - Application Circuit (Single-Ended Input Configuration)
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MT88L89
C1 R1 C2 DTMF/CP INPUT R3 R2 VRef VSS X-tal OSC1 OSC2 NC C4 DTMF OUTPUT C6 RLT NC TONE R/W/WR CS R4 R5 IN+ INGS MT88L89 VDD St/GT ESt D3 D2 D1 D0 NC NC IRQ/CP DS/RD RS0 To P or C R6 C5 R7 VDD C3
Notes: Example of External Component Values: R1, R4 = 100 k 1% *Microprocessor based systems can inject undesirable noise into the supply rails. R2 = 60.4 k 1% The performance of the MT88L89 can be optimized by keeping R6 = 374 k 1% noise on the supply rails to a minimum. The decoupling capacitor (C3) should be R7 = 3.3 k 10% connected close to the device and ground loops should be avoided. RLT = 10 k (min.) 50 k (max.) C1 = 10 nF 5% C2 = 10 nF 5% C3 = 100 nF 10% C4 = 0.1 F (to remove the DC component) C5= 100 nF 5% C6 = 10 nF 10% (to remove any high frequency components) X-tal = 3.579545 MHz For Unity Gain: R3 = 37.4 k 1% R5 = 100 k 1% For +2dB Gain: R3 = 40.2 k 1% R5 = 127 k 1%
Figure 14 - Application Circuit (Differential Input Configuration)
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MT88L89
Figure 8 - Description of Timing Events
Scaling Information 10 dB/Div Start Frequency = 0 Hz Stop Frequency = 3400 Hz Marker Frequency = 697 Hz and 1209 Hz
Figure 9 - Spectrum Plot
MC68L11/ MC68B11 A8-A15 AS AD0-AD3 E RW 12 (a) Motorola MT88L89 CS D0-D3 ALE RS0 DS/RD R/W/WR P0 RD WR 12 (b) Intel RS0 DS/RD R/W/WR D0-D3 8xL5x MT88L89
A8-A15
CS
Figure 12 a) & b) - MT88L89 Interface Connections for Various Intel and Motorola Micros
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MT88L89
INITIALIZATION PROCEDURE A software reset must be included at the beginning of all programs to initialize the control registers after power up. Description: 1) 2) 3) 4) 5) 6) Read Status Register Write to Control Register Write to Control Register Write to Control Register Write to Control Register Read Status Register RS0 1 1 1 1 1 1 Motorola Intel R/W WR RD 1 1 0 0 0 1 0 0 1 0 0 1 0 0 1 1 1 0 Data b2 b1 X X 0 0 0 0 0 0 0 0 X X
b3 X 0 0 1 0 X
b0 X 0 0 0 0 X
TYPICAL CONTROL SEQUENCE FOR BURST MODE APPLICATIONS Transmit DTMF tones of 50 ms burst/50 ms pause and Receive DTMF Tones. Sequence: RS0 1) Write to Control Register A 1 (tone out, DTMF, IRQ, Select Control Register B) 2) Write to Control Register B 1 (burst mode) 3) Write to Transmit Data Register 0 (send a digit 7) 4) Wait for an Interrupt or Poll Status Register 5) Read the Status Register 1 R/W 0 0 0 WR RD 0 1 0 0 1 1 b3 1 0 0 b2 1 0 1 b1 0 0 1 b0 1 0 1
1
1
0
X
X
X
X
-if bit 1 is set, the Tx is ready for the next tone, in which case... Write to Transmit Register 0 0 0 (send a digit 5) -if bit 2 is set, a DTMF tone has been received, in which case.... Read the Receive Data Register 0 1 1 -if both bits are set... Read the Receive Data Register Write to Transmit Data Register
1
0
1
0
1
0
X
X
X
X
0 0
1 0
1 0
0 1
X 0
X 1
X 0
X 1
NOTE: IN THE TX BURST MODE, STATUS REGISTER BIT 1 WILL NOT BE SET UNTIL 100 ms (2 ms) AFTER THE DATA IS WRITTEN TO THE TX DATA REGISTER. IN EXTENDED BURST MODE THIS TIME WILL BE DOUBLED TO 200 ms ( 4 ms)
Figure 15 - Application Notes
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MT88L89
Absolute Maximum Ratings*
Parameter 1 2 3 4 5 Power supply voltage VDD-VSS Voltage on any pin Current at any pin (Except VDD Storage temperature Package power dissipation
and VSS)
Symbol VDD -VSS VI TST PD
Min VSS-0.3 -65
Max 5.5 VDD+0.3 10 +150 1000
Units V V mA C mW
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter 1 2 3
Sym VDD TO
Min 2.7 -40
Typ 3
Max 3.6 +85
Units V C
Test Conditions
Positive power supply Operating temperature
Crystal clock frequency fCLK 3.575965 3.579545 3.583124 MHz Typical figures are at 25 C and for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - VSS=0 V.
Characteristics 1 Standby supply current Sym IDDQ Min Typ 2.0 3.0 Max 15.0 15.0 Units A Test Conditions Vdd = 2.7V Vdd = 3.6V TOUT and RxEN bits asserted to power-down mode Transmitter supply current IDDTX 2.0 7.0 mA Transmitter fully enabled and RxEN bit asserted to power-down mode Receiver fully enabled and TOUT bit asserted to power-down mode Device fully enabled
2
S U P P L Y
3
Receiver supply current
IDDRX
3.0
5.0
mA
4 5 6 7
I N P U T S
Operating supply current High level input voltage (OSC1) Low level input voltage (OSC1) Steering threshold voltage
IDD VIHO VILO VTSt 0.43 VDD 0.7 VDD
3.1
7.0
mA V
0.3 VDD 0.46 0.51 VDD VDD
V V VDD = 3V
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MT88L89
DC Electrical Characteristics (continued) - VSS=0 V.
Characteristics 8 9 10 11 12 13 14 15 16 17 18 19 20 21
D i g i t a l Data Bus ESt and St/GT O U T P U T S
Sym VOLO
Min
Typ
Max 0.1 VDD
Units V V
Test Conditions No load No load
Low level output voltage (OSC2) High level output voltage (OSC2) Output leakage current (IRQ) (Tone) VRef output voltage VRef output resistance Low level input voltage High level input voltage Input leakage current Output high impedance Source current Sink current Source current Sink current
0.9 VDD VOHO 1 IOZT VRef ROR VIL VIH IIZ IOZD IOHD IOLD IOHE IOLE 1.0 1.5 0.5 1.5 3.8 4.0 2.8 4 0.7 VDD 10 10 0.47 VDD 0.53 VDD 2.5 0.3 VDD 10
A V k V V A A mA mA mA mA VIN=VSS to VDD VIN=VSS to VDD VOH=0.9VDD VOL=0.1VDD VOH=0.9VDD VOL=0.1VDD No load Note 9
IRQ/ Sink current IOLI 0.7 9 mA VOL=0.1VDD CP Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25 C, VDD =5V and for design aid only: not guaranteed and not subject to production testing. * See "Notes" following AC Electrical Characteristics Tables.
Electrical Characteristics Gain Setting Amplifier - Voltages are with respect to ground (VSS) unless otherwise stated, VSS= 0V, VDD=3V, TO=25C.
Characteristics 1 2 3 4 5 Input leakage current Input resistance Input offset voltage Power supply rejection Common mode rejection Sym IIN RIN VOS PSRR CMRR 50 40 10 25 Min Typ Max 100 Units nA M mV dB dB Test Conditions VSS VIN VDD Note 9 Note 9 Note 9 1 kHz, See Note 9 VSS + 0.75V VIN VDD 0.75V biased at VREF = 1.5V Note 9 Note 9 Note 9 RLGS 100 k to VSS at GS, 3KHz Note 9 Note 9 Note 9
6 7 8
DC open loop voltage gain Unity gain bandwidth Output voltage swing
AVOL fc VO
32 0.3 2.2
dB MHz Vpp
9 10
Allowable capacitive load (GS) Allowable resistive load (GS)
CLGS RLGS 50
100
pF k
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MT88L89
Electrical Characteristics Gain Setting Amplifier - Voltages are with respect to ground (VSS) unless otherwise stated, VSS= 0V, VDD=3V, TO=25C.
Characteristics 11 Common mode range Sym VCM Min Typ 1.5 Max Units Vpp Test Conditions VDD = 3V, No Load Note 9
Typical figures are at 25C and for design aid only: not guaranteed and not subject to production testing.
MT88L89 AC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 R X Valid input signal levels (each tone of composite signal) Positive twist accept Negative twist accept Freq. deviation accept R X Freq. deviation reject Third tone tolerance Noise tolerance Dial tone tolerance 22 1.5% 2Hz 3.5% -16 -12 dB dB dB Sym Min -29 27.5 Typ Max -4 489 8 8 Units dBm mVRMS dB dB Notes* 1,2,3,5,6,13 1,2,3,5,6 2,3,6,9 2,3,6,9 2,3,5 2,3,5 2,3,4,5,9,10 2,3,4,5,7,9,10 2,3,4,5,8,9
2 3 4 5 6 7 8
Characteristics are over recommended operating conditions unless otherwise stated. Typical figures are at 25C, VDD = 3V, and for design aid only: not guaranteed and not subject to production testing. * *See "Notes" following AC Electrical Characteristics Tables.
AC Electrical Characteristics- Call Progress - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics 1 2 3 4 Accept Bandwidth Lower freq. (REJECT) Upper freq. (REJECT) Call progress tone detect level (total power) Sym fA fLR fHR 540 -30 Min 320 Typ Max 500 290 Units Hz Hz Hz dBm Conditions @ -25 dBm Note 9 @ -25 dBm Note 9 @ -25 dBm Note 9
Characteristics are over recommended operating conditions unless otherwise stated Typical figures are at 25C, VDD=3V, and for design aid only: not guaranteed and not subject to production testing
AC Electrical Characteristics - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics 1 2 3 4
T O N E I N
Sym tDP tDA tPStb3 tPStRX
Min 5 0.5
Typ 11 4
Max 14 8.5 20 11
Units ms ms s s
Conditions Note 11 Note 11 Figure 7, Note 9 Figure 7, Note 9
Tone present detect time Tone absent detect time Delay St to b3 Delay St to RX0-RX3
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MT88L89
AC Electrical Characteristics (continued) - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
X T A L T O N E O U T
Sym tBST tPS tBSTE tPSE VHOUT VLOUT dBP THD fD RLT fC tCLRF DCCL CLO tOST
Min 50 50 100 100 -17.3 -19.3
Typ
Max 52 52 104 104 -13.3 -15.3
Units ms ms ms ms dBm dBm dB dB % k MHz ns % pF ms
Conditions DTMF mode DTMF mode Call Progress mode Call Progress mode RLT=10k RLT=10k RLT=10k 25 kHz Bandwidth RLT=10k, Note 9 fC=3.579545 MHz Note 9 Note 9 Ext. clock, Note 9 Ext. clock, Note 9 Note 9
Tone burst duration Tone pause duration Tone burst duration (extended) Tone pause duration (extended) High group output level Low group output level Pre-emphasis Output distortion (Single Tone) Frequency deviation Output load resistance Crystal/clock frequency Clock input rise and fall time Clock input duty cycle OSC2 load capacitance Oscillator start-up time
2
3 -35
0.7 10
1.5 50 110
3.5759 3.5795 3.5831 40 50 60 30 10
Timing is over recommended temperature & power supply voltages. Typical figures are at 25C and for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics- MPU Interface - Voltages are with respect to ground (VSS), unless otherwise stated.
Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RD/WR low pulse width DS high pulse width Rise and fall time all digital inputs R/W setup time R/W hold time Address setup time (RS0) Address hold time (RS0) Data hold time (read) DS/RD to valid data delay (read) Data setup time (write) Data hold time (write) Chip select setup time Chip select hold time DS/RD set up time prior to CS assertion Sym tCL tCH tR,tF tRWS tRWH tAS tAH tDHR tDDR tDSW tDHW tCSS tCSH tRDS,tDSS 60 10 45 10 20 23 26 0 45 22 125 Min 200 200 Typ 400 400 20 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions Figure 16, Note 12 tCL + tCH 1000ns Figure 16, Note 12 tCL + tCH 1000ns Figure 16 Figures 17 Figures 17 Figures 17 - 19 Figures 17 - 19 Figures 17 - 18 Figures 17 - 18 Figures 17, 19 Figures 17, 19 Figures 17 - 19 Figures 17 - 19 Figures 17, 19
Characteristics are over recommended operating conditions unless otherwise stated Typical figures are at 25C, VDD=3V, and for design aid only: not guaranteed and not subject to production testing NOTES: 1) dBm=decibels above or below a reference power of 1 mW into a 600 ohm load
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MT88L89
2) Digit sequence consists of all 16 DTMF tones 3) Tone duration=40 ms. Tone pause=40 ms 4) Nominal DTMF frequencies are used 5) Both tones in the composite signal have an equal amplitude 6) The tone pair is deviated by 1.5%2 Hz 7) Bandwidth limited (3 kHz) Gaussian noise 8) The precise dial tone frequencies are 350 and 440 Hz (2%) 9) Guaranteed by design and characterization. Not subject to production testing 10) Referenced to the lowest amplitude tone in the DTMF signal 11) For guard time calculation purposes 12) Operation of microprocessor interface requires that t CL + tCH 1000ns 13) For Unity Gain Configuration
tR
tF
VHM
All Digital Inputs
VLM
*V HM = 0.7VDD, VLM = 0.3VDD
Figure 16 - Digital Signal Input Rise/Fall Times
tCL tRWS tCH
DS (E)
tDSS
tRWH
R/W
tAS
Read AD3-AD0 (RS0, D0-D3) Write AD3-AD0 (RS0-D0-D3) Addr
tDDR
tDHR
Data
Addr
Data
tDSW tAH tCSH
High Byte of Addr
tDHW
Addr * non-mux
AS *
CS = AS.Addr
tCSS
* microprocessor pins
Figure 17 - Motorola BUS Timing Diagram
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MT88L89
tCSS
ALE*
tRDS
RD
tCH tCL
WR
tAS
tAH
A0-A7
tDDR
Data
tDHR
P0* (RS0, D0-D3) P2 * (Addr)
A8-A15 Address
tCSH
CS = ALE.Addr * microprocessor pins
Figure 18 - Intel Read Timing Diagram
ALE*
RD** WR
tCSS tCL tCH tAS tAH
A0-A7
tDSW tDHW
Data
P0* (RS0, D0-D3) P2 * (Addr)
A8-A15 Address
tCSH
CS = ALE.Addr
* microprocessor pins ** RD must be high on the falling edge of CS for Intel Bus Timing
Figure 19 - Intel Write Timing Diagram
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