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M48T254V
3.3V, 16 Mbit (2 Mb x 8 bit) TIMEKEEPER(R) SRAM WITH PHANTOM CLOCK
FEATURES SUMMARY s 3.3V 10%
s
Figure 1. 168-ball PBGA Module
INTEGRATED ULTRA LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, BATTERY AND CRYSTAL REAL TIME CLOCK KEEPS TRACK OF TENTHS/HUNDREDTHS OF SECONDS, SECONDS, MINUTES, HOURS, DAYS, DATE, MONTHS, and YEARS. CLOCK FUNCTION IS TRANSPARENT TO RAM OPERATION. PRECISION POWER MONITORING and POWER SWITCHING CIRCUITRY AUTOMATIC WRITE-PROTECTION WHEN VCC IS OUT-OF-TOLERANCE POWER-FAIL DESELECT VOLTAGE: - VCC = 3.3V 10%; 2.8V VPFD 2.97V BATTERY LOW (BL) 10 YEARS of DATA RETENTION and CLOCK OPERATION IN THE ABSENCE OF POWER SNAPHAT HOUSING (BATTERY/CRYSTAL) IS REPLACEABLE 100ns ACCESS (READ = WRITE)
SNAPHAT (SH) Crystal/Battery 168-ball PBGA Module (ZA)
s
s
s
s
s
Figure 2. SNAPHAT Crystal/Battery
s s
s
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May 2003
Rev. 2.0
M48T254V
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M48T254V
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 3. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 4. PBGA Connections (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 5. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 6. M48T254V PBGA Module Solution (Side/Top) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 7. AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 8. Memory READ Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 9. Memory WRITE Cycle, WRITE Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 10. Memory WRITE Cycle, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 11. Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 8. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PHANTOM CLOCK OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 12. Comparison Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Clock Register Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 AM-PM/12/24 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Oscillator Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Zero Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 9. RTC Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 13. Phantom Clock READ Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 14. Phantom Clock WRITE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Battery Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 11. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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M48T254V
SUMMARY DESCRIPTION The M48T254V TIMEKEEPER(R) RAM is a 2Mbit x 8 non-volatile static RAM and real time clock organized as 2,097,152 words by 8 bits. The special BGA package provides a fully integrated battery back-up memory and real time clock solution. In the event of power instability or absence, a selfcontained battery maintains the timekeeping operation and provides power for a CMOS static RAM. Control circuitry monitors VCC and invokes write protection to prevent data corruption in the memory and RTC.
The clock keeps track of tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. The last day of the month is automatically adjusted for months with less than 31 days, including leap year correction. The clock operates in one of two formats: - a 12-hour mode with an AM/PM indicator; or - a 24-hour mode The M48T254V is a 168-ball PBGA module that integrates the RTC, the battery, and SRAM in one package.
Figure 3. Logic Diagram
VCC
Table 1. Signal Names
A0 - A20 DQ0 - DQ7 CE Address Inputs Data Input/Output Chip Enable WRITE Enable Inputs Output Enable Battery Low Output (Open Drain) No Connect Supply Voltage Ground
A0 - A20
WE
CE M48T254V WE OE
DQ0 - DQ7 BL
OE BL NC VCC
VSS
AI04217
VSS
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M48T254V
Figure 4. PBGA Connections (Top View)
41 40 39 38 33 32 31 A16 37 36 35 34 30 VCC VCC A17 A18
A11
A8
A13
VCC
A10
GND
A12
1 2 3 4 5 6 7 8 9
VCC A7 A6 A5 GND A4 A3 A2 A1
A14
A15
A9
29 28 27 26 25 24 23 22 21
M48T254V
A19 GND A20 CE OE WE
DQ3
GND
DQ2
DQ5
DQ1
DQ4
DQ0
DQ6
DQ7 19
A0
11
14
16
17
10
13
18
12
15
20
BL
AI04216
Note: This diagram is TOP VIEW perspective (view through package).
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M48T254V
Figure 5. Hardware Hookup
DQ0-DQ7
3.3V
M40Z300W 19 VCC VOUT
19
8
A0-A18 VCC .1F M68Z512W E G W 8
VOUT E
VCC M68Z512W E 3.3V G W
3.3V
M41T315V VCC D Q
THS VSS DQ0
RST BL
(Not Bonded) To Battery Monitor Circuitry
DQ0-DQ7
CE OE WE
CEI OE WE VCC CEO E1CON E A19 A20 A B THS VSS E2CON E3CON E4CON RST BL E VOUT 3.3V M40Z300W 19
19
8
VCC M68Z512W G W .1F
VCC M68Z512W E G W WE OE
8
AI04215
DQ0-DQ7
A0-A18
A0-A18
DQ0-DQ7 WE OE
A0-A18
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M48T254V
Figure 6. M48T254V PBGA Module Solution (Side/Top)
AI04214b
MAXIMUM RATING Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 2. Absolute Maximum Ratings
Symbol TA TSTG TSLD VCC VIO IO PD Operating Temperature Storage Temperature (VCC, Oscillator Off) Lead Solder Temperature for 10 seconds Parameter
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Value 0 to 70 -40 to 85 260 -0.3 to +4.6 -0.3 to VCC + 0.3 20 1
Unit C C C V V mA W
Supply Voltage (on any pin relative to Ground) Input or Output Voltages Output Current Power Dissipation
CAUTION! Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up Mode.
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M48T254V
DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the MeasureTable 3. DC and AC Measurement Conditions
Parameter VCC Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defined as the point where data is no longer driven.
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
M41T254V 3.0 to 3.6V 0 to 70C 50pF 5ns 0 to 3V 1.5V
Figure 7. AC Testing Load Circuit
645
DEVICE UNDER TEST
CL = 50 pF
1.75V
AI04644
Table 4. Capacitance
Symbol CIN COUT CIO(3) Parameter(1,2) Input Capacitance (A0-A18, OE, WE, CE) Input Capacitance (A19-A20) Output Capacitance (BL) Input / Output Capacitance Min Max 40 10 20 40 Unit pF pF pF pF
Note: 1. Effective capacitance measured with power supply at 3V. Sampled only; not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs were deselected.
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M48T254V
Table 5. DC Characteristics
Sym ILI ILO ICC1 ICC2 ICC3 VIL(2) VIH(2) VOL(3) VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (TTL Standby) VCC Power Supply Current Input Low Voltage Input High Voltage Output Low Voltage (Open Drain) Output Low Voltage Output High Voltage IOL = 10mA IOL = 2.0mA IOH = -1.0mA 2.4 2.80 2.5 2.97 CE = VIH CE = VCCI - 0.2 -0.3 2.2 5 2 Test Condition(1) 0V VIN VCC 0V VOUT VCC M48T254V Unit Min Typ Max 4 4 50 7 3 0.6 VCC + 0.3 0.4 0.4 A A mA mA mA V V V V V V V
VPFD(2) Power Fail Deselect VSO(2) Battery Back-up Switchover
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 3.0 to 3.6V (except where noted). 2. All voltages are referenced to Ground. 3. For BL pin (Open Drain).
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M48T254V
OPERATION MODES READ A READ cycle executes whenever WRITE Enable (WE) is high and Chip Enable (CE) is low (see Figure 8, page 10). The distinct address defined by the 21 address inputs (A0-A20) specifies which of the 2M bytes of data is to be accessed. Valid data will be accessed by the eight data output drivers within the specified Access Time (tACC) after the last address input signal is stable, the CE and OE access times, and their respective parameters are satisfied. When CE tACC and OE tACC are not satisfied, then data access times must be measured from the more recent CE and OE signals, with the limiting parameter being tCO (for CE) or tOE (for OE) instead of address access. Table 6. Operating Modes
Mode Deselect WRITE 3.0V to 3.6V READ READ Deselect Deselect VSO to VPFD (min)(1) VSO(1) VIL VIL X X VIL VIH X X VIH VIH X X DOUT High-Z High-Z High-Z Active Active CMOS Standby Battery Back-Up VCC CE VIH VIL OE X X WE X VIL DQ7-DQ0 High-Z DIN Power Standby Active
WRITE WRITE Mode occurs whenever CE and WE signals are low (after address inputs are stable, see Figure 9, page 10 and Figure 10, page 11). The most recent falling edge of CE and WE will determine when the WRITE cycle begins (the earlier, rising edge of CE or WE determines cycle termination). All address inputs must be kept stable throughout the WRITE cycle. WE must be high (inactive) for a minimum recovery time (tWR) before a subsequent cycle is initiated. The OE control signal should be kept high (inactive) during the WRITE cycles to avoid bus contention. If CE and OE are low (active), WE will disable the outputs for Output Data WRITE Time (tODW) from its falling edge.
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage 1. See Table 8, page 13 for details.
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M48T254V
Figure 8. Memory READ Cycle
tRC ADDRESSES tACC tCO CE tOD tOE OE tOH
tCOE
tCOE DQ0 - DQ7
DATA OUTPUT VALID
tODO
AI04230
Note: WE is high for a READ cycle.
Figure 9. Memory WRITE Cycle, WRITE Enable Controlled
tWC ADDRESSES tAW
CE tAH1 tWP WE tOEW tODW
HIGH IMPEDANCE
DQ0-DQ7
tDS
DATA IN STABLE
tDH1
AI05655
Note: 1. OE = VIH or VIL. If OE = VIH during a WRITE cycle, the output buffers remain in a high impedance state. 2. If the CE low transition occurs simultaneously with or later than the WE low transition in WE Controlled WRITE, the output buffers remain in a high impedance state during this period. 3. If the CE high transition occurs simultaneously with the WE high transition, the output buffers remain in a high impedance state during this period.
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M48T254V
Figure 10. Memory WRITE Cycle, Chip Enable Controlled
tWC ADDRESSES tAW tWP CE tOEW tAH2
WE tODW tCOE
DQ0-DQ7
tDS
tDH2
DATA IN STABLE
AI05656
Note: 1. OE = VIH or VIL. If OE = VIH during a WRITE cycle, the output buffers remain in a high impedance state. 2. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period.
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M48T254V
Table 7. AC Electrical Characteristics
Symbol tAVAV tAVQV tELQV tGLQV tELQX tAXQX tEHQZ tGHQZ tWLQZ tAVAV tWLWH tELEH tAVEL tWHAX tEHAX tWHQX tDVEH tDVWH tWHDX tEHDX tRC tACC tCO tOE tCOE(2) tOH tOD(2) tODO(2) tODW(2) tWC tWP(3) tAW tAH1 tAH2 tOEW(2) tDS tDH1 tDH2 tRR tWR(4) READ Cycle Time Access Time Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable or Output Enable Low to Output Transition Output Hold from Address Change Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Output Hi-Z from WE WRITE Cycle Time WE, CE Pulse Width Address Setup Time Address Hold Time from WE Address Hold Time from CE Output Active from WE Data Setup Time Data Hold Time from WE Data Hold Time from CE READ Recovery (Clock Access Only) WRITE Recovery (Clock Access Only) 100 70 0 5 25 5 40 0 20 20 20 5 5 35 35 35 Parameter(1) M48T254V Unit Min 100 100 100 55 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 3.0 to 3.6V (except where noted). 2. These parameters are sampled with a 5 pF load are not 100% tested. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tWR is a function of the latter occurring edge of WE or CE.
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M48T254V
Data Retention Mode Data can be read or written only when VCC is greater than VPFD. When VCC is below VPFD (the point at which write protection occurs), the clock registers and the SRAM are blocked from any access. When VCC falls below the Battery Switch Over threshold (VSO), the device is switched from VCC to battery backup (VBAT). RTC operation and SRAM data are maintained via battery backup until power is stable. All control, data, and address signals must be powered down when VCC is powered down. Figure 11. Power Down/Up Mode AC Waveforms
VCC tF VPFD (max) tR
The lithium power source is designed to provide power for RTC activity as well as RTC and RAM data retention when VCC is absent or unstable. The capability of this source is sufficient to power the device continuously for the life of the equipment into which it has been installed. For specification purposes, life expectancy is ten (10) years at 25C with the internal oscillator running without VCC. The actual life expectancy will be much longer if no battery energy is used (e.g., when VCC is present).
VPFD (min)
VSO
tFB
tPD
tREC
CE
DON'T CARE tDR
AI05657
Table 8. Power Down/Up Trip Points DC Characteristics
Symbol tREC tF tFB tR tPD tDR(2) Parameter(1) VPFD (max) to CE low VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSO VCC Fall Time VPFD (min) to VPFD (max) VCC Rise Time CE High to Power-Fail Expected Data Retention Time Min 40 300 10 0 0 10 Max 120 Unit ms
s s s s
Years
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VCC = 3.0 to 3.6V (except where noted). 2. At 25C, VCC = 0V; the expected tDR is defined as cumulative time in the absence of VCC with the clock oscillator running. (Requires use of three M4T32-BR12SH SNAPHAT (R) tops.)
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M48T254V
PHANTOM CLOCK OPERATION Communication with the Phantom Clock is established by pattern recognition of a serial bit-stream of 64 bits which must be matched by executing 64 consecutive WRITE cycles containing the proper data on DQ0. All accesses which occur prior to recognition of the 64-bit pattern are directed to memory. After recognition is established, the next 64 READ or WRITE cycles either extract or update data in the clock while disabling the memory. Data transfer to and from the timekeeping function is accomplished with a serial bit-stream under control of Chip Enable (CE), Output Enable (OE), and WRITE Enable (WE). Initially, a READ cycle using the CE and OE control of the clock starts the pattern recognition sequence by moving the pointer to the first bit of the 64-bit comparison register (see Figure 12, page 15). Next, 64 consecutive WRITE cycles are executed using the CE and WE control of the device. These 64 WRITE cycles are used only to gain access to the clock. Therefore, any address to the memory is acceptable. However, the WRITE cycles generated to gain access to the Phantom Clock are also writing data to a location in the mated RAM. The preferred way to manage this requirement is to set
aside just one address location in RAM as a Phantom Clock scratch pad. When the first WRITE cycle is executed, it is compared to Bit 1 of the 64-bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next WRITE cycle. If a match is not found, the pointer does not advance and all subsequent WRITE cycles are ignored. If a READ cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64 WRITE cycles as described above until all of the bits in the comparison register have been matched. With a correct match for 64-bits, the Phantom Clock is enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the Phantom Clock to either receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CE cycles without interrupting the pattern recognition sequence or data transfer sequence to the Phantom Clock.
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M48T254V
Figure 12. Comparison Register Definition
Hex Value C5
7 BYTE 0 1
6 1
5 0
4 0
3 0
2 1
1 0
0 1
BYTE 1
0
0
1
1
1
0
1
0
3A
BYTE 2
1
0
1
0
0
0
1
1
A3
BYTE 3
0
1
0
1
1
1
0
0
5C
BYTE 4
1
1
0
0
0
1
0
1
C5
BYTE 5
0
0
1
1
1
0
1
0
3A
BYTE 6
1
0
1
0
0
0
1
1
A3
BYTE 7
0
1
0
1
1
1
0
0
5C
AI04262
Note: The odds of this pattern being accidentally duplicated and sending aberrant entries to the RTC is less than 1 in 1019. This pattern is sent to the clock LSB to MSB.
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M48T254V
Clock Register Information Clock information is contained in eight registers of 8 bits, each of which is sequentially accessed one (1) bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the clock registers, each must be handled in groups of 8 bits. Writing and reading individual bits within a register could produce erroneous results. These READ/WRITE registers are defined in the clock register map (see Table 9). Data contained in the clock registers is in Binary Coded Decimal format (BCD). Reading and writing the registers is always accomplished by stepping through all eight registers, starting with Bit 0 of Register 0 and ending with Bit 7 of Register 7. AM-PM/12/24 Mode Bit 7 of the hours register is defined as the 12-hour or 24-hour mode select bit. When it is high, the 12hour mode is selected. In the 12-hour mode, Bit 5 is the AM/PM bit with the logic high being "PM." In the 24-hour mode, Bit 5 is the second 10-hour bit (20-23 hours). Oscillator Bit Bit 5 controls the oscillator. When set to logic '0,' the oscillator turns on and the RTC/calendar begins to increment. Zero Bits Registers 1, 2, 3, 4, 5, and 6 contain one (1) or more bits that will always read logic '0.' When writing to these locations, either a logic '1' or '0' is acceptable.
Table 9. RTC Register Map
Register 0 1 2 3 4 5 6 7
Keys: A/P = AM/PM Bit 12/24 = 12 or 24-hour mode Bit OSC = Oscillator Bit RST = Reset Bit 0 = Must be set to '0' 1 = Must be set to '1'
D7
D6
D5
D4
D3
D2
D1
D0
Function/Range BCD Format Seconds Seconds Minutes Hours Day Date Month Year 00-99 00-59 00-59 01-12/ 00-23 01-7 01-31 01-12 00-99
0.1 Seconds 0 0 12/24 0 0 0 0 0 0 0 10 Years 0 10 Seconds 10 Minutes 10/ A/P OSC 10 date 10M Hrs 1 0
0.01 Seconds Seconds Minutes Hours (24 Hour Format) Day of the Week Date: Day of the Month Month Year
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M48T254V
Figure 13. Phantom Clock READ Cycle
WE tRC tCW tCO CE tOW tOD tRR
OE tOE tOEE tCOE Q DATA OUTPUT VALID
AI04259
tODO
Figure 14. Phantom Clock WRITE Cycle
OE tWC tWP tWR
WE tCW CE tDH2 tDS D DATA INPUT STABLE
AI05658
tAH2
tDH1
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M48T254V
Battery Low The M48T254V automatically performs battery voltage monitoring upon power-up, and at factoryprogrammed time intervals of at least 24 hours. The Battery Low (BL) signal will be asserted if the battery voltage is found to be less than approximately 2.5V. The BL signal will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that one of the batteries is below 2.5V and may not be able to maintain data integrity in the SRAM. Data should be considered suspect, and verified as correct. All three SNAPHAT(R) tops should be replaced. If a battery low indication is generated during the 24-hour interval check, this indicates that one of the batteries is near end of life. However, data is
not compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during subsequent periods of battery back-up mode, the batteries should be replaced. The SNAPHAT top should be replaced with valid VCC applied to the device. The M48T254V only monitors the batteries when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique. The BL signal is an open drain output and an appropriate pull-up resistor should be chosen to control the rise time. Note: The BL signal is available only for the external SRAM, not for the Real-Time Clock.
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PART NUMBERING Table 10. Ordering Information Scheme
Example: M48T 254V -10 ZA 1
Device Type M48T
Supply Voltage and Write Protect Voltage 254V = VCC = 3.0 to 3.6V; VPFD = 2.8 to 2.97V
Speed -10 = 100ns
Package(1) ZA = 42.5mm x 42.5mm(2), 1.27mm Ball Pitch, BGA Module
Temperature Range 1 = 0 to 70C
Note: 1. The SOIC packages (SO28/SO44) require the battery/crystal package (SNAPHAT) which is ordered separately under the part number "M4T32-BR12SH" in plastic tube or "M4T32-BR12SHTR" in Tape and Reel form. 2. Where "Z" is the symbol for BGA packages and "A" denotes 1.27mm ball pitch
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. Table 11. SNAPHAT Battery Table
Part Number M4T32-BR12SH Description Lithium Battery (120mAh) SNAPHAT Package SH
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PACKAGE MECHANICAL INFORMATION Figure 15. PBGA-ZA - 168-ball Plastic Ball Grid Array Package Outline
A D GD JE A3 A A1 A2 E B1 B
SIDE VIEW (SH x 1) B HE HD TOP VIEW
45
GE
FE
PIN 1 CORNER
ddd C
SIDE VIEW (SH x 2)
E E1 e
DETAIL A
eee S C A S B S fff S C b
e
SOLDER BALL (Typ)
b
Detail A
e D1 FD
0.20 (4X)
D BOTTOM VIEW
Note: Drawing is not to scale.
PBGA-Z02
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Table 12. PBGA-ZA - 168-ball Plastic Ball Grid Array Package Mechanical Data
mm Symb Typ A A1 A2 A3 B B1 b D D1 E E1 e FD FE GD GE HD HE JE n 0.76 42.50 27.94 42.50 22.86 1.27 7.28 9.82 1.75 1.50 1.98 0.51 1.50 7.18 9.72 1.55 1.30 1.78 0.31 1.30 168 Tolerance ddd eee fff 0.15 0.30 0.15 7.38 9.92 1.95 1.70 2.18 0.71 1.70 42.30 42.70 38.54 2.94 0.89 11.53 Min 2.74 0.69 11.18 7.24 38.34 21.21 0.71 42.30 Max 3.14 1.09 11.88 8.00 38.74 21.84 0.81 42.70 0.030 1.673 1.100 1.673 0.900 0.050 0.287 0.387 0.069 0.059 0.078 0.020 0.059 0.283 0.383 0.061 0.051 0.070 0.012 0.051 168 Tolerance 0.006 0.012 0.006 0.291 0.391 0.077 0.067 0.086 0.028 0.067 1.665 1.681 1.517 Typ 0.116 0.035 0.454 Min 0.108 0.027 0.440 0.285 1.509 0.835 0.028 1.665 Max 0.124 0.043 0.468 0.315 1.525 0.860 0.032 1.681 inches
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M48T254V
Figure 16. SH - 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note: Drawing is not to scale.
Table 13. SH - 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mechanical Data
mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ Min Max 0.415 .0335 0.315 0.015 0.022 0.860 .0710 0.628 0.142 0.090 inches
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REVISION HISTORY Table 14. Document Revision History
Date September 2002 31-Mar-03 19-May-03 Rev. # 1.0 1.1 2.0 First Issue Updated test condition (Table 8) v2.2 template update; modify package dimensions (Table 12) Revision Details
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com
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