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RELEASED REFERENCE DESIGN PMC-970438 ISSUE 1
PMC-Sierra,Inc.
APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
APPS MULTI-PHY ADAPTER
SCI-PHY TO MULTI-PHY ADAPTER CARD
REFERENCE DESIGN
RELEASED ISSUE 1: FEBRUARY 1998
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
RELEASED REFERENCE DESIGN PMC-970438 ISSUE 1
PMC-Sierra,Inc.
APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
RELEASED REFERENCE DESIGN PMC-970438 ISSUE 1
PMC-Sierra,Inc.
APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
CONTENTS 1 2 3 4 5 6 7 8 FEATURES .............................................................................................. 1 APPLICATIONS ....................................................................................... 2 REFERENCES......................................................................................... 3 APPLICATION EXAMPLES ..................................................................... 4 BLOCK DIAGRAM ................................................................................... 5 DESCRIPTION......................................................................................... 6 CONNECTOR DESCRIPTIONS .............................................................. 7 IMPLEMENTATION ................................................................................ 30 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9 10 11 ROOT DRAWING, SHEET 1 ....................................................... 30 SCIPHY_X, SHEET 2.................................................................. 30 SCIPHY_Y, SHEET 3 .................................................................. 30 SWAN, SHEET 4......................................................................... 31 MICRO_MUX, SHEET 5.............................................................. 31 MULTIPHY _X, SHEET 6 ............................................................ 33 MULTIPHY_Y, SHEET 7 .............................................................. 33
SCHEMATICS ........................................................................................ 35 MATERIAL LIST ..................................................................................... 37 LAYOUT ................................................................................................. 39
I
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RELEASED REFERENCE DESIGN PMC-970438 ISSUE 1
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APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
LIST OF FIGURES FIGURE 1 MULTI-PHY ADAPTER CARD CONNECTING TWO SCI-PHY EVMBS AND A SWAN BOARD TO OCTAL-PLUS REFERENCE DESIGN. ................................................................... 4 FIGURE 2 MICRO INTERFACE SELECTION JUMPER POSITIONS............. 32
II
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RELEASED REFERENCE DESIGN PMC-970438 ISSUE 1
PMC-Sierra,Inc.
APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 TABLE 6 TABLE 7 TABLE 8 TABLE 9 MULTI-PHY ADAPTER CARD CONNECTORS ............................... 7 SCI-PHY #1 AND SCI-PHY #2 MICRO INTERFACE CONNECTOR .................................................................................. 8 SCI-PHY #1 MULTI-PHY INTERFACE CONNECTOR ................... 10 SCI-PHY #2 MULTI-PHY INTERFACE........................................... 14 SWAN CONNECTOR .................................................................... 17 MULTI-PHY-X INTERFACE............................................................ 19 MULTI-PHY-Y INTERFACE CONNECTOR .................................... 24 MICRO INTERFACE SELECTION JUMPER POSITIONS ............ 32 BILL OF MATERIAL ....................................................................... 37
III
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APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
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IV
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RELEASED REFERENCE DESIGN PMC-970438 ISSUE 1
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APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
1
FEATURES * * Flexibility to select between ordinary microprocessor control or enhanced with system reference clock features. Direct SCI-PHY to multi-PHY connection.
1
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APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
2
APPLICATIONS * Interconnect 2 SCI-PHY EVMB with dual multi-PHY ATM daughter board.
2
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APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
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REFERENCES 1. PMC-Sierra Inc., Octal S/UNI-PLUS with Automatic Protection Switching Optical Reference Design, Issue 2, February 1998 2. PMC-Sierra Inc., Saturn Compliant Interface for ATM Physical Layer Interconnect Evaluation Motherboard (SCI-PHY EVMB) Specification, Issue 3 June 1995 3. PMC-Sierra Inc., SWAN Timing and Micro Reference Design, Preliminary Issue 1, March 1997
3
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APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
4
APPLICATION EXAMPLES Figure 1 Multi-PHY adapter card connecting two SCI-PHY EVMBs and a SWAN board to Octal-PLUS Reference design.
Optical I/F #1
SCI-PHY EVMB #1 PM1502
SCI-PHY Micro I/F Multi-PHY-X Tx/Rx Cell I/F SWAN Micro Interface SCI-PHY Micro I/F Multi-PHY-Y Tx/Rx Cell I/F Multi-PHY-X & Micro I/F
155Mbit/sec SONET/SDH I/F
SWAN
SCI-PHY to Multi-PHY Adaptor Card
Multi-PHY-Y & Micro I/F
PM5947 Octal-PLUS
SCI-PHY EVMB #2 PM1502
155Mbit/sec SONET/SDH I/F
Optical I/F #8
The block diagram below is an example of how the SCI-PHY to Multi-PHY Adapter Card can be utilized to test the Octal PLUS reference design.
4
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APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
5
BLOCK DIAGRAM
SWAN Micro I/F
Power Connector
SCI-PHY #1 Micro I/F
Micro Interface Selection Mux
Multi-PHY-X & Micro I/F
SCI-PHY #1 Multi-PHY I/F
Multi-PHY-Y & Micro I/F
SCI-PHY #2 Micro I/F
SCI-PHY #2 Multi-PHY I/F
5
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APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
6
DESCRIPTION The Multi-PHY Adapter Card (MAC) facilitates the connection of two SCI-PHY EVMBs and a SWAN card to an ATM daughter card with two multi-PHY interfaces. Also, the MAC distributes power and microprocessor control to the SCI-PHY EVMBs, SWAN card and the multi-PHY interfaces. The microprocessor access to the Multi-PHY-X and Multi-PHY-Y interfaces is multiplexed between the SWAN, SCI-PHY EVMB #1 or SCI-PHY EVMB #2 microprocessor. Selection between these microprocessor interfaces is made with jumpers. The Multi-PHY-X Interface connects directly to the SCI-PHY #1 multi-PHY interface and the Multi-PHY-Y Interface connects directly to the SCI-PHY #2 multi-PHY interface The Power Connection block allows connection to an external power supply and includes over-current protection. Therefore, power connections to the other MAC peripheral boards are not required.
6
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SCI-PHY TO MULTIPHY ADAPTER CARD
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CONNECTOR DESCRIPTIONS The adapter board contains the following connectors: Table 1 Connector SCI-PHY #1 Micro I/F SCI-PHY #1 Multi-PHY I/F SCI-PHY #2 Micro I/F SCI-PHY #2 Multi-PHY I/F SWAN Interface Micro & Multi-PHY-X Interface Micro & Multi-PHY-Y Interface Multi-PHY Adapter Card Connectors Description 96 pin DIN female connector containing micro control signals from SCI-PHY #1 Micro Interface. 96 pin DIN female connector containing multi-PHY signals from SCI-PHY #1 Multi-PHY Interface. 96 pin DIN female connector containing micro control signals from SCI-PHY #2 Micro Interface. 96 pin DIN female connector containing multi-PHY signals from SCI-PHY #2 Multi-PHY Interface. 96 pin DIN female connector containing micro control signals from SWAN Timing and Micro card. 96 pin DIN male connector containing microprocessor address signals and multi-PHY signals to the Multi-PHY-X Interface. 96 pin DIN male connector containing microprocessor data and control signals and multi-PHY signals to the Multi-PHY-X Interface.
7
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APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
The SCI-PHY EVMB connectors are exactly the same and are described in the table below. Table 2 Pin Name CSB[0] CSB[1] CSB[2] CSB[3] CSB[4] CSB[5] CSB[6] CSB[7] GND VCC RSTB SCI-PHY #1 and SCI-PHY #2 Micro Interface Connector Type Input Pin # A25 A26 A27 A28 A29 A30 A31 A32 B1B25 B26B32 C2 Function Chip Select. CSB[7:0] asserts low to enable reading from and writing to the micro interface of the Multi-PHY interface. CSB[7:0] routes through the Micro Interface Selection mux.
Power Power Input
Ground +5V Power Reset. RSTB is an active low hardware reset that routes through the Micro Interface Selection mux. Write Strobe. WRB is an active low write strobe that routes through the Micro Interface Selection mux. Read Enable. RDB is an active low read enable that routes through the Micro Interface Selection mux. Address Latch Enable. ALE is an active high address latch enable that routes through the Micro Interface Selection mux. Interrupt. INTB is an active low maskable hardware interrupt and routes through the Micro Interface Selection mux.
WRB
Input
C3
RDB
Input
C4
ALE
Input
C5
INTB
Output
C6
8
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APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
Pin Name D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7]
Type I/O
Pin # C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 A1A24, C1, C7, C8, C25C32
Function Data Bus. D[7:0] is an eight bit microprocessor data bus that routes through the Micro Interface Selection mux.
Input
Address Bus. A[7:0] is an eight bit micro processor address bus that routes through the Micro Interface Selection mux.
N/C
Unconnected pins
9
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SCI-PHY TO MULTIPHY ADAPTER CARD
The SCI-PHY EVMB #1 Multi-PHY interface is described in the table below. All signals connect directly to the Multi-PHY-X Interface. Table 3 Pin Name TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15] RDAT[0] RDAT[1] RDAT[2] RDAT[3] RDAT[4] RDAT[5] RDAT[6] RDAT[7] RDAT[8] RDAT[9] RDAT[10] RDAT[11] RDAT[12] RDAT[13] RDAT[14] RDAT[15] SCI-PHY #1 Multi-PHY Interface Connector Type Input Pin # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 Function Transmit Data. TDAT[15:0] transfers data to the Multi-PHY-X Interface. TDAT[7:0] corresponds to the least significant byte of the data word and TDAT[15:8] corresponds to the most significant byte of the data word. TDAT[15:0] is synchronous to the rising edge of TFCLK. TDAT[15:0] routes to the Multi-PHY-X Interface.
Output
Receive Data. RDAT[15:0] transfers data from the Multi-PHY-X Interface. RDAT[7:0] corresponds to the least significant byte of the data word and RDAT[15:8] corresponds to the most significant byte of the data word. RDAT[15:0] is synchronous to the rising edge of RFCLK. RDAT[15:0] originates from the Multi-PHY-X Interface.
10
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APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
Pin Name GND
Type Power
Pin # B1B23, C2, C16, C18 B29 B32 C1
Function Ground
PWR +5V TFCLK
Power Input
+5V Power Transmit FIFO Clock. TFCLK synchronizes TDAT[15:0] to the Multi-PHY Interface. The Multi-PHY Interface updates TCAn and samples TWRENnB, TSOC, TXPRTY[1:0], and TDAT[15:0] on the rising edge of TFCLK. TFCLK routes to the Multi-PHY-X Interface. Transmit Start Of Cell. TSOC marks the start of cell on the TDAT bus. TSOC asserts when the first word of the cell structure is present on the TDAT bus. TSOC is synchronous to the rising edge of TFCLK and routes to the Multi-PHY-X Interface. Transmit Parity. TXPRTY[1:0] indicates the parity of the TDAT[15:0] bus. TXPRTY[1] is the parity calculation over the TDAT[15:8] bus. TXPRTY[0] is the parity calculation over the TDAT[7:0] bus. TXPRTY[1:0] is synchronous to the rising edge of TFCLK and routes to the Multi-PHY-X Interface. Transmit Cell Available. TCAn indicates when the nth channel of the Multi-PHY-X Interface can accept data. Four TCA inputs provide support for four channels. TCAn is synchronous to the rising edge of TFCLK and originates from the Multi-PHY-X Interface.
TSOC
Input
C3
TXPRTY[0] TXPRTY[1]
Input
C4 C5
TCA1 TCA2 TCA3 TCA4
Output
C6 C7 C8 C9
11
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APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
Pin Name TWREN1B TWREN2B TWREN3B TWREN4B
Type Input
Pin # C10 C11 C12 C13
Function Transmit Write Enable. The active low TWRENnB initiates writes to the nth channel transmit FIFO of the Multi-PHY-X Interface. Data on TDAT[15:0] is written into the nth channel transmit FIFO when the nth Multi-PHY-X Interface channel samples an asserted TWRENnB on the rising edge of TFCLK. No data is written into the transmit FIFO when the nth Multi-PHY-X Interface channel samples a negated TWRENnB on the rising edge of TFCLK. TWRENnB routes to the Multi-PHY-X Interface. Receive FIFO Clock. RFCLK synchronizes RDAT[15:0] from the Multi-PHY Interface. The Multi-PHY Interface samples RWRENnB and updates RCAn, RSOC, RXPRTY[1:0], and RDAT[15:0] on the rising edge of RFCLK. RFCLK routes to the Multi-PHY-X Interface. Receive Start Of Cell. RSOC marks the start of cell on the RDAT bus. RSOC asserts when the first word of the cell structure is present on the RDAT bus. RSOC is synchronous to the rising edge of RFCLK and originates from the Multi-PHY-X Interface. Receive Parity. RXPRTY[1:0] indicates the parity of the RDAT[15:0] bus. RXPRTY[1] is the parity calculation over the RDAT[15:8] bus. RXPRTY[0] is the parity calculation over the RDAT[7:0] bus. RXPRTY[1:0] is synchronous to the rising edge of RFCLK and originates from the Multi-PHY-X Interface. Receive Cell Available. RCAn indicates when the nth channel of the Multi-PHY-X Interface contains valid data. Four RCA inputs provide support for four channels. RCAn is synchronous to the rising edge of RFCLK and originates from the Multi-PHY-X Interface.
RFCLK
Input
C17
RSOC
Output
C19
RXPRTY[0] RXPRTY[1]
Output
C20 C21
RCA1 RCA2 RCA3 RCA4
Output
C22 C23 C24 C25
12
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APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
Pin Name RRDEN1B RRDEN2B RRDEN3B RRDEN4B
Type Input
Pin # C26 C27 C28 C29
Function Receive Read Enable. The active low RRDENnB initiates reads from the nth channel receive FIFO of the Multi-PHY-X Interface. Data is read from the nth Multi-PHY-X Interface channel receive FIFO and put on RDAT[15:0] when the nth Multi-PHY-X Interface channel samples an asserted RRDENnB on the rising edge of RFCLK. No data is read from the receive FIFO when the nth Multi-PHY-X Interface channel samples a negated RRDENnB on the rising edge of RFCLK. RRDENnB routes to the Multi-PHY-X Interface. Unconnected
N/C
B24B28, C14, C15, C30C32
The SCI-PHY EVMB #2 Multi-PHY interface is described in the table below. All signals connect directly to the Multi-PHY-Y Interface.
13
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Table 4 Pin Name TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15] RDAT[0] RDAT[1] RDAT[2] RDAT[3] RDAT[4] RDAT[5] RDAT[6] RDAT[7] RDAT[8] RDAT[9] RDAT[10] RDAT[11] RDAT[12] RDAT[13] RDAT[14] RDAT[15] GND
SCI-PHY #2 Multi-PHY Interface Type Input Pin # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 B1B23, C2, C16, C18 Function Transmit Data. TDAT[15:0] transfers data to the Multi-PHY-Y Interface. TDAT[7:0] corresponds to the least significant byte of the data word and TDAT[15:8] corresponds to the most significant byte of the data word. TDAT[15:0] is synchronous to the rising edge of TFCLK. TDAT[15:0] routes to the Multi-PHY-Y Interface.
Output
Receive Data. RDAT[15:0] transfers data from the Multi-PHY-Y Interface. RDAT[7:0] corresponds to the least significant byte of the data word and RDAT[15:8] corresponds to the most significant byte of the data word. RDAT[15:0] is synchronous to the rising edge of RFCLK. RDAT[15:0] originates from the Multi-PHY-Y Interface.
Power
Ground
14
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APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
Pin Name PWR +5V TFCLK
Type Power Input
Pin # B29 B32 C1
Function +5V Power Transmit FIFO Clock. TFCLK synchronizes TDAT[15:0] to the Multi-PHY Interface. The Multi-PHY Interface updates TCAn and samples TWRENnB, TSOC, TXPRTY[1:0], and TDAT[15:0] on the rising edge of TFCLK. TFCLK routes to the Multi-PHY-Y Interface. Transmit Start Of Cell. TSOC marks the start of cell on the TDAT bus. TSOC asserts when the first word of the cell structure is present on the TDAT bus. TSOC is synchronous to the rising edge of TFCLK and routes to the Multi-PHY-Y Interface. Transmit Parity. TXPRTY[1:0] indicates the parity of the TDAT[15:0] bus. TXPRTY[1] is the parity calculation over the TDAT[15:8] bus. TXPRTY[0] is the parity calculation over the TDAT[7:0] bus. TXPRTY[1:0] is synchronous to the rising edge of TFCLK and routes to the Multi-PHY-Y Interface. Transmit Cell Available. TCAn indicates when the nth channel of the Multi-PHY-Y Interface can accept data. Four TCA inputs provide support for four channels. TCAn is synchronous to the rising edge of TFCLK and originates from the Multi-PHY-Y Interface.
TSOC
Input
C3
TXPRTY[0] TXPRTY[1]
Input
C4 C5
TCA1 TCA2 TCA3 TCA4
Output
C6 C7 C8 C9
15
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SCI-PHY TO MULTIPHY ADAPTER CARD
Pin Name TWREN1B TWREN2B TWREN3B TWREN4B
Type Input
Pin # C10 C11 C12 C13
Function Transmit Write Enable. The active low TWRENnB initiates writes to the nth channel transmit FIFO of the Multi-PHY-Y Interface. Data on TDAT[15:0] is written into the nth channel transmit FIFO when the nth Multi-PHY-Y Interface channel samples an asserted TWRENnB on the rising edge of TFCLK. No data is written into the transmit FIFO when the nth Multi-PHY-Y Interface channel samples a negated TWRENnB on the rising edge of TFCLK. TWRENnB routes to the Multi-PHY-Y Interface. Receive FIFO Clock. RFCLK synchronizes RDAT[15:0] from the Multi-PHY Interface. The Multi-PHY Interface samples RWRENnB and updates RCAn, RSOC, RXPRTY[1:0], and RDAT[15:0] on the rising edge of RFCLK. RFCLK routes to the Multi-PHY-Y Interface. Receive Start Of Cell. RSOC marks the start of cell on the RDAT bus. RSOC asserts when the first word of the cell structure is present on the RDAT bus. RSOC is synchronous to the rising edge of RFCLK and originates from the Multi-PHY-Y Interface. Receive Parity. RXPRTY[1:0] indicates the parity of the RDAT[15:0] bus. RXPRTY[1] is the parity calculation over the RDAT[15:8] bus. RXPRTY[0] is the parity calculation over the RDAT[7:0] bus. RXPRTY[1:0] is synchronous to the rising edge of RFCLK and originates from the Multi-PHY-Y Interface. Receive Cell Available. RCAn indicates when the nth channel of the Multi-PHY-Y Interface contains valid data. Four RCA inputs provide support for four channels. RCAn is synchronous to the rising edge of RFCLK and originates from the Multi-PHY-Y Interface.
RFCLK
Input
C17
RSOC
Output
C19
RXPRTY[0] RXPRTY[1]
Output
C20 C21
RCA1 RCA2 RCA3 RCA4
Output
C22 C23 C24 C25
16
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SCI-PHY TO MULTIPHY ADAPTER CARD
Pin Name RRDEN1B RRDEN2B RRDEN3B RRDEN4B
Type Input
Pin # C26 C27 C28 C29
Function Receive Read Enable. The active low RRDENnB initiates reads from the nth channel receive FIFO of the Multi-PHY-Y Interface. Data is read from the nth Multi-PHY-Y Interface channel receive FIFO and put on RDAT[15:0] when the nth Multi-PHY-Y Interface channel samples an asserted RRDENnB on the rising edge of RFCLK. No data is read from the receive FIFO when the nth Multi-PHY-Y Interface channel samples a negated RRDENnB on the rising edge of RFCLK. RRDENnB routes to the Multi-PHY-Y Interface. Unconnected
N/C
B24B28, C14, C15, C30C32
Table 5 Pin Name TXFP+ TXFP-
SWAN Connector Type Output Pin # A1 A2 Function Transmit Frame Pulse. TXFP+/- is a differential signal pair used for system synchronization feedback. TXFP+/- is synchronous to SRCLK+/- and originates from the Multi-PHY-X Interface connector. Receive Alarm. RALM indicates a Multi-PHY Interface channel has a loss of signal condition. RALM asserts high and originates from the Multi-PHY-X Interface connector. Receive Frame Pulse. RXFP+/- is a differential signal pair used for system synchronization feedback. RXFP+/- is synchronous to SRCLK+/- and originates from the Multi-PHY-Y Interface connector.
RALM
Output
A4
RXFP+ RXFP-
Output
A6 A7
17
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Pin Name SRCLK+ SRCLK-
Type Input
Pin # A14 A15
Function System Reference Clock. SRCLK+/- is a differential system reference clock for the PHY channels of the Multi-PHY Interface. SRCLK+/- routes directly to the Multi-PHY-Y Interface connector. Chip Select. CSB[7:0] asserts low to enable reading from and writing to the micro interface of the Multi-PHY interface. CSB[7:0] routes through the Micro Interface Selection mux.
CSB[0] CSB[1] CSB[2] CSB[3] CSB[4] CSB[5] CSB[6] CSB[7] GND VCC RSTB
Input
A25 A26 A27 A28 A29 A30 A31 A32 B1B25 B26B32 C2
Power Power Input
Ground +5V Power Reset. RSTB is an active low hardware reset that routes through the Micro Interface Selection mux. Write Strobe. WRB is an active low write strobe that routes through the Micro Interface Selection mux. Read Enable. RDB is an active low read enable that routes through the Micro Interface Selection mux. Interrupt. INTB is an active low maskable hardware interrupt and routes through the Micro Interface Selection mux. Data Bus. D[7:0] is an eight bit microprocessor data bus that routes through the Micro Interface Selection mux.
WRB
Input
C3
RDB
Input
C4
INTB
Output
C6
D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7]
I/O
C9 C10 C11 C12 C13 C14 C15 C16
18
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SCI-PHY TO MULTIPHY ADAPTER CARD
Pin Name A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7]
Type Input
Pin # C17 C18 C19 C20 C21 C22 C23 C24 A3, A5, A8A13, A16A24, C1, C5, C7, C8, C25C32
Function Address Bus. A[7:0] is an eight bit micro processor address bus that routes through the Micro Interface Selection mux.
N/C
Unconnected pins
Table 6 Pin Name XTFCLK
Multi-PHY-X Interface Type Output Pin # A1 Function Multi-PHY-X FIFO Clock. XTFCLK synchronizes data transfer transactions to the Multi-PHY-X Interface. Clock rates up to 52 MHz are supported. The Multi-PHY-X Interface samples XTWRENB[3:0], XTSOC, XTXPRTY[1:0], XTDAT[15:0] and XRRDENB[3:0] on the rising edge of XTFCLK. XTFCLK originates from the SCI-PHY EVMB #1 Interface connector.
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APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
XTSOC
Output
A3
Multi-PHY-X Transmit Start Of Cell. XTSOC marks the start of cell on the XTDAT bus. XTSOC asserts high on the rising edge of XTFCLK when the first word of the data structure is present on the XTDAT bus. XTSOC originates from the SCI-PHY EVMB #1 Interface connector. Multi-PHY-X Transmit Parity. XTXPRTY[1:0] indicates the parity of the XTDAT[15:0] bus. The Multi-PHY-X Interface samples XTXPRTY[1:0] on the rising edge of XTFCLK. XTXPRTY[1] is the parity calculation over the XTDAT[15:8] bus. XTXPRTY[0] is the parity calculation over the XTDAT[7:0] bus. XTXPRTY[1:0] originates from the SCI-PHY EVMB #1 Interface connector. Multi-PHY-X Transmit Data. XTDAT[15:0] transfers data to the corresponding Multi-PHY-X Interface channel on the rising edge of XTFCLK when one of XTWRENB[3:0] is asserted. XTDAT[7:0] corresponds to the least significant byte of the data word while XTDAT[15:8] corresponds to the most significant byte of the data word. XTDAT[15:0] originates from the SCI-PHY EVMB #1 Interface connector.
XTXPRTY[0] XTXPRTY[1]
Output
C1 C3
XTDAT[0] XTDAT[1] XTDAT[2] XTDAT[3] XTDAT[4] XTDAT[5] XTDAT[6] XTDAT[7] XTDAT[8] XTDAT[9] XTDAT[10] XTDAT[11] XTDAT[12] XTDAT[13] XTDAT[14] XTDAT[15] XTCA[0] XTCA[1] XTCA[2] XTCA[3]
Output
A11 A10 A9 A8 A7 A6 A5 A4 C11 C10 C9 C8 C7 C6 C5 C4 B5 B4 B2 B1
Input
Multi-PHY-X Transmit Cell Available. XTCA[n] indicates when the nth channel of the Multi-PHY-X Interface can accept data. Four XTCA inputs are provided to support four channels and the Multi-PHY-X Interface updates XTCAn on the rising edge of XTFCLK. XTCA[3:0] routes to the SCI-PHY EVMB #1 Interface connector.
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APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
XTWRENB[0] XTWRENB[1] XTWRENB[2] XTWRENB[3]
Output
B11 B10 B8 B7
Multi-PHY-X Transmit Write Enable. The active low XTWRENB[n] initiates writes to the nth channel transmit FIFO of the Multi-PHY-X Interface. Data on XTDAT[15:0] is written into the nth channel transmit FIFO when the nth Multi-PHY-X Interface channel samples an asserted XTWRENB[n] on the rising edge of XTFCLK. No data is written into the transmit FIFO when the nth Multi-PHY-X Interface channel samples a negated XTWRENB[n] on the rising edge of XFCLK. XTWRENB[3:0] originates from the SCI-PHY EVMB #1 Interface connector. Address Bus. A[7:0] is an eight bit micro processor address bus that originates from the Micro Interface Selection mux.
A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] CSB[0] CSB[1] CSB[2] CSB[3] CSB[4] CSB[5] CSB[6] CSB[7] TXFP+ (TXFP[1]) TXFP(TXFP[0])
Output
A13 A14 A15 A16 A17 A18 A19 A20 C13 C14 C15 C16 C17 C18 C19 C20 B15 B16
Output
Chip Select. CSB[7:0] asserts low to enable reading from and writing to the micro interface of the Multi-PHY interface. CSB[7:0] originates from the Micro Interface Selection mux.
Input
Transmit Frame Pulse. The differential transmit frame pulse inputs provide the SWAN Micro and Timing card an 8KHz feedback signal for external clock synchronization. TXFP+/- routes directly to the SWAN Micro Interface connector. Receive Alarm. Receive Alarm indicates a loss of signal (LOS) condition has occurred at the PHY channel selected to provide the TXFP+/- signals. RALM routes directly to the SWAN Micro Interface connector.
RALM
Input
B18
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XRFCLK
Output
A32
Multi-PHY-X Receive FIFO Clock. XRFCLK synchronizes data transfer transactions to the Multi-PHY-X Receive Interface. Clock rates up to 52 MHz are supported. The Multi-PHY-X Interface updates XRCA[3:0], XRSOC, XRXPRTY[1:0], XRDAT[15:0] and XTCA[3:0] on the rising edge of XRFCLK. Multi-PHY-X Receive Start Of Cell. XRSOC marks the start of cell on the XRDAT bus. XRSOC asserts high on the rising edge of XRFCLK when the first word of the data structure is present on the XRDAT bus. XRSOC routes to the SCI-PHY EVMB #1 Interface connector. Multi-PHY-X Receive Parity. XRXPRTY[1:0] indicates the parity of the XRDAT[15:0] bus. XRXPRTY[1] is the parity calculation over the XRDAT[15:8] bus. XRXPRTY[0] is the parity calculation over the XRDAT[7:0] bus. XRXPRTY[1:0] routes to the SCI-PHY EVMB #1 Interface connector. Multi-PHY-X Receive Data. XRDAT[15:0] transfers data from the Multi-PHY-X Interface channel on the rising edge of XRFCLK when one of XRRDENB[3:0] is asserted. XRDAT[7:0] corresponds to the least significant byte of the data word while XRDAT[15:8] corresponds to the most significant byte of the data word. XRDAT[15:0] routes to the SCI-PHY EVMB #1 Interface connector.
XRSOC
Input
A30
XRXPRTY[0] XRXPRTY[1]
Input
C32 C30
XRDAT[0] XRDAT[1] XRDAT[2] XRDAT[3] XRDAT[4] XRDAT[5] XRDAT[6] XRDAT[7] XRDAT[8] XRDAT[9] XRDAT[10] XRDAT[11] XRDAT[12] XRDAT[13] XRDAT[14] XRDAT[15]
Input
A29 A28 A27 A26 A25 A24 A23 A22 C29 C28 C27 C26 C25 C24 C23 C22
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APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
XRCA[0] XRCA[1] XRCA[2] XRCA[3]
Input
B32 B31 B29 B28
Multi-PHY-X Receive Cell Available. XRCA[n] indicates when the nth channel of the Multi-PHY-X Interface contains valid data. Four XRCA inputs are provided to support four Multi-PHY-X channels. The nth Multi-PHY-X Interface channel asserts XRCA[n] when data can be read from its receive FIFO. The nth Multi-PHY-X Interface channel negates XRCA[n] when its receive FIFO is empty. XRCA[3:0] routes to the SCI-PHY EVMB #1 Interface connector. Multi-PHY-X Receive Write Enable. The active low XRRDENB[n] initiates reads from the nth channel receive FIFO of the Multi-PHY-X Interface. Data is read from the nth Multi-PHY-X Interface channel receive FIFO and put on XRDAT[15:0] when the nth Multi-PHY-X Interface channel samples an asserted XRRDENB[n] on the rising edge of XRFCLK. No data is read from the nth Multi-PHY-X Interface channel receive FIFO when the nth Multi-PHY-X Interface channel samples a negated XRRDENB[n] on the rising edge of XRFCLK. XRRDENB[3:0] originates from the SCI-PHY EVMB #1 Interface connector. Ground
XRRDENB[0] XRRDENB[1] XRRDENB[2] XRRDENB[3]
Output
B26 B25 B23 B22
GND
Power
B3 B6 B9 B12 B13 B14 B17 B19 B21 B24 B27 B30
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PWR +5V
Power
A2 A12 A21 A31 C2 C12 C21 C31
+5V Power
Table 7 Pin Name YTFCLK
Multi-PHY-Y Interface Connector Type Output Pin # A1 Function Multi-PHY-Y FIFO Clock. YTFCLK synchronizes data transfer transactions to the Multi-PHY-Y Interface. Clock rates up to 52 MHz are supported. The Multi-PHY-Y Interface samples YTWRENB[3:0], YTSOC, YTXPRTY[1:0] YTDAT[15:0] and YRRDENB[3:0] on the rising edge of YTFCLK. YTFCLK originates from the SCI-PHY EVMB #2 Interface connector. Multi-PHY-Y Transmit Start Of Cell. YTSOC marks the start of cell on the YTDAT bus. YTSOC asserts high on the rising edge of YTFCLK when the first word of the data structure is present on the YTDAT bus. YTSOC originates from the SCI-PHY EVMB #2 Interface connector. Multi-PHY-Y Transmit Parity. YTXPRTY[1:0] indicates the parity of the YTDAT[15:0] bus. The Multi-PHY-Y Interface samples YTXPRTY[1:0] on the rising edge of YTFCLK. YTXPRTY[1] is the parity calculation over the YTDAT[15:8] bus. YTXPRTY[0] is the parity calculation over the YTDAT[7:0] bus. YTXPRTY[1:0] originates from the SCI-PHY EVMB #2 Interface connector.
YTSOC
Output
A3
YTXPRTY[0] YTXPRTY[1]
Output
C3 C1
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YTDAT[0] YTDAT[1] YTDAT[2] YTDAT[3] YTDAT[4] YTDAT[5] YTDAT[6] YTDAT[7] YTDAT[8] YTDAT[9] YTDAT[10] YTDAT[11] YTDAT[12] YTDAT[13] YTDAT[14] YTDAT[15] YTCA[0] YTCA[1] YTCA[2] YTCA[3]
Output
A11 A10 A9 A8 A7 A6 A5 A4 C11 C10 C9 C8 C7 C6 C5 C4 B5 B4 B2 B1
Multi-PHY-Y Transmit Data. YTDAT[15:0] transfers data to the corresponding Multi-PHY-Y Interface channel on the rising edge of YTFCLK when one of YTWRENB[3:0] is asserted. YTDAT[7:0] corresponds to the least significant byte of the data word while YTDAT[15:8] corresponds to the most significant byte of the data word. YTDAT[15:0] originates from the SCI-PHY EVMB #2 Interface connector.
Input
Multi-PHY-Y Transmit Cell Available. YTCA[n] indicates when the nth channel of the Multi-PHY-Y Interface can accept data. Four YTCA inputs are provided to support four channels and the Multi-PHY-Y Interface updates YTCAn on the rising edge of YTFCLK. YTCA[3:0] routes to the SCI-PHY EVMB #2 Interface connector. Multi-PHY-Y Transmit Write Enable. The active low YTWRENB[n] initiates writes to the nth channel transmit FIFO of the Multi-PHY-Y Interface. Data on YTDAT[15:0] is written into the nth channel transmit FIFO when the nth Multi-PHY-Y Interface channel samples an asserted YTWRENB[n] on the rising edge of YTFCLK. No data is written into the transmit FIFO when the nth Multi-PHY-Y Interface channel samples a negated YTWRENB[n] on the rising edge of YTFCLK. YTWRENB[3:0] originates from the SCI-PHY EVMB #2 Interface connector.
YTWRENB[0] YTWRENB[1] YTWRENB[2] YTWRENB[3]
Output
B11 B10 B8 B7
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APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] RSTB
Output
A13 A14 A15 A16 A17 A18 A19 A20 C13
Data Bus. D[7:0] is an eight bit microprocessor data bus that routes through the Micro Interface Selection mux.
Output
Reset. RSTB is an active low hardware reset that routes through the Micro Interface Selection mux. Interrupt. INTB is an active low maskable hardware interrupt and routes through the Micro Interface Selection mux. Address Latch Enable. ALE is an active high address latch enable that routes through the Micro Interface Selection mux. Board Select. BSB is an active low board select that enables microprocessor access to the Multi-PHY Interface. BSB originates from the Micro Interface Selection mux. Read Enable. RDB is an active low read enable that routes through the Micro Interface Selection mux. Write Strobe. WRB is an active low write strobe that routes through the Micro Interface Selection mux. System Reference Clock. SRCLK+/- is a jitter free 19.44MHz differential system reference clock for the PHY channels of the Multi-PHY Interface. SRCLK+/- originates from the SWAN Micro Interface connector. Receive Frame Pulse. RXFP+/- is a differential signal pair used for system synchronization feedback. RXFP+/- is synchronous to SRCLK+/- and connects directly to the SWAN Micro Interface.
INTB
Input
C14
ALE
Output
C15
BSB
Output
C16
RDB
Output
C18
WRB
Output
C20
SRCLK+ (SRCLK[1]) SRCLK(SRCLK[0]) RXFP+ RXFP-
Output
B14 B15
Input
B18 B19
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SCI-PHY TO MULTIPHY ADAPTER CARD
YRFCLK
Output
A32
Multi-PHY-Y Receive FIFO Clock. YRFCLK synchronizes data transfer transactions to the Multi-PHY-Y Interface. Clock rates up to 52 MHz are supported. The Multi-PHY-Y Interface updates YRCA[3:0], YRSOC, YRXPRTY[1:0], YRDAT[15:0] and YTCA[3:0] on the rising edge of YRFCLK. YRFCLK originates from the SCI-PHY EVMB #2 Interface connector. Multi-PHY-Y Receive Start Of Cell. YRSOC marks the start of cell on the YRDAT bus. YRSOC asserts high on the rising edge of YRFCLK when the first word of the data structure is present on the YRDAT bus. YRSOC routes to the SCI-PHY EVMB #2 Interface connector. Multi-PHY-Y Receive Parity. YRXPRTY[1:0] indicates the parity of the YRDAT[15:0] bus. YRXPRTY[1] is the parity calculation over the YRDAT[15:8] bus. YRXPRTY[0] is the parity calculation over the YRDAT[7:0] bus. YRXPRTY[1:0] routes to the SCI-PHY EVMB #2 Interface connector. Multi-PHY-Y Receive Data. YRDAT[15:0] transfers data from the Multi-PHY-Y Interface channel on the rising edge of YRFCLK when one of YRRDENB[3:0] is asserted. YRDAT[7:0] corresponds to the least significant byte of the data word while YRDAT[15:8] corresponds to the most significant byte of the data word. YRDAT[15:0] routes to the SCI-PHY EVMB #2 Interface connector.
YRSOC
Input
A30
YRXPRTY[0] YRXPRTY[1]
Input
C32 C30
YRDAT[0] YRDAT[1] YRDAT[2] YRDAT[3] YRDAT[4] YRDAT[5] YRDAT[6] YRDAT[7] YRDAT[8] YRDAT[9] YRDAT[10] YRDAT[11] YRDAT[12] YRDAT[13] YRDAT[14] YRDAT[15]
Input
A29 A28 A27 A26 A25 A24 A23 A22 C29 C28 C27 C26 C25 C24 C23 C22
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SCI-PHY TO MULTIPHY ADAPTER CARD
YRCA[0] YRCA[1] YRCA[2] YRCA[3]
Input
B32 B31 B29 B28
Multi-PHY-Y Receive Cell Available. YRCA[n] indicates when the nth channel of the Multi-PHY-Y Interface contains valid data. Four YRCA inputs are provided to support four Multi-PHY-Y channels. The nth Multi-PHY-Y Interface channel asserts YRCA[n] when data can be read from its receive FIFO. The nth Multi-PHY-Y Interface channel negates YRCA[n] when its receive FIFO is empty. YRCA[3:0] routes to the SCI-PHY EVMB #2 Interface connector. Multi-PHY-Y Receive Write Enable. The active low YRRDENB[n] initiates reads from the nth channel receive FIFO of the Multi-PHY-Y Interface. Data is read from the nth Multi-PHY-Y Interface channel receive FIFO and put on YRDAT[15:0] when the nth Multi-PHY-Y Interface channel samples an asserted YRRDENB[n] on the rising edge of YRFCLK. No data is read from the nth Multi-PHY-Y Interface channel receive FIFO when the nth Multi-PHY-Y Interface channel samples a negated YRRDENB[n] on the rising edge of YFCLK. YRRDENB[3:0] originates from the SCI-PHY EVMB #2 Interface connector. Ground
YRRDENB[0] YRRDENB[1] YRRDENB[2] YRRDENB[3]
Output
B26 B25 B23 B22
GND
Power
B3 B6 B9 B13 B16 B17 B20 B21 B24 B27 B30
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SCI-PHY TO MULTIPHY ADAPTER CARD
PWR +5V
Power
A2 A12 A21 A31 C2 C12 C21 C31
+5V Power
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8 8.1
IMPLEMENTATION Root Drawing, Sheet 1 Function: 1. Provides an overview of the major functional blocks of the SCI-PHY to Multi-PHY Adapter board circuitry. 2. Illustrates the interconnecting data paths. 3. Shows power connection and protection. Implementation This sheet interconnects the SCIPHY_X, SCIPHY_Y, SWAN, MICRO_MUX, MULTIPHY_X and MULTIPHY_Y blocks. It also shows the power connections and related power circuitry. +5V and GND power connections to the board are made via a screw-down type terminal block J3. The +5V routes through four identical networks that consist of a 5A fuse current protection, power indication LED with current limiting resistor, current feedback prevention diode, zener diode over-voltage protection and filtering capacitor.
8.2
SCIPHY_X, Sheet 2 Function: 1. Provides the electrical interface to the SCI-PHY #1 Evaluation Motherboard microprocessor interface and the SCI-PHY ATM cell interface. Implementation: This sheet shows two DIN-96 edge connectors. P1 provides the complete microprocessor interface which includes control signals, 8-bit data bus, 8-bit address bus and eight chip select signals. P2 provides the complete multi-PHY interface for the Multi-PHY-X Interface. This interface includes 16-bit data buses, parity, start-of-cell, cell available and read/write enable signals for the receive and transmit directions respectively. Power and ground connections are made in both connectors. Place the decoupling capacitors near to the connector for filtering VCC.
8.3
SCIPHY_Y, Sheet 3 Function:
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1. Provides the electrical interface to the SCI-PHY #2 Evaluation Motherboard microprocessor interface and the SCI-PHY ATM cell interface. Implementation: This sheet shows two DIN-96 edge connectors. P4 provides the complete microprocessor interface which includes control signals, 8-bit data bus, 8-bit address bus and eight chip select signals. P5 provides the complete multi-PHY interface for the Multi-PHY-Y Interface. This interface includes 16-bit data buses, parity, start-of-cell, cell available and read/write enable signals for the receive and transmit directions respectively. Power and ground connections are made in both connectors. Place the decoupling capacitors near to the connector for filtering VCC. 8.4 SWAN, Sheet 4 Function: 1. Provides the electrical interface to the SWAN Microprocessor and Reference Timing Card. Implementation: This sheet shows one DIN-96 edge connector that provides a portion of the electrical connections to the SCI-PHY to Multi-PHY Adapter board. Connector P3 has the complete microprocessor interface which includes control signals, 8-bit data bus, 8-bit address bus and eight chip select signals. P3, also has the Transmit Frame Pulse (TXFP+/-), Receive Frame Pulse (RXFP+/-) and System Reference Clock (SRCLK+/) signals for the system reference clock card. Also, power and ground connections are made in connector P3. Place the decoupling capacitors near to the connector for filtering VCC. 8.5 MICRO_MUX, Sheet 5 Function: 1. Provides manual selection of the Multi-PHY Interface microprocessor control between either the SWAN microprocessor or the SCI-PHY EVMB #1 microprocessor. 2. Incorporates 3 sources of reset for the Multi-PHY Interface. 3. Provides logic for the board select signal (BSB). Implementation:
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This sheet shows the multiplexing between the SCI-PHY #1, SCI-PHY #2 or the SWAN microprocessor signals U1, U2, U3 and U4 multiplex the microprocessor signals to the Multi-PHY Interface. Jumpers J1 and J2 correctly select which multiplex path is active. When the jumper is in place (closed), the SWAN microprocessor path is selected. When the jumper is removed (open), the SCI-PHY microprocessor path is selected. Figure 2 Micro Interface Selection Jumper Positions
J1
1 2 1
J2
2
J1
1 2 1
J2
2
J1
1 2 1
J2
2
Table 8 J1 Pin 1-2 Closed Pin 1-2 Closed Pin 1-2 Open
Micro Interface Selection Jumper Positions J2 Pin 1-2 Closed Pin 1-2 Open Pin 1-2 Closed Description Selects the SCI-PHY #1 Micro Interface to control the Multi-PHY Interface microprocessor. Selects the SCI-PHY #2 Micro Interface to control the Multi-PHY Interface microprocessor. Selects the SWAN Micro Interface to control the Multi-PHY Interface microprocessor.
An external hardware reset, an external software reset and a local hardware reset are the three sources for the Multi-PHY reset. The SCI-PHY #1, SCI-PHY #2 and the SWAN microprocessors provide the external reset signals dependent on the micro multiplexer selection. The normally open push button switch and capacitor C28 provide the local hardware reset. The two AND gates of U6 provide a logical OR function of these signals since they are active low. 4-input AND gates of U7 and the 2-input AND gate of U6 combine to assert BSB low when any of the CSB signals are asserted low.
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The inputs of the unused gates of U6 are connected to ground (logic 0). Capacitors for decoupling power pins are also provided. 8.6 MULTIPHY _X, Sheet 6 Function: 1. Provides the electrical interface for the address bus of a microprocessor to Octal PLUS board. 2. Provides the electrical interface for the Multi-PHY-X Interface of the Octal PLUS board. 3. Provides the external system reference clock feedback signal interface (TXFP+/-). 4. Provides VCC and GND connections to the Octal PLUS board. Implementation: This sheet shows one DIN-96 edge connector that provides a portion of the electrical connections to the Octal PLUS board. Connector P6 has the complete Multi-PHY-X and the 16 bit microprocessor address bus. Connector P6, also has the Transmit Frame Pulse (TXFP+/-) feedback signals for an external system reference clock card. Place the decoupling capacitors near to the connector for filtering the incoming VCC. 8.7 MULTIPHY_Y, Sheet 7 Function: 1. Provides the electrical interface for the data bus and control signals of a microprocessor to Octal PLUS board. 2. Provides the electrical interface for the Multi-PHY Multi-PHY-Ys to the Octal PLUS board. 3. Provides the external system reference clock feedback signal interface (RXFP+/-), alarm signal interface (RALM) and the reference clock signal (SRCLK+/-). 4. Provides VCC and GND connections to the Octal PLUS board. Implementation: This sheet shows one DIN-96 edge connector that provides a portion of the electrical connections to the Octal PLUS board. Connector P7 has the complete Multi-PHY-Y, the 8 bit microprocessor data bus and the microprocessor control signals. Connector P7, also, has the differential System Reference Clock signals (SRCLK+/-), the differential feedback signals (RXFP+/-), and the single ended
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alarm signal interface (RALM). Place the de coupling capacitors near to the connector to provide clean power to the Octal PLUS board.
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9
SCHEMATICS
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SCI-PHY TO MULTIPHY ADAPTER CARD
10
MATERIAL LIST Table 9 Item 1 2 3 4 5 Bill of Material Reference D2, D4, D9, D11 U6 U7 C7, C34C49 C3, C5, C6, C9C11, C14C17, C28 C1, C2, C4, C8, C12, C13, C18-C21 C22-C27, C29-C33, C50-C52 RN1 P6, P7 P1-P5 D1, D3, D10, D12 F1-F4 J1, J2 D5-D8 SW1 J3 Qty 4 1 1 17 11 Description 1N5400 Rectifier Diode, 3A Quad 2-input AND 74HC08 Dual 4-input AND 74LS21 0.01UF Capacitor, 50V, X7R-805 0.1UF Capacitor , 50V, X7R-1206
6
10
10UF Capacitor, 10V, SMD Tantalum TEH
7
14
68UF Capacitor, 6.3V, SMD Tantalum TEH
8 9 10 11 12 13 14 15 16
1 2 5 4 4 2 4 1 1
4.7K Resistor Network SMD SOIC16 96pin Right Angle DIN Connector Socket (female), AMP 650462-5 96pin Right Angle DIN Connector Plug (Male), AMP 650473-5 6.2V Zener Diode 1W SMD 5A Nano Fuse SMD Headers, 0.025" square pins, 0.1" spacing LED, Super Red SMD Normally Open Push Button Switch Screw down Terminal Block
37
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-970438 ISSUE 1
PMC-Sierra,Inc.
APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
Item 17 18 19
Reference U1-U5 R1-R4 R9, R10, R12, R13, R15 R5-R8 R11, R14 TP1-TP5
Qty 5 4 5
Description 24:6 Mux/Demux High Speed CMOS QuickSwitch QS33X253, QVSOP48 1.0 Resistor, 5%, 805 1.0K Resistor, 5%, 805
20 21 22
4 2 5
200 Resistor, 5%, 805 4.7K Resistor, 5%, 805 Headers, 0.025" square pins, 0.1" spacing
38
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-970438 ISSUE 1
PMC-Sierra,Inc.
APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
11
LAYOUT
39
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-970438 ISSUE 1
PMC-Sierra,Inc.
APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
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40
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-970438 ISSUE 1
PMC-Sierra,Inc.
APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
NOTES
41
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RELEASED REFERENCE DESIGN PMC-970438 ISSUE 1
PMC-Sierra,Inc.
APPS MULTIPHY ADAPTER
SCI-PHY TO MULTIPHY ADAPTER CARD
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1998 PMC-Sierra, Inc. PM-970438 (R1) ref PMC-960553 (R2) Issue date: February 1998
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE

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