View 1971133_963866.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
Implementation of a Packet Over SONET/SDH Transmission System using the SPECTRA-155.
Preliminary Issue 1
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
TABLE OF CONTENTS 1 OVERVIEW.............................................................................................. 1 1.1 1.2 1.3 1.4 2 INTRODUCTION ........................................................................... 1 FRAME STRUCTURES FOR IMPLEMENTING POS ................... 1 PACKET OVER SONET FRAME FORMAT ................................... 2 PAYLOAD SCRAMBLING.............................................................. 3
SYSTEM ARCHITECTURE FOR TRANSPORTING POS ....................... 4 2.1 POS MAPPED OVER A STS-3C OR STS-1 SONET/SDH SPE ... 4
3 4
SPECTRA-155 CONFIGURATION .......................................................... 7 IMPLEMENTATION DETAILS ................................................................ 10 4.1 4.2 SPECTRA-155 TO POS HDLC PROCESSOR INTERFACE....... 10 POS HDLC PROCESSOR TO LINK LAYER DEVICE INTERFACE .................................................................................................... 11
5
POS HDLC PROCESSOR DESIGN ...................................................... 12 5.1 5.2 5.3 5.4 FCS GENERATOR ...................................................................... 13 BYTE STUFFING ........................................................................ 14 BYTE DESTUFFING ................................................................... 25 FCS CHECK................................................................................ 25
6 7 8
FUNCTIONAL TIMING........................................................................... 33 DISCLAIMER ......................................................................................... 38 REFERENCES....................................................................................... 39
i PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 BYTE STUFFING CHARACTERS ................................................. 14 TRANSMIT FCSSEL CONFIGURATION ....................................... 17 FLAGSEL CONFIGURATION ........................................................ 17 BYTE DESTUFFING CHARACTERS ............................................ 25 RECEIVE FCSSEL CONFIGURATION.......................................... 27
ii PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
LIST OF FIGURES FIGURE 1: A SONET/SDH STS-1/STM-0 FRAME SHOWING THE TOH.......... 1 FIGURE 2: A SONET/SDH STS-3C/STM-1 FRAME SHOWING THE TOH ....... 2 FIGURE 3: POS HDLC FRAME FORMAT.......................................................... 2 FIGURE 4: POS OVER AN STS-3C/STM1 OR STS-1/STM-0 LINK .................. 4 FIGURE 5: SPECTRA-155 TO POS HDLC PROCESSOR INTERFACE ......... 10 FIGURE 6: POS HDLC PROCESSOR TO LINK LAYER DEVICE.................... 11 FIGURE 7: TRANSMIT SECTION.................................................................... 12 FIGURE 8: CRC-32 GENERATOR ................................................................... 14 FIGURE 9: TRANSMIT HDLC CONTROLLER ................................................. 15 FIGURE 10: TRANSMIT HDLC CONTROLLER - DETAILED VIEW ................ 18 FIGURE 11: TRANSMIT HDLC CONTROLLER STATE MACHINE .................. 19 FIGURE 12: TRANSMIT FIFO .......................................................................... 21 FIGURE 13: RECEIVE SECTION..................................................................... 24 FIGURE 14: CRC-32 DECODER...................................................................... 26 FIGURE 15: RECEIVE HDLC CONTROLLER.................................................. 26 FIGURE 16: RECEIVE HDLC CONTROLLER - DETAILED VIEW................... 28 FIGURE 17: RECEIVE HDLC CONTROLLER STATE MACHINE..................... 29 FIGURE 18: RECEIVE FIFO............................................................................. 30 FIGURE 19: TRANSMIT HDLC CONTROLLER - SPECTRA-155 TIMING ...... 33 FIGURE 20: TRANSMIT HDLC CONTROLLER - FIFO INTERFACE TIMING . 34 FIGURE 21: TRANSMIT FIFO - LINK LAYER TIMING..................................... 35 FIGURE 22: RECEIVE HDLC CONTROLLER - SPECTRA-155 TIMING ........ 35
iii PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
FIGURE 23: RECEIVE HDLC CONTROLLER - FIFO TIMING ........................ 36 FIGURE 24: RECEIVE FIFO - LINK LAYER TIMING ....................................... 37
iv PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
1 1.1
OVERVIEW Introduction This application note addresses the need to transfer a point to point protocol (such as the Internet Protocol, IP, or any other packet based PPP) over a SONET/SDH payload envelope STS-3c/STM-1(AU3) or STS-1/STM-0 frame structures. This functionality is easily implemented, as described in this document, using PMCSierra's PM5342 SPECTRA-155 chip and a POS Processor. Transportation of POS over the higher rate concatenated SONET/SDH payloads can be accomplished using the S/UNI-622. This is described in a separate application note described in PMC-Sierra document number PMC-960724.
1.2
Frame Structures for implementing POS Figure 1 shows the STS-1/STM-0 mapping. Fixed stuff bytes exist at columns 30 and 59 and can optionally be programmed to carry POS data. The remaining payload is used entirely for the POS data. Figure 1:
3 b yte s
A SONET/SDH STS-1/STM-0 Frame Showing the TOH
90 b yte s 87 b yte s
S T S -1 /S T M -0 T ra ns p o rt O v erh ea d
A1 A2 C1
C o lu m n 1
J1
C o lum n 3 0
P OS F rame F I
C o lum n 5 9
S e c tio n O v er h ea d P o in ter
B1 B3 C2 H1 H2 H3 G1 B2 K2 F2 P OS F rame
F I X E D
X E D
9 b yte s
S T S T U F F P OS F rame
Lin e O v er h ea d
H4 Z3 Z4 Z2 Z5
U F F
* F ixed stuff col um ns op tion all y filled w ith ce lls * C 2 b y te m us t b e p ro g r am m e d to ind ic ate P P P in the p ay lo ad
Figure 2 shows the STS-3c (STM-1) mapping. In this mapping, no stuff columns are included in the SPE. The entire SPE is used for PPP cell bytes.
1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
Figure 2:
9 b yte s
A SONET/SDH STS-3c/STM-1 Frame Showing the TOH
27 0 b y te s 26 1 b y te s
J1 Section Ov erhe ad (Regen. Section) Pointer B3 C2 G1 F2 H4 Z3 Z4 Z5
P O S F ra m e
P O S F ra m e
9 b y te s
Line O verhe ad (Multiplex S ection)
P O S F ra m e
P O S F ra m e
S T S - 3c T ra ns p o rt O ve rh ea d S T M - 1 S ec tio n O ve r he ad
A1 B1 D1 H1 B2 D4 D7 D10 S1 Z1 Z1 H1 B2 H1 B2 A1 A1 A2 E1 D2 H2 K1 D5 D8 D11 Z2 Z2 M1 H2 H2 A2 A2 J0 F1 D3 H3 K2 D6 D9 D12 E2 H3 H3 Z0 Z0
C 2 b yte m u s t b e s et to ind ic a te P P P
1.3
Packet over SONET frame format
The POS HDLC Processor provides for flexible implementation of Packet Over SONET, which allows to encapsulate various types of packets based protocols. The basic POS frame format is illustrated in Figure 3. POS frames are separated by a Flag Sequence, the 8 bit character 0x7E. This Flag Sequence is also used to fill inter-frame spacing when there is no data to be sent.. There must be a minimum of one Flag Sequence to delineate two POS frames. The POS frame closing Flag is normally preceded by either a 2 byte CRC-CCITT or 4 byte CRC-32 Frame Check Sequence (FCS). The FCS allows for error detection at the far end which can discard packets if errors are detected. The rest of the POS frame is the encapsulated data or packet. The POS HDLC processor does not process the packet data, other than byte stuffing, and provides a transparent transmission from end to end. Figure 3:
F la g
POS HDLC Frame Format
In form a tion P a c ke t (P P P or oth er) P O S H D LC F ram e
2
FCS
F la g
F la g
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
1.4
Payload Scrambling Payload scrambling is extremely important in order to prevent a malicious user from causing problems on a network. In order to see how a malicious user could cause problems on a network it is important to understand the SONET scrambler in more detail. The SONET scrambler is a frame synchronous scrambler with the generating 6 7 polynomial 1+X +X . Since this is a frame synchronous scrambler, the scrambler is reset on each SONET frame. This means that the starting point of the scrambler is deterministic and not based on the previous history of the data stream. Also since th the SONET scrambler is a 7 order scrambler, the pseudo random sequence 7 repeats itself every 127 (2 -1) bit periods. The sequence coming out of the scrambler is xored with the data to be transmitted. The sequence coming out of the scrambler is easily determinable and thus a malicious user can, by making a 1/127 assumption as to where his data lands in the SPE, control the output of the scrambled signal. Applying a self-synchronous scrambler to the payload makes it virtually impossible for a malicious user to cause problems on a network. A self-synchronous scrambler is not aligned to any frame and thus the starting point is not deterministic and is in fact based on the previous history of the data stream. Thus a malicious user would have to know the entire history of the scrambler in order to create a data stream that would cause the output of the scrambler to be a sequence of constant identical digits. Note that by applying a self-synchronous scrambler to the payload and then applying the SONET scrambler to the SONET frame (not including the framing bytes) means that a malicious user would have to be able to control the output of 43 the x +1 self-synchronous scrambler in such a way as to produce a pattern (that would land in the correct position in the SPE) that would cause the SONET scrambler to generate a sequence of constant identical digits.
3 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
2
SYSTEM ARCHITECTURE FOR TRANSPORTING POS The PM5342 SPECTRA-155 device can be used to transport data at either the STS-3c/STM-1 or the STS-1/STM-0 rate. The hardware architectures for both implementations are identical. The only difference between these two modes is that certain registers, described later on in this document in the SPECTRA-155 configuration section, must be set differently.
2.1
POS Mapped Over a STS-3c or STS-1 SONET/SDH SPE Figure 4 below shows the system architecture required for implementing POS over a STS-3c/STM-1or STS-1/STM-0 rate using the SPECTRA-155. Figure 4: POS over an STS-3c/STM1 or STS-1/STM-0 Link
ODL
PM 5342
S P E C T R A -15 5
POS HDLC P ro c e s s o r
P M C -S ie rra , In c ., S N O W B o a rd
P a c k e t-o v e r-S O N E T D a u g h te r C a rd
The complete system is composed of two separate boards. The SONET/SDH Node Optical design with WAN filtering or SNOW board allows for the evaluation and demonstration of the PM5342 SPECTRA-155 device. This board has been specifically designed to mate with a system side application board to form an ATM, HDLC or SONET/SDH cross connect system. The SNOW board is comprised of two main blocks: ODL The optical data link (ODL) can be any optical transceiver designed to operate up to and including OC-3 (155 Mbits/s) rates.
4 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
SPECTRA-155 The SPECTRA-155 is a SONET/SDH Extractor/Aligner for use in STS-1 (STM0/AU3), STS-3 (STM-1/AU3) or STS-3c (STM-1/AU4) interface applications. For a complete description of the SPECTRA-155 please refer to the PM5342 SPECTRA155 Datasheet and the SNOW board reference design. The SPECTRA-155 has been designed to allow for easy implementation of Packet over SONET (POS) applications. The system side interface of the PM5342 SPECTRA-155 can be configured to operate in a byte wide data bus mode. By using the SPECTRA-155 in this mode it is very easy to insert/extract POS data from the device. The SPECTRA-155 can also be configured to apply a self-synchronous X^43+1 scrambler/descrambler to the data stream. The Packet over SONET daughter card is designed to mate to the SNOW board to implement a POS HDLC System. The POS daughter card is comprised of the POS HDLC Processor and an interface to a link layer device. POS HDLC Processor The POS HDLC Processor consists of a transmit HDLC Controller and FIFO and a receive HDLC Controller and FIFO. In the transmit direction, the HDLC controller performs the following functions: * * * * * * * * Encapsulates PPP packets within a POS HDLC frame. Generates opening and closing flag sequence insertion. Can optionally insert a programmable number of flags between consecutive packets. Performs byte stuffing to provide transparency to control characters. Performs frame check sequence generation. The HDLC controller supports the generation of both CRC-CCITT and CRC-32 frame check sequences. Can optionally insert FCS errors for diagnostic purposes. Aborts packets under the direction of the host or when the FIFO underflows. Generates an interrupt if the FIFO underflows
5 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
*
The HDLC controller does not perform self synchronous packet scrambling (1+X43 polynomial) since this function is performed by the SPECTRA-155.
In the receive direction, the HDLC Controller performs the following functions: * * Performs flag sequence detection and terminates the received HDLC frame. Performs frame check sequence (FCS) validation. The HDLC controller supports the validation of both CRC-CCITT and CRC-32 frame check sequences. Performs Control Escape de-stuffing. Checks for a packet abort sequence. The HDLC controller does not perform self synchronous PPP de-scrambling on the SPE payload since this function is already performed by the SPECTRA-155. Generates interrupts on FIFO overflows.
* * *
*
The TX and RX FIFO's allow for rate decoupling between the line side and system side timing domains. Link Layer Interface In the transmit direction, the link layer interface passes data from memory to the HDLC Processor. In the receive direction, data is passed from the HDLC Processor to the link layer interface which sends the data to memory.
6 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
3
SPECTRA-155 CONFIGURATION As mentioned previously, this implementation requires that the system side interface of the SPECTRA-155 be configured for Byte Data mode. This is accomplished by connecting the SMODE[2:0] pins in the following manner:
Pin SMODE[2] SMODE[1] SMODE[0]
Configuration O - GND 1 - VDD 1 - VDD
In Byte (and Nibble) data mode it is possible to configure the SPECTRA-155 to scramble/descramble the PPP data. The scrambler/descrambler uses a self synchronous x^43 + 1 polynomial.
Register 0X87
Name SPECTRA-155 Data Mode Configuration
Bit 5 1
Function RDM_SCR MEN TDM_SCR MEN
Set 1 1
As shown below, certain registers also need to be configured depending on whether a STS-3c or STS-1 line side interface is required.
7 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
STS-3c Configuration:
Register 0X00
Name SPECTRA-155 Configuration
Bit 7 6 1 0
Function TMODE[1] TMODE[0] RMODE[1] RMODE[1]
Set 1 1 1 1
STS-1 Configuration: In STS-1 mode it is possible to configure the SPECTRA-155 to use the Fixed Stuff columns of the STS-1 SPE to carry data. The TDM_FSEN/RDM_FSEN bits must be set in order to configure the device to insert/extract data to/from the fixed stuff columns. STS-1 mode with the Fixed Stuff columns configured to carry data:
Register 0X00
Name SPECTRA-155 Configuration
Bit 7 6 1 0
Function TMODE[1] TMODE[0] RMODE[1] RMODE[1]
Set 0 0 0 0
0X87
SPECTRA-155 Configuration
Data
Mode 4 0
RDM_FSEN 1 TDM_FSEN 1
8 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
STS-1 mode with the Fixed Stuff columns configured to NOT carry data:
Register 0X00
Name SPECTRA-155 Configuration
Bit 7 6 1 0
Function TMODE[1] TMODE[0] RMODE[1] RMODE[1]
Set 0 0 0 0
0X87
SPECTRA-155 Configuration
Data
Mode 4 0
RDM_FSEN 0 TDM_FSEN 0
9 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
4
IMPLEMENTATION DETAILS In order to implement the system described above, two interfaces need to be defined. Interface 1 is between the SPECTRA-155 and the HDLC Processor and interface 2 is between the HDLC Processor and an upstream link layer device. All signals are defined in detail in the POS HDLC Processor Design section.
4.1
SPECTRA-155 to POS HDLC Processor Interface The system side interface of the SPECTRA-155 can be configured to operate in a byte wide data bus mode. In this mode of operation the SPECTRA-155 maps/demaps the byte data stream into/from a STS-1 (STM-0/AU3) or STS-3c (STM-1/AU4) SPE. The DROP interface on the SPECTRA-155 consists simply of a receive output clock (which provides the timing for the receive HDLC controller) and an eight bit receive data bus. The ADD bus interface also has an eight bit transmit data bus but consists of two clock signals. The transmit output clock is used to provide timing for the upstream HDLC controller. The transmit input clock is used to clock data into the SPECTRA-155. below shows the interface between the SPECTRA-155 and the POS HDLC Processor. Figure 5: SPECTRA-155 to POS HDLC Processor Interface
DM R O CLK D M R D A T [7:0 ]
D M R IC LK D M R D A T [7 :0]
R eceiv e H D LC C ontro lle r
F IFO
P M 5 34 2 S P E C T R A-1 5 5
D M T IC LK D M T D A T [7:0] D M T O C LK DM TO CLK
P O S H D LC P ro cessor (F P G A ) T ransm it HDLC C ontrolle r
D M T D A T [7:0] D M T IC LK
F IFO
10 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
4.2
POS HDLC Processor to Link Layer Device Interface This interface is designed to directly connect to a POS link layer processor using a 256 byte synchronous FIFO interface over which packets are transferred. Figure 6 below shows the interface between the POS HDLC Processor and a PPP link layer processor. Figure 6: POS HDLC Processor to Link Layer Device
P O S H D L C P roc essor T F C LK TENB TDA TSOP TPRT Y T D A T [1 5:0] TM OD TEOP TERR R F C LK RE NB F IF O F U LL RS O P RPRTY R D A T [15:0] RM O D RE O P RE RR Link Layer D ev ice T F C LK TENB TDA TSOP TPRTY T D A T [1 5:0] TM OD TEOP TERR R F C LK RE NB RDA RS O P RP RTY R D A T [15:0] RM O D RE O P RE RR
11 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
5
POS HDLC PROCESSOR DESIGN The POS HDLC Processor is designed into a FPGA. As shown in Figure 5, the POS HDLC Processor is broken down into 2 main sections; transmit and receive. The transmit section is also broken down into two separate blocks; a transmit HDLC controller and a transmit FIFO. Figure 7: Transmit Section
T ran sm it F IF O T IC L K REN B F IFO E M P T Y T X D A T [7:0] TXSO P TXEO P T ransm it H D LC C ontroller T O C LK TENB TDA T D A T [7:0] SO P EO P D M T IC LK
T F C LK TW ENB TDA TPRT Y T D A T [15:0] TM OD TSOP TEOP TERR T P A R IN T T FIF O O V R TPARS EL
T FIF O U R TPAB
D M T D A T [7:0] D M T O C LK
T FC S S E L [1:0] T F C S IN V T FL A G S E L[1:0]
E xtern al pin s
The transmit HDLC controller performs the following functions: * * * * * Encapsulates PPP packets within a POS HDLC frame. Generates opening and closing flag sequence insertion. Can optionally insert a programmable number of flags between consecutive packets. Performs byte stuffing for transparency processing. Performs frame check sequence generation. The HDLC controller supports the generation of both CRC-CCITT and CRC-32 frame check sequences.
12 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
* * *
Can optionally insert FCS (by inverting the FCS) errors for diagnostic purposes. Aborts packets under the direction of the host or when the FIFO underflows. Generates an interrupt if the FIFO underflows
The transmit HDLC controller is clocked by DMTICLK, provided by the SPECTRA155. Flags are inserted whenever the Transmit FIFO is empty and there is no packet to transmit. When there is a new packet in the transmit FIFO, the HDLC Controller operates normally; it removes the packets from the Transmit FIFO and transmits them to the SPECTRA-155 ADD interface. In addition, FCS generation and byte stuffing is performed on the data stream. In the event of a FIFO underflow caused by the FIFO being empty while a packet is being transmitted, the packet is aborted by transmitting the abort sequence. The abort sequence consists of an escape control character (0x7D) followed by the flag sequence (0x7E). Bytes associated with this aborted frame are still read from the FIFO but are discarded and replaced with the flag sequence in the outgoing data stream. Transmission of data resumes when a start of packet is encountered in the FIFO data stream. 5.1 FCS Generator The FCS Generator performs a CRC-CCITT or CRC-32 calculation on the whole POS frame, before byte stuffing and data scrambling. A parallel implementation of the CRC polynomial is used. The CRC algorithm for the frame checking sequence (FCS) field is either a CRC-CCITT or CRC-32 function. The CRC-CCITT is two bytes in size and has a generating polynomial g(X) = 1 + X5 + X12 + X16. The CRC-32 is four bytes in size and has a generating polynomial g(X) = 1 + X + X2 + X4 + X5 + X7 + X8 + X10 + X11 + X12 + X16 + X22 + X23 + X26 + X32. The first FCS bit transmitted is the coefficient of the highest term. When transmitting a packet from the Transmit FIFO, the FCS generator appends the result after the last data byte, before the closing flag.
13 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
Figure 8:
CRC-32 Generator
g1
g2
g n-1
D0
D1
D2
D n-1
M e ssa ge
LS B
P arity C heck D igits
MSB
An error insertion mechanism is provided for system diagnosis purposes. Error insertion is performed by inverting the resulting FCS value, before transmission. This should cause an FCS Error at the far end. 5.2 Byte Stuffing The transmit HDLC controller provides transparency by performing byte stuffing. Byte stuffing is required to escape real data that looks like special control characters. This operation is done after the FCS calculation. Two characters are being escaped (see Table 1 below), the Flag Sequence (0x7E) and the Escape Character itself (0x7D). When a character is being escaped, it is xored with 0x20 before transmission and preceded by the Control Escape (0x7D) character. Table 1 Byte Stuffing Characters Escaped sequence 7D-5E 7D-5D
Original PPP Data 7E (Flag Sequence) 7D (Control Escape)
The transmit HDLC controller is shown below in Figure 9.
14 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
Figure 9: Transmit HDLC Controller
T ransm it H D LC C ontroller T O C LK TENB TDA T D A T [7:0] SO P EO P D M T IC LK
T FIF O U R TPAB
D M T D A T [7:0] D M T O C LK
T FC S S E L[1 :0] T F C S IN V T FL A G S E L[1:0]
Pin Name TOCLK
Type Output
Function The Transmit Output Clock (TOCLK) is a buffered version of DMTICLK and is used to clock data out of the transmit FIFO into the transmit HDLC controller. The Transmit Enable signal is used to initiate reads from the transmit FIFO. When sampled low using the rising edge of TOCLK, a byte is transferred from the transmit FIFO to the transmit HDLC controller. This signal is updated on the rising edge of TOCLK. The Transmit Data Available signal indicates that there is data in the FIFO ready to be transmitted. The TDA signal will transition high when the minimum packet length (2 bytes) of data has been written into the FIFO. TDA will transition low when the FIFO is empty. TDA is sampled on the rising edge of TOCLK. The Transmit Data (TDAT) bus contains the raw POS data. TDAT is sampled on the rising edge of TOCLK. The Start of Packet (SOP) signal indicates that the byte being currently read in is the first byte of the packet. SOP is sampled on the rising edge of TOCLK.
15
TENB
Output
TDA
Input
TDAT[7:0] SOP
Input Input
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
EOP
Input
The End of Packet (EOP) signal indicates that the byte being currently read in is the last byte of the packet. EOP is sampled on the rising edge of TOCLK. The Data Mode Transmit Input Clock (DMTICLK) is the timing reference for the HDLC controller. DMTICLK is tied to both the TOCLK, which is used to clock data into the HDLC controller from the transmit FIFO, and the DMTOCLK, which is used to clock data into the SPECTRA-155. DMTICLK is nominally a 18.72 MHz or 6.192 MHz clock generated by gapping a 19.44 MHz or 6.48 MHz clock respectively. The Data Mode Transmit Data (DMTDAT) bus contains the HDLC frame to be mapped into the SONET/SDH SPE. DMTDAT is updated on the rising edge of DMTICLK. The Data Mode Transmit Output Clock (DMTOCLK) provides timing to clock data into the SPECTRA-155. The Transmit FCS Select (TFCSSEL) input pins are used to select between no CRC insertion, CRC-CCITT insertion, or CRC-32 insertion. See Table 2 for configuration specifications. The TFSCSEL pins are sampled on the rising edge of TOCLK. The Transmit FCS Invert (TFCSINV) signal is used to invert the FCS which should cause an FCS error at the far end. TFCSINV is sampled on the rising edge of TOCLK. The Transmit Flag Select (TFLAGSEL) pins are used to program the number of flags to be transmitted between consecutive packets. See Table 3 below for configuration details. This signal is sampled on the rising edge of TOCLK. The Transmit FIFO Under Run (TFIFOUR) signal is used to indicate that a FIFO under run occurred, that is, the FIFO emptied before an End of Packet was detected. This signal is updated on the rising edge of TOCLK. The Transmit Packet Abort (TPAB) signal is used to indicate that the packet currently transmitted was aborted. This signal is updated on the rising edge of TOCLK.
16
DMTICLK
Input
DMTDAT[7:0]
Output
DMTOCLK TFCSSEL[1:0]
Output Input
TFCSINV
Input
TFLAGSEL[1:0]
Input
TFIFOUR
Output
TPAB
Output
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
Table 2
Transmit FCSSEL Configuration Description No FCS insertion 2 byte CRC-CCITT insertion 4 byte CRC-32 insertion Reserved
FCSSEL[1:0] 00 01 10 11
Table 3
FLAGSEL Configuration Description 1 flag sequence is transmitted between consecutive packets. That is only one Flag sequence is used to indicate both the end of packet and the start of packet if the packet are immediately after each other, that is, there is no time delay between transmitting the end of packet flag for packet n and transmitting the first byte of packet n+1. 2 flag sequences is transmitted between consecutive packets. That is, each packet is started with a flag sequence and ended with a flag sequence. 8 flag sequences are transmitted between consecutive packets 16 flag sequences are transmitted between consecutive packets
FLAGSEL[1:0] 00
01
10 11
17 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
Figure 10: Transmit HDLC Controller - detailed view
TSO PI F IF O U R PA B TE N B TD A F LAG SEL [1 :0] F C SIN V F C SSE L [1:0 ] SO P EO P Insert A bor t S equ en ce
C on trol
Insert F lag sequenc e
C a lc u la te FCS
In sert F C S
B yte S tuff
D a ta
The flow of data in the transmit direction is shown above in Figure 10. As data is read out of the transmit FIFO it passes through the Byte Stuff block which searches for Control Escape characters and "stuffs" them to provide transparency in the transmit stream. At the same time, control signals from the transmit FIFO, such as SOP and EOP tell the controller whether the byte is the first byte or the last byte of the packet. , The controller appropriately insert flag sequences by controlling the input to the mux. The assertion of both the SOP and EOP signals simultaneously indicates that the current packet should be aborted and the controller consequentially inserts the abort sequence in the transmit data stream. When an EOP is detected, the controller inserts both the FCS and a flag sequence, in that order, into the transmit data stream.
18 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
T ransm it D ata M ux
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
Figure 11: Transmit HDLC Controller State Machine
S tate: S 1 - insert F lag sequ en ces accordin g to F L AG S E L [1 :0 ] settin gs - deass ert TE N B
SOP EOP SO P
S1
A ny
D a ta
D id a S O P e rro r o c cur?
S tate: S 2 - if B Y TE stu ffin g deassert T E N B for 1 cycle
A ny
N
o
S2
A s se rt TS O P I inte rrup t
Y es
D a ta EOP
Y
es
Is F L A G S E L = 1
N o
D id T D A g o lo w ?
S tate: S 3 - in sert F C S an d E O F - deass ert TE N B for 3 or 5 cycles depen din g on F C SS E L
D a ta
Y
es
N o
SOP
S3
A s se rt F IF O und e r run i nte r rup t
S tate: S 4 - tran sm it abort sequ en ce - deass ert TE N B
SO P
S4
A ny TERR A ny
S tate: S 5 - tran sm it con tin ou s flags
S5
A ny
The Transmit HDLC (THDLC) Controller State Machine is comprised of 5 states. State S5 is the default state. In this state the THDLC Controller will continuously transmit flag sequences until a Start of Flag signal is detected, at which point the state machine will transition to state S2. Note that in this situation, a transition to state S1 does not occur because a Start of Flag sequence does not have to be inserted in the transmit stream since in state S5 the THDLC Controller was already continuously transmitting flag sequences. In state S2, the data is just transmitted directly unless an escape sequence is detected, in which case byte stuffing is performed. The state machine will remain in state S2 as long as the control signals indicate that data is being transmitted. The THDLC Controller will transition to state S4 if any signal other than the End of Packet signal is detected. If, for example, the FIFO empties (that is TDA goes Low) before an End of Packet signal is detected, the THDLC Controller will assert the FIFO underrun interrupt signal and transition
19 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
into state S4. The state machine will transition from state S2 to state S3 if an End of Packet signal is detected. In state S3, the End of Packet flag sequence is inserted in the transmit data stream. The FCS can also optionally, depending on the FCSSEL[1:0] settings, be inserted into the transmit data stream. The FCS precedes the End of Packet flag sequence. A transition to the default state, S5, will occur if any signal other than the Data or Start of Packet signal is detected. If either the Data or Start of Packet signals are detected, a transition to either state S2 or state S1 will occur depending on the FLAGSEL[1:0] settings. If FLAGSEL[1:0] is set to 00, that is, only one flag sequence is transmitted between consecutive packets, than the state machine will transition from state S3 to state S2 otherwise the transition will be from state S3 to state S1. A transition into state S4 indicates that an error has occurred and that the current packet is to be aborted. Hence in state S4, the current packet is aborted by transmitting the abort sequence. The Packet Abort signal is also asserted. The state machine will transition from state S4 to S5 if any signal other than the Start of Packet signal, in which case a transition to state S1 will occur, is detected. In state S1 the Start of Flag sequence is inserted into the transmit data stream. If any other signal other than the Data or End of Packet signals are detected the state machine will transition from state S1 to S4. The state machine will transition from state S1 to S2 if the control signals indicate that the next byte is Data or will transition from state S1 to S3 if the next byte is also the end of packet. The transmit FIFO, shown in Figure 12, is responsible for holding packets provided through the input interface until they are transmitted. The transmit FIFO can accommodate a maximum of 256 bytes. Octets are written in with a single 16 bit data bus clocked by TFCLK and read out with a single 8 bit data bus clocked by TICLK. Separate read and write clocks provide for rate decoupling between the line side and system side timing domains.
20 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
Figure 12: Transmit FIFO
T ransm it F IF O
T F C LK TW ENB TDA TPRTY T D A T [1 5:0] TM OD TSOP TEOP TERR T P A R IN T T FIF O O V R TP ARSE L
T IC LK RENB F IFO E M P T Y
T X D A T [7:0] T XS O P T XE O P
Pin Name TFCLK
Type Input
Function The Transmit FIFO Clock (TFCLK) is used to write POS data into the 256 byte transmit FIFO. TFCLK cycles at a 50 MHz or lower instantaneous rate.
TWENB
Input
The Transmit Write Enable (TWENB) signal is an active low input which is used to initiate writes to the transmit FIFO. When sampled low using the rising edge of TFCLK, the word on the TDAT bus is written into the transmit FIFO. When sampled high using the rising edge of TFCLK, no write is performed. The TDA signal indicates that the FIFO is not full and thus can accept at least a full word. When TDA is low the FIFO is full. This signal is updated on the rising edge of TFCLK. The Transmit Start Of Packet (TSOP) signal marks the start of a packet on the TDAT bus. When TSOP is high, the first word of the packet structure is present on the TDAT bus. TSOP is required to be present at the beginning of every packet. An interrupt is generated if TSOP is high during any word other than the first word of the packet structure. TSOP is sampled on the rising edge of TFCLK and is considered valid only when TENB is simultaneously asserted.
21
TDA
Output
TSOP
Input
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
TPRTY
Input
The Transmit Parity (TPRTY) signal indicates the parity of the TDAT[15:0] bus. Odd or even parity selection is made using the PARSEL input.
TDAT[15:0]
Input
The Transmit Data Bus (TDAT[15:0]) carries the POS packet octets that are written to the transmit FIFO. TDAT[15:0] is sampled on the rising edge of TFCLK and is considered valid only when TENB is simultaneously asserted. The Transmit Transfer size signal (TMOD) indicates the number of bytes transferred in the current word (modulo 2). TMOD is only used during the last cycle of a packet transfer, that is, when TEOP is asserted. This signal is sampled on the rising edge of TFCLK. The Transmit Error (TERR) signal is used to indicate the current packet should be aborted. This signal is sampled on the rising edge of TFCLK. The Transmit End Of Packet (TEOP) signal is used to indicate the last word of a packet transfer. The receive size TMOD signal identifies how many bytes are valid during an end of packet cycle. This signal is sampled on the rising edge of TFCLK. The Transmit Parity Select (TPARSEL) signal is used to select between odd or even parity. A logic level High on this input selects odd parity while a logic level Low selects even parity. This signal is sampled on the rising edge of TFCLK. The Transmit Parity Interrupt (TPARINT) signal is used to indicate that a parity error was detected on TDAT[15:0]. This signal is updated on the rising edge of TFCLK. The Transmit FIFO Over Run (TFIFOOVR) signal is used to indicate that a FIFO over run has occurred. This signal is updated on the rising edge of TFCLK.
TMOD
Input
TERR
Input
TEOP
Input
TPARSEL
Input
TPARINT
Output
TFIFOOVR
Output
22 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
TXSOP
Output
The Transmit Start of Packet (TXSOP) signal is used to indicate, to the HDLC controller, that the byte currently being read out of the FIFO is the first byte of the packet. This signal is updated on the rising edge of TICLK. The Transmit End of Packet (TXEOP) signal is used to indicate, to the HDLC controller, that the byte currently being read out of the FIFO is the last byte of the packet. This signal is updated on the rising edge of TICLK. The Transmit Data (TXDAT) bus contains the raw data. This data is encapsulated in an HDLC frame by the transmit HDLC controller. This signal is updated on the rising edge of TICLK. The FIFOEMPTY signal indicates that there is no more data in the FIFO. The FIFOEMPTY signal will transition low when the minimum packet length (2 bytes) of data has been written into the FIFO. FIFOEMPTY will transition high when the FIFO is empty. The Receive Enable (RENB) signal is used to initiate reads from the transmit FIFO. This signal is sampled on the rising edge of TICLK. The Transmit Input Clock (TICLK) is used to clock data out of the transmit FIFO.
TXEOP
Output
TXDAT[7:0]
Output
FIFOEMPTY
Output
RENB
Input
TICLK
Input
The receive section is also broken down into two separate blocks; a receive HDLC controller and a receive FIFO.
23 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
Figure 13: Receive Section
R eceiv e F IFO R F C LK RRE NB RDA RPRTY R D A T [1 5:0] RM O D RSO P REO P RER R RP AR SEL R F IF O O V R R IC LK REN B F IF O F U LL R X D A T [7 :0] RXSO P RXEO P RXER R R ece iv e H D LC C on trolle r R O C LK REN B RDA R D A T [7:0] SO P EO P ERR R F C S S E L[1:0] R F C S IN V D M R IC LK
D M R D A T [7 :0]
E xternal pins
The receive HDLC controller performs the following functions: * * Performs flag sequence detection and terminates the received HDLC frame. Performs frame check sequence (FCS) validation. The HDLC controller supports the validation of both CRC-CCITT and CRC-32 frame check sequences. Performs Control Escape de-stuffing. Checks for a packet abort sequence. The HDLC controller does not perform self synchronous PPP de-scrambling on the SPE payload since this function is already performed by the SPECTRA-155. Generates interrupts on FIFO overflows.
* * *
*
The receive HDLC controller accepts data one byte at a time from the SPECTRA155 and arranges it as POS framed octets. Frame boundaries are found by searching for the Flag Character (0x7E). Flags are also used to fill inter-packet spacing. This block removes the Flag Sequence and passes the data onto the Byte Destuffing block. In the event of a FIFO overflow caused by the FIFO being full while a packet is being received, the packet is marked with an error, by asserting the ERR signal, so
24 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
it can be discarded by the system. Following bytes associated with this now aborted packet are discarded by the Receive HDLC Controller. Reception of POS data resumes when a Start of Packet is encountered. 5.3 Byte Destuffing The byte destuffing algorithm searches the Control Escape character (0x7D). These characters are added for transparency in the transmit direction, as shown in Table 1, and must be removed to recover the user data. When the Control Escape character is encountered, it is removed and the following data byte is XORed with 0x02. Only the Flag Sequence (0x7E) and the Control Escape character itself are expected to have been escaped in the transmit direction, but this implementation does not preclude escaping other values as well. Table 4 Byte Destuffing Characters De-stuffed Data 7E 7D
Stuffed POS Data 7D-5E 7D-5D 5.4 FCS Check
The FCS Generator performs a CRC-CCITT or CRC-32 calculation the whole POS frame, after byte destuffing and data descrambling scrambling. A parallel implementation of the CRC polynomial is used. The CRC algorithm for the frame checking sequence (FCS) field is either a CRC-CCITT or CRC-32 function. The CRC-CCITT is two bytes in size and has a generating polynomial g(X) = 1 + X5 + X12 + X16. The CRC-32 is four bytes in size and has a generating polynomial g(X) = 1 + X + X2 + X4 + X5 + X7 + X8 + X10 + X11 + X12 + X16 + X22 + X23 + X26 + X32. The first FCS bit transmitted is the coefficient of the highest term. The decoder is designed such that after computation over the whole packet, including the FCS field, the result should be all zeros. A different value indicates an error. Packets with FCS errors are marked as such and should be silently discarded by the system.
25 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
Figure 14: CRC-32 Decoder
g1
g2
gr-1
M e ssag e
+
D0
+
D1
+
...
+
D r-1
The Receive HDLC controller is shown below in Figure 15. Figure 15: Receive HDLC Controller
R ece iv e H D LC C on trolle r RO CLK RE NB RDA R D A T [7:0 ] SO P EO P ERR R F C S S E L[1:0] R F C S IN V D M R IC LK
D M R D A T [7 :0]
Pin Name ROCLK RENB
Type Output Output
Function The Receive Output Clock (ROCLK) is a buffered version of DMRICLK and is used to clock data into the receive FIFO. The Receive Read Enable (RENB) signal is used to initiate reads from the receive FIFO. RENB is updated on the rising edge ROCLK. The Receive Data Available (RDA) signal is used to indicate that the FIFO is not full and thus can accept at least one word of data. The Receive Data (RDAT) bus contains the extracted POS data. RDAT is updated on the rising edge of ROCLK.
26
RDA
Input
RDAT[7:0]
Output
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
DMRICLK
Input
The Data Mode Receive Input Clock (DMRICLK) is the timing reference for the receive HDLC controller. DMRICLK is tied to ROCLK, which is used to clock data from the receive HDLC controller into the receive FIFO. DMRICLK is used to clock in DMRDAT. The Data Mode Receive Data (DMRDAT) bus contains the SONET/SDH SPE receive payload data. DMRDAT is sampled on the falling edge of DMRICLK. The Receive FCS Select (RFCSSEL) pins are used to select between no CRC, CRC-CCITT or CRC-32 calculation. See Table 5 below for configuration details. RFCSSEL pins are sampled on the rising edge of ROCLK. The Receive FCS Invert (RFCSINV) signal is used to invert the FCS calculation. When RFCSINV is High, the FCS calculation is inverted. When RFCSINV is Low, the FCS is calculated normally. RFCSINV is sampled on the rising edge of ROCLK. The Start of Packet (SOP) signal is used to indicate that the byte currently being written out of the receive HDLC controller is the first byte of the packet. This signal is updated on the rising edge of ROCLK. The End of Packet (EOP) signal is used to indicate that the byte currently being written out of the receive HDLC controller is the last byte of the packet. This signal is updated on the rising edge of ROCLK. The Error (ERR) signal is used to indicate that an error in the receive data stream was encountered, that is, and abort sequence could have been detected or an insufficient number of flags between packets, etc. This signal is updated on the rising edge of ROCLK.
DMRDAT[7:0]
Input
RFCSSEL[1:0]
Input
RFCSINV
Input
SOP
Output
EOP
Output
ERR
Output
Table 5
Receive FCSSEL Configuration Description No FCS calculation
27
FCSSEL[1:0] 00
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
FCSSEL[1:0] 01 10 11 CRC-CCITT calculation CRC-32 calculation Reserved
Description
Figure 16: Receive HDLC Controller - detailed view
F C S IN V F C S S E L[1:0 ] R EN B
C ontrol
RDA SOP EOP ERR
D ata
F la g D elin eate
B yte D e-S tuff
FCS
R D A T[7:0 ]
The flow of data through the receive HDLC Controller is shown above in Figure 16. As data is received, flag sequences are removed from the data path. The controller keeps track of whether or not the flag sequence is the first flag sequence, indicating a SOP (Start of Packet), or the second flag sequence, indicating an EOP (End of Packet) of the received packet. The data is then de-stuffed, that is, escape characters that were inserted in the transmit stream are removed (see Sections 5.2 and 5.3). When the controller detects an End of Packet, it removes the preceding two or four bytes, depending on the FCS selection (CRC-CCITT or CRC-32). A FCS is calculated on the de-stuffed data. The calculated FCS is then compared to the FCS removed from the data stream to see if they match. If they match, then the data can be assumed to have been received correctly, otherwise an error has occurred and the controller will assert the ERR signal.
28 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
Figure 17: Receive HDLC Controller State Machine
S tate: S 1 - rem ove F lag sequ en ce - insert S OP - deassert R E N B for 1 cycle
S1
D a ta
S tate: S 2
N
o es
- if B Y T E destu ffin g deassert R E N B for 1 cycle
Is F L A G S E L = 1
S2
Y
EO P D a ta
SOP
Ins e rt S O P
A ny
S tate: S 3 - com pare an d rem ove F C S - deassert R E N B for 3 or 5 cyc les depen din g on F C SS E L - rem ove E O F - insert E OP
SOP SO P D a ta
S3
A ny
Is F L A G S E L = 1
Y es N
SO P
o
F C S E rr or
S tate: S 4 - assert R E R R - deassert R E N B
S4
Is F L A G S E L = 1
N
o
Y es
A ny A ny
S tate: S 5 - H u nt state
S5
A ny
The Receive HDLC (RHDLC) Controller State Machine is comprised of 5 states. State S5 is the default state. In this state, the RHDLC Controller is continuously searching for a flag sequence followed by a byte of data. If this flag sequence followed by a byte of data sequence is detected than the state machine will transition from state S5 to state S1, otherwise it will remain in state S5. In state S1, the flag sequence is removed from the data stream. The data byte, along with a Start of Packet indication is written into the FIFO. A transition from state S1 to state S2 will occur if the next byte is a Data byte, anything else will cause a transition to state S4. In state S2 the incoming data is written directly into the FIFO unless an escape sequence is detected, in which case the data is de-stuffed. The state machine will remain in state S2 as long as Data is being received. The reception of a flag sequence would indicate an end of packet and will cause a transition from state S2 to S3, anything else will cause a transition to state S4. In state S3 the FCS, which was calculated on the just received packet, is compared to the FCS
29 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
transmitted for the current packet to check for errors. If errors are detected, a transition to state S4 occurs. If the RHDLC Controller is configured to detect only one flag sequence between consecutive packets and the byte following the just received flag sequence is data, and not another flag sequence, then a transition from state S3 to S2 will occur. The start of packet indication will also be asserted. If errors are detected, a transition to state S4 occurs. If the RHDLC Controller is not configured to detect only one flag sequence between consecutive packets and the byte following the just received flag sequence is data, and not another flag sequence, then a transition from state S3 to S4 will occur. If the RHDLC Controller is configured to detect more than one flag sequence between packets and the byte following the last received flag sequence is another flag sequence than a transition from state S3 to S5 will occur. If the RHDLC Controller is configured to detect more than one flag sequence between packets and the byte following the last received flag sequence is data and not another flag sequence than a transition from state S3 to S4 will occur. In state S4 the RERR signal is asserted to indicate to the link layer device that an error has occurred with the current packet and that it should be aborted. The receive FIFO is used to provide rate decoupling between the line side and system side timing domains. The receive FIFO interface is shown below in Figure 18. Figure 18: Receive FIFO
R eceiv e F IF O R F C LK RRE NB RDA RPRTY R D A T [1 5:0] RM O D RSO P REO P RER R PAR SEL F IFO O V R R IC LK REN B F IF O F U LL R X D A T [7 :0] RXSO P RXEO P RXER R
Pin Name RFCLK
Type Input
Function The Receive FIFO Read Clock (RFCLK) is used to read the POS packets from the receive FIFO's. RFCLK must cycle at a 50 MHz or lower instantaneous rate, but at a high enough rate
30
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
to avoid FIFO overflows. RRENB Input The Receive Read Enable (RRENB) signal is used to initiate reads from the receive FIFO. When sampled low using the rising edge of RFCLK, a byte is read (if one is available) from the receive FIFO and output on the RDAT bus. RRENB must operate in conjunction with RFCLK to access the FIFO's at a high enough rate to prevent FIFO overflows. The Link layer device may de-assert RENB at anytime if it is unable to accept another byte. RRENB is sampled on the rising edge of RFCLK. RDA Output The Receive Data Available (RDA) signal indicates that there is data in the FIFO available to be read out. RDA is updated on the rising edge of RFCLK. The Receive Start of Packet (RSOP) signal marks the start of a packet on the RDAT bus. RSOP is updated on the rising edge of RFCLK. The Receive Parity (RPRTY) signal indicates the parity of the RDAT bus. Odd or even parity selection is made using the PARSEL pin. RPRTY is updated on the rising edge of RFCLK. The Receive Packet Data Bus (RDAT[15:0]) carries the POS packet octets that are read from the receive FIFO. RDAT is updated on the rising edge of RFCLK. The Receive transfer size (RMOD) signal indicates the number of bytes transferred in the current word (modulo 2). RMOD is only used during the last cycle of a packet transfer, that is, when REOP is asserted. RMOD is updated on the rising edge of RFCLK. The Receive End Of Packet (REOP) signal indicates the last word of a packet transfer. The receive size RMOD signal identifies how many bytes are valid during an end of packet cycle. REOP is updated on the rising edge of RFCLK. The Receive Error (RERR) indicator is used to indicate that the current packet is aborted and should be discarded. RERR is updated on the rising edge of RFCLK. The Receive Input Clock is a buffered version of DMROCLK
31 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
RSOP
Output
RPRTY
Output
RDAT[15:0]
Output
RMOD
Output
REOP
Output
RERR
Output
RICLK
Input
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
and is used to clock data in to the receive FIFO from the receive HDLC controller. RENB Input The Receive Enable (RENB) signal is used initiate writes into the receive FIFO from the receive HDLC controller. RENB is sampled on the rising edge of RICLK. The FIFOFULL signal is used to indicate to the HDLC controller that the FIFO is full and can accept no more writes. FIFOFULL is updated on the rising edge of RICLK. The Receive Data (RXDAT) bus contains the POS data. RXDAT[7:0] are sampled on the rising edge of RICLK. The Receive Start of Packet (RXSOP) signal is used to indicate that the byte currently being read into the FIFO is the first byte of the packet. This signal is sampled on the rising edge of RICLK. The Receive Endo of Packet (RXEOP) signal is used to indicate that the byte currently being read into the FIFO is the last byte of the packet. RXEOP is sampled on the rising edge of RICLK. The Receive Error (RXERR) signal is used to indicate that the packet currently being read out of the FIFO has been aborted. RXERR is sampled on the rising edge of RICLK.
FIFOFULL
Output
RXDAT[7:0] RXSOP
Input Input
RXEOP
Input
RXERR
Input
32 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
6
FUNCTIONAL TIMING Figure 19: Transmit HDLC Controller - SPECTRA-155 Timing
DM T IC LK DM T O C LK DM T DA T [7:0] 1 2 3 260 261 262 263 264
Figure 19 above shows the basic transmit bus timing between the SPECTRA-155 and the transmit HDLC Controller. DMTOCLK is a gapped clock used to clock data to the SPECTRA-155. Data bytes on the DMTDAT[7:0] bus are updated on the rising edge of DMTICLK. In STS-1 (STM-0/AU3) data mode, the gapped clock is generated using a 6.48 MHz clock. The nominal frequency of DMTICLK is 6.048 MHz if each transmitted synchronous payload envelope (SPE) has two fixed stuff columns. Otherwise, the nominal frequency of DMTICLK is 6.192 MHz. In STS-3c (STM-1/AU4) data mode, the gapped clock is generated using a 19.44 MHz clock. The nominal frequency of DMTICLK is 18.72 MHz.
33 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
Figure 20: Transmit HDLC Controller - FIFO Interface timing
TOCLK TDA TENB TDAT SOP EOP ERR FLAGSEL1 FLAGSEL0 FCSSEL1 FCSSEL0
1 2 3 4 1 2
12
1
2
Figure 20 above shows the basic functional timing between the Transmit HDLC Controller and the transmit FIFO.
34 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
Figure 21: Transmit FIFO - Link Layer Timing
TFCLK FIFOFULL TWENB TDAT[15:0] TSOP TEOP TMOD TERR 1-2 3-4 5-6 7-8 1-2 31-2
The transmit FIFO timing diagram (Figure 21) illustrates the basic operation of the drop side transmit FIFO timing. Assertion of the FIFOFULL signal indicates that the FIFO is full and can accept no more writes. TSOP must be high during the first word of the packet and must be present (reasserted) for each packet. TMOD is only used on the last word of the packet and is used to determine if the last word of the packet is composed of one or two bytes. If TSOP is asserted and the previous word transfer was not marked with a TEOP, the input interface realigns itself to the new timing, and the previous packet is marked to be aborted. Figure 22: Receive HDLC Controller - SPECTRA-155 Timing
D M R IC LK D MR D A T [7:0] 1 2 3 260 261 262 263 264
Figure 22 above shows the basic receive bus timing between the SPECTRA-155 and the receive HDLC Controller. DMRICLK is a gapped clock. Data bytes on the DMRDAT[7:0] bus are updated on the falling edge of DMRICLK. In STS-1 (STM-0/AU3) data mode, the gapped clock is generated using a 6.48 MHz clock. The nominal frequency of DMRICLK is 6.048 MHz if each received synchronous payload envelope (SPE) has two fixed stuff columns. Otherwise, the nominal frequency of DMRICLK is 6.192 MHz. In STS-3c (STM-1/AU4) data mode, the
35 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
gapped clock is generated using a 19.44 MHz clock. The nominal frequency of DMRICLK is 18.72 MHz. Figure 23: Receive HDLC Controller - FIFO Timing
ROCLK RDA RENB RDAT SOP EOP ERR FLAGSEL FCSINV FCSSEL1 FCSSEL0
1 2 3 4 1 2 1 2
7D 7E
x
x
1
2
3
Figure 23 above shows the basic timing between the Receive HDLC Controller and the Receive FIFO.
36 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
Figure 24: Receive FIFO - Link Layer Timing
RFCLK RDA RRENB RDAT[15:0] RSOP REOP RMOD RERR 1-2 3-4 5-6 7-8 1-2 31-2
The Receive FIFO timing diagram (Figure 24) illustrates the basic timing of the drop side receive FIFO. The receive FIFO indicate that there is data available by asserting the RDA signal. RDA remains high until the receive FIFO is empty. At anytime, the downstream device can throttle back reception of words by deasserting RRENB.
37 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
7
DISCLAIMER The circuits presented in this application note have not been built or simulated. These circuits are therefore preliminary in this release of this document.
38 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
8
REFERENCES 1) PMC-Sierra, Inc., PM5342 SPECTRA-155 Data Sheet, Issue 2, Dec, 1996. 2) Network Working Group Request For Comments: RFC 1619 , May 1994.
39 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
NOTES
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1998 PMC-Sierra, Inc. PM-971133 (R4) ref PMC-xxxxxx (Rx) Issue date: February 1998
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
PRELIMINARY APPLICATION NOTE PMC-971133 ISSUE 1
PM5342
PACKET OVER SONET
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1998 PMC-Sierra, Inc. PM-971133 (R4) ref PMC-xxxxxx (Rx) Issue date: February 1998
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000

▲Up To Search▲

Price & Availability of 1971133

	To Download 1971133 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .