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PM73121 AAL1GATOR II
ERRATA PMC-980825 ISSUE 3 EIGHT LINK CIRCUIT EMULATION SERVICE ON A CHIP
PM73121
EIGHT LINK CIRCUIT EMULATION SERVICE ON A CHIP
REVISION A DEVICE ERRATA
ISSUE 3: FEBRUARY 1999
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000
PM73121 AAL1GATOR II
ERRATA PMC-980825 ISSUE 3 EIGHT LINK CIRCUIT EMULATION SERVICE ON A CHIP
CONTENTS 1 FEATURES ............................................................................................... 1 1.1 1.2 2 DEVICE IDENTIFICATION............................................................. 1 REFERENCES .............................................................................. 1
FUNCTIONAL DEFICIENCY LIST ........................................................... 2 2.1 2.2 2.3 2.4 2.5 DOES NOT ALWAYS GENERATE A ZERO POINTER WHEN STARTING A QUEUE IN SDF-MF MODE...................................... 3 DATA CELLS MAY BE DROPPED WHEN OAM CELLS ARE GENERATED ................................................................................. 7 BIT INTEGRITY IS NOT ALWAYS MAINTAINED UNDER CERTAIN ERROR CONDITIONS................................................................... 8 BANDWIDTH FOR A DS3 LINE CANNOT ALWAYS BE MAINTAINED WITH A 38.88 MHZ SYSTEM CLOCK .................... 8 BEHAVIOR OF RPHY_SOC WITH RESPECT TO RPHY_CLAV IN PHY MODE.................................................................................... 9
3
(UPDATED) CHANGES TO TIMING PARAMETERS .............................. 10
i PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PM73121 AAL1GATOR II
ERRATA PMC-980825 ISSUE 3 EIGHT LINK CIRCUIT EMULATION SERVICE ON A CHIP
1
FEATURES This document is the Device Errata Sheet for the Revision A of PM73121.
1.1
Device Identification This document applies only to Revision A of the PM73121. As illustrated in Figure 1.1, the Revision Code is marked on the face of the device. The PM73121 Revision A is in a 240-pin PQFP package.
180 121
181
120
PMC LOGO
Name
TM
AAL1gator II
Part Number
PM73121-RI L_______A Lyyww
Wafer Batch Code
240
61
Assembly Date Code
Index Mark
1 60
TOP VIEW SCALE : 3:1 (APPROX.)
Figure 1.1: PM73121-RI Branding Format. 1.2 References
1. PMC-980620, AAL1 SAR Processor Long Form Datasheet, Issue 3 (January 1999).
1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PM73121 AAL1GATOR II
ERRATA PMC-980825 ISSUE 3 EIGHT LINK CIRCUIT EMULATION SERVICE ON A CHIP
2
FUNCTIONAL DEFICIENCY LIST This section describes the known functional deficiencies associated with Revision A of the PM73121, as of the publication date of this document. For each deficiency, the known work-around is also described. Please report any functional deficiencies not covered in this document to PMC-Sierra, Inc. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: (604) 415-6000 Fax: (604) 415-6001 Product information: Applications information: Web Site: info@pmc-sierra.bc.ca apps@pmc-sierra.bc.ca http://www.pmc-sierra.com
2 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PM73121 AAL1GATOR II
ERRATA PMC-980825 ISSUE 3 EIGHT LINK CIRCUIT EMULATION SERVICE ON A CHIP
2.1
Does Not Always Generate a Zero Pointer When Starting a Queue in SDF-MF Mode
Description In SDF-MF mode, the AAL1gator II does not conform with the following text contained in ITU-T Recommendation I.363.1: "... the first structured block to be transmitted after the AAL connection is established uses the P format with sequence count value in the SAR-PDU header equal to 0 and with the first octet of the structured data placed in the second octet of the SAR-PDU payload." Specifically, the start of the structure may not occur in the second octet of the SAR-PDU payload in SDF-MF mode. The AAL1gator II begins sending a cell in the frame in which it is scheduled. Since this frame may or may not be the start of a multiframe, the first byte may or may not be the first byte of a new structure. The pointer will point to wherever the structure begins. The initial (first) pointer generated in SDF-MF mode is deterministic and can be calculated from the following expressions: Let X = Remainder(FRAMES_PER_CELL / MF_SIZE) x NUM_CHAN + SIG_BYTES where: MF_SIZE (for E1) = 16 MF_SIZE (for T1) = 24 SIG_BYTES = the number of signaling bytes in the structure NOTE: If the remainder is 0, then SIG_BYTES should be ignored and the initial pointer is 0.
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PM73121 AAL1GATOR II
ERRATA PMC-980825 ISSUE 3 EIGHT LINK CIRCUIT EMULATION SERVICE ON A CHIP
For full cells:
if X 93 then initial pointer = X else first cell built(sn = 0) will not contain a pointer. initial pointer will be in 3rd cell built (sn = 2). initial pointer = X - (47 x 2) ((47 x 2) accounts for the bytes in the first two cells.) endif
For partial cells:
if X BYTES_PER_CELL then initial pointer = X elseif BYTES_PER_CELL < X (2 x BYTES_PER_CELL) then initial pointer = 46 + (X - BYTES_PER_CELL) else initial pointer will be in sn = 2 cell (3rd cell built). initial pointer = X - (2 x BYTES_PER_CELL) endif
Work Around This non-conformance is not known to cause any incompatibility problems. No workaround is necessary. Typically, robust AAL1 cell receivers can tolerate pointers of any value if the initial pointer is lost in the network. You can also force initial multiframe alignment, and an initial pointer of 0 by increasing the FRAMES_PER_CELL value for the queue so it falls on a multiframe boundary in the transmitter data buffer. Since FRAMES_PER_CELL controls how far back in time data is read, delay increases if FRAMES_PER_CELL increases. The increase will be 125 s for each frame added. For example, for an E1 line with 32 channels allocated, fully filled cells, the initial pointer will be: X = Remainder (3 /16) x 32 + 16 = 112. Since X > 93, the initial pointer = X - (47 x 2) = 18.
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PM73121 AAL1GATOR II
ERRATA PMC-980825 ISSUE 3 EIGHT LINK CIRCUIT EMULATION SERVICE ON A CHIP
Since all queues are added in frame 0 of multiframe 0, the TALP starts building the cell FRAMES_PER_CELL = 3 frames back in the transmit buffer from frame 0 in multiframe. To generate an initial pointer of 0, the TALP must start building the cell on a multiframe boundary (for example, multiframe x frame 0). This can be accomplished by increasing FRAMES_PER_CELL to 16. For T1, with its 24 channels, FRAMES_PER_CELL should be increased to 24 to generate an initial pointer of 0. Figure 1 shows the transmit data organization for E1 and Figure 2 shows the transmit data organization for T1.
M F 0 Fram e 1 M F 0 Fram e 0 M F 7 Fram e 15 M F 7 Fram e 14 M F 7 Fram e 13 M F 7 Fram e 12 ... M F 7 Fram e 2 M F 7 Fram e 1 M F 7 Fram e 0 M F 6 Fram e 15 M F 6 Fram e 14
FR A M E S _ P E R _ C E L L = 1 6 re s u lts in TA L P s ta rtin g h e re . (In itia l p o in te r = 0 ) FR A M E S _ P E R _ C E L L = 3 re s u lts in TA L P s ta rtin g h e re . (In itia l p o in te r = 1 8 ) Q u e u e s a lw a y s a d d e d in M F 0 , fra m e 0 .
Figure 1: Transmit Data Buffer Organization for E1
M F 0 Fram e 1 M F 0 Fram e 0 M F 3 Fram e 23 M F 3 Fram e 22 M F 3 Fram e 21 M F 3 Fram e 20 ... M F 3 Fram e 2 M F 3 Fram e 1 M F 3 Fram e 0 M F 2 Fram e 15 M F 2 Fram e 14
FR AM E S_ PE R _C E LL = 24 r es ul ts in TA LP s tarti ng h e re. ( Initi al p o in te r = 0) FR AM E S_ PE R _C E LL = 3 r es ul ts i n TA LP s tarti ng h er e. (I nitial poin ter = 84) Q ue ues alw a ys ad de d in M F 0, fra m e 0.
Figure 2: Transmit Data Buffer Organization for T1
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PM73121 AAL1GATOR II
ERRATA PMC-980825 ISSUE 3 EIGHT LINK CIRCUIT EMULATION SERVICE ON A CHIP
Table 1 shows the initial (first) pointer value generated in SDF-MF mode and the specific value required to generate an initial pointer of 0 for full cells. Table 1: Initial Pointer for Full Cell Situations
NUM_CHAN FRAMES_ PER_CELL SIG_BYTES 1st Pointer (E1) 1st Pointer (T1) Frames per Cell For 1st Pointer = 0 (for E1) n/a 32 32 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Frames per Cell for 1st Pointer = 0 (for T1) n/a 48 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 n/a n/a n/a n/a n/a n/a n/a n/a
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48 25 17 13 11 9 8 7 7 6 6 5 5 5 5 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3
1 0 0 1 19 3 2 5 53 2 54 54 3 58 58 3 57 57 4 60 60 4 60 60 5 68 68 5 65 65 6 72 72 6 66 66 7 72 72 7 77 77 8 83 83 8 72 72 9 77 77 9 81 81 10 86 86 10 90 90 11 1* 1* 11 5* 5* 12 10* 10* 12 84 84 13 88 n/a 13 91 n/a 14 1* n/a 14 4* n/a 15 8* n/a 15 11* n/a 16 15* n/a 16 18* n/a NOTE* indicates the pointer is in sn = 2.
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PM73121 AAL1GATOR II
ERRATA PMC-980825 ISSUE 3 EIGHT LINK CIRCUIT EMULATION SERVICE ON A CHIP
2.2
Data Cells May Be Dropped When OAM Cells Are Generated
Description If the transmit UTOPIA FIFO fills up due to backpressure on the UTOPIA bus and the last cell written into the FIFO is an OAM cell and another cell request is pending, the pending cell will be dropped. This situation can occur only if an OAM cell fills the FIFO and a cell request is pending as the last byte of the OAM cell is being written into the FIFO. Symptoms of this problem will be SN errors and lost cells detected on the remote end. Since OAM cells are sent at a low rate (usually one per second), the error rate caused by this problem will be quite low. SN processing should minimize the impact of this problem. Work Around Two solutions to this problem are: 1) minimize backpressure on the transmit UTOPIA port, or 2) generate OAM cells by some other means. 1. The UTOPIA bus has a 2-cell FIFO. The shortest amount of time that an OAM could be written into the FIFO is 139 SYS_CLK cycles (3.6 s if SYS_CLK = 38.88 MHz). Therefore, the first cell in the FIFO needs to be written out within 3.6 s to guarantee the FIFO will not fill up. With no backpressure (/TATM_FULL always high) and a 25 MHz UTOPIA clock rate, it takes 2.1 s to write out a cell. Therefore, the worst-case backpressure per cell must be less than 1.5 s.
NOTE: As more lines and queues are added, the time it takes to build an OAM cell increases, since it takes more time to access the processor bus for each word. Therefore, more backpressure can be tolerated before the FIFO fills up. 2. The second solution is to generate OAM cells farther down stream, past the transmit UTOPIA port. Since this problem exists only with OAM cells, the problem cannot occur.
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PM73121 AAL1GATOR II
ERRATA PMC-980825 ISSUE 3 EIGHT LINK CIRCUIT EMULATION SERVICE ON A CHIP
2.3
Bit Integrity is Not Always Maintained Under Certain Error Conditions
Description Bit integrity will not always be maintained when fewer than six cells are missing, or when a single errored cell occurs. There are two specific cases where bit integrity will not be maintained. * If the cell containing a pointer value of 00 or the cell before a cell containing a pointer value of 00 has an SN error and the structure size is greater than the available payload of two cells. For full cell queues that meet these characteristics, there is about a 0.3% chance that a lost cell would cause bit integrity to be lost. If the following sequence of events occurs: (SN = 4, lost cell, lost cell, SN = 7, SN = 0, lost cell) and a pointer is in the cell with SN = 0 and the cell with SN = 7 is the first cell after an underrun. For both of these cases, the AAL1gator II will detect a pointer mismatch error with the next pointer received after the lost cell, and will resynchronize to the next pointer. Work Around There is no work-around for this problem. The chance of this condition occurring is very small, and the overall impact is very minimal. 2.4 Bandwidth for a DS3 Line Cannot Always be Maintained with a 38.88 MHz System Clock
*
Description Bandwidth for a DS3 line cannot always be maintained with a 38.88 MHz system clock. Work Around The AAL1gator II can support a 40 MHz system clock. By using a 40 MHz system clock, the DS3 bandwidth can be maintained as long as the processor accesses the AAL1gator fewer than 100 times per millisecond.
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PM73121 AAL1GATOR II
ERRATA PMC-980825 ISSUE 3 EIGHT LINK CIRCUIT EMULATION SERVICE ON A CHIP
2.5
Behavior of RPHY_SOC with respect to RPHY_CLAV in PHY Mode
Description When PM73121 UTOPIA interface is configured in PHY mode, the devices asserts RPHY-SOC, Receive UTOPIA Layer Start of Cell, when RPHY_DATA contains the first valid byte of the cell. While receiving ATM cells, if the ATM Layer Device keeps /RPHY_EN, Receive PHY Layer Enable, asserted for longer than a cell time, the PM73121 will deassert RPHY_CLAV, Receive UTOPIA Layer Cell Available, at the completion of the cell and simultaneously assert RPHY_SOC. This behavior may confuse some ATM Layer Devices that do not qualify RPHY_SOC signal with RPHY_CLAV signal as required by UTOPIA Level 1 specification: "RxCLAV indicates cycles when there is valid information on RxData/RxSOC." Work Around For those ATM Layer Devices that do not qualify RPHY_SOC with RPHY_CLAV, the solution is to connect the PM73121 RPHY_SOC and RPHY_CLAV signals into an AND gate, and then connect the AND gate output to the RxSOC input of the ATM Layer Device.
9 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE
PM73121 AAL1GATOR II
ERRATA PMC-980825 ISSUE 3 EIGHT LINK CIRCUIT EMULATION SERVICE ON A CHIP
3
(UPDATED) CHANGES TO TIMING PARAMETERS The following timing parameters have been updated in issue 2 of PM73121 AAL1gator Datasheet (PMC-980620). Please refer to the datasheet for additional information:
Fig1 55 58
Description Transmit Side Interface Bit Timing Transmit Side HighSpeed Interface Bit Timing Receive Side LowSpeed Interface Timing Transmit UTOPIA ATM Timing TUTOPIA SPHY Timing TUTOPIA MPHY Timing RAM Write Cycle Timing Microprocessor Memory Write Cycle Timing Microprocessor Memory Write Cycle Timing Memory Read Cycle Timing Memory Read Cycle Timing
Symbol Th Th
Parameter Clock hold Clock hold
Signal RL_SER RL_SER[0]
Min 2 2
Max
Unit ns ns
59
Tq
Clock-to-output delay Clock-to-output delay Clock-to-output delay Clock-to-output delay Write pulse width Clock-to-output delay Clock-to-output delay Clock-to-output delay Clock-to-output delay for activation of /MEM_OE Clock-to-output delay
TL_SIG, TL_SER TATM_DATA RPHY_DATA RPHY_DATA /MEM_WE /PROC_ACK
2
14
ns
63 64 65 74 76
Tq Tq Tq Twp Tq
2 2 2 Tch-1.3 2
13 13 13 Tch+0.3 18
ns ns ns ns ns
76
Tq
/MEM_CS
2
18
ns
77 77
Tq Tqmoe
/MEM_CS /MEM_OE
2 2
18 25
ns ns
78
Microprocessor Command Register Write Cycle Timing
Tq
/PROC_ACK
2
18
ns
1
Figure numbers are from PM73121 Datasheet (PMC-980620).
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PM73121 AAL1GATOR II
ERRATA PMC-980825 ISSUE 3 EIGHT LINK CIRCUIT EMULATION SERVICE ON A CHIP
Fig 82
1
Description Interrupt Timing
Symbol Tq
Parameter Clock-to-output delay
Signal PROC_INTR
Min 2
Max 17
Unit ns
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PM73121 AAL1GATOR II
ERRATA PMC-980825 ISSUE 3 EIGHT LINK CIRCUIT EMULATION SERVICE ON A CHIP
NOTES
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PM73121 AAL1GATOR II
ERRATA PMC-980825 ISSUE 3 EIGHT LINK CIRCUIT EMULATION SERVICE ON A CHIP
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1999 PMC-Sierra, Inc. PMC-980825 (P3) Issue date: February, 1999
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE

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