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| PM6388 EOCTL DEVICE ERRATA PM6388 TM PM6388 EOCTL EOCTL Octal E1 Framer Device Errata Released Issue 2: May, 2001 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use Document ID: PMC-1980835, Issue 2 PM6388 EOCTL DEVICE ERRATA Legal Information Copyright (c) 2001 PMC-Sierra, Inc. The information is proprietary and confidential to PMC-Sierra, Inc., and for its customers' internal use. In any event, you cannot reproduce any part of this document, in any form, without the express written consent of PMC-Sierra, Inc. PMC-1980835 (R2) Disclaimer None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. Trademarks EOCTL, PMC and PMC-Sierra are trademarks of PMC-Sierra, Inc. Patents The technology discussed may be protected by one or more Patents. Relevant patent applications may also exist. Revision History Issue No. 1 2 Issue Date July 27, 1998 May 2001 ECN # None 3984 Details of Change Notification of additional information and errors to EOCTL Data Sheet Issue P4. HDLC controller bit (section 2.1 - 2.3) Transmit Backplane Configuration (section 3.1), CEFP pin description (section 3.2) Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use Document ID: PMC-1980835, Issue 2 2 PM6388 EOCTL DEVICE ERRATA Contacting PMC-Sierra PMC-Sierra 8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: (604) 415-6000 Fax: (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Web Site: http://www.pmc-sierra.com Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use Document ID: PMC-1980835, Issue 2 3 PM6388 EOCTL DEVICE ERRATA Table of Contents Legal Information.................................................................................................................2 Contacting PMC-Sierra........................................................................................................3 Table of Contents.................................................................................................................4 1 Introduction ..................................................................................................................5 1.1 1.2 2 2.1 Device Identification ............................................................................................5 References..........................................................................................................5 Use of the HDLC Controller in E1 Mode (Internal HDLC Controller and Idle Code Insertion) .............................................................................................................6 2.1.1 2.1.2 2.1.3 2.1.4 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.3 2.3.1 2.3.2 2.3.3 2.3.4 3 3.1 Description .............................................................................................6 Workarounds ..........................................................................................6 Performance with workaround ...............................................................6 Performance without workaround ..........................................................6 Description .............................................................................................7 Workarounds ..........................................................................................7 Performance with workaround ...............................................................7 Performance without workaround ..........................................................7 Description .............................................................................................7 Workarounds ..........................................................................................7 Performance with workaround ...............................................................7 Performance without workaround ..........................................................7 Device Functional Deficiency List................................................................................6 Using the Internal HDLC Controller for Timeslot One.........................................7 Using the Internal HDLC Controller to Insert Data in Sa-bit Positions................7 Documentation Deficiency List ....................................................................................8 Transmit Backplane Configuration ......................................................................8 3.1.1 3.1.2 3.1.3 3.2 3.2.1 3.2.2 3.2.3 Location..................................................................................................8 Original Wording.....................................................................................8 Replacement Wording............................................................................8 Location..................................................................................................8 Original Wording.....................................................................................9 Replacement Wording............................................................................9 CEFP Pin Description .........................................................................................8 Notes .................................................................................................................................10 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use Document ID: PMC-1980835, Issue 2 4 PM6388 EOCTL DEVICE ERRATA 1 Introduction In this document: * * Section 2 lists the known functional errata for Revision D of the PM6388 EOCTL. Section 3 lists documentation errors found in Issue 6 of the Data Sheet (PMC-1971019). 1.1 Device Identification The information contained in Section 2 relates to Revision D of the PM6388 Device only. The device revision code is marked at the end of the Wafer Batch Code on the face of the device. Figure 1 PM6388 EOCTL Branding Format Pin 1 Reference 128 103 1 102 PMC Logo Part Number PM6388-RI C ______ D M yyww KOREA 38 65 Wafer Batch Code Assembly Date Code 39 64 Country of Origin 1.2 References * * Issue 6 of the Device PM6388 EOCTL Data Sheet (PMC-1971019). PM6388 EOCTL Technical Overview, Issue 1 (PMC-1971173). Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use Document ID: PMC-1980835, Issue 2 5 PM6388 EOCTL DEVICE ERRATA 2 Device Functional Deficiency List This section lists the known functional deficiencies for Revision D of the EOCTL as of the publication date of this document. For each deficiency, the known workaround and the operating constraints, with and without the workaround, are also described. Please report any functional deficiencies not covered in this document to PMC-Sierra. 2.1 2.1.1 Use of the HDLC Controller in E1 Mode (Internal HDLC Controller and Idle Code Insertion) Description The two least significant bits of timeslot N, where N is a number between 0 and 31, can be corrupted when any of the below statements are true: 1. Timeslot N+1 is configured for HDLC transmission (via the TDPR) and timeslot N is configured for idle code insertion (via the TPSC). 2. Timeslot N is configured for both HDLC transmission and idle code insertion. 3. Timeslot 31 (N = 31) is configured for idle code insertion and the Si-bit of timeslot 0 is configured for HDLC transmission. 2.1.2 Workarounds The following workarounds apply to the above statements respectively: 1. External insertion of idle codes or the use of an external HDLC controller will prevent idle code data corruption. We recommend you use an external HDLC controller if it is necessary to insert idle codes in a timeslot immediately preceding HDLC data. 2. Disable idle code insertion for timeslots that are also configured to transmit HDLC data. 3. External insertion of idle codes or the external insertion of HDLC data in the Si-bit position will prevent idle code data corruption. 2.1.3 Performance with workaround Normal operation. 2.1.4 Performance without workaround The two least significant bits of timeslot N may be corrupted. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use Document ID: PMC-1980835, Issue 2 6 PM6388 EOCTL DEVICE ERRATA 2.2 2.2.1 Using the Internal HDLC Controller for Timeslot One Description If data is inserted into timeslot 1 (via the internal HDLC controller) and the Sa8-bit is configured as externally inserted (via the backplane), the Sa8-bit can be corrupted. 2.2.2 Workarounds The Sa8 bit is not corrupted when insertion is done via the E1-TRAN National Bits Codeword register. We recommend you do not use an internal HDLC Controller for timeslot one. 2.2.3 Performance with workaround Normal operation. 2.2.4 Performance without workaround The Sa8-bit can potentially be corrupted. 2.3 2.3.1 Using the Internal HDLC Controller to Insert Data in Sa-bit Positions Description If the internal HDLC controller is used to insert HDLC data in the Sa8, Sa7, Sa6 or Sa5 bit positions, the more significant bit adjacent to the inserted bit can be corrupted. In other words, HDLC data inserted in Sa8 can corrupt Sa7 and likewise data inserted in Sa5 can corrupt Sa4. 2.3.2 Workarounds National Use Bits (Sa-bits) inserted using the internal E1-TRAN block are always inserted correctly. Avoid using the internal HDLC controller to insert data into the Sa8, Sa7, Sa6, and Sa5 bit positions. 2.3.3 Performance with workaround Normal operation. 2.3.4 Performance without workaround Potential corruption of a National Use (Sa) bit. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use Document ID: PMC-1980835, Issue 2 7 PM6388 EOCTL DEVICE ERRATA 3 Documentation Deficiency List This section lists the known documentation deficiencies for Issue 6 of the Data Sheet (PMC-1971019) as of the publication date of this document. For each specific deficiency, the location of the passage in question, the deficient text, and the replacement text are described. New text is shown in bold. Deleted text is shown as underlined. For more general issues, a description of the nature of the error is given, along with a passage that correctly describes the concept or device function. Please report any documentation deficiencies not covered in this document to PMC-Sierra. 3.1 Transmit Backplane Configuration Registers 018H, 098H, 118H, 198H, 218H, 298H, 318H, 398H: Transmit Backplane Configuration. 3.1.1 Location The description of the Transmit Backplane configuration registers is found in section 10 - Normal Mode Register Description - (on page 98 of the PM6388 EOCTL datasheets). 3.1.2 Original Wording The framing edge (FE) bit determines the edge of CECLK on which the frame pulse (CEFP) pulse is sampled. If FE is a logic 0, CEFP is sampled on the falling edge of CECLK. If FE is a logic 1, CEFP is sampled on the rising edge of CECLK. In the case where FE is not equal to DE, FE is sampled or updated one clock edge before DE. This bit only has effect in clock slave mode. 3.1.3 Replacement Wording The framing edge (FE) bit determines the edge of CECLK on which the frame pulse (CEFP) pulse is sampled. If FE is a logic 0, CEFP is sampled on the falling edge of CECLK. If FE is a logic 1, CEFP is sampled on the rising edge of CECLK. In the case where FE is not equal to DE, EFP is sampled one clock edge before or updated three clock edges before ED and ESIG are sampled. This bit only has effect in clock slave mode. 3.2 CEFP Pin Description CEFP - Common Egress Frame Pulse. 3.2.1 Location The CEFP pin description given in the table in section 8 (page 19). Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use Document ID: PMC-1980835, Issue 2 8 PM6388 EOCTL DEVICE ERRATA 3.2.2 Original Wording Common Egress Frame Pulse (CEFP). CEFP may be used to frame align the framers to the system backplane. If frame alignment only is required, a pulse at least 1 CECLK cycle wide must be provided on CEFP every 256 bit times. 3.2.3 Replacement Wording Common Egress Frame Pulse (CEFP). CEFP may be used to frame align the framers to the system backplane. If frame alignment only is required, a pulse at least 1 CECLK cycle wide must be provided on CEFP every 256 bit times. If operating in "Mixed Mode" (some framers operating in Clock Master Mode and other framers operating in Clock Slave mode) while the Clock Master Mode PLL is referenced to RLCLK[x], you should remove CEFP after the framers in Clock Slave Mode are aligned. Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use Document ID: PMC-1980835, Issue 2 9 PM6388 EOCTL DEVICE ERRATA Notes Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use Document ID: PMC-1980835, Issue 2 10 |
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