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| PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN PM5357 S/UNI-622-POS SATURN USER NETWORK INTERFACE (622-POS) REFERENCE DESIGN PROPRIETARY AND CONFIDENTIAL PRELIMINARY ISSUE 2: FEBRUARY 2000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN PUBLIC REVISION HISTORY Issue No. 2 Issue Date January 2000 Details of Change Rev 2 to Rev 3 schematic change: Removed the analog 8KHz t o77.76MHz PLL. The reference designations on the Issue 3 schematics match those on the Rev 1 PCB. At this time, there are no plans to build a PCB to Issue 3 schematics. Rev 1 to Rev 2 schematic change to support uP cPCI: Removed WAN clocking, removed local uP in lieu of the cPCI I/F, analog 8KHz to 77.76MHz PLL was added for internal testing, replaced 5V to 3.3V Linear regulator filter for S/UNI-622-POS analog power pins with RC passive 3.3V filters, add programmable FPGA for drop side ATM/Packets. Rev 1 PCB was fabricated to Rev 2 schematics. Issue 1.5 document was never issued. Document created with Rev 1 Schematics. No PCB made to Rev 1 Schematics. Only a paper design. Document posted on intranet. 1.5 August 2000 1 Nov 1998 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN CONTENTS 1 2 3 INTRODUCTION...................................................................................... 1 S/UNI-622-POS BLOCK DIAGRAM......................................................... 3 APPLICATIONS ....................................................................................... 4 3.1 3.2 3.3 3.4 3.5 3.6 4 5 6 ATM DROP SIDE LOOP-BACK .................................................... 4 ATM TRANSPARENT.................................................................... 5 POS SOURCE AND RECEIVE PACKETS.................................... 6 POS TRANSPARENT ................................................................... 6 REFERENCE PCB WITH OTHER PMC-SIERRA ATM CHIPS..... 7 USING THE REFERENCE BOARD WITH PACKET SWITCH ..... 8 REFERENCES......................................................................................... 9 SYSTEM FUNCTIONAL DESCRIPTION ............................................... 10 FUNCTIONAL DESCRIPTION................................................................11 6.1 6.2 6.3 6.4 6.5 BLOCK DIAGRAM .......................................................................11 S/UNI-622-POS............................................................................11 MICROPROCESSOR INTERFACE ............................................ 13 EXTERNAL CONNECTORS ....................................................... 13 UTOPIA AND POS-PHY DROP SIDE INTERFACE .................... 13 7 IMPLEMENTATION DESCRIPTION ...................................................... 15 7.1 7.2 ROOT DRAWING, SHEET 1 ....................................................... 15 ODL AND 77.76 MHZ REFERENCE, SHEET 2 .......................... 15 7.2.1 622 MBIT/S OPTICAL INTERFACE ................................. 15 7.2.2 77.7600 MHZ REFERENCE CLOCK CIRCUITRY ........... 18 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE i PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 7.3 POS_BLOCK, SHEET 3.............................................................. 23 7.3.1 LOOP FILTER CAPACITOR ............................................. 24 7.3.2 PULLUP AND PULLDOWN RESISTORS ........................ 24 7.4 POWER SUPPLY FILTER FOR THE PM5357 SHEET 4............ 25 7.4.1 PASSIVE RC LOW PASS POWER SUPPLY FILTER ...... 25 7.4.2 LINEAR REGULATOR FILTER METHOD ........................ 29 7.5 7.6 FPGA, SHEET 5 AND 6 .............................................................. 31 CPCI BUS INTERFACE SHEET 7 .............................................. 31 7.6.1 CPCI BACKPLANE CONNECTOR J1.............................. 32 7.6.2 PLX CPCI BRIDGE CHIP, PCI9050 ................................. 32 7.6.3 SERIAL EEPROM ............................................................ 32 7.6.4 POWER SUPPLY ............................................................. 34 7.7 SYS_INTERFACE, SHEET 8 ...................................................... 34 7.7.1 50MHZ UTOPIA OSCILLATOR ........................................ 34 7.7.2 J5 UTOPIA CONNECTOR................................................ 34 8 SOFTWARE CONSIDERATIONS ......................................................... 38 8.1 8.2 PATH SIGNAL LABEL `C2' .......................................................... 38 SONET OR SDH CONFIGURING............................................... 38 9 PCB CONSIDERATIONS....................................................................... 40 9.1 9.2 PECL INTERFACE ISSUES........................................................ 41 CLOCK AND DATA RECOVERY................................................. 42 10 APS (AUTOMATIC PROTECTION SWITCHING) ................................. 43 10.1 10.2 APS HARDWARE CONFIGURATION: ....................................... 43 APS SOFTWARE CONFIGURATION ......................................... 44 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE ii PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 11 POWER SUPPLY CONSIDERATIONS.................................................. 47 11.1 11.2 11.3 POWER UP/DOWN CONSIDERATIONS ................................... 47 GROUNDING .............................................................................. 47 SYSTEM SIDE TRANSMISSION LINE TERMINATIONS ........... 48 12 TYPICAL JITTER MEASUREMENTS.................................................... 51 12.1 12.2 INTRINSIC JITTER ..................................................................... 51 JITTER TOLERANCE ................................................................. 52 13 OSCILLOSCOPE MEASUREMENTS.................................................... 54 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 13.9 DIFFERENTIAL SCOPE PROBE................................................ 54 RFPO (RECEIVE FRAME PULSE OUT) .................................... 55 RXD+/- (RECEIVE DATA) ........................................................... 55 RCLK ( RECOVERED CLOCK) .................................................. 56 REFCLK+/-.................................................................................. 56 RXD+/- EYE WITH OC-12 TEMPLATE...................................... 57 TRANSMIT REFERENCE CLOCK, TCLK 77.76MHZ................. 57 TXD+/- EYE WITH OC-12 TEMPLATE ....................................... 58 DIFFERENTIAL TXD+/- WITH TCLK AS THE TRIGGER ........... 59 14 15 16 17 SCHEMATICS REVISION 3..................................................................... 1 PCB LAYOUT REVISION 1 ..................................................................... 1 REV 3 BOM (BILL OF MATERIALS)........................................................ 1 FPGA ATM LOOPBACK SOURCE VHDL CODE..................................... 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE iii PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN LIST OF FIGURES FIGURE 1: S/UNI-622POS CHIP ....................................................................... 2 FIGURE 2: PICTURE OF S/UNI-622-POS REFERENCE DESIGN PCB ........... 2 FIGURE 3: S/UNI-622-POS BLOCK DIAGRAM................................................. 3 FIGURE 4: ATM DROP SIDE LOOP-BACK........................................................ 5 FIGURE 5: ATM TRANSPARENT....................................................................... 5 FIGURE 6: PACKET GENERATION AND RECEIVING USING FPGA............... 6 FIGURE 7: POS TRANSPARENT TO BACKPLANE .......................................... 7 FIGURE 8: S/UNI-622-POS WITH PMC-SIERRA ATM CHIPSETS ................... 7 FIGURE 9: S/UNI-622-POS REF DESIGN WITH POS LINK LAYER DEVICE .. 8 FIGURE 10: SYSTEM LEVEL BLOCK DIAGRAM............................................ 10 FIGURE 11: REFERENCE DESIGN BLOCK DIAGRAM...................................11 FIGURE 12: MICROPROCESSOR INTERFACE ............................................. 13 FIGURE 13: ODL LINE INTERFACE TERMINATIONS .................................... 16 FIGURE 14: RXD+/- PCB LAYOUT .................................................................. 17 FIGURE 15: 77.7600 MHZ REFERENCE OSCILLATOR ................................. 19 FIGURE 16: MIXING PECL 5V AND 3.3V ODL AND 77MHZ OSCILLATORS . 20 FIGURE 17: PECL STS-12 VP-P ..................................................................... 21 FIGURE 18: PM5357 TXD+/- OPEN DRAIN CURRENT DRIVERS ................. 22 FIGURE 19: LOCATION OF TERMINATIONS OF TXD+/- ............................... 23 FIGURE 20: TANTALUM & X5R CERAMIC IMPEDANCE VS. FREQ.............. 26 FIGURE 21: PASSIVE RC ANALOG POWER SUPPLY FILTERING ............... 27 FIGURE 22: RC PASSIVE FILTER METHOD MECHANICAL DIAGRAM ........ 28 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE iv PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN FIGURE 23: LINEAR REGULATOR POWER SUPPLY FILTER SCHEMATIC. 29 FIGURE 24: LINEAR REGULATOR FILTER MECHANICAL LAYOUT............. 30 FIGURE 25: EXTERNAL CLOCK AND DATA RECOVERY .............................. 42 FIGURE 26: "1+1" APS USING PM5356 BUILT IN APS FUNCTION ............... 46 FIGURE 27: SYSTEM INTERFACE TERMINATIONS...................................... 48 FIGURE 28: SERIES SOURCE TERMINATION .............................................. 50 FIGURE 29: JITTER TOLERANCE TEST SET-UP .......................................... 52 FIGURE 30: JITTER TOLERANCE WITHOUT OPTICAL ATTENUATION....... 52 FIGURE 31: JITTER TOLERANCE WITH OPTICAL ATTENUATION .............. 53 FIGURE 32: JITTER TOLERANCE WITH OPTICAL ATTENUATION .............. 53 FIGURE 33: DIFFERENTIAL SCOPE PROBE ANALYSIS............................... 54 FIGURE 34: WHAT THE DIFFERENTIAL PROBE ACTUALLY SEES ............. 54 FIGURE 35: DIAGRAM RFPO (RECEIVE FRAME PULSE) ............................ 55 FIGURE 36: RXD+/- EYE (RECEIVE DATA) .................................................... 55 FIGURE 37: RCLK (RECOVERED CLOCK) .................................................... 56 FIGURE 38: REFCLK+/-, 77.76MHZ REFERENCE CLOCK............................ 57 FIGURE 39: RXD+/- EYE WITH OC-12 TEMPLATE........................................ 57 FIGURE 40: 77.7600 MHZ REFERENCE CLOCK ........................................... 58 FIGURE 41: TXD+/- EYE WITH OC-12 TEMPLATE ........................................ 58 FIGURE 42: DIFFERENTIAL TXD+/- WITH TCLK AS TRIGGER .................... 59 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE v PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN LIST OF TABLES TABLE 1: PLX EPROM CONFIGURATION CODE........................................... 33 TABLE 2: J5 UTOPIA LEVEL 2 CONNECTOR................................................. 35 TABLE 3: SONET VS. SDH CONFIGURATION ............................................... 39 TABLE 4: REFERENCE DESIGN PCB STACK UP.......................................... 40 TABLE 5: APS CONFIGURATION OF THE WORKING FRAMER ................... 43 TABLE 6: APS HW CONFIGURATION OF THE PROTECTION FRAMER ...... 44 TABLE 7: REGISTER SET-UP DURING NORMAL OPERATION .................... 45 TABLE 8: REGISTER CONFIGURATION IN PROTECTION OPERATION...... 45 TABLE 9: INTRINSIC JITTER CALIBRATION TESTS ..................................... 51 TABLE 10: INTRINSIC JITTER TEST RESULTS WITH HP 717 ...................... 51 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE vi PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 1 INTRODUCTION The PM5356 S/UNI-622-MAX performs ATM processing and the PM5357 S/UNI622-POS performs both ATM processing and Packet Over SONET (POS). Both these devices have the same footprint and they are pin for pin compatible. Even though only reference to the PM5357 is made, this document relates to both the devices The PM5357 S/UNI-622-POS standard product is a SATURN User Network Interface with SONET/SDH processing, ATM and Packet mapping functions at the STS-12c (STM-4-4c) 622.08 Mbit/s rate. This chip also features an integral CRU and CSU for clock/data recovery and generation. The S/UNI-622-POS is intended for use in equipment implementing Asynchronous Transfer Mode (ATM) User-Network Interface (UNI), ATM Network-Network Interfaces (NNI), and Packet Over SONET/SDH (POS) interfaces. The POS interface can be used to support several packet based protocols, including the Point-to-Point Protocol (PPP). The S/UNI-622-POS may find application at either end of switch-toswitch links or switch-to-terminal links, both in public network (WAN) and private network (LAN) situations. This S/UNI-622-POS reference design provides a physical interface implementation of a SONET/SDH line card for both ATM and POS applications. It provides one single-mode or multi-mode optical interface, 5V or 3.3 V, at OC12c rate and a UTOPIA Level 2, 50MHz, 16-bit wide bus system side synchronous interface. The onboard programmable FPGA provides a simple means to manipulate ATM cells and POS packets. The PM5357 S/UNI-622-POS features two drop side synchronous interfaces. For ATM applications, standard 50 MHz, 16 bit UTOPIA Level 2 and 100MHz, 8bit UTOPIA Level 3 interfaces are provided. For POS (Packet over SONET) designs, a SATURN compliant POS-PHY Level 2 and Level 3 interface is used. More on this interface is explained later in this document. This POS Reference board implements a subset of the full capabilities of the S/UNI-622-POS and this board does not support APS. Both the PM5357 and the PM5356 are packaged in a 304 pin Super Ball Grid Array (SBGA) as shown below. For detailed information on these devices please refer to their respective data TM sheets. The terms cPCI and CompactPCI will be used interchangeably. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 1 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Figure 1: S/UNI-622POS Chip S/UNI622-POS PM5357-BI-P CC621660B M9927 R Figure 2: Picture of S/UNI-622-POS Reference Design PCB J5 - UTOPIA Level 2 Drop Side 50MHz Drop Four Side EPROMs for UTOPIA FPGA Oscillator J1 - cPCI Connector cPCI I/F chip FPGA S/UNI-622POS ATM or POS Framer Linear Regulator Analog Power Supply Filter OC12 SONET/SDH ODL 77.7600MHz Line Reference Oscillator System Status LED FPGA Status LEDs EPROM for PCI I/F Chip FPGA Serial Download Cable ERPOM Selector for FPGA * * * Provides one single-mode or multi-mode OC-12c rate 622.08 Mbit/s SONET/SDH Physical Layer Port Provides a Utopia Level 2, 50 MHz, 16-bit ATM Single-PHY System Interface to the FPGA or cPCI J5. Provides a POS-PHY Level 2, 50 MHz, 16-bit Packet Over SONET/SDH Single-PHY System Interface to the FPGA or cPCI bus J5 connector. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 2 2 PMC-1981070 PRELIMINARY REFERENCE DESIGN TDI TCK TLD TMS TDO TSD TCLK TRSTB TFPO TFPI SYSSEL TLDCLK ATM_POS TSDCLK LIFSEL TXD+/TENB TDREF1, TDREF2 Section/ Line DCC Insert JTAG Test Access Port TFCLK ATP[0] Tx POS Frame Processor Tx Section O/H Processor Tx ATM Cell Processor Tx Line O/H Processor Tx Path O/H Processor ISSUE 2 TCA/TPPA TSOC/TSOP TPRTY TDAT[15:0] TMOD TEOP TERR RFCLK RENB RCA/RPA RSOC/RSOP Tx Line I/F PTCLK POUT[7:0] S/UNI-622-POS BLOCK DIAGRAM FPOUT Figure 3: S/UNI-622-POS Block Diagram RBYP PECLV REFCLK+/- RXD+/- PMC-Sierra, Inc. RRCLK+/- UTOPIA ATM/SATURN POS-PHY Level 2 UTOPIA ATM/SATURN POS-PHY Level 3 System Interface SD Rx Line I/F C1, C0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE a a Section Trace Buffer Path Trace Buffer WAN Synch. Rx ATM Cell Processor Rx Section O/H Processor Rx Line O/H Processor Rx Path O/H Processor Rx POS Frame Processor Section/ Line DCC Extract Rx APS, Sync Status, BERM ALE RLD CSB RSD WRB A[8:0] RCLK D[7:0] RFPO RALRM RLDCLK RSDCLK APSP[4:0] Microprocessor Interface RDB RPRTY RDAT[15:0 ] RMOD REOP RERR RVAL INTB ATP[1] PICLK PIN[7:0] S/UNI-622-POS REFERENCE DESIGN 3 FPIN OOF PM5357 S/UNI-622-POS RSTB PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 3 APPLICATIONS The S/UNI-622-POS reference design demonstrates the physical interface implementation for both ATM and POS applications. The list below shows the networking equipment that can incorporate the S/UNI-622-POS device: * * * WAN and Edge ATM switches physical interfaces LAN switches and hubs physical interfaces Packet switches and hubs physical interfaces The POS Reference Board can be used in four modes: * * * * Drop Side ATM Loop-Back ATM Transparent POS Generation/Receiving POS Transparent. This S/UNI-622-POS reference PCB can be configured to demonstrate ATM drop side loopback, ATM transparent to the backplane, POS generation/receiving, and POS transparent to the backplane as described in more detail below. 3.1 ATM Drop Side Loop-Back In an ATM application, the S/UNI-622-POS reference design interfaces to one OC-12c rate SONET/SDH signal on the line side. On the drop side, the S/UNI622-POS interfaces directly to an FPGA that can be programmed to do drop side loop-back as shown in figure 1 below. An external ATM/SONET tester must generate ATM cells within SONET OC-12c frames. The POS device must be programmed for ATM mode by strapping the POS_ATMB pin (Y21) low. In addition, register 0x48, Transmit Path Signal Label, the SONET C2 byte, defaulted to 0x01, must be set to 0x13 to identify the payload to be ATM cells. The FPGA must be configured from the ATM Loop-back EPROM by selecting the correct EPROM via the dial up switch on the PCB before boot-up. The FPGA source VHDL code is enclosed in the Appendix at the end of this document. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 4 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Figure 4: ATM Drop Side Loop-Back S/UNI-POS REFERENCE BOARD R1 FPGA UTOPIA L2 PM5357 S/UNI-POS in ATM mode or PM5356 S/UNI-MAX OC-12c ATM TESTER (Adtech OC-12c AX4000) cPCI J5 ATM Loop-back STS-12c ODL 3.2 ATM Transparent FPGA can also be configured to act like a transparent interface between the POS UTOPIA L2 and the cPCI J1 connector. The user can then connect a UTOPIA L2 compliant ATM Link layer device to the cPCI J1 connector and a SONET/ATM tester on the OC-12c side as shown in figure below. Figure 5 below shows how the S/UNI-622-POS reference design can be used in a complete ATM switching design. Figure 5: ATM Transparent S/UNI-POS REFERENCE BOARD R1 FPGA UTOPIA L2 UTOPIA L2 PM5357, S/UNI-POS in ATM mode or PM5356, S/UNI-MAX OC-12c ATM Tester OC-12c (Adtech AX4000) ATM Transparent Configuration STS-12c UTOPIA L2 ATM Tester cPCI J5 ODL PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 5 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 3.3 POS Source and Receive Packets The FPGA can be configured to generate packets and compare these packets when they are looped back as shown below. In a Packet Over SONET/SDH application using the PPP protocol, the S/UNI-622-POS reference design interfaces to an OC-12c rate SONET/SDH signal on the line side. On the drop side, the S/UNI-622-POS reference design interfaces directly with an FPGA programmed to act as a link layer processor using a 256 byte synchronous FIFO SATURN POS-PHY Level 2 interface over which packets are transferred. Figure 6: Packet generation and receiving using FPGA S/UNI-POS REFERENCE BOARD R1 FPGA Terminate Packets FPGA Configured for POS-PHY Packet generation & Level 2 Termination 50MHz 16-bit Generate Packets PM5357, S/UNI-POS in POS Mode STS-12c Fiber Loop-back ODL OC-12c uP I/F 3.4 POS Transparent The FPGA can be configured to be packet transparent while connected to an external stand-alone SATURN compliant, POS-PHY tester or a POS link layer device. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 6 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Figure 7: POS Transparent to backplane S/UNI-POS REFERENCE BOARD R1 FPGA POS-PHY Level 2 50MHz, 16bit Fiber Loopback POS Transparent Configuration PM5357, S/UNI-POS POS-PHY Level 2 50MHz 16bit STS-12c ODL OC-12c UTOPIA L2 POS Tester cPCI J5 3.5 Reference PCB with other PMC-Sierra ATM chips This reference board can be potentially used within a larger system utilizing PMC-Sierra's ATM chip sets. Figure 8: S/UNI-622-POS with PMC-Sierra ATM Chipsets Utopia Level 2 Utopia Level 2 Optics PM73488 PM73488 QSE PM73487 QRT Traffic Manager PM7322 RCMP-800 ATM Layer PM5357 S/UNI-622POS Ref Design OC-12 ATM Switch Fabric Optics PM73487 QRT Traffic Manager PM7322 RCMP-800 ATM Layer PM5357 S/UNI-622POS Ref Design OC-12 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 7 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 3.6 Using the Reference board with Packet Switch This reference board can also be potentially used within a larger system utilizing packet switch and link layer processors as shown below. Figure 9: S/UNI-622-POS Ref Design with POS Link Layer Device POS-PHY Level 2 Optics Packet/IP Switch Packet PHY Port Interface Processor PM5357 S/UNI-622POS Ref Design OC-12 Optics Packet PHY Port Interface Processor PM5357 S/UNI-622POS Ref Design OC-12 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 8 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 4 REFERENCES * * * * * * * * PMC-Sierra, Inc., PMC-980911 "PM5357 S/UNI-622-POS Data Sheet", Issue 3, Jan. 15, 1999 PMC-Sierra, Inc., PMC-980589 "PM5356 S/UNI-622-MAX Data Sheet", Issue 4, Jan. 15, 1999 Bell Communication Research - SONET Transport Systems: Common Generic Criteria, GR-253-CORE, Issue 2, December 1995 CompactPCITM specification, PICMG 2.0 R2.1, September 2, 1997. ATM Forum - AF-PHY-0039.00, "UTOPIA Level 2, Version 1.0", June, 1995. ATM Forum - STR-PHY-UL3-01.00, "UTOPIA Level 3", April, 1999 PMC-Sierra's web site for this device, the IBIS models, BSDL file, and drivers can be found on PMC-Sierra's Internet Site. Digital High Speed Design, A Handbook of Black Magic, Prentice Hall PTR, by Howard W. Johnson, Martin Graham, PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 9 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 5 SYSTEM FUNCTIONAL DESCRIPTION This Reference Design Board utilized a cPCI form factor hence it may only be tested within the cPCI environment. This system is composed of a cPCI chassis, the POS Reference PCB, Pentium PCI board with operating system SW, and an external Pentium PC with dumb terminal software. In addition an external SONET ATM and/or POS tester is required to generate and receive ATM or POS data to/from the S/UNI-622-POS framer. Figure 10: SYSTEM LEVEL BLOCK Diagram cPCI CHASSIS Power supply SONET/SDH ATM or POS Tester S/UNI-622-POS Reference Design PCB OC-12c uP I/F J5 cPCI Backplane Floppy Operating System HD cPCI Pentium PCB RS-232 UTOPIA Level 2 (UL2) and POS-PHY Level 2 Interface UL2 ATM or POS-PHY Level 2 Tester (optional) PENTIUM PC PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 10 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 6 6.1 FUNCTIONAL DESCRIPTION BLOCK DIAGRAM The figure below shows the major components on the reference design. Figure 11: Reference Design Block Diagram Power supply filters LEDs 50mHz osc. One of 4 EPROMS External Download Four PM5357 S/UNI-622-POS ODL OC-12 (3.3V or 5V) OR FPGA (ATM and POS Generation, Loopback & Transparent) PECL STS-12 PM5356 S/UNI-622-MAX J5 UTOPIA/ POS-PHY LEVEL 2 UTOPIA/ POS-PHY LEVEL 2 77.76 MHz Osc. uP I/F cPCI BRIDGE PCI-9050 J1 cPCI PCI BUS 6.2 S/UNI-622-POS The PM5357 S/UNI-622-POS and the PM5356 S/UNI-622-MAX are very similar devices. The PM5356 implements ATM framing and the PM5357 implements ATM and POS framing. These SATURN User Network Interfaces are monolithic integrated circuits that implement SONET/SDH processing, ATM mapping and Packet Over SONET/SDH mapping functions at the STS-12c/STM-4-4c, 622.08 Mbit/s rate. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 11 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN The S/UNI-622-POS receives SONET/SDH streams using a bit serial interface, recovers the clock and data and processes section, line, and path overhead. The S/UNI-622-POS can also be configured for clock and data recovery and clock synthesis by-pass where it receives SONET/SDH frames via a byte-serial interface. When used to implement an ATM UNI or NNI, the PM5357 S/UNI-622-POS and the PM5356 S/UNI-622-MAX frame to the ATM payload using cell delineation. When used to implement packet transmission over a SONET/SDH link, the PM5357 S/UNI-622-POS, extracts Packet Over SONET/SDH (POS) frames from the SONET/SDH synchronous payload envelope. The S/UNI-622-POS transmits SONET/SDH streams using a bit serial interface. This framer chip can also be configured for clock and data recovery and clock synthesis by-pass where it transmits the SONET/SDH frames via a byte-serial interface. When used to implement an ATM UNI or NNI, ATM cells are written to an internal four cell FIFO using a 16-bit wide UTOPIA Level 2 (clocked up to 50 MHz) or an 8-bit wide Utopia Level 3 compatible (clocked up to 100 MHz) datapath interface. Idle/unassigned cells are automatically inserted when the internal FIFO contains less than one complete cell. When used to implement a Packet over SONET/SDH link, the S/UNI-622-POS inserts POS frames into the SONET/SDH synchronous payload envelope. Packets to be transmitted are written into a 256-byte FIFO through a 16-bit SATURN POS-PHY Level 2 or Level 3 system side interface. No line rate clocks are required directly by these chips, as they synthesize the transmit clock and recover the receive clock using a 77.76 MHz reference clock. These framers output serial differential PECL line data (TXD+/-). The S/UNI-622-POS is configured, controlled and monitored via a generic 8-bit microprocessor bus interface. These devices also provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary scan board test purposes. Both these devices are implemented in low power, +3.3 Volt, CMOS technology. They have TTL compatible digital inputs and TTL/CMOS compatible digital outputs. High speed inputs and outputs support 3.3V and 5.0V compatible pseudo-ECL (PECL). Detailed information about the PM5357 S/UNI-622-POS is available in the data sheet PMC-980911 and the PM5356 in data sheet PMC980589. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 12 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 6.3 Microprocessor Interface The S/UNI-622-POS chip and rest of the reference board is controlled through the cPCI interface connector J1. All read and writes to the S/UNI-622-POS chip and the FPGA are executed through this cPCI bus. Figure 12: Microprocessor Interface cPCI CHASSIS Floppy Operating System HD POS SONET OC-12c uP I/F J5 PCI-9050 8-bit uP Bus cPCI Pentium PCB FPGA Config EPROM cPCI Backplane RS-232 S/UNI-622-POS PM-5357 Reference Design PCB PENTIUM PC At the physical level, the POS chip address and data bus is connected to the PLX chip (a PCI-9050 bus interface chip). The Address, A[10:2] and data bus, D[7:0], are multiplexed. The data bus is 8-bits wide (single byte) and the PLX chip must be programmed for this mode via it's external configuration EMPROM. The local cPCI PCB P should be running an operating system that allows the user to be able to access the PM5356/PM5357 registers. 6.4 External Connectors The S/UNI-622-POS reference design contains two main back-plane connectors, TM J1 for the CompactPCI bus and J5 for the external UTOPIA/POS-PHY Level 2 drop-side. J3, an 8-pin header is used to download the FPGA during code debugging from the PC to the reference board via a DLC4 Parallel Xchecker cable. 6.5 UTOPIA and POS-PHY drop side interface For ATM applications, the PM5356/PM5357 and S/UNI-622-POS/MAX supports UTOPIA Level 2, Level 3 (UL2 and UL3) synchronous drop side interfaces. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 13 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN For packet data (POS) applications the S/UNI-622-POS supports POS-PHY Level 2 and Level 3 bus interface. On this PCB only the ATM Forum UTOPIA Level 2 (UL2) is supported at 50 MHz and 16 bits wide. The UL2 is used on many other PMC-Sierra ATM framers such as the S/UNI-LITE, S/UNI-ULTRA and S/UNI-622. The UTOPIA Level 3 runs at 100MHz at 8-bits wide but is not supported on this PCB. For more information on these interfaces please consult the data sheets. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 14 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 7 IMPLEMENTATION DESCRIPTION In this document, the S/UNI-622-POS schematics refer to the schematics titled "S/UNI-622-POS reference design". The S/UNI-622-POS reference design schematics were captured using Cadence software, Concept Schematics Capture Tool. 7.1 ROOT DRAWING, Sheet 1 This sheet provides an overview of the major functional blocks of the S/UNI-622POS reference design. The schematic was designed in a hierarchical format. The interconnections between the OPTICS_BLOCK, POS_BLOCK, POS BLOCK POWER SUPPLY FILTERS, SYS_INTERFACE, FPGA, FPGA EPROMs and PCI BUS Interface are labeled with a xxx\I. 7.2 ODL and 77.76 MHz reference, Sheet 2 This page includes the OC-12, 622mHz Optical Interface and the 77.7600 MHz line side clock reference interface to the POS chip. 7.2.1 622 Mbit/s Optical Interface The ODL circuit consists of power supply filtering, ODL, TX and RX PECL terminations and SD connection. The PECL signals run on 50 Ohm controlled impedance signal lines and are properly terminated at the ODL and at the S/UNI-622-POS device. The S/UNI-622-POS device interfaces to one HP HFCT-5208 Single mode Fiber Transceivers. The HFCT-5208 transceivers are in a 1 x 9-pin package with a duplex SC receptacle. There are several manufacturers that market OC-12 ODL's including HP and Siemens in 5V and 3.3V options. It's important that the oscillator is PECL and not the cheaper CMOS or TTL output type. Any jitter at the S/UNI-622-POS reference input may be seen at the TXD+/- data outputs and this translates into Optical output jitter. The 3.3V Connor Winfield EE14-541, 77.7600MHz Oscillator is specified at 10ps RMS output jitter and it's PECL outputs have rise/fall times of 550ps. The Connor Winfield 5V EH13-541 is specified at a much higher rise/fall times of 2.3ns max. Although no extensive tests were done with these two oscillators, no appreciable intrinsic jitter difference was noticed. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 15 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Figure 13: ODL Line Interface Terminations Vcc1 0.1uF 63.4ohm Vcc 49.9, 63.4, and 100 ohm resistors are on the solder side of the PCB TXDP 49.9ohm vias 49.9ohm TXDN ODL Vcc1 2.7ohm + 10uF 0.1uF Vss 5V PECL ODL and Oscillator Vcc1 Rb Vp 5V 330ohm gnd 3.3V PECL ODL and Oscillator 3.3V 150ohm 3.3V RXN Rb Vp SD Rb PECLV SD Zo=50 ohm RDRXP Vcc PECL outputs Zo=50 ohm TXPlace the far end external parallel termination resistors (not part of the chip) after the chip pins. Zo=50 ohm TX+ S/UNI-622-POS Zo=50 ohm Rb RD+ vias 100 The S/UNI-622-POS reference design provides a single optical interface running at 622 Mbit/s OC-12c rate. The line interface consists of one single mode or multimode optical data link (ODL) and a termination scheme for the PECL signal into and out from the S/UNI-622-POS transmit, TXD+/- and receive, RXD+/signal pairs. The suggested termination scheme for the PECL transmit and receive signals is shown in Figure 4 for 3.3V and 5V ODLs. Notice in the schematic above, that the far end terminating resistors in dotted lines are placed after the chip (or ODL) pins so that transmission stubs are avoided and reflections are reduced. A suggested layout with the terminating 100 ohm resistor is shown below. Similarly the TXD+/- 49.9 ohm resistor termination circuit should be located on the solder side of the PCB and after the ODL pins. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 16 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Figure 14: RXD+/- PCB layout RXD+ RXD- ODL Top View 50 ohm transmission lines both equal length Via 100 ohm termination after RXD+/- balls under the chip Via RXD+/- balls S/UNI-622-POS ball layout In normal operation, the S/UNI-622-POS performs clock and data recovery on the incoming serial stream. As an option, internal clock and data recovery may be bypassed by setting the RBYP pin high and providing an externally recovered receive clock on the RRCLK+/- pins. In this mode RXD+/- is sampled on the rising edge of RRCLK+/-. This reference design is intended to use the PM5356/PM5357 internal clock and data recovery only and provides a footprint fitting the HFCT-5208 type ODL with a 1x9 pin duplex SC receptacle only. Optionally, a footprint and function compatible, Siemens 3.3V ODL can be used, PN# V23826-H18-C363. Comparable jitter performance was observed with the 5V and the 3.3V ODL. In loss of signal condition, indicated by the SD (signal degrade) pin or a lack of data transitions for 80 consecutive bit periods, the S/UNI-622-POS will squelch the receive data and the clock recovery unit will switch to the reference clock (77.76MHz) to keep the recovered clock in range. This technique guarantees that the S/UNI-622-POS will generate a LOS indication when the ODL loses incoming light. The ODL power supplies are filtered as recommended by the manufacturer. The TX and RX supplies are filtered with a 1H series coiI, a 10F bulk Tantalum and a ceramic 0.1F ceramic cap. However, if the power supply is `noisy', greater than 100mVp-p, additional filtering may be required. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 17 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 7.2.2 77.7600 MHz Reference Clock Circuitry The SONET OC-12 line reference clock can be categorized into two classes of applications, WAN and LAN. The scope of this document only covers the LAN case. For WAN applications, a WAN compliant clock must be employed. This type of reference basically must be Phase Lock Looped (Line Timed) to the WAN network and must have no phase hits during a switch-over if loss of network reference is lost and have a long hold over. To achieve such a stringent requirement, an external digital PLL with a VCXO could be utilized to synchronize to the recovered 77.76MHz clock, RCLK or 8KHz frame pulse, RFPO. For LAN applications, a 77.76 MHz reference on this board consist of a PECL differential output, 77.76MHz oscillator. For LAN applications or edge switches, a 20ppm oscillator is adequate. The PM5356 band PM5357 can accommodate either 5V or 3.3V PECL inputs. The PECLV pin selects which voltage range, 5V or 3.3V PECL, both the REFCLKP/N and RXD+/- pins will comply to. Both signals have to be either 3.3V or 5V PECL, depending on the PECLV pin. Both 3.3V and 5V PECL have a 0.8Vp-p swing but the 5V PECL is typically 3.2V to 4.1V. The 3.3V PECL is 1.6V to 2.4 V. The PECLV pin on the framer programs both the ODL PECL I/F pins and the 77.76MHz Oscillator PECL inputs. Therefore, if the ODL is the same voltage as the Oscillator (both are either 3.3V or 5V type) then you can use the Oscillator circuit shown in Figure 15: 77.7600 MHz Reference Oscillator below. If the ODL and the oscillator are of different voltage, (ODL is 5V and Oscillator is 3.3V), then you must A.C. couple the oscillator with 0.01uF capacitors as shown in Figure 16: Mixing PECL 5V and 3.3V ODL and 77MHz Oscillators. A single 100 ohm terminating resistor across the PECL signals is preferred over the two resistors per PECL trace method unless the signal is a.c. coupled as in Figure 16: Mixing PECL 5V and 3.3V ODL and 77MHz Oscillators. The single resistor method offers fewer components and because of component congestion near the 304 ball SBGA, it is easier to place one resistor than four. To avoid a transmission stub and reflections, place the terminating resistor(s) after the PCB trace contacts the chip pins (balls). In addition, keep the TXD+/- and RXD+/traces to less than 4cm and ensure each pair is of equal length. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 18 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Figure 15: 77.7600 MHz Reference Oscillator S/UNI-622-POS REFCLK+ 2.7 Vcc + Vcc Out+ Rb 77.7600 MHz Oscillator Vss OutPECL outputs Rb Zo=50 100 Zo= 50 Vp 5V PECL 3.3V PECL ODL & ODL & Oscillator Oscillator REFCLKPECLV 10 F 0.1F Vcc Rb Vp 5V 330ohm gnd 3.3V 150ohm 3.3V It is recommended that a low jitter oscillator be used to achieve the 0.10UIp-p (0.01UIrms) output Intrinsic Jitter. Low reference jitter is required because the clock synthesis unit (CSU) has to multiply the 77MHz reference by eight to generate the transmit 622Mhz. The jitter and noise is also multiplied. Special attention must be given to ensure the Oscillator has a clean power supply since the output frequency will be modulated (jitter) by the DC voltage level or the AC noise. A RC type of voltage low pass filter is utilized to produce pole at 6Khz. A 2.7Ohm series resistor is used followed by 10F Tantalum capacitor and a 0.1F ceramic. The 2.7ohm resistor can't be too large because of DC IR loss. The 10F Tantalum eliminates low frequency noise. Ceramic capacitor is used for high frequency de-coupling since ceramic capacitors have a much better high frequency response than Tantalum. The two PECL devices, ODL and the 77.76 PECL Reference Oscillator, can be of different voltage type, 5V or 3.3V. However it is preferable to strap the PECLV pin for the ODL's requirements because the SD signal is a DC signal and level shifting will require extra active components. You can AC couple (use 0.01F ceramic caps) and level shift the oscillator appropriately as shown below. Ensure that the 100 ohm resistor is placed after the chip pins instead of before the pins, otherwise a short stub may cause reflection problems. It is not recommended to use a TTL oscillator and convert to PECL since this would introduce extraneous jitter. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 19 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Figure 16: Mixing PECL 5V and 3.3V ODL and 77MHz Oscillators 49.9 ohm, 100 ohm, R1 and R2 are external resistors and not internal to any of these devices. They are shown like this to illustrate that they must be physicaly placed past the chip pins/balls on the underside side of the PCB ferrite choke, less than 1 ohm resistance Vcc1 Vcc1 63.4 0.1F Zo = 100 4cm max TX+ 49.9ohm TXDP S/UNI-622-POS TX- 49.9ohm TXDN ODL RXP Vcc PECL outputs Zo = 100 Zo = 100 RD+ 1H + Rb1 100 Zo = 100 10F 0.1F Vss 5V PECL ODL 3.3V PECL ODL SD Vcc1 5V 3.3V Rb 330ohm 150ohm Vp gnd 3.3V R1 68.1ohm 82.5ohm R2 196ohm 127ohm Vb1 3.7Vdc 2.0Vdc 5V OSC = Rb2= 330ohms 3.3V Osc = Rb2= 150 ohms 1 ohm Vcc2 10uF 0.1uF Rb1 RXN Rb1 RDPECLV SD Vp Vcc1 REFCLK+ Out+ Rb2 77.7600MHz PECL OSC. 50 ohm R1 Vb1 R2 0.01F Vcc1 0.01F OutRb2 50 ohm REFCLK- R1 Vb1 R2 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 20 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 7.2.2.1 TXD+/- 15mA Current Drivers The PM5357/PM5356 use CMOS open Drain 15mA current steered differential drivers as shown below. Since these TXD+/- drivers are not standard PECL BIPOLAR logic (Emitter Coupled Logic), with open emitter outputs, it is important to use exactly the circuit illustrated in "Figure 18: PM5357 TXD+/- Open Drain Current Drivers", to interface to the ODL. At any one time, only one of the framer TXD outputs is sinking 15mA of current while the other one is off in a high impedance state. Here is an analysis of the TXD+/- drivers: 15mA x 49.9 = 750mVp - p and 15mA x 63.4 = 0.951mVdc Since 15mA always flows through the 63.4 resistor, there will always be a DC drop of 0.951V across this resistor. An extra 0.1F capacitor is added across the 63.4 to make sure that this 2.35Vdc, an `ac ground' voltage, has no ripple or noise. So the ac voltage at the ODL TXDP and TXDN inputs are as shown in figure below. The same calculations can be used for the 5V ODL with the same peak to peak voltage of 0.75 Vp-p but level shifted up and centered around 3.7V Figure 17: PECL STS-12 Vp-p 3.3V 3.3V PECL levels 2.35Vmax 1.975V 1.6Vmin 750mVp-p TXDN Eye Pattern 0.95V TXDP 5V 5V PECL levels 4.05Vmax 3.675V 3.3Vmin 1.6ns (622.08MHz) time It's critical that controlled PCB transmission line type traces be used for this highspeed 622.08 MHz signals with typical edge rates of 250ps. Even though the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 21 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN symbol rate is actually only half that speed, at 311.04 MHz, the 250ns edges must be treated like transmission line to achieve the desired jitter performance. Because the terminations are outside the ODL and not inside the ODL package, there is a short stub on the ODL PCB. Ideally the terminating resistors should be located on the ODL PCB at the inputs to the driver as shown below. Because of this stub, the ODL should not be farther than 4cm away from the S/UNI-622-POS. For longer traces, a PECL buffer is recommended on the TXD+/- signals and an ODL with integrated termination like the Siemens V23826-H18-C313 AC/DC option. Figure 18: PM5357 TXD+/- Open Drain Current Drivers 63.4ohm Terminations are on the solder side of PCB and physicaly placed after the 0.95V ODL pins. 750mVp-p AC TXDP Vcc1= 3.3V 0.1uF 50 ohm TX+ S/UNI-622-POS D G Q S D G S 2.35 Vmax 49.9 49.9 OPTICAL FIBER TXDN ODL 2.35Vdc 50 ohm 15mA TX- Q 15mA 15mA 1.60 Vmin Ensure that the 49.9ohm resistors are placed after the ODL pins to avoid having a stub in the PCB trace as shown in Figure 19: Location of Terminations of TXD+/-. The terminating impedance, two resistors in this case, must be placed at the farthest end of a transmission line. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 22 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Figure 19: Location of Terminations of TXD+/Ideally, the termination resistors should be located here on the ODL PCB Stubs STS-12 traces 4cm max length S/UNI-POS Reference PCB ODL PCB 49.9 ohm Terminations and traces on solder side of main PCB 7.3 POS_BLOCK, Sheet 3 The POS_BLOCK shows the PM5357 S/UNI-622-POS chip, all interface signals and power connections. If only ATM functionality is required, the PM5356 S/UNI622-MAX may be soldered in the same footprint. There are no Series resistors used to source terminate the UTOPIA/POS-PHY bus lines because the traces to the terminating device, the FPGA, are very short. However, if the traces were longer, one could use 51 termination resistors combined with the output impedance of the UTOPIA/POS-PHY pads matches the impedance of the trace at 65 Ohms. A 2K Ohm resistor is placed across the TDREF0 and TDREF1 pins. An LED displays line RX alarm status for the S/UNI-622-POS via a buffer 74HC04 chip. The RALRM output must be enabled in register 0x00E and 0x00F. RALRM out can be programmed to go high if there is alarms such as LAIS, PAIS, LRDI, PRDI, LOS< RDI, LOF, OOF, LOP, pointer AIS, LOPC, LCD, SFBER, and SDBER. A 1K Ohm resistor is also placed in series with the power supply to limit the Vbias and Pbias current to prevent latch-up. A 0.1F is added to eliminate high frequency noise. A 100 series resistor is also required to the QAVD biasing pins to prevent latchup. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 23 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN PECLV pin can be tied high or low with the resistor option, depending on whether 3.3V or 5V PECL interfaces are used for the 77.76 MHz clock reference and ODL. The board has several test points such as RCLK and TCLK to facilitate debugging. APS[4:0] pins are tied low through 4.7K resistors. The APS pins provide a control bus between two S/UNI-622-POS devices to implement a 1+1 APS function. When using APS mode, line data is passed from one S/UNI-622-POS device to another using the FPIN, PIN[7:0], FPOUT, and POUT[7:0] pins. The APS function is not implemented in this reference design. Care must be employed to ensure good PECL termination. In a far-end parallel termination scheme as employed on this case, usually the 100 resistor should be placed after the chip pins otherwise the traces may be seen as stubs and reflections may occur. Reflections can cause poor jitter performance. For more information on the PM5356 and PM5357 please refer to the data sheets. 7.3.1 Loop Filter Capacitor A 47nF capacitor is placed across the loop filter pins, C1 and C0 to ensure a stable recovered clock. To maintain jitter transfer peaking of less than 0.1db over the life of the product, the capacitor must be a stable 47nF +/-5%. The best practical choice is a Class 2 X7R SMT ceramic type which has low aging characteristics, and a +5% to -10% capacitance change over -40C to +85C temperature. 7.3.2 Pullup and Pulldown Resistors All unused CMOS inputs should be tied off high or low. Unused PECL pins such as RRCLK+ and RRCLK- (or RRCLKP and RRCLKN respectively) should be tied to the opposite polarity. Failure to tie RRCLK+ and RRCLK- to complementary values will result in signal contention within the device which may cause problems with device operation. When tying an input to ground, the pin may be connected directly to ground. When tying an input to 3.3V or 5V, a 4.7Kohm resistor should be used in order to prevent latch up during power up. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 24 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 7.4 Power Supply Filter for the PM5357 Sheet 4 This page shows how to clean up the power supply to the S/UNI-622-POS. Because this IC has mixed analog and digital circuits, care must be used to eliminate noise from affecting the critical analog sections. The analog power supply must be filtered as shown below. In addition, 0.1F ceramic capacitors are used to filter the digital supply. These chips will function in either a 3.3V only system or a mixed 3.3V and 5V TTL UTOPIA bus environment. Typical power planes should be used in a multi layer board with sufficient filtering with high quality high frequency ceramic 0.1F caps on the digital rail and bulk filtered at the board connectors. The S/UNI-622-POS performs clock and data recovery at a very high speed. Analog circuitry responsible for clock and data recovery must be free of noise to ensure reliable operation. Less sensitive analog power pins are grouped together and filtered with a single 0.1 F capacitor. The more sensitive analog power pins of the S/UNI-622-POS are de-coupled using a low pass RC filter method. If there is a lot of power supply noise, >100mVp-p in the 3.3V rail, and a 5V supply is available, then a linear regulator approach is recommended. 7.4.1 Passive RC low pass power supply Filter If there is no 5V rail available and the 3.3V supply is not very noisy (less than 100mVp-p at all frequencies), then this method is acceptable. Several capacitors may have to be paralleled to achieve the filtering across the desired frequency band. The 10F capacitors should be X5R ceramic type and not Tantalum. Also use a 0.1F X5R for high frequency noise reduction. The Issue 3 schematics use this passive filter method. The X5R type capacitors have excellent low and high frequency response as seen in the graph below. The lower the impedance is, the better the capacitor for filtering. An excellent manufacturer of small size, non-polarized ceramic capacitors is Taiyo Yuden of 1930 North Thoreau, Drive, Suite 190, Schaumburg IL, 60173 USA, 1-80036-TAIYO. The X5R capacitors are similar to X7R except the high temperature spec is +85C instead of 125C for the X7R. These X5R ceramics are available up to 10F at 6.3 Volts. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 25 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Figure 20: Tantalum & X5R Ceramic Impedance vs. Freq. 100,000 10,000 1,000 Impedance ESR (ohms 100 10 1 0.1 0.01 0.001 0.1 10uF Tantalum 10uF X5R 0.1uF X5R 1 100 1,000 10,000 100,000 10 Frequency (kHz) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 26 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Figure 21: Passive RC Analog Power Supply Filtering 4.7 3.3V Pin-P1, AVD8 (CRU-AVD4) Pin-AC5, AVD17 (CRU-AVD5) 47F + 0.1F 0.1F Tantalum 10F X 5R 6V 5V for 5V tolerant TTL I/O else 3.3V 1K Pin P2 (name C0) 0.1F Vbias0 pin W20 Pbias1 pin E20 Pbias0 pin W2 Pbias1 pin V3 Pbias2 pin R3 Pbias3 pin M2 4.7 Pin-C4, AVD31 (CSU-AVD0) 47nF X7R +/-5% Pin P3 (name C1) connect cap to these pins for WAN Jitter transfer applications else leave open. 10F X 5R 10F 0.1F X 5R 15 Pin-A3, AVD30 (CSU-AVD1) One 0.1uF cap as close as possible at each of these 9 analog pins: AVD2, pin F2 3.3V AVD3, Pin H3 AVD6, Pin K3 0.1F AVD7, Pin L3 AVD10, Pin U3 (9caps) AVD11, Pin Y1 AVD15, Pin AA5 AVD20, Pin AA8 AVD26, Pin C7 10F X 5R NOTES 0.1F 15 Pin-A4, AVD29 (CSU-AVD2) 10F X 5R 0.1F - place 0.1uF as close to power pin as possible. - 10uF caps are 10V X5R ceramic, 1210 size, from Tayio-Yuden, LMK325BJ106MN, www.t-yuden.com - 10uF and 47uF caps and resistors do not have to be very close to power pins - 0.1uF caps are ceramic X7R or X5R - resistors are 1/10 Watt - the two 10uF X5R on pin C4 can be replaced by one 22uF, 10V, X5R LMK432BJ226MM from Tayio Yuden - all other power pins not mentioned do not need extra filtering. 15 Pin-D2, AVD1 (CSU-AVD3) Pin-D3, AVD0 (CSU-AVD4) One 0.1uF cap as close as possible at each of these 9 digital pins: 3.3V 10F X 5R 0.1F 0.1F (9caps ) VDD, pin C21 VDD, pin M20 VDD, pin V20 VDD, pin AA21 VDD, pin D12 VDD, pin B2 VDD, pin M4 VDD, pin AB2 VDD, pin Y12 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 27 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Figure below shows relative size of components and is not meant to show placement location since it's difficult to place components on the solder side of a BGA. Figure 22: RC Passive Filter Method Mechanical Diagram CSU-AVD2 Pin-A4, AVD29 CSU-AVD1 PinA3, AVD30 15 15 10 F 0.1F 10 F 0.1F 0.1F 0.1F 0.1F 0.1F 10 F 15 CSU-AVD3 Pin-D2 & D3, AVD1 S/UNI-622-POS 31 by 31 mm 0.1F 0.1F CSU-AVD0 Pin-C4, AVD31 0.1F 0.1F 0.1F 0.1F 0.1F 10F 0.1F X7R +/-5% for Loop Filter name C0, C1 pins P2, P3 4.7 10 F 10 F 0.1F 47nF CRU-AVD4 Pin-P1, AVD8 4.7 47F 7.3by 4.3mm 0.1F 0.1F 1K 0.1F 0.1F 0.1F Vbias, Pbias pins 0.1F 0.1F 0.1F 0.1F CRU-AVD5 Pin-AC5, AVD17 Parts Count 6 - 10uF 10V, X5R, 1210 (3.2 x 2.5 mm) size ceramic caps, LMK325BJ106MN 24 - 0.1uF, X7R, 0805 body (2 by 1.25mm) Note: the resistors and the 10uF/ 1 - 47nF +/-5% ceramic X7R Class 2 capacitor 3 - 15 ohm R's, 1/10 W, 0805 body (2 by 1.25mm) 47uF caps do not have to be close 2 - 4.7 ohm Resistor, 1/10 W, 0805 body (2 by 1.25mm) to the chip pins. 1 - 47uF Tantalum capacitor, 6.3V, SMT PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 28 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 7.4.2 Linear Regulator Filter Method If there is a 5V supply available, and the 3.3V supply has a lot of noise (>100mVp-p), then a better method to filter the analog supplies is with a "low drop-out voltage regulator" such as the LT1129-3.3 from Linear Technology. This regulator typically has about a 50db noise rejection up to about 500 kHz. Further noise attenuation is achieved with a front end the RC pre-filter (2.7 ohm + 10 F) and a high frequency 0.1F ceramic at the input to the regulator. A 10 F Tantalum is required at the output for regulator stability. Figure 23: Linear Regulator Power Supply Filter Schematic 3.3V Regulator Linear Tech LT11293.3 0.1uF 2.7 ohms 5V 10uF + 10uF + Pin-P1 AVD8 0.1uF Pin-AC5 AVD17 5V if TTL I/O required to be 5V tolerant, else 3.3V 1K 0.1uF 0.1uF Pin P2 (name C0) Pin-C4 AVD31 Vbias0 pin W20 Pbias1 pin E20 Pbias0 pin W2 Pbias1 pin V3 Pbias2 pin R3 Pbias3 pin M2 47nF X7R +/-5% Pin P3 (name C1) connect cap to these pins for WAN Jitter transfer applications else leave open. 0.1uF Pin-A3 AVD30 Pin-A4 AVD29 0.1uF Pin-D2 AVD1 Pin-D3 AVD0 0.1uF One 0.1uF cap as close as Pin F2 possible at each of these 9 Pin H3 analog pins: Pin K3 Pin L3 3.3V Pin U3 Pin Y1 Pin AA5 0.1uF Pin AA8 (9 caps) Pin C7 NOTES - place 0.1uF as close to power pin as possible. - 0.1uF caps are ceramic X7R or X5R - resistors are 1/10 Watt - all other power pins not mentioned do not need extra filtering. - 47nF ceramic +/-5% X7R capacitor One 0.1uF cap as close as possible at each of these 9 digital pins: VDD, pin C21 VDD, pin M20 3.3V VDD, pin V20 VDD, pin AA21 VDD, pin D12 0.1uF VDD, pin B2 (9 caps) VDD, pin M4 VDD, pin AB2 VDD, pin Y12 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 29 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Figure below shows relative size of components and is not meant to show placement location since it's difficult to place components on the solder side of a BGA. Figure 24: Linear Regulator Filter Mechanical Layout 4.7 10 F 3.3V Regulator 10 F PinA3 0.1uF Ball A3 0.1uF Ball C4 0.1uF Ball C7 0.1uF Ball B2 0.1F 0.1uF Ball C21 0.1F Pin-D2 & D3 0.1uF Ball F2 0.1uF Ball D12 0.1uF Ball H3 0.1uF Ball K3 0.1uF Ball L3 0.1uF Ball M20 S/UNI-622-POS or S/UNI-622-MAX 31 x 31 mm (Bottom View) 0.1uF Ball V20 Vbias, Pbias 1K 0.1uF Ball M4 47nF 0.1uF 0.1uF Ball P1 X7R +/-5% for Loop Filter labels C0, C1 pins P2, P3 0.1uF Ball U3 0.1uF Ball Y12 0.1uF Ball AA21 0.1uF Ball AA8 0.1uF Ball AA5 0.1uF Ball AB2 0.1uF Ball AC5 0.1uF Ball Y1 Parts Count 2 - 10uF 10V, Tantalum, 6V 26 - 0.1uF, X7R, 0805 body (2 by 1.25mm) 1 - 47nF +/-5% ceramic X7R capacitor 1 - 2.7 ohm Resistor, 1/10 W, 0805 body (2 by 1.25mm) 1 - 1Kohm resistor 1 - 3.3VLinear Regulator, SOT-23 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 30 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 7.5 FPGA, Sheet 5 and 6 This reference board has a large general purpose Xilinx XC4000 series FPGA (XC4036XLA-HQ240-9NS), filtering, configuration EEPROMs (XC1701), external download header J3, and thumb-wheel switch selector the EPROMS. The FPGA, U13, is used to interface to the S/UNI-622-POS drop side to give this board some ATM and packet functionality. We chose the largest and fastest device we could find so that we were not restricted during our development. Information on this device is available from Xilinx. At the time of this document, only the ATM drop side loopback was implemented and debugged. The ATM loopback code for the FPGA is enclosed in this document. ATM transparent, POS generation and POS transparent may be available in the future. Several pins were brought out into headers (TP's) just in case we wanted to use this device for a different function than originally envisioned. Although they are tied off to ground, provision was made so that the ground trace can be easily cut. The FPGA has eight LEDs connected to the general purpose I/O pins so that code could be written to selectively light these depending on the FPGA performance at power up and real time status. At power up, all the LEDs are on and when the FPGA is downloaded correctly from the EPPROMS, only the first LED is left on. A header, J2 is used to select how the FPGA is to be configured at power up. With all the jumpers installed, the FPGA is programmed via the J3 (on page 6), serial cable adapter from a PC development setup. This is only used at time of code debugging. With all the J6 jumpers removed, the FPGA is configured at power up from one of four serial EEPROMs located on page 6 of the schematics. The serial EEPROMs, U9, U12, U17 and U17 can be used to configure the FPGA for ATM loopback, ATM transparent to the J5 backplane, Packet generation/receiving, and packet transparent. Depending on the thumb wheel selector switch, U1, one of four different functions can be jammed into the FPGA at power up. The XC1701L EEPROM devices contain 832,528 bits. 20 pin PLCC sockets are used to facilitate ease of changing these programmable devices. 7.6 cPCI BUS Interface Sheet 7 This page contains the CompactPCITM bus backplane interface circuitry. It consists of the cPCI connector J1, the PLX bridge chip PCI-9050-1, serial EEPROM, NM93CS46 and power supply. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 31 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 7.6.1 cPCI Backplane Connector J1 The J1 cPCI connector details can be found in the CompactPCI specification, PICMG 2.0 R2.1. All register accesses to the S/UNI-622-POS and FPGA are performed through connector. J1 can optionally supply 3.3V and 5V power to the board. Not all cPCI pins are used in this design. Please refer to the enclosed schematic for a detailed pin description. 7.6.2 PLX cPCI Bridge chip, PCI9050 The PCI 9050 provides a compact high performance PCI bus target (slave) interface for adapter boards. For more information on this device, please refer to the manufacturer's specification found on the PLX Technology web site. This device is programmed, via the external serial EEPROM, U14 at power up, for a multiplexed, 8 bit local data bus. The PLX chip allows the board to map several devices such as the S/UNI-622-POS and the FPGA to the cPCI bus. The signals from the J1 connector to the PLX chip are tightly controlled and must adhere to the cPCI physical specification for proper operation. Ten ohm series terminating resistors are used to minimize reflection in all the signals. Any unused inputs such as the unused LAD (address/data) pins are pulled up with 4.7K resistors. Also, all tri-state outputs, such as RDB, are pulled up via a 4.7K resistor to prevent the bus from chattering during power up. We added a couple of test points (RST_POS_FPGA, R_A) isolated by 10 ohm resistors to allow us to reset each chip manually by grounding a node. This allowed us to reset each chip without resetting the whole system which takes a few minutes re-boot from disk. The address/data bus is multiplexed and the lowest order address is A2. The PLX does 32 bit, 4 byte accesses to/from the framer/FPGA and the cPCI system Software selects the bottom byte only. Notice that the top three data bytes on the PLX are not connected to the bus. 7.6.3 Serial EEPROM The PLX chip, PCI9050, requires a configuration EEPROM during power up to configure itself. A serial device, U14, NM93CS46 contains the following code to configure the PLX for our system. TM PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 32 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Table 1: PLX EPROM Configuration Code EPROM Register Offset Offset 0 2 4 6 8 A C E 10 12 14 16 18 1A 1C 1E 20 22 24 26 28 2A 2C 2E 30 32 34 36 38 3A 3C 3E 40 42 44 46 48 4A 4C 4E 50 52 54 56 58 5A 5C 5E 60 62 PCI 02 PCI 00 PCI 0A PCI 08 PCI 2E PCI 2C PCI 3E PCI 3C LOCAL 02 LOCAL 00 LOCAL 06 LOCAL 04 LOCAL 0A LOCAL 08 LOCAL 0E LOCAL 0C LOCAL 12 LOCAL 10 LOCAL 16 LOCAL 14 LOCAL 1A LOCAL 18 LOCAL 1E LOCAL 1C LOCAL 22 LOCAL 20 LOCAL 26 LOCAL 24 LOCAL 2A LOCAL 28 LOCAL 2E LOCAL 2C LOCAL 32 LOCAL 30 LOCAL 36 LOCAL 34 LOCAL 3A LOCAL 38 LOCAL 3E LOCAL 3C LOCAL 42 LOCAL 40 LOCAL 46 LOCAL 44 LOCAL 4A LOCAL 48 LOCAL 4E LOCAL 4C LOCAL 52 LOCAL 50 EEPROM Value Register Description 9050 10B5 0680 0000 5357 11F8 FFFF 01FF 0FFF FF00 0FFF F800 0000 0000 0000 0000 0FFF 0000 0000 0001 0000 1001 0000 0000 0000 0000 0000 0000 5401 40C0 0080 0000 0080 0000 0080 0000 0000 0000 0000 1101 0000 1801 0000 0000 0000 0000 0000 0000 0002 4492 Device ID Vendor ID Class code Class code (revision is not loadable) Subsystem ID Subsystem Vendor ID (Maximum Latency and Minimum Grant are not loadable.) Interrupt Pin (Interrupt Line Routing is not loadable.) MSW of Range for PCI to Local Address Space 0 (1 MB) LSW of Range for PCI to Local Address Space 0 (1 MB) MSW of Range for PCI to Local Address Space 1 LSW of Range for PCI to Local Address Space 1 MSW of Range for PCI to Local Address Space 2 LSW of Range for PCI to Local Address Space 2 MSW of Range for PCI to Local Address Space 3 LSW of Range for PCI to Local Address Space 3 MSW of Range for PCI to Local Expansion ROM (62 KB) LSW of Range for PCI to Local Expansion ROM (62 KB) MSW of Local Base Address (Remap) for PCI to Local Address Space 0 LSW of Local Base Address (Remap) for PCI to Local Address Space 0 MSW of Local Base Address (Remap) for PCI to Local Address Space 1 LSW of Local Base Address (Remap) for PCI to Local Address Space 1 MSW of Local Base Address (Remap) for PCI to Local Address Space 2 LSW of Local Base Address (Remap) for PCI to Local Address Space 2 MSW of Local Base Address (Remap) for PCI to Local Address Space 3 LSW of Local Base Address (Remap) for PCI to Local Address Space 3 MSW of Local Base Address (Remap) for PCI to Local Expansion ROM LSW of Local Base Address (Remap) for PCI to Local Expansion ROM MSW of Bus Region Descriptors for Local Address Space 0 LSW of Bus Region Descriptors for Local Address Space 0 MSW of Bus Region Descriptors for Local Address Space 1 LSW of Bus Region Descriptors for Local Address Space 1 MSW of Bus Region Descriptors for Local Address Space 2 LSW of Bus Region Descriptors for Local Address Space 2 MSW of Bus Region Descriptors for Local Address Space 3 LSW of Bus Region Descriptors for Local Address Space 3 MSW of Bus Region Descriptors for Expansion ROM Space LSW of Bus Region Descriptors for Expansion ROM Space MSW of Chip Select (CS) 0 Base and Range Register LSW of Chip Select (CS) 0 Base and Range Register MSW of Chip Select (CS) 1 Base and Range Register LSW of Chip Select (CS) 1 Base and Range Register MSW of Chip Select (CS) 2 Base and Range Register LSW of Chip Select (CS) 2 Base and Range Register MSW of Chip Select (CS) 3 Base and Range Register LSW of Chip Select (CS) 3 Base and Range Register MSW of Interrupt Control/Status Register LSW of Interrupt Control/Status Register MSW of EEPROM Control and Miscellaneous Control Register LSW of EEPROM Control and Miscellaneous Control Register PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 33 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 7.6.4 Power Supply The board is powered via the J1 connector from the system cPCI backplane. The 5V and the 3.3V rails are bulk filtered as they enter the board with 47F tantalum capacitors. These power rails are also fused with 2 Amp fuses to prevent the board from severe damage in case of a circuit failure. Because a fuse has a finite "on resistance/impedance", a second 47F is located on the other side of this fuse. An LED is provided for each supply to alert the user if the power is on. 7.7 SYS_INTERFACE, Sheet 8 The SYS_INTERFACE block contains the J5 UTOPIA board connector and the UTOPIA bus clock oscillator. 7.7.1 50mHz UTOPIA Oscillator A 50 MHz oscillator, 100ppm, is used for the POS-PHY Level 2 or Utopia Level interface rate. If there was a UTPOIA Level 3 provision, a 100 MHz crystal oscillator could have been used. The oscillator does not need any special power supply filter since jitter is not an issue like it is for the 77.7600MHz line side clock reference. However, because of the tight bus timing requirements, a buffer is used to provide low skewed clocks to the PM5357, the FPGA, and to the external J5 connector. 7.7.2 J5 UTOPIA Connector The J5 connector uses a PMC-Sierra Inc. proprietary pin out for the UTOPIA Level 2 bus as shown in Table 2: J5 UTOPIA Level 2 Connector. The S/UNI-622-POS UTOPIA Level 2 interface is connected to the drop side J5 connector through the FPGA. The pin names shown below have the prefix "SYS_" added on the signal names of the schematic. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 34 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Table 2: J5 UTOPIA Level 2 Connector Pin Name RDAT[0] RDAT[1] RDAT[2] RDAT[3] RDAT[4] RDAT[5] RDAT[6] RDAT[7] RDAT[8] RDAT[9] RDAT[10] RDAT[11] RDAT[12] RDAT[13] RDAT[14] RDAT[15] RPRTY RENB RCA Type Output Pin No. D2 B2 E3 D3 B3 A3 E4 D4 B4 A4 E5 D5 B5 A5 E6 D6 B6 A6 B11 Function UTOPIA: Receive Cell Data Bus For Utopia Level 2 this bus carries the ATM cell octets that are read from the receive FIFO. For Utopia Level 3 only RDAT[7:0] are valid. POS-PHY: Receive Packet Data Bus For POS-PHY Level 2 this bus carries Packets that are read from the selected receive FIFO. For POS-PHY Level 3, only RDAT[7:0] are valid. Receive bus parity. The receive parity signal indicates the parity of the RDAT bus. Receive Write Enable. The RENB signal is an active low input which is used to initiate reads from the receive FIFO. UTOPIA: Receive Direct Cell Available This signal indicates an available cell. POS-PHY: Direct Receive Packet Available. For POS-PHY Level 2, this signal indicates when data is available in the receive FIFO. For POS-PHY Level 3 this signal is not used as RVAL signals valid data on the bus. UTOPIA: Receive Start of Cell This signal marks the start of cell on the RDAT bus. POS-PHY: Receive Start of Packet This signal marks the start of packet on the RDAT bus. POS-PHY: Receive Error This signal indicates that the current packet has been aborted. This signal is ignored in Utopia ATM modes. Output Input Output RPA RSOC Output B11 D7 RSOP RERR Output D7 E8 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 35 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Pin Name REOP Type Output Pin No. B7 Function POS-PHY: Receive End of Packet This signal marks the end of packet on the RDAT bus. This signal is ignored in Utopia ATM modes. RX modulo: Indicates number of bytes in the last RDAT bus transaction of a packet. In POS mode, RAVL indicates signals RDAT, RSOP, REOP, RMOD, RPRTY and RERR are valid. 50 MHz UTOPIA bus clock buffered by the FPGA and same time delay as the actual UTOPA signals. 50 MHz UTOPIA bus clock straight from the oscillator buffer. Utopia and POS-PHY: Transmit Write Enable. The TENB signal is an active low input which is used to initiate writes to the transmit FIFO Utopia: Transmit cell available signal This signal is used to indicate available cell FIFO space by the PHY port. POS-PHY: Direct Transmit Packet Available. This signal transitions to high when a programmable minimum number of free space is available in the transmit FIFO. Utopia: Transmit Start of Cell The transmit start of cell signal marks the start of cell on the TDAT bus. POS-PHY: Transmit Start of Packet For POS-PHY Level 2 this signal indicates the first word of a packet. In POS-PHY Level 3 this signal indicates the first byte in a packet. POS-PHY: Transmit Error This signal indicates the current packet must be aborted. This signal is ignored in Utopia ATM mode POS-PHY: Transmit End of Packet This signal marks the end of a packet on the TDAT bus. This signal is ignored in Utopia ATM modes. RMOD RVAL RFCLK3 RFCLK1 TENB Output Output Output Output Input B7 D8 A1 C1 E17 TCA Output D12 TPA TSOC Input D12 B16 TSOP B16 TERR Input A15 TEOP Input D16 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 36 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Pin Name TMOD Type Input Pin No. E16 Function POS-PHY: Transmit Word Modulo For POS-PHY Level 2, this signal indicates the size of the current word. For POS-PHY Level 3 this signal is ignored. This signal is ignored in Utopia ATM modes. Transmit bus parity. The transmit parity signal indicates the parity of the TDAT bus. Utopia: Transmit Cell Data Bus This bus carries the ATM cell octets that are written to the selected transmit FIFO. TPRTY TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15] TFCLK2 TFCLK1 NC 3.3VDC GND INPUT INPUT D17 B21 D21 A20 B20 D20 E20 A19 B19 D19 E19 A18 B18 D18 E18 A17 B17 A1 C1 D9... C3, C4 B1, D1 POS-PHY: Transmit Packet Data Bus This data bus carries the POS packet octets that are written to the selected transmit FIFO. For POS-PHY Level 3, only TDAT[0:7] are valid. Output Output NC Power Power 50 MHz UTOPIA bus clock buffered by the FPGA and same time delay as the actual UTOPIA signals. 50 MHz UTOPIA bus clock straight from the oscillator buffer. Many No Connect Pins. See schematic 3.3V power supply Ground PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 37 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 8 8.1 SOFTWARE CONSIDERATIONS Path Signal Label `C2' Upon reset the S/UNI-622-POS/MAX register 0x48, Path Signal Label, SONET/SDH C2 byte, defaults to 0x01, which signifies an equipped unspecific payload. This device will stuff a 0x01 into the C2 byte in the SONE path overhead until it is changed. This register should be reprogrammed with the value 0x13 when in ATM mode or value 0xCF when in Packet over SONET (POS) mode so that the Path C2 byte will contain the correct payload type. The receiver should have a matching C2 byte so that a signal label mismatch (PSLM) alarm is not declared. If there is a path signal label mismatch the PSLMPAIS bit in register 0x0D will enable path AIS insertion. In this case all ones will be inserted into the receive SONET/SDH payload, the PM5356/PM5357 will not be able to acquire cell delineation and a PATH alarm will be declared. Upon power up, register 0x54 should be programmed with the expected path signal label of 0x13 for ATM and 0xCF for Packet over SONET (POS). 8.2 SONET or SDH Configuring The SONET and SDH fiber standards for optical networking are very similar, with only minor differences in overhead processing. The main difference between the SONET and SDH standards lies in the handling of some of the overhead bytes. Other details, like framing, and data payload mappings are equivalent in SONET and SDH. By default, PMC's S/UNI-POS powers up in SONET mode. However, it can be configured to operate in SDH mode. The bit error rate (BER) monitoring requirements are also slightly different between Bellcore GR-253-CORE (SONET) and ITU.707 (SDH) An application note, PMC-950820, explains in detail the different parameters for the RASE block. The table below shows the various register settings to configure the POS for either SONET or SDH mode PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 38 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Table 3: SONET vs. SDH Configuration Register/bits SDH_J0/Z0 (0x01)1 ENSS (0x3D)2 LEN16(Path, 0x28)3 LEN16(Section, 0x50)3 S[1:0] (0x46)4 Notes: 1) SONET requires Z0 bytes to be set to the number corresponding to the STS1 column number. SDH considers those bits as reserved. 2) SDH specification requires the detection of SS bits to be "10" 3) SONET uses 64 bytes message/SDH uses 16 bytes message 4) SS is undefined for SONET but must be set to "10" for SDH SONET 0 0 0 0 00 SDH X 1 1 1 10 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 39 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 9 PCB CONSIDERATIONS Because of the high speed 622MHz PECL differential drivers, and other fast edge signals such as the UTOPIA bus, this PCB requires careful layout. Typically the drivers for these have rise/fall times in excess of 1ns. High speed traces should be as short as possible, transmission lines are to be used where indicated and standard terminations must be incorporated to prevent signal reflections. Standard FR-4 PCB material can be used for this application with as many layers as is required to derive the final board thickness, achieve enough layers for signal routing and attain the required trace impedance. Please refer to the first page of the artwork for more detail on the reference design PCB. We chose the following stack up layers: Table 4: Reference Design PCB Stack Up Layer Top 3.3V PLANE GND_PLANE SIG1 SIG2 VCC_PLANE GNDA_PLANE BOTTOM Location Top Signal Layer , Component side Power Ground Signal Layer Signal Layer 5V Power Layer Ground Bottom layer, Solder Side Although only one ground plane is required, two are used to attain the desired board thickness and correct trace impedance. A ground layer or a power plane can be used to achieve the desired signal transmission line trace impedance assuming there is adequate coupling between them. The PECL 622MHz and 50 MHz traces are 50 ohms and they are 8 mil wide. The rest of the board is laid out with 5 mil and these are 65 ohm impedance. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 40 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Traces that are long and have a signal that has relatively fast rise/fall times should be routed with a Stripline. T l= r D l = length of rising edge, in Inches Tr = rise time of edge (ps) D = delay of material (ps/in) Stripline delay for FR-4 PCB material is about 188 ps/in, PECL drivers typically exhibit 250ps rise/fall times, and UTOPIA drivers are about 1ns. Therefore: T 250 = 1.33in. (3.4cm) l= r = D 180 l , are considered lumped and do not need 6 1.33in terminations. PECL traces that are less than = 0.22in/0.56cm, and CMOS 6 level UTOPIA bus traces less than 0.89in/2.26cm, do not need to be terminated. Traces with length less than Please refer to the High Speed Digital Design Handbook for more detail regarding transmission lines and terminations. 9.1 PECL Interface Issues All unused differential PECL inputs should be tied such that the positive input and negative input are complementary (have opposite logic values). For example if RRCLK+ is tied to 3.3V, therefore RRCLK- should be tied to ground. Or; RRCLK+ is tied to ground and RRCLK- should be tied to 3.3V. The PECLV and PBIAS pins affect both the optical PECL interface as well as the REFCLK+/- interface. Therefore REFCLK+/- must have the same signal reference level as the optical PECL interface. Because of the transmission stub created by the ODL internal PCB trace and through-hole solder mounting pins, traces between the optics and the S/UNI622-POS should be limited to a maximum of 4 cm long. No vias should be present on the point to point traces except where required for the terminating components. Any vias present along the traces will degrade jitter performance. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 41 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN These differential traces should be of equal length and have as few bends as possible. To prevent transmission stubs, terminating components (resistors) should be placed after the IC pin(s) and usually on the solder side (bottom) of the PCB. 9.2 Clock and Data Recovery Although the S/UNI-622-POS(MAX) has an optional external clock/data recovery interface, it is best to use the internal clock and data recovery. This is the cheapest method, has the lowest parts count, takes up the least amount of board space and exceeds jitter requirements of Bellcore GR-253/CORE. The external clock/data recovery can be utilized by using the framer's parallel interface through the chip's PIN[7:0], RRCLK+/-, FP, OOF and POUT[7:0] pins. As illustrated below, devices like the HP RGR2622 Clock/Data SONET Receiver Module, which have their own clock recovery circuit, can be used in conjunction with an Optical Transmitter to interface the S/UNI-622-POS to the SONET fiber. Figure 25: External Clock and Data Recovery POUT[7:0] OC-12 Transmitter STS-12c PTCLK PM5357 FPOUT S/UNI-622-POS or LIFSEL PM5356 S/UNI-622-MAX OOF FPIN PICLK PIN[7:0] OC-12c OC-12 Receiver with clock recovery Vcc PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 42 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 10 APS (AUTOMATIC PROTECTION SWITCHING) The PM5357 S/UNI-622 POS, and the PM5356 S/UNI-622-MAX, have added circuitry and special function pins to allow two of these devices to be optionally configured to operate in a "1+1" APS mode. For more information on APS, please refer to section 5.3 of GR-253-CORE. APS is a feature that allows redundant circuits to be switched in if a fiber is broken or a circuit board has failed. 10.1 APS Hardware Configuration: For APS, the S/UNI-622-POS framer registers must be set up as follows: Table 5: APS configuration of the Working framer S/UNI-622MAX/POS pin LIFSEL PICL PIN[7:0] FPIN PTCLK POUT[7:0] APS[4:0] FPOUT TCLK GND GND GND GND GND Connect to PIN[7:0] of the protection PM5356/PM5357 Connect to the APS[4:0] of the protection PM5356/PM5357 Connect to FPIN of protection PM5356/PM5357 Connect to PICLK of protection PM5356/PM5357 Description of connection Both the working and the protection S/UNI-622-POS/MAX timing must be synchronous. They can't be independently looptimed. * The FIFO on the Protection S/UNI needs to be reset during system reset and when the CSU is held in Reset. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 43 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN * During normal operation, when the RX traffic is selected from the working channel the register must be set up as listed below: Table 6: APS HW configuration of the Protection framer S/UNI-622MAX/POS pin LIFSEL PICL PIN[7:0] FPIN PTCLK POUT[7:0] APS[4:0] FPOUT GND TCLK from the working PM5356/PM5357 Connect to POUT[7:0] of the working PM5356/PM5357 Connect to the FPOUT of the working PM5356/PM5357 GND Not Used Connect to the APS[4:0] of the working PM5356/PM5357 Not used Description of connection 10.2 APS Software Configuration For "1+1" APS, S/UNI-622-POS/MAX framer must have register 0x06H set up as follows. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 44 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Table 7: Register set-up during normal operation Register 0x06H BIT LABEL APSFEBE APSRDI APSPD APSPOE APSEN WORKING PM5356/PM5357 0 0 0 0 1 PROTECTION PM5356/PM5357 0 0 1 1 1 During protection operation, when the RX traffic is selected from the protection channel the register must be set up as follows: Table 8: Register configuration in Protection Operation Register 0x06H BIT LABEL APSFEBE APSRDI APSPD APSPOE APSEN WORKING PM5356/PM5357 0 0 0 0 1 PROTECTION PM5356/PM5357 0 0 1 1 1 Bellcore GTR-253-CORE requires that the APS protection occurs at the Path level as in the PM5356/PM5357 shown below. If only fiber protection is required, the PM5356/PM5357 protection/working devices can be located on the same system PCB or for added protection, on separate cards within a system chassis. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 45 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Figure 26: "1+1" APS using PM5356 built in APS function STS-12c STS-12c STS-12c STS-12c RX CRU TX CSU TX CSU RX CRU PM5356/PM5357 RSOP, RSLOP TSOP, TLOP FPIN PICLK LIFSEL PTCLK FPOUT TCLK LIFSEL PICLK PIN[7:0] FPIN PTCLK PM5356/PM5357 TSOP, TLOP RSOP, RSLOP Protection Channel POUT[7:0] Working Channel Not Used RDI FEBE FIFO PIN[7:0] APS[4:0] 8 POUT[7:0] TPOP RPOP TPOP RPOP RXCP/ RXFP TXCP/ TXFP TXCP/ TXFP RXCP/ RXFP APS[4:0] 5 Not Used UTOPIA Level 2 or POS-PHY System Drop Side Interface Rx ATM/POS Traffic (Protection) RDI[2:0], FEBE[1:0] TX ATM/POS Traffic (Working) Rx ATM/POS Traffic (Working) LINK LAYER HARDWARE PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 46 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 11 POWER SUPPLY CONSIDERATIONS 11.1 Power Up/Down Considerations Due to ESD protection structures in the pads it is necessary to exercise caution when powering a device up or down. ESD protection devices behave as diodes between power supply pins and from I/O pins to power supply pins. Under extreme conditions it is possible to blow these ESD protection devices or trigger latch up. For more information on the required power up sequence, refer to the S/UNI-622-POS data sheet. The following features on the S/UNI-622-POS reference design ensure power up and power down occur properly. * A 1.0K Ohm resistor is placed in series between the 5V supply and the VBIAS and PBIAS pins. This resistor prevents excessive current from flowing from VDD through VBIAS and PBIAS to the 5V supply in case the 3V supply to VDD is applied before the 5V supply is applied to the bias pins. The QADV pins also needs a 100 ohm series resistor to limit inrush currents and prevent latch-up. VDD, QAVD, and regular AVD pins are supplied from the same 3.3V power plane. This keeps the voltage difference between the AVD pins, VDD and QAVD pins small thus preventing current flow from AVD pins to the VDD, and QAVD pins. Sensitive AVD pins are filtered using a 3.3V, 100mA voltage regulator powered from the 5V power plane. These sensitive AVD pins are current limited by the voltage regulator so that each pin cannot draw current higher than the 100 mA maximum latch up current. * * 11.2 Grounding Only one ground plane is recommended with no power or ground cuts in these planes. This one ground plane is shared among digital and analog signals. One ground plane simplifies design and layout. As in this design, more than one ground plane layers can be used, but all ground connections (vias) are made to all layers to make it appear as one ground plane. A trace characteristic impedance can be realized by providing the current return path either through a ground or power plane. It is very important to ensure proper analog supply decoupling as outlined below. Since the Optical interfaces (ODL's) are optically isolated, there is no requirement for heavy duty high-voltage and/or high energy protection as in other metallic physical mediums such as T1/E1. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 47 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 11.3 System Side Transmission Line Terminations The S/UNI-622-POS is capable of system side interface speeds up to 100 MHz. Because of the high frequency content of the system side signals, trace termination may be required to ensure reliable data transmission across the interface. All signals on the system side interface of the S/UNI-622-POS Reference Design are short point to point 50 MHz UL2 between the POS and the FPGA do not require any terminations. A "series source terminating resistors" may be required in a system where the UTOPIA Bus drivers have a fast rise/fall time and the distance between the POS chip and the link layer device is substantial. If we consider that these CMOS UTOPIA drivers have typical 1ns edges then traces longer than 0.89in/2.26cm should be terminated. See section 9, "PCB considerations", for detail on transmission lines. Because the drivers are CMOS and have limited current drive/source capabilities, parallel far end terminations can't be used. For point to point transmission like this, series source termination is a good option. The figure below illustrates the relative positioning and values of these series source termination resistors. Resistor values may vary depending on Zo transmission line impedance and the output impedance of the I/O driver. Figure 27: System Interface Terminations Link Layer Device S/UNI-622-POS Input 5 pF Output R1 Zo Output RO1 RO2 Notes: R2 Zo 5 pF Input - Terminations shown are for 3.3V Link Layer Device - Zo (trace impedance) 65 R1 = Zo - RO1 56 R2 = Zo - RO2 56 This termination scheme assumes that the link layer device drives signals at 3.3V levels. Because of the relative uncertainty of the output impedance (RO1 and RO2), it's best to have Zo as large as possible so that the output impedance PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 48 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN is as small as possible relative to Zo. However, a large Zo means a narrow, difficult to manufacture PCB trace. A small Zo would require wide traces and would take up a lot of PCB real-estate. However, a narrow trace is required to be able to route the trace between chip pins/balls. As a compromise, a 50ohm Zo was chosen for the 622MHz signals and the 77.76MHz clocks. The rest of the PCB traces are a compromise at 65 ohms. It is difficult to measure or control the a.c. output impedance of a driver consistently. In addition, this impedance is different for the rising and the falling edge. The impedance for device outputs is not typically published unless it's a "bus Driver" type of IC. However, for practical applications, the output a.c. impedance is typically around 10-25 ohms. In this case, if the traces were longer than 2.26cm, 56 ohm series resistors could have been used. This "series source termination" scheme relies on the fact that the far end is infinite impedance. However, as shown in Figure 28: Series Source Termination, all CMOS type infinite impedance inputs have finite capacitive inputs of about 5pF. So, initially when the signal, rising or falling edge, hits the input pin, it looks like a short circuit until the capacitor is charged/discharged and then the input looks like an infinite impedance. This causes a small glitch reflected back which may cause a problem. A simple way to solve this is to put another series resistor (65 ohm in this case), right at the input to the far-end pin, equal to the impedance of the transmission line. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 49 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Figure 28: Series Source Termination 0 T TIME Glitch due to input Capacitance 2T Link Layer Device S/UNI-622-POS Ro 2 R2 Zo = 65 Zin = Zo = 65 Input Ro2 + R 2 = Zo = 65 Outputs Zin = // Xc Zin = Rs + // Xc Input C 5pF Inputs Ro 2 R2 Zo = 65 Rs = Zo C 5pF 0 T TIME No Glitch 2T T = time it takes for edge to reach far end of transmission trace. each trace shows voltage vs. time at this position PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 50 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 12 TYPICAL JITTER MEASUREMENTS 12.1 Intrinsic Jitter This reference board exceeded GR-253-CORE Intrinsic Jitter specifications of 0.1 UI p-p and 0.01 UI rms. Typical Transmit Intrinsic jitter measurements are as follows. All measurements were taken with an HP 717 jitter test set transmitting PRBS-23 data, and the 12 kHz HP filter enabled on the RX side as per GR-253CORE. Because the HP717 did not have provisions for originating ATM cells, UTOPIA drop-side loop-back was not possible during the jitter tests. Table 9: Intrinsic jitter calibration tests ATM/SONET Data Source Adtech AX4000 HP 717 Table 10: Intrinsic jitter test results with HP 717 Test Method Standard test: Non-loop time mode, (using the on board PECL 77.76 MHz) reference oscillator) and HP717 originating optical data into POS reference board. No optical signal into the POS reference board. Nonloop time mode, using the on board PECL 77.76 MHz reference oscillator. Serial Line Loop Back. SLLE bit enabled in register 0x02 of POS chip with data originated from HP 717 Loop time mode using a HP717 tester as the OC-12 optical data source and LOOPT bit set in Register 0x02 of the POS chip. Jitter UIpp 0.056 Jitter UIrms 0.005 Jitter UIpp 0.117 0.004 Jitter UIrms 0.014 0.001 0.048 0.003 0.009 0.007 0.002 0.002 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 51 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 12.2 Jitter Tolerance Jitter Tolerance was measured using an HP 717 Jitter Tolerance test set with and without optical attenuation. We used 5V ODL (HP's HFCT5208B) and 3.3V ODL (Siemens V23826-H18-C363) and the results below exceeded Bellcore requirements. Typical measurements are shown below. Figure 29: Jitter Tolerance Test Set-up CompactPCI TM CHASSIS Power supply Floppy Operating System SONET/SDH Jitter Tolerance Test Set HP 717 HD OC-12c S/UNI-622-POS PM-5357 Reference Design PCB uP I/F J5 cPCI Backplane cPCI Pentium PCB RS-232 PENTIUM PC with Software Figure 30: Jitter Tolerance without Optical Attenuation PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 52 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Figure 31: Jitter Tolerance with Optical Attenuation CompactPCI TM CHASSIS Power supply Floppy Operating System SONET/SDH Jitter Tolerance Test Set HP 717 HD OC-12c S/UNI-622-POS PM-5357 Reference Design PCB uP I/F J5 cPCI Backplane cPCI Pentium PCB RS-232 Optical Attenuator Tektronix OCP 5002 PENTIUM PC with Software Figure 32: Jitter Tolerance with Optical Attenuation PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 53 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 13 OSCILLOSCOPE MEASUREMENTS This section presents sample oscilloscope measurements. They were performed with a fiber loop-back cable installed and TCLK was used as the scope trigger. 13.1 Differential Scope Probe A lot of the signals shown here were done with a Tektronix differential probe. The measurements taken show that the signal has a peak to peak voltage of twice of what we expected. As illustrated below, this is because the probe chooses one of the inputs as the reference, and measures the other signal with respect to this reference: Figure 33: Differential scope probe analysis REFCLK+, reference signal for Differential Probe 2.35Vmax 3.3V PECL levels 1.975V 1.6Vmin -0.8V 800mVp-p Eye Pattern time REFCLK+ +0.8V REFCLK4.05Vmax 3.675V 3.3Vmin 5V PECL levels Figure 34: What the differential probe actually sees flattened out reference signal for differential Probe +0.8V REFCLK+ -0.8V REFCLKtime Scope shows 1.6Vp-p PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 54 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 13.2 RFPO (Receive Frame Pulse Out) The board is in Fiber loopback mode. Channel 3 is RFPO (pin AB19 - PM5357) and Channel 2 is the TCLK (pin B19- PM5357) used as the trigger. Figure 35: Diagram RFPO (Receive Frame Pulse) 13.3 RXD+/- (Receive Data) Board is in fiber Loopback. Channel 1 is a differential measurement of the RXD+/- (across the 100 ohm terminating resistor near the RXD+/- pins of the PM5357) and Channel 2 is the TCLK (pin B19 - PM5357) used as the trigger. Figure 36: RXD+/- Eye (Receive Data) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 55 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 13.4 RCLK ( Recovered Clock) The PCB is in fiber loopback. Channel two, the trigger, is the Transmit 77Mhz clock and channel 3 is the recovered divide by eight Receive clock, RCLK. Figure 37: RCLK (Recovered Clock) 13.5 REFCLK+/Differential scope probe measurement of the Reference clock, REFLCK+ and REFCLK-, at the terminating 100 ohm resistor. Due to an anomaly of the differential probe, the clock is actually 0.8Vp-p not 1.6Vp-p as shown below. The probe looks at one of the signals and uses as a reference and thus the other signal is either -0.8V or +0.8V with respect to that reference. See section "Differential Scope Probe" for explanation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 56 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Figure 38: REFCLK+/-, 77.76mHz Reference clock 13.6 RXD+/- eye with OC-12 template Differential scope measurement of the TXD+/- signal at the RXD pin 100 ohm terminating resistor. Included in this figure is the OC-12 mask. Figure 39: RXD+/- eye with OC-12 template 13.7 Transmit Reference Clock, TCLK 77.76MHz This is a differential 0.8Vp-p clock. The Differential probe shows this signal to be twice the voltage. . See section "Differential Scope Probe" for explanation. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 57 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Figure 40: 77.7600 MHz Reference Clock 13.8 TXD+/- Eye with OC-12 Template This differential signal was measured across the termination 49.9 ohm resistors close to the Optical Device. Figure 41: TXD+/- Eye with OC-12 Template PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 58 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 13.9 Differential TXD+/- with TCLK as the trigger Channel 1 shows the TXD+/- signal and channel 2 shows the TCLK trigger. Figure 42: Differential TXD+/- with TCLK as Trigger PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 59 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 14 SCHEMATICS REVISION 3 The enclosed PCB (silk-screened as "...1.0 1999") layout is manufactured to Issue 2 schematics. The enclosed Issue 3 schematic are only slightly modified unreleased Rev 2 schematics. Please see the "Public Revision History" section in the front of this document for detail change list. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 1 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 15 PCB LAYOUT REVISION 1 The enclosed PCB (silk-screened as "...1.0 1999") layout is manufactured to Issue 2 schematics. The enclosed Issue 3 schematic are only slightly modified unreleased Rev 2 schematics. Please see the "Public Revision History" section in the front of this document for detail change list. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 1 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 16 REV 3 BOM (BILL OF MATERIALS) Description Distributor Manufacturer Info. Ten output low PI49FCT3807A skew clock buffer S JEDEC Ref Des Type SOIC20 U18 W SOIC14 U10 SOIC20 U4 W 603 C48 Qt y 1 Part Name - Value 74FCT807_SOIC2-BASE 74HC04_SOIC-123 74HC541, SOIC-HCMOS CAPACITOR-0.047F, X7R_0805 CAPACITOR-0.1F, 50V, X7R_805 Hex HC Inverter Octal HC Buffer 74HC541DW AVX08055C473JATN 1 1 1 Ceramic, Class 2, NEWARK -X7R, +/-5% 85F219 tolerance Ceramic CAPACITOR-10F, 10V, TANT TEH Tantalum DIGI-KEY -PCT2106CTND DIGI-KEY -PCT2476CTND DIGIKEY -F1224CT-ND DIGI-KEY S1011-36-ND DIGI-KEY S2012-36-ND DIGI-KEY S1011-36-ND DIGI-KEY -LU20095-ND CAPACITOR-47F, 10V, TANT TEH Tantalum FUSE__SMD_SOCKET-2.0 2 Amp Fuse 00A, NANO HEADER1-BASE HEADER_3X2_JUMPERBASE HEADER_8_100 MIL-BASE LED-GREEN, PCB RIGHT LED ANGLE LED10-RED, 25MA, 2.1V LED SMDCA C1, C4, P805 C8-C11, C15, C17, C19, C20, C22, C25C28, C31C47, C49C60, C63, 71-C81, C84-C109 SMDTA C2, C3, NCAP_ C5-C6, C C12, C29, C30 NEC_D C13, C14, C18, C21, C23, C24 NANO_ F1, F2 SMF_S OC KET TST_PT TP4, 7-11, _1 13,16,18, 19, 56, 57 HEADE J2 R_3X2 SIP8 J3 DIGI-KEY -LT1066-ND LED D1-D4 65 7 6 2 12 1 1 4 1 DIP20_ U2 SOCKE T PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 1 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Part Name - Value 47uF Tantalum capacitor Description 47uF, 6.3V, Tantalum 352152-1 CONNECTOR ZPACK5X22FH_BSCPI_2M ZPACK cPCI 2MM M HM 110 POS. TYPE B WITH GND SHIELD 352068-1 CONNECTOR ZPACK5X22FH_ASCPCI_2 ZPACK cPCI 2MM MM HM 110 POS. TYPE A WITH GND SHIELD INDUCTOR-1.0H, , 1H SMT choke, PANASONIC less than 1 Ohm Resistance LT1129CST_SOT-3.3V Low Drop out 3.3V Linear Voltage Regulator 8-pin dip socket NM93CS46EN Serial EEPROM for PLX chip 1-Kbit Serial EEPROM OTP Distributor Info. Digikey Manufacturer JEDEC Ref Des Type C47 ZPACK5 J5 X22FH_ BSCPCI Qt y AMP AMP ZPACK5 J1 X22FH_ ASCPCI DIGI-KEY -Panasonic PN# PCT1187CT- ELJ-FD1R0KF ND LT1129CST-3.3 Linear Technology, LT1129-3.3 SMDRE L1, L2 S805 SOT223 U8 -3 2 1 DIP8_S U12 OCKET 1 1 OSC_PECL_-77.76MHZ, 20 PPM NM93CS46EN National 8 pin dip U12 (Fairchild) Semiconductor M93CS46.html, National PN#NM93CS46E N 77.7600 MHz http://www.con 5V type, Saronix CRYS14 Y1 Crystal Oscillator win.com/cgi99T27M or type, 20 PPM, PECL bin/psearch.cgi Connor Winfield differential ?type=Clock&f EH13-541 or 3.3V outputs. Low amily=PECL type from Connor output jitter and Winfield EH14fast rise/fall times 541 Oscillator, 50.00 MHz 100 PPM, 3.3V, TTL output cPCI Bus Interface Chip DIGI-KEY -CTX176-ND PCI9050-1 CTS Reeves PN# CRYS14 Y3 MXO45HS50.0000 PLX PN# PCI9050-1 PQFP16 U13 0 603 R6, R7 1 OSC_TTL_DIP-50.0000M HZ, 100 PPMA PCI9050_PQFP-BASE RESISTOR-0, 5%, 603 1 1 2 0 ohm SMT resistor PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 2 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Part Name - Value 10F X5R ceramic capacitors Description Taiyo Yuden of 1930 North Thoreau, Drive, Suite 190 , Schaumburg IL, 60173 USA, 180036-TAIYO Distributor Info. Manufacturer JEDEC Ref Des Type 0805 Qt y RESISTOR-0, 5%, 805 DIGI-KEY -DIGI-KEY -P SMDRE R9-R12, 7 S805 R23, R24, R29 RESISTOR-1.0, 5%, 805 RESISTOR-1.0K, 5%, 805 RESISTOR-10, 5%, 805 RESISTOR-100, 5%, 603 RESISTOR-150, 5%, 805 RESISTOR-2.7, 5%, 805 RESISTOR-270, 5%, 805 RESISTOR-2K00, 1%, 805 RESISTOR-33, 5%, 805 RESISTOR-4.7K, 5%, 805 DIGI-KEY -DIGI-KEY -DIGI-KEY -DIGI-KEY -DIGI-KEY -DIGI-KEY -DIGI-KEY -- SMDRE R3, R17, S805 R22, R39, R41 SMDRE R40 S805 SMDRE R31 S805 603 R18-R20 SMDRE S805 SMDRE S805 SMDRE S805 SMDRE S805 SMDRE S805 SMDRE S805 5 1 1 3 R35-R38, 5 R47 R25 1 R8, R14- 4 R16 R21 1 R30, R51 2 RESISTOR-49.9, 1%, 805 RESISTOR-63.4, 1%, 805 RES_ARRAY_4_SMD-10 DIGI-KEY -DIGI-KEY -DIGI-KEY -- R1, R2, 9 R49, R50, R52-R56 SMDRE R32, R34 2 S805 SMDRE R33 S805 RN4 RN14R23, 34, 35 RN4 RN9-11, 36-40 1 12 RES_ARRAY_4_SMD-33 DIGI-KEY -Y4 8 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 3 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Part Name - Value RES_ARRAY_4_SMD-4.7K Description Distributor Info. DIGI-KEY -- Manufacturer R_SIP9-330 330 ohm sip, 9 position SUNI622POS_SBGA-BASE PM5357 S/UNI622-POS packet/ATM framer or PM5356 S/UNI-622-MAX ATM framer THUMB_WHEEL_SWCOMMO N CW, C&K TST_PT-BASE TST_PT-BASE TST_PT-BASE TST_PT-BASE TST_PT-BASE TST_PT-BASE TST_PT-BASE TST_PT-BASE TST_PT-BASE TST_PT-BASE TST_PT-BASE TST_PT-BASE TST_PT-BASE TST_PT-BASE DIGIKEY -CKN6000-ND JEDEC Ref Des Type RN4 RN2-8, 12, 13, 24-33, 4144 SIP10 RN1 SBGA_3 U7 04 Qt y 23 1 1 PMC-Sierra Inc. C&K CNK3M U1 Components Inc. 12 PN#3M120 DIGI-KEY S1011-36-ND TST_PT TP27_1 TP55 LED10 DIGI-KEY S1011-36-ND TST_PT TP1 _1 LED9 DIGI-KEY S1011-36-ND TST_PT TP2 _1 NEG_LED10 DIGI-KEY S1011-36-ND TST_PT TP3 _1 RCLK DIGI-KEY S1011-36-ND TST_PT TP17 _1 REFCLKN DIGI-KEY S1011-36-ND TST_PT TP6 _1 REFCLKP DIGI-KEY S1011-36-ND TST_PT TP5 _1 RFPO DIGI-KEY S1011-36-ND TST_PT TP15 _1 RST_POS_FP GA DIGI-KEY S1011-36-ND TST_PT TP21 _1 R_A DIGI-KEY S1011-36-ND TST_PT TP26 _1 TCLK DIGI-KEY S1011-36-ND TST_PT TP20 _1 UR0 DIGI-KEY S1011-36-ND TST_PT TP22 _1 UR1 DIGI-KEY S1011-36-ND TST_PT TP23 _1 UR2 DIGI-KEY S1011-36-ND TST_PT TP24 _1 1 29 1 1 1 1 1 1 1 1 1 1 1 1 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 4 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN Part Name - Value TST_PT-BASE 20 pin PLCC Description UR3 20 Pin PLCC socket OC-12 ODL, single or Mulitmode fiber, SONET/SDH Distributor Info. DIGI-KEY S1011-36-ND Digikey PN# ED80007-ND V23826-H18-C363-3.3V XC1701L_PC20C Serial EEPROM EEPROM OTP, 832,528 bits XC4036XLA_HQ240_HQF FPGA XC4036XLAP -9NS 09HQ240 JEDEC Type TST_PT _1 Mill-Max PN# 540- PLCC20 99-020-17-400_SOCK X00X, ET Insight HP Co. ODL, LCDComponents HFBR-5208- 5v, PMDInc., mulitmode,HFCT- SOCK Richmond, BC, 5208B-5v, single- ET Canada mode, or Siemens V23826-H18C363, 3.3V, single-mode. PLCC20 HQ240 Manufacturer Ref Des TP25 U9, U12, U16, U17 U3 Qt y 1 4 1 U9, U12, 4 U16, U17 U13 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 5 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN 17 FPGA ATM LOOPBACK SOURCE VHDL CODE library IEEE; use IEEE.std_logic_1164.all; entity ATM_Loopback_latched is port ( TCA: in STD_LOGIC; RCA: in STD_LOGIC; RDAT: in STD_LOGIC_VECTOR (15 downto 0); TDAT: out STD_LOGIC_VECTOR (15 downto 0); RENB: out STD_LOGIC; TENB: out STD_LOGIC; RSOC: in STD_LOGIC; TSOC: out STD_LOGIC; TFCLK: in STD_LOGIC; RFCLK: in STD_LOGIC; RESETB: in STD_LOGIC; LED: out STD_LOGIC_VECTOR(6 downto 0); ALE: in STD_LOGIC; LBEB: in STD_LOGIC_VECTOR(1 downto 0); LAD: inout STD_LOGIC_VECTOR(1 downto 0); BAD: inout STD_LOGIC_VECTOR(1 downto 0); WRB: in STD_LOGIC; RDB: in STD_LOGIC -FPGA_BAD: out STD_LOGIC_VECTOR(10 downto 0); -FPGA_WRB: out STD_LOGIC; -FPGA_RDB: out STD_LOGIC; -FPGA_ALE: out STD_LOGIC ); end ATM_Loopback_latched; architecture ATM_Loopback_arch of ATM_Loopback_latched is signal signal signal begin RENB_D <= TCA NAND RCA; RENB <= RENB_Q; LED <= "0000000"; FPGA_BAD <= "ZZZZZZZZZZZ"; FPGA_WRB <= 'Z'; FPGA_RDB <= 'Z'; FPGA_ALE <= 'Z'; RENB_D : STD_LOGIC; RENB_Q : STD_LOGIC; ENB_D1_D2 : STD_LOGIC; ----- -- Latch RENB -- D Flip Flop with Asynchronous Reset -TFCLK: in STD_LOGIC; -RESETB: in STD_LOGIC; -RENB_D: in STD_LOGIC; -RENB_Q: out STD_LOGIC; process (RFCLK, RESETB) begin if RESETB='0' then --asynchronous RESET active Low PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 1 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN RENB_Q <= '1'; elsif (TFCLK'event and TFCLK='1') then RENB_Q <= RENB_D; end if; end process; --TFCLK rising edge -- First latch for TENB -- D Flip Flop with Asynchronous Reset -TFCLK: in STD_LOGIC; -RESETB: in STD_LOGIC; -RENB_Q: in STD_LOGIC; -ENB_D1_D2: out STD_LOGIC; process (TFCLK, RESETB) begin if RESETB='0' then --asynchronous RESET active Low ENB_D1_D2 <= '1'; elsif (TFCLK'event and TFCLK='1') then --TFCLK rising edge ENB_D1_D2 <= RENB_Q; end if; end process; -- Second latch for TENB -- D Flip Flop with Asynchronous Reset -TFCLK: in STD_LOGIC; -RESETB: in STD_LOGIC; -ENB_D1_D2: in STD_LOGIC; -TENB: out STD_LOGIC; process (TFCLK, RESETB) begin if RESETB='0' then --asynchronous RESET active Low TENB <= '1'; elsif (TFCLK'event and TFCLK='1') then --TFCLK rising edge TENB <= ENB_D1_D2; end if; end process; -- Register for TDAT -- Register -TFCLK: in STD_LOGIC; -RESETB: in STD_LOGIC; -RDAT: in STD_LOGIC; -TDAT: out STD_LOGIC; process (TFCLK, RESETB) begin if RESETB='0' then --RESET active Low TDAT <= "0000000000000000"; elsif (TFCLK'event and TFCLK='1') then --TFCLK rising edge TDAT <= RDAT; end if; end process; -- D-flip flop for TSOC -- D-flip flop with asynchronous RESET -TFCLK: in STD_LOGIC; -RESETB: in STD_LOGIC; -RENB_Q: in STD_LOGIC; -RSOC: in STD_LOGIC; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 2 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN -TSOC: out STD_LOGIC; process (TFCLK, RESETB) begin if RESETB='0' then --asynchronous RESET active Low TSOC <= '0'; elsif (TFCLK'event and TFCLK='1') then --TFCLK rising edge TSOC <= RSOC; end if; end process; end ATM_Loopback_arch; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 3 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN NOTES PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 1 PRELIMINARY REFERENCE DESIGN PMC-1981070 ISSUE 2 PMC-Sierra, Inc. PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com Document Information: Corporate Information: Application Information: Web Site: None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2000 PMC-Sierra, Inc. PMC-1981070 (P2) ref PMC-1980911 (R3) Issue date: February 2000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE |
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